TOSHIBA TC74VHCT573AF/AFW/AFT TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74VHCTS73AF, TC74VHCT573AFW, TC74VHCT573AFT OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT The TC74VHCT573A is an advanced high speed CMOS OCTAL LATCH with 3-STATE OUTPUT fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8- bit D-type latch is controlled by a latch enable input (LE) and a_output enable input (OE). When the OE input is high, the eight outputs are in a high impedance state. The input voltage are compatible with TTL output voltage. This device may be used as a level converter for interfacing 3.3V to 5V system. Input protection and output circuit ensure that 0 to 5.5V can be applied to the input and output*! pins without regard to the supply voltage. These structure prevents device destruction due to mismatched supply and input/output voltages such as battery back up, hot board insertion, etc. *1: output in off-state FEATURES : High Speeds-sssssstsssceeees -tod = 7.7ns(typ.) at Voc = 5V Low Power Dissipation loc = 42A(Max.) at Ta = 25C e Compatible with TTL outputs ---- Vi, =0.8V (Max.) Vin = 2.0V (Min.) Power Down Protection is provided on all inputs and outputs. e Balanced Propagation Delays-----toLH=tpHL 0 Low Noise ----s1essssssesessesseesssesseaces Votp = 1.6V (Max.) e Pin and Function Compatible with the 74 series (74AC /HC /F/ALS/LS ete.) 573 type. ee ae amine 1 1 F (SOP20-P-300-1.27) FW (SOL20-P-300-1.27) Weight: 0.22g(TYP.) Weight : 0.46g (TYP) ) 20 & 4 \ Sr % @ 1 FT (TSSOP20-P-0044-0.65) Weight : 0.08g (TYP.) PIN ASSIGNMENT OE 1 20 Vee DO 2 19 QO Di 3 18 Q1 D2 4 17, Q2 D3 5 16 Q3 D4 6 15 Q4 D5 7 14 Q5 D6 8 13 Q6 D7 9 12 Q7 GND 10 11 LE (TOP VIEW) TRUTH TABLE IEC LOGIC SYMBOL INPUTS = OUTPUT OE] LE | D H}X |] X Z L L x Qn L H L L L H H H X : Dont Care Z : High Impedance Qn : Q outputs are latched at the time when the LE input is taken to a low logic level. GE EN LE DO Qo D1 Qi D2 2 D3 3 D4 Q4 DS 5 D6 Q6 D7 7 Q61001EBAZ @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can maifunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. tt is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, arid to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human tife, bodily injury or damage to property. In developing your designs, please ensyre that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor eliability Handbook. 359 1997-01-30 1/6TOSHIBA TC74VHCT573AF/AFW/AFT SYSTEM DIAGRAM 7 D2 D 5 3 D4 DS D6 D 4 6 7 8 9 D D D D D 9 1% $219 12% [1 1.9 aw & D L& 18| 7 16| 15] 14| 13| Qi Q2 Q3 Q4 Qs Q6 Q?7 ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL VALUE UNIT Supply Voltage Range Vec ~0.5~7.0 Vv DC Input Voltage Vin -0.5~7.0 Vv DC Output Voltage Vour 0.5~7.0 (Note 1) Vv 0.5~VCC +0.5 (Note 2) Input Diode Current he 20 mA Output Diode Current lox +20 (Note 3) mA DC Output Current lout 25 mA DC Vee/Ground Current lee +75 mA Power Dissipation Py 180 mw Storage Temperature Tstg 65~ 150 C (Note 1) Output in Off-State (Note 2) High or Low State. Igyut absolute maximum rating must be observed. (Note 3) VoUT<GND, VoutT>Vcc RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL VALUE UNIT Supply Voltage Vee 4.5~5.5 Vv Input Voltage Vin O~5.5 Vv 0~5.5 (Note 4) Output Voltage Vour O~VCC (Note 5) Vv Operating Temperature Topr 40~85 C Input Rise and Fall Time dt/dV 0~20 ns/V (Note 4) Output in Off-State (Note 5) High or Low State 261001 EBA2 3 The products described in this document are subject to foreign exchange and foreign trade contral laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 360 1997-01-30 2/6TOSHIBA TC74VHCT573AF/AFW/AFT DC ELECTRICAL CHARACTERISTICS Ta = 25 Ta = 40~85 PARAMETER SYMBOL CONDITON asec 8 er unit Vee(V) | MIN. | TYP. |[MAX.] MIN. [ MAX. High - Level ~ ~ _ _ input Voltage Vin 4.5~5.5] 2.0 2.0 V Low - Level _ _ ~ Input Voltage Vie 4.5~5.5) 0.8 08 | Vv High - Level Vox Vin= lon= - 502A] 4.5 | 440] 450] |] 440] Vv Output Voltage YworVic [low=-8mA | as [394] - | | 3a0] Low - Level Vo. | Wine lo. = 504A 45 ~ [oo |or] - or]. Output Voltage Vigor Viz lo = 8MA 45 _ _ 0.36 _ 0.44 3-State Output Vin = Vin or Vie _ {4 | Off -State Current loz Vout = Vec or GND 55 0.25 2.50 Input Leakage Current tin Vin =5.5V or GND O~5.5} _ +0.1 > 41.0 HA \ Vin = Vcc or GND 5. - - | 40] - | 400 Quiescent Supply < Insc 0 Current PER INPUT => Viy=3.4V _ _ _ leet | OTHER INPUT : Vcc or GND 55 1.35 1.50 | mA Output Leakage top> | Vour = 5-5V 0 - | - | o5 | ~ | 50 | za TIMING REQUIREMENTS (input t,=tr=3ns) Ta=25 Ta = ~40~85C PARAMETER symaot | TEST CONDITION as 2s 8 UNIT Vec(V) | TYP. LIMIT LIMIT Minimum Pulse Width inimu (LE) ' tw (H) 5.0+0.5 _ 6.5 8.5 Minimum Set-up Time ts 5.0405 - 15 1.5 ns Minimum Hold Time th 5.0+0.5 - 3.5 3.5 361 1997-01-30 3/6TOSHIBA TC74VHCT573AF/AFW/AFT AC ELECTRICAL CHARACTERISTICS ( Input t, = t; = 3ns) T = 25 = ~ 40~85 PARAMETER SYMBOL EST CONDITION Ta =25C Ta 40~85C| UNIT Vec(V) | CL(pF) | MIN. | TyP. | MAX. | MIN. | MAX. Propagation Delay Time toLy 50+05 15 7 77 12.3 1.0 | 13.5 (LE-Q) toHL To 50 8.5 | 13.3 | 1.0 | 14.5 Propagation Delay Time toLy 5.0+05 15 = 5.1 8.5 1.0 9.5 (D-Q) tpHL TT 50 [59 [ 95 [ 10 [105 3-State Output Enable Time | teZt | ri=tka [5.040. 15 6.3. | 10.9 | 1.0 | 12.5 wip tozH 5.0205/5_| 171 [19] 101135) 3-State Output Disable Time pz rL=1ko |5.0+0.5} 50 | 88 |112 | 1.0 | 12.0 pl Output to Output Skew fost (Note 6)|5.0+0.5| 50 - - 1.0} 1.0 S| input Capacitance Cin - 4 10 _ 10 Output Capacitance Cout _ 6 ~ _ _ pF Power Dissipation Capacitance Cpp (Note 7) _ 25 - ~ - (Note 6) Parameter guaranteed by design. toy = totum totun |, tosue = Itoutm tonin! (Note 7) Cpp is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: lec (opr) =Cpp Vec- f nttec/8 ( per latch ) And the total Cpp when n pes. of Latch operate can be gained by the following equation: Ceo (total) =144+11-n NOISE CHARACTERISTICS (input t,= t= 3ns) PARAMETER SYMBOL TEST one ~ = x UNIT Rakimum'Dynamic Vo, | Your C. = 50pF 5.0 12 1.6 v Minimum Dynamic Vo, | Wow C, = 50pF 50 | 1.2 16 |v Dynamic Inpat Voltage Vino C. = 50pF >.0 _ 2.0 V Meximumiow Level | vo | _c=soer | so | - | 08 |v 362 1997-01-30 4/6