LH28F016SA 16M (1M × 16/ 2M × 8) Flas h Memory
FEATURES
•• User-Se lectab le 3 .3 V or 5 V VCC
•• User-C onfig urable ×8 or ×16 Opera tion
•• Access Ti mes:
Fo r 3.3 V Read : 12 0/150 n s
Fo r 5 V R ead : 70/1 0 0 ns
•• 0.43 MB/sec Write Transfer Ra te
•• 1 Million Erase Cycles pe r Bl ock
•• 56-L ead , 1.2 mm × 14 mm × 20 mm
TSOP Package
•• Revolutionary Architecture
– Pipe lin ed C omman d Execu tio n
– Write Du ring Erase
– Co mma nd Su perse t o f SHAR P’s
LH 28F0 08SA
•• 1 m A Typ ical ICC in Static Mod e
•• 1 µA Typical Deep Power-Down
•• 32 Ind epe nde ntly Lo ckabl e Blocks
•• State-of-the-Art 0.6 µm ETOX TM 1 Fl ash
Technology
DESCRIPTION
S HA RP’s L H28F016SA 16M F lash Mem ory is a revo-
lutionary architecture which enables the design of truly
mobile, high-performance, personal computing and
communication products. With innovative capabilities,
low power operation and very high read/write perform-
ance, the LH28F016SA is also the ideal choice for
designing embedded mass storage flash memory sys-
tems.
The LH28F016SA is a v e ry high density, highest per-
for mance non-volat ile read/write solution f or solid-state
stor age applications. Its symmetrically blocked archi-
tecture (100% compatible with the LH28F008SA 8M
Flash memory), extended cycling, low power 3.3 V
operation, very fast write and read performance and
selective block locking provide a highly flexible memory
component suitable for high-density memory cards,
R esident Flash Arrays and PCMCIA-AT A Flash Drives.
The LH 28F016SA’s dual read vol ta ge enab les the de-
sign of memory cards which can interchangeably be
read/written in 3.3 V and 5.0 V systems. Its ×8/×16
architect ure a ll ows the optimization of memory to proc-
essor interface. The flexible block locking option en-
abl e s bundli n g o f executable app licatio n software in a
Resident Flash Array or memory card. Manufactured
on SHARP’s 0.6 µm ETO XTM 1 process technology, th e
LH28F016SA is the most cost-effective, high-density
3.3 V flash memory.
1 ETOX is a trademar k of Intel Cor poration.
7-69
1. 0 INTRODUCTION
The documentation of the SHARP LH28F016SA mem-
ory device includes this data sheet, a detailed user’s
manual, and a number of application notes, al l of w h ich
are referenced at the end of th is data sheet.
The data sheet is intended to give an overview of th e
chip feature-set and of the operating AC/DC specifica-
tions. The LH28F016SA User’s Manual provides com-
plete descriptions of the user modes, system interface
examples, and detailed descriptions of all principles of
operation. It also contai n s the full list of softwa re algo-
rithm flowcharts, and a brief section on compatibility
with SHARP LH28F008SA.
1. 1 Produ ct Ov erview
The LH28F016SA is a high-performance 16M
(16,777,216 bit) block erasable non-volatile random
access memory organize d as either 1 Mword × 16 or
2 Mbyte × 8. The LH28F016SA includes thirty-two 64KB
(65,536) blocks or thirty-two 32-KW (3 2,768) blocks. A
chi p memory map i s shown in Figure 3.
The implementation of a new architecture, with many
enhanced features, will improve the device operating
characteri stics and re su lts in greater product reliability
and ease of use.
S ome sign ificant enh ancements o f the LH 28F016SA
include:
•• 3.3 V Low Power C apability
•• Improved Write Performance
•• Dedicated Block Write/E rase Protecti on
A 3/5# input pi n reconfigures the device internally for
optimized 3.3 V or 5.0 V read/write operation.
The LH28F016SA will be available in a 56-lead,
1.2 mm thick, 14 mm × 20 mm TSOP type 1 package.
This form factor and pinout allow for very high board
layout densi ties.
A Co mmand User Interface (CUI) serves as the sys-
tem interface between the microprocessor or micro-
controlle r and the internal memory ope ration.
Internal Algorithm Automation allows Byte/Word
Writes and Block Erase operations to be executed using
a Two-Write command sequence to the CUI in the same
w ay as the LH 28F008S A 8M Flash memory.
A Superset of commands have been added to the
basic LH28F008SA command-set to achieve higher
write performance and provide additional capabilities.
These new comman ds and features include:
•• Page Buffer Wri tes to Fl ash
•• Command Queuing Cap ability
•• Automatic Data Writes Du ri ng Erase
•• Software Locking of Memory Bl ocks
•• Two-Byte S uccessive Writes i n 8-bi t Systems
•• Erase All Unlocked Blocks
Writing of memory data is performed i n either byte or
word increments typically within 6 µsec, a 33% improve-
ment over the LH28F00 8SA. A Block Erase operation
erases one of the 32 bl ocks in typical ly 0.6 sec, inde-
pendent of the other blocks, which is about 65%
improvement over the LH 28F008SA.
Each bl ock can be written and erased a minimum of
100,000 cycles. Systems can achieve 1 million Block
Erase Cycles by providing wear-leveling algorithms and
graceful block retirement. These techniques have
already been employed in many flash file systems and
Ha rd Di sk D rive d esigns.
The LH28F016SA incorporates two Page Buffers of
256 Byt es (128 Wor ds) each to allow page data writes.
This fea ture can improve a system write perfo rma nce
by up to 4. 8 times over previous f lash m emory devices.
All operations are started by a sequence of Write
commands to the device. Three Status Registers
(described in detail later) and a RY/BY# output pin
provide information on the progress of the requested
operation.
While the LH28F008SA requires an operat ion t o com-
pl ete before the next ope ration can be re quested, the
LH28F016SA allows queuing of the next operation while
the mem ory ex ecut es t he cur rent operat ion. Th is elimi -
nates system overhead when writing several bytes in
a ro w to t he array or er as ing sever al blocks at the same
time. The LH28F016S A can also perform write opera-
tions to one block of memory while performing erase
of another block.
The LH28F016SA provides user-selectable block lock-
ing to protect code or data such as Device Drivers,
PCMCIA card information, ROM-Executable O/S or
App licatio n Code. Each block has an associated non-
volatile lock-bit which determines the lock status of t h e
b lock. In addition, the LH28F016SA has a m aster Write
Protect pin (WP# ) which prevents any modifications to
memory blocks whose lock-bi ts are set.
LH28F016SA 16M (1M × 16/2M × 8 ) F la sh Memory
7-70
The LH28F016SA contains three types of Status Reg-
is ters to accompl ish various fun c ti ons:
•• A Compatible Status Register (CSR) which is 100%
compatible with the LH28F008SA Flash memory’s
Status Register. This register, when used alone,
provides a straightforward upgrade capability to the
LH28F0 16SA from a LH28F008SA-based desi gn.
•• A Global Status Register (GSR) which informs the
system of command Queue status, Page Buffer
status, and overall Write Status Machine (WSM)
status.
•• 32 Block Status Registers (BSRs) which provide
block-specific status information such as the block
lock-bit status.
The GSR and BSR memory maps for Byte-Wide and
Word-Wide modes are shown in Figures 4.1 and 4.2.
The LH28F016SA incorporates an open drain RY/BY#
output p in. This f eature a llo ws t he user to OR-t ie many
RY/BY# pins together in a multiple memory configur a-
tion such as a Resident Flash Array.
Other configurations of the RY/BY# pin are enabl ed
via special CUI commands and are described in detail
in the LH28F016SA User’s Manual.
The LH28F016SA also incorporates a dual chip-en-
able function with two input pins, CE0# and C E1#. These
pins have exactly the same functionality as the regular
chip-enable pin CE# on the LH28F008SA. For minimum
chip designs, CE1# may be tied to ground and use CE0#
as the chip enable input. The LH28F016SA uses the
logical combination of these two signal s to enable or
disable the entire chip. Both CE0# and CE1# must be
active low to enable the device and if either one
becomes inactive, the chip will be disabled. This feature,
along with the open drain RY/BY# pin, allows the system
designer to reduce the number of control pins used in
a large a rray of 16M devices.
The BYT E# pin allows either ×8 or ×16 read/writes to
the LH28F016SA. BYTE# at logic low selects 8-bit
mode with address A0 selecting between low byte and
high byte. On the other hand, BYTE# at logic high
ena bles 16-bit operation with address A1 becoming the
l owest or der addr ess and address A0 is not used ( don’t
care). A devi ce di agra m is sh own in Figure 1.
The LH2 8F016SA is spe cified for a maximum access
time of 70 ns (t ACC) at 5. 0 V operat ion (4. 75 V to 5.25 V)
over the commercial temperature range (0°C to +70°C).
A corresponding maximum access time of 120 ns at
3.3 V (3.0 V to 3.6 V and 0°C to +70°C) is achieved
for reduced po wer consumption applications.
The LH28F016SA incorporates an Automatic Power
Saving (APS) feature which substantially reduces the
active current when the device is in static mode of
operati on (addresses not swi tching).
In APS mode, the typical ICC current is 1 mA at 5.0 V
(0.8 mA at 3.3 V).
A Deep Power-Down mode of operation is invoked
when the RP# (calle d PWD on the LH28F008SA) pin
transitions low. This mode brings the device power
consumption to less than 1.0 µA, typically, and provides
additional write protection b y acting as a device reset
pi n d urin g powe r t ransi tions. A reset time of 400 ns is
required from RP# switching high until outputs are again
va lid. In the De ep Power- Down stat e, the W SM is reset
(any current operation w il l ab ort ) and the CSR , GSR,
and BS R regi sters are cleared.
A CMOS Standby m ode of oper ation is ena bled when
either CE0# or CE1# transitions high and RP# stays high
w it h al l input cont rol pins at CMO S levels. In this mode,
the device typically draws an ICC standby current of
50 µA.
2.0 DEVICE PINOUT
The LH28F016SA 56L-TSOP Type I pinout configura-
tion is shown in Fi gure 2.
16M (1M × 16/2M × 8) Flash Memory LH28F016SA
7-71
Output
Buffer Output
Buffer
ID
Register
CSR
Data
Comparator
DQ
0-7
DQ
8-15
CUI
Y GATING/SENSING
64-KBYTE
Block 0
64-KBYTE
Block 1
X-DECODER
Y-DECODER
ADDRESS
COUNTER
I/O Logic 3/5#
BYTE#
CE0#
CE1#
OE#
WE#
WP#
RY/BY#
RP#
V
PP
3/5#
V
CC
GND
Program/Erase
Voltage Switch
A
0-20
Input
Buffer
Input
Buffer Input
Buffer
OUTPUT MULTIPLEXER
64-KBYTE
Block 30
64-KBYTE
Block 31
WSM
ESRs
ADDRESS
QUEUE
LATCHES
PAGE
BUFFERS
DATA
QUEUE
REGISTERS
Figure 1. LH28F016SA Block Diagram
Archit ect ural Evol ution Includes Page Buffer s, Q ueue Registers, and Extended Status Registers
LH28F016SA 16M (1M × 16/2M × 8) F la sh Memory
7-72
2. 1 Lead Descripti ons
Name and Function
BYTE-SELECT ADDRESS: Selects between high and low byte when
device is in x8 mode. This address is latched in x8 Data Writes. Not used
in x16 mode (i.e., the A
0
input buffer is turned off when BYTE# is high).
WORD-SELECT ADDRESSES: Select a word within one 64-Kbyte
block. A
6-15
selects 1 of 1024 rows, and A
1-5
selects 16 of 512
columns. These addresses are latched during Data Writes.
BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase blocks. These
addresses are latched during Data Writes, Erase and Lock-Block
operations.
LOW-BYTE DATA BUS: Inputs data and commands during CUI write
cycles. Outputs array, buffer, identifier or status data in the appropriate
Read mode. Floated when the chip is de-selected or the outputs are
disabled.
HIGH-BYTE DATA BUS: Inputs data during x16 Data-Write operations.
Outputs array, buffer or identifier data in the appropriate Read mode; not
used for Status register reads. Floated when the chip is de-selected or
the outputs are disabled.
CHIP ENABLE INPUTS: Activate the device's control logic, input
buffers, decoders and sense amplifiers. With either CE
0
# or CE
1
# high,
the device is de-selected and power consumption reduces to Standby
levels upon completion of any current Data-Write or Erase operations.
Both CE
0
#, CE
1
# must be low to select the device.
All timing specifications are the same for both signals. Device Selection
occurs with the latter falling edge of CE
0
# or CE
1
#. The first rising edge
of CE
0
# or CE
1
# disables the device.
RESET/POWER-DOWN: RP# low places the device in a Deep Power-
Down state. All circuits that burn static power, even those circuits
enabled in standby mode, are turned off. When returning from Deep
Power-Down, a recovery time of 400 ns is required to allow these circuits
to power-up.
When RP# goes low, any current or pending WSM operation(s) are
terminated, and the device is reset. All Status registers return to ready
(with all status flags cleared).
OUTPUT ENABLE: Gates device data through the output buffers when
low. The outputs float to tri-state off when OE# is high.
NOTE:
CE
X
# overrides OE#, and OE# overrides WE#.
WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue
Registers and Address Queue Latches. WE# is active low, and latches
both address and data (command or array) on its rising edge.
READY/BUSY: Indicates status of the internal WSM. When low, it
indicates that the WSM is busy performing an operation. RY/BY# high
indicates that the WSM is ready for new operations (or WSM has
completed all pending operations), or Erase is Suspended, or the device
is in deep power-down mode. This output is always active (i.e., not
floated to tri-state off when OE# or CE
0
#, CE
1
# are high), except if a
RY/BY# Pin Disable command is issued.
A
0
A
1
-A
15
A
16
-A
20
DQ
0
-DQ
7
DQ
8
-DQ
15
CE
0
#, CE
1
#
RP#
OE#
WE# INPUT
INPUT
INPUT
INPUT
INPUT/OUTPUT
INPUT/OUTPUT
INPUT
INPUT
INPUT
RY/BY# OPEN DRAIN
OUTPUT
Symbol Type
16M (1M × 16/2M × 8) Flash Memory LH28F016SA
7-73
2. 1 Lead Descripti ons (Con tin ued )
NOTE:
56-LEAD TSOP Mechanical D iagrams and Dimensions ar e shown at the end of this specification
Name and Function
WP#
BYTE#
3/5#
NC
INPUT
Symbol Type
WRITE PROTECT: Erase blocks can be locked by writing a non-volatile lock-bit for
each block. When WP# is low, those locked blocks as reflected by the Block-Lock
Status bits (BSR.6), are protected from inadvertent Data Writes or Erases. When
WP# is high, all blocks can be Written or Erased regardless of the state of the lock-
bits. The WP# input buffer is disabled when RP# transitions low (deep power-down
mode).
BYTE ENABLE: BYTE# low places device in x8 mode. All data is then input or output
on DQ
0-7
, and DQ
8-15
float. Address A0 selects between the high and low byte.
BYTE# high places the device in x16 mode, and turns off the A
0
input buffer. Address
A
1
, then becomes the lowest order address.
3.3/5.0 VOLT SELECT: 3/5# high configures internal circuits for 3.3V operation.
3/5# low configures internal circuits for 5.0V operation.
NOTES:
Reading the array with 3/5# high in a 5.0V system could damage the device.
There is a significant delay from 3/5# switching to valid data.
ERASE/WRITE POWER SUPPLY: For erasing memory array blocks or writing words/
bytes/pages into the flash array.
DEVICE POWER SUPPLY (3.3V ± 0.3V, 5.0V ± 0.5V):
Do not leave any power pins floating.
GROUND FOR ALL INTERNAL CIRCUITRY:
Do not leave any ground pins floating.
NO CONNECT:
No internal connection to die, lead may be driven or left floating.
GND
V
CC
V
PP
INPUT
INPUT
SUPPLY
SUPPLY
SUPPLY
3/5# 1
CE1# 2
NC 3
A20 4
A19 5
A18 6
A17 7
A16 8
VCC 9
A15 10
A14 11
A13 12
A12 13
CE0# 14
VPP 15
RP# 16
A11 17
A10 18
A9 19
A8 20
GND 21
A7 22
A6 23
A5 24
A4 25
A3 26
A2 27
A1 28
56 WP#
55 WE#
54 OE#
53 RY/BY#
52 DQ15
51 DQ7
50 DQ14
49 DQ6
48 GND
47 DQ13
46 DQ5
45 DQ12
44 DQ4
43 V CC
42 GND
41 DQ11
40 DQ3
39 DQ10
38 DQ2
37 V CC
36 DQ9
35 DQ1
34 DQ8
33 DQ0
32 A0
31 BYTE#
30 NC
29 NC
LH28F016SA
56-LEAD TSOP PINOUT
14mm x 20mm
TOP VIEW
Figure 2. TS OP Configuration
LH28F016SA 16M (1M × 16/2M × 8) F la sh Memory
7-74
3. 0 MEMORY MAPS
64 KByte Block 31
64 KByte Block 30
64 KByte Block 29
64 KByte Block 28
64 KByte Block 27
64 KByte Block 26
64 KByte Block 25
64 KByte Block 24
64 KByte Block 23
64 KByte Block 22
64 KByte Block 21
64 KByte Block 20
64 KByte Block 19
64 KByte Block 18
64 KByte Block 17
64 KByte Block 16
64 KByte Block 15
64 KByte Block 14
64 KByte Block 13
64 KByte Block 12
64 KByte Block 11
64 KByte Block 10
64 KByte Block 9
64 KByte Block 8
64 KByte Block 7
64 KByte Block 6
64 KByte Block 5
64 KByte Block 4
64 KByte Block 3
64 KByte Block 2
64 KByte Block 1
64 KByte Block 0
1FFFFF
1F0000
1EFFFF
1E0000
1DFFFF
1D0000
1CFFFF
1C0000
1BFFFF
1B0000
1AFFFF
1A0000
19FFFF
190000
18FFFF
180000
17FFFF
170000
16FFFF
160000
15FFFF
150000
14FFFF
140000
13FFFF
130000
12FFFF
120000
11FFFF
110000
10FFFF
100000
0FFFFF
0F0000
0EFFFF
0E0000
0DFFFF
0D0000
0CFFFF
0C0000
0BFFFF
0B0000
0AFFFF
0A0000
09FFFF
090000
08FFFF
080000
07FFFF
070000
06FFFF
060000
05FFFF
050000
04FFFF
040000
03FFFF
030000
02FFFF
020000
01FFFF
010000
00FFFF
000000
Figure 3. LH28F016SA Memory Map ( Byt e-Wi de Mode)
16M (1M × 16/2M × 8) Flash Memory LH28F016SA
7-75
3.1 Extended Status Registers Memory Map
X8 MODE A[20:0]
1F0006H
1F0005H
1F0004H
1F0003H
1F0002H
1F0001H
1F0000H
000005H
000004H
000003H
000002H
000001H
000000H
000006H
010002H
RESERVED
GSR
RESERVED
BSR31
RESERVED
RESERVED
GSR
RESERVED
BSR0
RESERVED
RESERVED
RESERVED
RESERVED
Figure 4.1. Extended Status R egister
Me mory Map (Byte-Wide Mod e )
X16 MODE A[20:1]
F8003H
F8002H
F8001H
F8000H
00002H
00001H
00000H
00003H
08001H
RESERVED
GSR
RESERVED
BSR31
RESERVED
RESERVED
GSR
RESERVED
BSR0
RESERVED
RESERVED
RESERVED
RESERVED
Figure 4.2. Extended S tatus Register
Memory Map ( Word-Wi de M ode)
LH28F016SA 16M ( 1M × 16/2M × 8 ) F la sh Memory
7-76
4.0 BUS OPERAT IONS, CO MMANDS AND STATUS REGISTER DEFINITIONS
4. 1 Bus Op eration s for W ord-Wide Mo de (BYTE# = VIH)
4. 2 Bus Op eration s For Byte-Wid e Mode (BYTE# =VIL)
NOTES:
1. X can be VIH or VIL for address or cont rol pins except for RY/BY#, which is either VOL or VOH.
2. R Y/ BY# output is open drain. When the WSM i s ready, Erase is suspended or the device is in deep power-down mode, R Y/ BY# w il l be at
VOH if it is t ied t o VCC through a resistor. When the RY/BY# at VOH is i ndependent of OE# wh ile a WSM operat ion is in progress.
3. RP# at GND ±0.2 V ensures the lowest deep power-down current .
4. A0 and A1 at V IL provide manufactur er ID codes in ×8 and ×16 modes respectively.
A0 and A1 at V IH provide device I D codes in ×8 and ×16 modes respectively. A ll ot her addresses ar e set to zero.
5. Commands for differ ent Erase operations, Data Wr it e operations of Lock-Block operat ions can only be successfully completed wh en
VPP = VPPH.
6. While the WSM is running, RY/BY# in Level-Mode (default) stays at VOL until a ll operat ions ar e complet e. RY/ BY# goes t o VOH when t he
WSM is not busy or in erase suspend mode.
7. R Y/ BY# may b e at VOL wh ile the W SM is busy perf orming v ar ious operations. For example, a st atus regist er r ead during a w rit e oper ation.
Mode Notes RP# CE
1
# CE
0
# OE# WE# A
1
DQ
0-15
RY/BY#
Read
Output Disable
Deep Power-Down
Manufacturer ID
Device ID
Write
Standby
1,2,7
1,6,7
1,6,7
1,3
4
4
1,5,6
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
X
V
IL
V
IL
X X X X
X
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
X
X X
X
X
V
OH
V
OH
V
OH
D
OUT
High Z
High Z
High Z
0089H
66A0H
D
IN
X
V
IL
V
IH
V
IH
V
IH
V
IL
V
IH
X X X
Mode Notes RP# CE
1
# CE
0
# OE# WE# A
0
DQ
0-7
RY/BY#
Read
Output Disable
Deep Power-Down
Manufacturer ID
Device ID
Write
Standby
1,2,7
1,6,7
1,6,7
1,3
4
4
1,5,6
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
X
V
IL
V
IL
X X X X
X
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
X
X X
X
X
V
OH
V
OH
V
OH
D
OUT
High Z
High Z
High Z
89H
A0H
D
IN
X
V
IL
V
IH
V
IH
V
IH
V
IL
V
IH
X X X
16M (1M × 16/2M × 8) Flash Memory LH28F016SA
7-77
4.3 LH28F008SA-Compatib le Mod e Co mmand Bus Defi nitions
NOTES:
1. Fol low ing the intellig ent identifier command, two Read operat ions access t he manufactur er and device signature codes.
2. The C SR is automat ically available after device enter s Dat a Write, Era se, or Suspend operations.
3. C lears CSR.3, CSR. 4 and C SR.5. A lso c lear s GSR. 5 and all BSR.5 and BS R.2 b its.
See Stat us regist er definit ions.
Command Notes First Bus Cycle Second Bus Cycle
Oper Addr Data Oper Addr Data
Read Array
Intelligent Identifier
Read Compatible Status Register
Clear Status Register
Word/Byte Write
Alternate Word/Byte Write
Block Erase/Confirm
Erase Suspend/Resume
1
2
3
Write
Write
Write
Write
Write
Write
Write
Write
X
X
X
X
X
X
X
X
FFH
90H
70H
50H
40H
10H
20H
B0H
Write
Write
Write
Write
Read
Read
Read
AA
IA
WA
WA
BA
X
X
AD
ID
CSRD
WD
WD
D0H
D0H
ADDRESS
AA = Array Address
B A = B lock A ddr e ss
IA = Identifier Address
WA = Write Address
X = Don’t Care
DATA
A D = Ar ray Dat a
CSRD = CSR Data
I D = Identifier Data
WD = Wr it e Data
LH28F016SA 16M (1M × 16/2M × 8) F la sh Memory
7-78
4.4 LH28F016SA-Performance Enhancement Command Bus Definitions
Command Mode Notes First Bus Cycle Second Bus Cycle Third Bus Cycle
Read Extended
Status Register
Single Load to
Page Buffer
Sequential Load to
Page Buffer
Page Buffer Write
to Flash
Lock
Block/Confirm
Upload Status
Bits/Confirm
Upload Device
Information
Erase All Unlocked
Blocks/Confirm
RY/BY# Enable to
Level-Mode
RY/BY# Pulse-On-
Write
RY/BY# Disable
Sleep
Abort
Page Buffer Swap
Two-Byte Write
RY/BY# Pulse-On-
Erase
x8
x8
x8
x16
x16
1
4,6,10
4,5,6,10
3,4,9,10
4,5,10
3
2
8
8
8
8
Oper Addr Data
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
71H
72H
74H
E0H
E0H
0CH
0CH
FBH
77H
97H
99H
A7H
96H
96H
96H
96H
F0H
80H
Oper Addr Data
Read
Read
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
RA
PA
PA
X
X
A0
X
A0
BA
X
X
X
X
X
X
X
GSRD
BSRD
PD
PD
BCL
WCL
BC(L,H)
WCL
WD(L,H)
D0H
D0H
D0H
D0H
01H
02H
03H
04H
Oper Addr Data
Write
Write
Write
Write
Write
X
X
WA
WA
WA
BCH
WCH
BC(H,L)
WCH
WD(H,L)
Read Page Buffer
7
Write X 75H
ADDRESS
B A = B lock A ddr e ss
PA = Page Buffer Addr ess
R A = Extended Regist er Address
WA = Write Address
X = Don’t Care
DATA
A D = Arr ay Data
PD = P a ge Buffer Data
BSRD = BSR Data
GSRD = GSR Dat a
WC ( L.H) = Wor d Count (Low, H igh)
BC (L. H) = Byte Count (Low, H igh)
WD (L.H) = Write Dat a (Low, High)
16M (1M × 16/2M × 8) Flash Memory LH28F016SA
7-79
NOTES:
1. R A can be the G SR address or any BSR address. See Figure 4.1 and 4.2 for Extended Stat us Register Memory M aps.
2. Upon device power -up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the actual lock-bit
status.
3. A0 is aut omatically complem ented to load second byte of data. B Y TE# m ust be at VIL.
A0 value deter mines w h ich WD/BC is supplied first: A 0 = 0 lo oks at the WDL/BCL, A0 = 1 looks at the WDH/BCH.
4. BCH/WCH must be at 00H for this product because of the 256-Byte (128 Word) Page Buffer size and to avoid writing the Page Buffer
content s int o mor e than one 256-Byte segm ent w it hin an arr ay block. They are s im p ly shown for futur e Page Buffer expandability.
5. In ×16 mode, only the lower byte DQ0-7 is used for WCL and WCH. The upper byte DQ8-15 is a don’t care.
6. PA and PD (Whose count is given in cycles 2 and 3) are supplied star ting in the 4th cycle which is not shown.
7. T his com mand a llows the user to swap between ava ilable P age Buff ers ( 0 or 1).
8. These comm ands r econf igure RY/BY# output to one of two pulse-modes or enable and disable the RY/BY# function.
9. Write address, WA, is the Destinat ion address in the flash array which must match the Source address in the Page Buffer.
Refer to t he LH28F016SA User ’s Manual.
10. BC L = 0 0H corr esponds to a Byte count of 1. Sim il arly, WCL = 00H corr esponds to a Word count of 1.
4.5 Co mpatible S t atus Reg is ter
CSR.2-0 = RESERVED FOR FUTURE ENHANCEMENTS
These b it s are r es erv ed for futur e use: m ask them out when polling the CSR.
WSMS ESS ES DWS VPPS R R R
7 6 5 4 3 2 1 0
NOTES:
C SR .7 = WR ITE S TATE MACH IN E STATU S
1 = Ready
0 = Busy
RY/BY# output or WSMS bit must be checked to
determine completion of an operation (Erase
Suspend, Erase or Data Write) before the
appropriate Status bit (ESS, ES or DWS) is checked
for success.
C SR .6 = E RA SE-SU SPE ND S TATUS
1 = Erase Suspended
0 = Erase in Progress/Completed
C SR. 5 = E RAS E S TATUS
1 = Error in Block Erasure
0 = Successful Block Erase If DWS and ES are set to “1” during an erase
attempt, an improper command sequence was
entered. Cl ear the CS R and attempt the operation
again.
C SR .4 = D ATA-WRITE STAT US
1 = Error i n D ata Write
0 = Data Write Successful
CSR .3 = VPP STAT US
1 = VPP Low Detect, Op eration Abort
0 = VPP OK
The VPPS bit, unlike an A/D converter, does not
provide continuous indication of VPP level. The
WSM interrogates VPP’s level o nly after the Data-
Write or Erase command sequences have been
entered, and informs the system if VPP has not been
switched on. VPPS is not guaranteed to report
accurate feedback betw een VPPL and VPPH.
LH28F016SA 16M (1M × 16/2M × 8 ) F la sh Memory
7-80
4.6 Gl obal St atu s Regi ste r
NOTE:
1. When m ultiple oper ations ar e queued, checking B SR.7 on ly provides indication of completion for that particular block.
GSR.7 provides indication when all queued operat ions are com p leted.
WSMS
7 6 5 4 3 2 1 0
OSS DOS DSS QS PBAS PBS PBSS
NOTES:
GSR .7 = WR ITE S TATE MACHINE STATU S
1 = Ready
0 = Busy
[1] RY/BY# output or WSMS b it m ust be checked
to determine completion of an operation (Block
Lock, Suspend, any RY/BY# reconfiguration,
Upload Status Bits, Erase or Data Write) before
the appropriate Status bit (OSS or DOS) is
checked f o r success.
GSR.6 = OPERATION SUSPEND STATUS
1 = Operation Suspended
0 = Operation in Progress/Completed
GS R .5 = D EVIC E OPE RAT ION S TATUS
1 = Operation Unsuccessful
0 = Operation Successfu l or Currentl y R unning
GSR.4 = D EV IC E SLEEP S TATUS
1 = Device i n Sleep
0 = Device No t in Sleep
MATRIX 5/4
0 0 = Operati on Successful or Currently R unnin g
0 1 = Device i n S leep Mo de or Pending S leep
1 0 = Operation Unsuccessful
11 = Operation Unsuccessful or Aborted
I f operati on currently running, then GSR.7 = 0.
I f devi ce pendi ng sleep, then GS R.7 = 0.
Operation aborted: Unsuccessful due to Abort
command.
GSR .3 = QUE UE S TATUS
1 = Queue Full
0 = Queue Avail able
GSR .2 = PA GE BUF FER AVAILABLE S TATUS
1 = One or Two Page Buffers Available
0 = N o Page Buffer Available Th e devi ce con tai ns two Page Buffers.
GSR.1 = PA GE BU FFER S TATU S
1 = Selected Page Buffer R eady
0 = Selected Page Buffer Busy Selected Page Buf f er is current ly busy with WSM
operation.
GSR.0 = PA GE BU FFER S ELE CT S TATU S
1 = Page Buffer 1 Sel e cted
0 = Page Buffer 0 Sel e cted
16M (1M × 16/2M × 8) Flash Memory LH28F016SA
7-81
4.7 Block Status Register
NOTES:
B SR. 1-0 = RE SER VE D FOR F UT URE E NH ANC EMENT S
These b it s are r es erv ed for futur e use; m ask them out when polling the BSRs.
1. When m ultiple oper ations ar e queued, checking B SR.7 on ly provides indication of completion for that particular block.
GSR.7 provides indication when all queued operat ions are com p leted.
BOAS VPPS R R
7 6 5 4 3 2 1 0
QS
BOSBLSBS
NOTES:
B SR.7 = B LOCK STATU S
1 = Ready
0 = Busy
[1] RY/BY# outpu t or B S bit must be checked to
determine completion of an operation (Block
Lock, S uspend, E rase or D a ta W ri te) be fore the
appropriate Status bits (BOS, BLS) is checked
for success.
B SR.6 = B LOCK-LOCK STATU S
1 = Block Unl ocked for Write/E rase
0 = B lock Locked for Write/E rase
B SR.5 = B LOCK OPERAT ION S TATUS
1 = Operation Unsuccessful
0 = Operation Successfu l or Currentl y R unning
B SR.4 = B LOCK OPE RAT ION ABORT STAT US
1 = Operation Aborted
0 = Op eration Not Aborted The BOAS bi t wi ll not be set u ntil BSR .7 = 1.
MATRIX 5/4
0 0 = Operati on Successful or Currently Running
0 1 = Not a valid Combination
1 0 = Operation Unsuccessful
11 = Operation Aborted Operation halted via Abort command.
B SR.3 = QUE UE S TATUS
1 = Queue Full
0 = Queue Avail able
B SR.2 = V PP STAT US
1 = VPP Low Detect, Op eration Abort
0 = VPP OK
LH28F016SA 16M (1M × 16/2M × 8) F la sh Memory
7-82
5. 0 ELECTRICAL SPECIF IC AT IONS
5. 1 Absolut e Maximum Ratin gs *
Temperature Under Bias 0°C to + 8 0°C
Storage Temperature -6 5°C to + 125°C
* WARNING:
Str essing t he device beyond the "Absolute M aximum Ratings" may cause perm anent damage. These are stress ratings only.
O per ation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device rel iability.
VCC = 3.3 V ±0.3 V Sys tems (5)
VCC = 5.0 V ±0.5 V, VCC = 5 .0 V ±0.25 V Syste ms (5,6)
NOTES:
1. Operating temperat ure is for commer c ia l product def ined by th is specification.
2. M inimum DC voltage is - 0.5 V on input/ out put pins. During transitions, this level may undershoot to - 2.0 V for periods <20 ns. Maximum
DC voltage on input/output pins is VCC + 0.5 V wh ich, dur ing transitions, may overshoot to VCC + 2.0 V for per iods <20 ns.
3. M aximum DC voltage on VPP may ove rshoot to + 14.0 V for per iods <20 ns.
4. O utput shor ted f or no m or e than one second. No m ore than one output short ed at a time.
5. AC specifications are v alid at both voltage ranges. See D C Charact erist ics tab les f or voltage range-specif ic specifications.
6. 5% VCC specif ications ref er to the LH28F016SA-70 in its High Speed Test conf iguration.
Symbol Parameter Notes Min Max Units Test Conditions
T
A
V
CC
V
PP
I
I
OUT
V
Operating Temperature, Commercial
V
CC
with Respect to GND
V
PP
Supply Voltage with Respect to GND
Voltage on any Pin (except V
CC
, V
PP
)
with Respect to GND
Current into any Non-Supply Pin
Output Short Circuit Current
Ambient Temperature1
2
2,3
2
4
0
- 0.2
- 0.2
- 0.5
70
7.0
14.0
V
CC
+ 0.5
± 30
100
˚C
V
V
V
mA
mA
Symbol Parameter Notes Min Max Units Test Conditions
T
A
V
CC
V
PP
I
I
OUT
V
Operating Temperature, Commercial
V
CC
with Respect to GND
V
PP
Supply Voltage with Respect to GND
Voltage on any Pin (except V
CC
, V
PP
)
with Respect to GND
Current into any Non-Supply Pin
Output Short Circuit Current
Ambient Temperature1
2
2,3
2
4
0
- 0.2
- 0.2
- 2.0
70
7.0
14.0
7.0
± 30
100
˚C
V
V
V
mA
mA
16M (1M × 16/2M × 8) Flash Memory LH28F016SA
7-83
5.2 Capacitance
For a 3 .3 V System:
For a 5 .0 V System:
NOTE:
1. Sampled, not 10 0% tested.
Symbol Parameter Note Typ Max Units Test Conditions
C
IN
Capacitance Looking into an
Address/Control Pin T
A
= 25˚C, f = 1.0 MHz1 6 8 pF
C
OUT
C
LOAD
Capacitance Looking into an Output Pin
Load Capacitance Driven by Outputs
for Timing Specifications
Equivalent Testing Load Circuit
1
1
8 12
50
2.5
pF
pF
ns
T
A
= 25˚C, f = 1.0 MHz
For V
CC
= 3.3V ± 0.3V
50Ω transmission
line delay
Symbol Parameter Note Typ Max Units Test Conditions
C
IN
Capacitance Looking into an
Address/Control Pin T
A
= 25˚C, f = 1.0 MHz1 6 8 pF
C
OUT
C
LOAD
Capacitance Looking into an Output Pin 1
1
8 12
100
30
pF
pF
ns
T
A
= 25˚C, f = 1.0 MHz
For V
CC
= 5.0V ± 0.5V
25Ω transmission
line delay
Load Capacitance Driven by Outputs
for Timing Specifications
Equivalent Testing Load Circuit for
V
CC
± 10%
Equivalent Testing Load Circuit for
V
CC
± 5%
2.5
2.5 ns
pF
83Ω transmission
line delay
For V
CC
= 5.0V ± 0.25V
LH28F016SA 16M (1M × 16/2M × 8) F la sh Memory
7-84
5.3 Timing Nomenclature
A ll 3.3 V system timings are measured from where signals cross 1 .5 V.
For 5.0 V systems use the standard JEDEC cross point definitions.
E ach timing parameter con sists of 5 characters. So me common examples are defined bel ow:
tCE tELQV time(t) from CE# (E) going low (L) to the outputs (Q) becoming valid (V)
tOE tGLQV time(t) from OE# (G) going l ow (L) to the outputs (Q) becoming valid (V)
tACC tAVQV time(t) from address (A) vali d (V) to the outputs ( Q) beco ming val id (V)
tAS tAVWH time(t ) f rom address (A) val id (V) to WE# ( W) going high (H)
tDH tWHDX time(t) from WE# (W) going high (H) to w hen the data (D) can beco me undefined (X )
AC test inputs are driven at VOH (2.4 V T TL) for a Logic “1” and VOL (0. 45 V TTL) for a Logic “0. ” I nput timing begins at VIH (2. 0 VTTL) and
VIL (0. 8 VTTL). Out put t im ing ends at VIH and VIL. Input rise and fa ll t im es (10% to 90%) <10 ns.
AC test inputs are driven at 3. 0 V for a Logic “1” and 0.00 V for a Logic “0.” Input t im ing begins, and output timing e nds, at 1.5 V. I nput rise
and f all times ( 10% to 90%) <10 ns.
NOTES:
1. Testing characteristics for LH28F016SA-080/LH28F016SA-100.
2. Testing characteristics for LH28F016SA-070/LH28F016SA-120/LH28F016SA-150.
Pin Characters
Address Inputs
Pin States
A
D
Q
E
G
W
P
R
V
Y
5V
3V
H
L
V
X
Z
Data Inputs
Data Outputs
CE# (Chip Enable)
OE# (Output Enable)
WE# (Write Enable)
RP# (Deep Power-Down Pin)
RY/BY# (Ready Busy)
Any Voltage Level
3/5# Pin
V
CC
at 4.5V Minimum
V
CC
at 3.0V Minimum
High
Low
Valid
Driven, but not necessarily valid
High Impedance
TEST POINTSINPUT OUTPUT
2.0
0.8
2.0
0.8
2.4
0.45
Figure 5. Transient Input/Output Reference Waveform
(VCC = 5.0 V) for Standard Test Conf igurati on (1)
TEST POINTSINPUT OUTPUT
1.5 1.5
3.0
0.0
Figure 6. Transient Input/Output Reference Waveform
(VCC = 3. 3 V) High Speed Reference Wavef orm (2) (VCC = 5.0 V ±5%)
16M (1M × 16/2M × 8) Flash Memory LH28F016SA
7-85
From Output
Under Test Test
Point
2.5 ns of 25Ω Transmission Line
Total Capacitance = 100 pF
Figure 7. Transient Equivalent Testing Load Circuit
(VCC = 5 .0 V)
From Output
Under Test Test
Point
2.5 ns of 50Ω Transmission Line
Total Capacitance = 50 pF
Figure 8. Transient Equivalent Testing Load Circuit
(VCC = 3 .3 V)
From Output
Under Test Test
Point
2.5 ns of 83Ω Transmission Line
Total Capacitance = 30 pF
Fi gur e 9. High Speed Transi ent Equivalent Testi ng
Lo ad Circuit ( VCC = 5.0 V ±5%)
LH28F016SA 16M (1M × 16/2M × 8) F la sh Memory
7-86
5.4 DC Ch ara cteristics
VCC = 3.3 V ±0.3 V, TA = 0°C to + 7 0°C
3/5# = Pi n Se t Hi gh for 3.3 V Operations
Symbol Parameter Notes Typ Max Units Test Conditions
I
IL
V
CC
= V
CC
Max, V
IN
= V
CC
or GND1 ± 1 µA
Min
Input Load Current
I
LO
Output Leakage
Current 1 ± 10 µA V
CC
= V
CC
Max, V
IN
= V
CC
or GND
V
CC
= V
CC
Max,
CE
0
#, CE
1
#, RP# = V
CC
± 0.2V
BYTE#, WP#, 3/5# = V
CC
±
0.2V or GND ± 0.2V
V
CC
= V
CC
Max,
CE
0
#, CE
1
#, RP# = V
IH
BYTE#, WP#, 3/5# = V
IH
or V
IL
501,5 100 µA
mA41
I
CCS
V
CC
Standby Current
I
CCD
V
CC
Deep Power-Down
Current 1 1 5 µA RP# = GND ± 0.2V
V
CC
= V
CC
Max,
CMOS: CE
0
#, CE
1
# = GND ± 0.2V
BYTE# = GND ± 0.2V or V
CC
± 0.2V
Inputs = GND ± 0.2V or V
CC
± 0.2V,
TTL: CE
0
#, CE
1
# = V
IL
,
BYTE# = V
IL
or V
IH
Inputs = V
IL
or V
IH
,
f = 8 MHz, I
OUT
= 0 mA
I
CCR
1 V
CC
Read Current 1,4,5 30 35 mA
V
CC
= V
CC
Max,
CMOS: CE
0
#, CE
1
# = GND ± 0.2V,
BYTE# = V
CC
± 0.2V or GND ± 0.2V
Inputs = GND ± 0.2V or V
CC
± 0.2V,
TTL: CE
0
#, CE
1
# = V
IL
BYTE# = V
IH
or V
IL
Inputs = V
IL
or V
IH
,
f = 4 MHz, I
OUT
= 0 mA
I
CCR
2 V
CC
Read Current 1,4,5 15 20 mA
I
CCW
V
CC
Write Current 1 8 12 mA Word/Byte Write in
Progress
I
CCE
V
CC
Block Erase
Current
I
CCES
V
CC
Erase Suspend
Current
I
PPS
V
PP
Standby Current
I
PPD
V
PP
Deep Power-Down
Current
1
1,2
1
1
6
3
± 1
0.2
12
6
± 10
5
mA
mA
µA
µA
Block Erase in Progress
CE
0
#, CE
1
# =V
IH
Block Erase Suspended
V
PP
< V
CC
RP# = GND ± 0.2V
16M (1M × 16/2M × 8) Flash Memory LH28F016SA
7-87
5. 4 DC Chara cteristics (Continued)
VCC = 3.3 V ±0.3 V, TA = 0°C to + 7 0°C
3/5# = Pi n Se t Hi gh for 3.3 V Operations
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 3. 3 V, VPP = 12.0 V, T = 25°C. These currents are valid for all
product versions ( package and speeds).
2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of ICCES and
ICCR.
3. B lock Erases, Word/Byte Writes, and Lock Block operations are inhib ited when VPP = VPPL an d not guarant eed i n the r a nge between VPPH
and VPPL.
4. Automatic Power Saving (APS) reduces ICCR to less than 1 mA in st atic oper at ion.
5. CMO S Inputs are either VCC ±0.2 V or GND ±0.2 V. T TL I nputs are either VIL or VIH.
Symbol Parameter Notes Typ Max Units Test Conditions
I
PPR
V
PP
> V
CC
1 200 µA
Min
V
PP
Read Current
I
PPW
V
PP
Write Current 1 15 V
PP
= V
PPH
,
Word/Byte Write in Progress
V
PP
= V
PPH
,
Block Erase in Progress
41 10
200
I
PPE
V
PP
Erase Current
V
IL
Input Low Voltage - 0.3
2.0
0.4
V
I
OH
= - 2.0 mA
V
CC
= V
CC
Min
11.4 12.6
10 mA
mA
I
PPES
V
PP
Erase Suspend
Current 1 µA V
PP
= V
PPH
,
Block Erase Suspended
V
IH
Input High Voltage
0.8
V
CC
+ 0.3
V
V
OL
Output Low Voltage V V
CC
= V
CC
Min and
I
OL
= 4 mA
V
OH
1 Output High Voltage 2.4 V
V
OH
2 V
CC
- 0.2 I
OH
= - 100 µA
V
CC
= V
CC
Min
V
PP
L V
PP
during Normal
Operations 3 0.0 6.5 V
V
PP
H V
PP
during Write/
Erase Operations
V
LK
O V
CC
Erase/Write
Lock Voltage 2.0
V
V
12.0
LH28F016SA 16M (1M × 16/2M × 8) F la sh Memory
7-88
5.5 DC Ch ara cteristics
VCC = 5.0 V ±0.5 V, TA = 0°C to + 7 0°C
3/5# Pin Se t Low for 5 V Operations
Symbol Parameter Notes Typ Max Units Test Conditions
I
IL
V
CC
= V
CC
Max
V
IN
= V
CC
or GND
1 ± 1 µA
Min
Input Load
Current
I
LO
Output Leakage
Current 1 ± 10 µA V
CC
= V
CC
Max
V
IN
= V
CC
or GND
V
CC
= V
CC
Max
CE
0
#, CE
1
#, RP# = V
CC
± 0.2V
BYTE#, WP#, 3/5# = V
CC
± 0.2V
or GND ± 0.2V
V
CC
= V
CC
Max
CE
0
#, CE
1
#, RP# = V
IH
BYTE#, WP#, 3/5# = V
IH
or V
IL
501,5 100 µA
mA42
I
CCS
V
CC
Standby
Current
I
CCD
V
CC
Deep
Power-Down
Current
1 1 5 µA RP# = GND ± 0.2V
V
CC
= V
CC
Max,
CMOS: CE
0
#, CE
1
# = GND ± 0.2V
BYTE# = GND ± 0.2V or V
CC
± 0.2V
Inputs = GND ± 0.2V or V
CC
± 0.2V,
TTL: CE
0
#, CE
1
# = V
IL
,
BYTE# = V
IL
or V
IH
Inputs = V
IL
or V
IH
,
f = 10 MHz, IOUT = 0 mA
I
CCR
1 V
CC
Read
Current 1,4,5 50 60 mA
V
CC
= V
CC
Max,
CMOS: CE
0
#, CE
1
# = GND ± 0.2V
BYTE# = V
CC
± 0.2V or GND ± 0.2V
Inputs = GND ± 0.2V or V
CC
± 0.2V
TTL: CE
0
#, CE
1
# = V
IL
,
BYTE# = V
IH
or V
IL
,
Inputs = V
IL
or V
IH
,
f = 5 MHz, IOUT = 0 mA
I
CCR
2 V
CC
Read
Current 1,4,5 30 35 mA
I
CCW
V
CC
Write
Current 1 25 35 mA Word/Byte in Progress
I
CCE
V
CC
Block
Erase Current
I
CCES
V
CC
Erase
Suspend Current
I
PPS
V
PP
Standby
Current
1
1,2
1
18
5
25
10
± 10
mA
mA
µA
Block Erase in Progress
CE
0
#, CE
1
# =V
IH
Block Erase Suspended
V
PP
< V
CC
16M (1M × 16/2M × 8) Flash Memory LH28F016SA
7-89
5. 5 DC Chara cteristics (Continued)
VCC = 5.0 V ±0.5 V, TA = 0°C to + 7 0°C
3/5# Pin Se t Low for 5 V Operations
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5. 0 V, VPP = 12.0 V, T = 25°C. These currents are valid for all
product versions ( package and speeds).
2. ICCES is specified wit h t he device deselect ed. I f the device is read whi le in erase suspend m ode, current draw is t he sum of ICCES and ICCR.
3. B lock Erases, Word/Byte Writes, and Lock Block operations are inhib ited when VPP = VPPL an d not guarant eed i n the r a nge between VPPH
and VPPL.
4. Automatic Power Saving (APS) reduces ICCR to less than 2 mA in Stat ic operat ion.
5. CMO S Inputs are either VCC ±0.2 V or GND ±0.2 V. T TL I nputs are either VIL or VIH.
Symbol Parameter Notes Typ Max Units Test Conditions
IPPR VPP > VCC
1 200 µA
Min
VPP Read Current
IPPW VPP Write Current 1 12 V PP = VPPH
Word/Byte Write in Progress
VPP = VPPH
Block Erase in Progress
51 10
200
IPPE VPP Block Erase
Current
VIL Input Low Voltage - 0.5
2.0
0.45
V
IOH = - 2.5 mA
VCC = VCC Min
11.4 12.6
7 mA
mA
IPPES VPP Erase Suspend
Current 1 µA V PP = VPPH
Block Erase Suspended
VIH Input High Voltage
0.8
VCC + 0.5
V
VOL Output Low Voltage V V CC = VCC Min
IOL = 5.8 mA
VOH1 Output High Voltage 0.85
VCC V
VOH2 V CC - 0.4 IOH = - 100 µA
VCC = VCC Min
VPPL VPP during Normal
Operations 3 0.0 6.5 V
VPPH VPP during Erase/
Write Operations
VLKO VCC Erase/Write
Lock Voltage 2.0
V
V
12.0
IPPD VPP Deep Power-
Down Current 1 0.2
65
5 µA RP# = GND ± 0.2V
65
LH28F016SA 16M (1M × 16/2M × 8) F la sh Memory
7-90
5.6 AC Characteristics - Read On ly Op eratio ns (1)
VCC = 3.3 V ±0.3 V, TA = 0°C to +70°C
Symbol Parameter Notes
LH28F016SA-150LH28F016SA-120 Units
Min
t
AVAV
Read Cycle Time
MaxMax Min
Versions
(5)
120 150 ns
t
AVEL
Address Setup to
CE# Going Low
t
AVGL
Address Setup to
OE# Going Low
t
AVQV
Address to Output Delay
t
ELQV
CE# to Output Delay
t
PHQV
RP# High to Output Delay
t
GLQV
OE# to Output Delay
t
ELQX
CE# to Output in Low Z
t
EHQZ
CE# to Output in High Z
t
GLQX
OE# to Output in Low Z
t
GHQZ
OE# to Output in High Z
t
OH
Output Hold from Address,
CE# or OE# Change,
Whichever Occurs First
t
FLQV
t
FHQV
BYTE# to Output Delay
t
FLQZ
BYTE# Low to Output
in High Z
t
ELFL
t
ELFH
CE# Low to BYTE#
High or Low
3,4
3,4
2
2
3
3
3
3
3
3
3
3
10
0
0
0
0
120
120
620
45
50
30
120
30
5
0
10
0
0
0
150
150
750
50
55
40
150
40
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
16M (1M × 16/2M × 8) Flash Memory LH28F016SA
7-91
5.6 AC Characteristics - Read On ly Op eratio ns (1) (Continued)
VCC = 5.0 V ±0.5 V, TA = 0°C to +70°C
NOTES:
1. See A C Input/ Output R ef erence Wavefor ms f or timing measurement s, F igures 5 and 6.
2. O E# may be d elayed up to tELQV - t GLQV aft er the f allin g edge of CE # without im pact on tELQV.
3. Sampled, not 1 00% teste d.
4. This timing parameter is used t o lat ch the correct BSR data onto the outputs.
5. Device Speeds are defined as:
70/ 80 ns at VCC = 5.0 V equivalent to 120 ns at VCC = 3.3 V
100 ns at VCC = 5. 0 V equivalent to 150 ns at VCC = 3.3 V
6. See A C Input/Output Reference Waveform s and AC Testing Load C ir cuits f or H igh S peed Test Configur ation.
7. See Standard A C Input/O utput Refer ence Wavef orms and A C Testing Load Circuit.
Symbol Parameter
LH28F016SA-070
(6)
Units
Min
t
AVAV
Read Cycle Time
MaxMax Min
Versions
(5)
70 ns
Address Setup
to CE# Going
Low
3,4 10
VCC ± 5%
VCC ± 10%
Notes
LH28F016SA-080
(7)
LH28F016SA-100
(6)
MaxMin
t
AVEL
10
80 100
t
AVGL
Address Setup
to OE# Going
Low
3,4 0 0 0
ns
ns
10
t
AVQV
Address to
Output Delay 70 80 100 ns
t
ELQV
CE# to Output
Delay 2 70 80 100 ns
t
PHQV
t
GLQV
t
ELQX
t
EHQZ
t
GLQX
t
GHQZ
t
OH
t
ELQV
t
FHQV
t
FLQZ
t
ELFL
t
ELFH
RP# to Output
Delay
OE# to Output
Delay
CE# to Output
in Low Z
CE# to Output
in High Z
OE# to Output
in Low Z
OE# to Output
in High Z
Output Hold
from Address,
CE# or OE#
Change,
Whichever
Occurs First
BYTE# to
Output Delay
BYTE# Low to
Output in High Z
CE# Low to
BYTE# High or
Low
2
3
3
3
3
3
3
3
3
0
0
0
400
30
25
25
25
70
5
0
0
0
480
35
30
30
80
30
5
0
0
0
550
40
35
35
100
30
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LH28F016SA 16M (1M × 16/2M × 8) F la sh Memory
7-92
V
CC
POWER-UP STANDBY DEVICE AND
ADDRESS SELECTION OUTPUTS ENABLED DATA VALID V
CC
POWER-DOWN
STANDBY
ADDRESSES (A) V
IL
CEx# (E) (1)
OE# (G)
WE# (W)
DATA (D/Q)
RP# (P)
V
CC
HIGH Z
t
AVAV
t
EHQZ
t
GHQZ
t
OH
t
GLQV
t
ELQV
t
GLQX
t
ELQX
t
AVQV
t
PHQV
VALID OUTPUT
V
IH
ADDRESSES STABLE
t
AVEL
t
AVGL
V
OL
V
OH
GND
5.0 V
V
IL
V
IH
NOTE: CE
X
# is defined as the latter of CE
0
# or CE
1
# going Low or the first of CE
0
# or CE
1
# going High.
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
HIGH Z
Figure 10. Read Timing Waveforms
16M (1M × 16/2M × 8) Flash Memory LH28F016SA
7-93
ADDRESSES (A)
DATA (DQ8 - DQ15)
CEx# (E)(1)
OE# (G)
BYTE# (F)
DATA (DQ0 - DQ7) HIGH Z HIGH Z
t
AVAV
t
EHQZ
t
OH
ADDRESSES STABLE
t
GHQZ
V
OL
V
OH
t
AVFL
= t
ELFL
t
AVEL
t
ELFL
t
AVGL
t
FLQV
= t
AVQV
t
GLQV
t
ELQV
t
GLQX
t
ELQX
t
AVQV
DATA
OUTPUT
t
FLQZ
HIGH Z
DATA
OUTPUT
DATA
OUTPUT
HIGH Z
V
OL
V
OH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
NOTE: CE
X
# is defined as the latter of CE
0
# or CE
1
# going Low or the first of CE
0
# or CE
1
# going High.
Figure 11. BYTE# Timing Waveforms
LH28F016SA 16M (1M × 16/2M × 8) Fla sh Memory
7-94
5. 7 Power-Up and Reset Ti mings
NOTES:
CE0#, CE1#, and OE# ar e switched lo w after Power-Up.
1. M inimum of 2 µs is r equired t o meet the specified tPHQV times.
2. The po wer supply may start t o s witch concurrent ly w it h RP# going L ow.
3. The address access time and RP# high to data valid time are shown for 5 V VCC operat ion. Refer t o the AC Characteristics Read Only
Operations 3.3 V VCC operat ion and al l other speed options.
V
CC
POWER UP
RP#
(P)
3/5#
(Y)
VCC
(3V, 5V)
Address
(A)
Data
(Q)
t
YHPH
t
YLPH
5.0V
4.5V
t
PL5V
t
PLYL
3.3V
0V
VALID VALID
t
AVQV
t
AVQV
VALID
3.3V OUTPUTS VALID
5.0V OUTPUTS
t
PHQV
t
PHQV
Figure 12. VCC Power-Up and RP# Reset Waveforms
Symbol Parameter
RP# Low to 3/5 # Low (High)
3/5# Low (High) to RP # High
RP# Low to V
CC
at 4.5V Minimum
(to V
CC
at 3.0V min or 3.6V max)
Address Valid to Data Valid
for V
CC
= 5V ± 10%
RP# High to Data Valid for
V
CC
= 5V ± 10%
Note Min
0
2
0
Max
80
480
Unit
µs
µs
µs
ns
ns
1
2
3
3
t
PLYL
t
PLYH
t
YLPH
t
YHPH
t
PL5V
t
PL3V
t
AVQV
t
PHQV
16M (1M × 16/2M × 8) Flash Memory LH28F016SA
7-95
5.8 AC Ch ara cteristics for WE # - Con t ro lled Co m mand Write Operati ons (1)
VCC = 3.3 V ±0.3 V, TA = 0°C to + 7 0°C
Symbol Parameter Notes
LH28F016SA-150LH28F016SA-120 Unit
t
AVAV
Write Cycle Time
MaxMax Min
Versions
120 150 ns
t
VPWH
V
PP
Setup to WE# Going High
t
PHEL
RP# Setup to CE# Going Low
t
ELWL
CE# Setup to WE# Going Low
t
AVWH
Address Setup to WE#
Going High
t
DVWH
Data Setup to WE# Going High
t
WLWH
WE# Pulse Width
t
WHDX
Data Hold from WE# High
t
WHAX
Address Hold from WE# High
t
WHEH
CE# Hold from WE# High
t
WHEL
WE# Pulse Width High
t
GHWL
Read Recovery before Write
t
WHRL
WE# High to RY/BY# Going Low
t
RHPL
RP# Hold from Valid Status
Register (CSR, GSR, BSR) Data
and RY/BY# High
t
PHWL
RP# High Recovery to
WE# Going Low
t
WHGL
Write Recovery before Read
t
QVVL
V
PP
Hold from Valid Status
Register (CSR, GSR, BSR) Data
and RY/BY# High
t
WHQV
2 Duration of Block
Erase Operation
t
WHQV
1 Duration of Word/Byte
Write Operation
TypTypMin
3
2,6
2,6
2
2
3
4,5
4
100
480
10
75
75
75
10
10
10
45
0
0
1
95
0
5
0.3
100 100
9 9
0.3
5
0
120
1
0
0
75
10
10
10
75
75
75
10
480
100 ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
µs
s
LH28F016SA 16M (1M × 16/2M × 8) F la sh Memory
7-96
AC Characteristics for WE # - Cont ro lled Co mmand Write Operations (1) (Continued)
VCC = 5.0 ±0.5 V, TA = 0°C to + 70°C
NOTES:
CE # is def ined as the lat ter of C E0# o r CE 1# going Low or the first of CE0# or CE1# going High.
1. Read timing during write and er ase are the sam e as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% t ested.
4. Write/Erase durations are measured to v alid Stat us Regist er (CSR) Data.
5. Wor d/Byte write operat ions are t ypically perf ormed w it h 1 Program ming Pulse.
6. Address and Data are latched on the rising edge of WE# for a ll Command Write operat ions.
Symbol Parameter Notes
LH28F016SA-100LH28F016SA-080 Unit
tAVAV Write Cycle Time
Versions
3
ns
ns
tVPWH
MaxTypMin MaxTypMin MaxTypMin
LH28F016SA-070VCC ± 5%
VCC ± 10%
VPP Setup to WE# Going
High
tPHEL RP# Setup to CE# Going
Low
tELWL CE# Setup to WE#
Going Low
tAVWH Address Setup to WE#
Going High
tWLWH WE# Pulse Width
tWHDX
Data Hold from WE# High
tWHAX Address Hold from WE#
High
tWHEH
CE# Hold from WE# High
tWHWL WE# Pulse Width High
tGHWL Read Recovery before
Write
tWHRL WE# High to RY/BY#
Going Low
tRHPL RP# Hold from Valid
Status Register (CSR,
GSR, BSR) Data and
RY/BY# High
tWHQV2 Duration of Block Erase
Operation
tPHWL RP# High Recovery to
WE# Going Low
tWHGL Write Recovery before
Read
tQVVL
V
PP
Hold from Valid Status
Register (CSR, GSR, BSR)
Data and RY/BY# High
tWHQV1 Duration of Word/Byte
Write Operation
tDVWH Data Setup to WE#
Going High
2,6
2,6
2
2
3
4,5
4
70
100
480
0
50
50
40
0
10
10
30
0
0
1
60
0
4.5
0.3
6
100
0.3
4.5 6
0
65
1
0
100
0
30
10
10
0
50
50
50
0
480
100
80 100
100
480
0
50
50
50
0
10
10
50
0
100
0
1
80
0
4.5
0.3
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
µs
s
16M (1M × 16/2M × 8) Flash Memory LH28F016SA
7-97
NOTES:
1. This address string depict s Data-Write/Erase cycles with corresponding verif icat ion via E SRD.
2. This address string depict s Data-Write/Erase cycles with corresponding verif icat ion via CS RD.
3. This cycle is invalid when using C SRD for verif icat ion during Dat a-Write/Erase operat ions.
4. CEX# is def ined as the latter of CE0# or CE1# going Low or the first of C E0# or CE1# going High.
5. RP # low tr ansition is only t o show t RHPL; not valid for above Read and Write cycles.
ADDRESSES (A)
NOTE 1
VPP (V)
AIN A=RA
A=RA
READ COMPATIBLE
STATUS REGISTER DATA
NOTE 3
NOTE 5
DEEP
POWER-DOWN WRITE DATA-WRITE OR
ERASE SETUP COMMAND
WRITE VALID ADDRESS
& DATA (DATA-WRITE) OR
ERASE CONFIRM COMMAND
AUTOMATED DATA-WRITE
OR ERASE DELAY WRITE READ EXTENDED
REGISTER COMMAND READ EXTENDED
STATUS REGISTER DATA
VIH
VIH
VIH
VIH
VIH
VIH
VOH
VOL
VIH
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VPPH
VPPL
VIH
VIL
RP# (P)
RY/BY# (R)
DATA (D/Q)
WE# (W)
OE# (G)
CEx# (E)
NOTE 4
ADDRESSES (A)
NOTE 2
tAVAV tAVWH tWHAX
tAVAV tAVWH tWHAX
tELWL
tWHGL
tGHWL
tWHQV 1, 2
tWHWL
tWLWH
tWHDX
DIN DIN
tDVWH
HIGH Z
tPHWL
tWHRL
DIN DOUT DIN
tVPWH tQVVL
tRHPL
tWHEH
AIN
Figu re 13. AC Waveforms for Command Write Operations
LH28F016SA 16M (1M × 16/2M × 8) F la sh Memory
7-98
5. 9 AC Chara cteristics for CE# - Controll ed Comma nd Wr ite Operations (1)
VCC = 3.3 V ±0.3 V, TA = 0°C to 70°C
Symbol Parameter Notes
LH28F016SA-150LH28F016SA-120 Unit
t
AVAV
Write Cycle Time
MaxMax Min
Versions
120 150 ns
t
PHWL
RP# Setup to WE# Going Low
t
VPEH
V
PP
Setup to CE# Going High
t
WLEL
WE# Setup to CE# Going Low
t
AVEH
Address Setup to
CE# Going High
t
DVEH
Data Setup to CE# Going High
t
ELEH
CE# Pulse Width
t
EHDX
Data Hold from CE# High
t
EHAX
Address Hold from CE# High
t
EHWH
WE# Hold from CE# High
t
EHEL
CE# Pulse Width High
t
GHEL
Read Recovery before Write
t
EHRL
CE# High to RY/BY# Going Low
t
RHPL
RP# Hold from Valid Status
Register (CSR, GSR, BSR) Data
and RY/BY# High
t
PHEL
RP# High Recovery to
CE# Going Low
t
EHGL
Write Recovery before Read
t
QVVL
VPP Hold from Valid Status
Register (CSR, GSR, BSR) Data
and RY/BY# High
t
EHQV
2 Duration of Block
Erase Operation
t
EHQV
1 Duration of Word/Byte
Write Operation
TypTypMin
3
2,6
2,6
2
2
3
4,5
4
480
100
0
75
75
75
10
10
10
45
0
0
1
95
0
5
0.3
100 100
9 9
0.3
5
0
120
1
0
0
75
10
10
10
75
75
75
0
100
480 ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
µs
s
0
16M (1M × 16/2M × 8) Flash Memory LH28F016SA
7-99
AC Characteristics for CE# - Controlled Command Write Operations (1) (Continued)
VCC = 5.0 V ±0.5 V, TA = 0°C to 70°C
NOTES:
CE # is def ined as the lat ter of C E0# o r CE 1# going Low or the first of CE0# or CE1# going High.
1. Read timing during write and er ase are the sam e as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% t ested.
4. Write/Erase durations are measured to v alid Stat us Dat a.
5. Word/ Byt e write operations are t ypically perf ormed w ith 1 Programm ing P ulse.
6. Address and Data are latched on the rising edge of CE# for al l Comm and Wr ite Operat ions.
Symbol Parameter Notes
LH28F016SA-100LH28F016SA-080 Unit
tAVAV Write Cycle Time
Versions
3
ns
ns
tPHWL
MaxTypMin MaxTypMin MaxTypMin
LH28F016SA-070VCC ± 5%
VCC ± 10%
RP# Setup to WE#
Going Low
tVPEH VPP Setup to CE#
Going High
tWLEL WE# Setup to CE#
Going Low
tAVEH Address Setup to CE#
Going High
tELEH CE# Pulse Width
tEHDX
Data Hold from CE# High
tEHAX Address Hold from CE#
High
tEHWH
WE# Hold from CE# High
tEHEL CE# Pulse Width High
tGHEL Read Recovery before
Write
tEHRL CE# High to RY/BY#
Going Low
tRHPL RP# Hold from Valid
Status Register (CSR,
GSR, BSR) Data and
RY/BY# High
tEHQV2 Duration of Block Erase
Operation
tPHEL RP# High Recovery to
CE# Going Low
tEHGL Write Recovery before
Read
tQVVL
V
PP
Hold from Valid Status
Register (CSR, GSR, BSR)
Data and RY/BY# High
tEHQV1 Duration of Word/Byte
Write Operation
tDVEH Data Setup to CE#
Going High
2,6
2,6
2
2
3
4,5
4
70
480
100
0
50
50
40
0
10
10
30
0
0
1
60
0
4.5
0.3
6
100
0.3
4.5 6
0
65
1
0
100
0
30
10
10
0
50
50
50
0
100
480
80 100
480
100
0
50
50
50
0
10
10
50
0
100
0
1
80
0
4.5
0.3
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
µs
s
3
LH28F016SA 16M (1M × 16/2M × 8) F la sh Memory
7-100
NOTES:
1. This address string depict s Data-Write/Erase cycles with corresponding verif icat ion via E SRD.
2. This address string depict s Data-Write/Erase cycles with corresponding verif icat ion via CS RD.
3. This cycle is invalid when using C SRD for verif icat ion during Dat a-Write/Erase operat ions.
4. CEX# is def ined as the latter of CE0# or CE1# going Low or the first of C E0# or CE1# going High.
5. RP # low tr ansition is only t o show t RHPL; not valid for above Read and Write cycles.
WE# (W)
CEx# (E)
NOTE 4
ADDRESSES (A)
NOTE 1
VPP (V)
AIN A=RA
READ COMPATIBLE
STATUS REGISTER DATA
NOTE 3
NOTE 5
DEEP
POWER-DOWN WRITE DATA-WRITE OR
ERASE SETUP COMMAND
WRITE VALID ADDRESS
& DATA (DATA-WRITE) OR
ERASE CONFIRM COMMAND
AUTOMATED DATA-WRITE
OR ERASE DELAY WRITE READ EXTENDED
REGISTER COMMAND READ EXTENDED
STATUS REGISTER DATA
VIH
VIH
VIH
VIH
VIH
VIH
VOH
VOL
VIH
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VPPH
VPPL
VIH
VIL
RP# (P)
RY/BY# (R)
DATA (D/Q)
OE# (G)
ADDRESSES (A)
NOTE 2
tAVAV tAVEH tEHAX
tAVAV tAVEH tEHAX
tWLEL
tEHGL
tGHEL
tEHQV 1, 2
tEHEL
tEHDX
DIN DIN
HIGH Z
tPHEL
tEHRL
DIN DOUT DIN
tVPEH tQVVL
tRHPL
tEHWH
tELEH
tDVEH
AIN
Figure 14. Alter nat e AC Waveforms for
Command Write Operations
16M (1M × 16/2M × 8) Flash Memory LH28F016SA
7-101
5.10 AC Characteristics for Page Buffer Write Operations (1)
VCC = 3.3 V ±0.3 V, TA = 0°C to + 70°C
VCC = 5.0 V ±0.5 V, TA = 0°C to + 70°C
NOTES:
CE # is def ined as the lat ter of C E0# o r CE 1# going Low or the first of CE0# or CE1# going High.
1. These are WE#-controlled write timings, equivalent C E#-cont rolled write timings appl y.
2. Sampled, but not 100% t ested.
3. Address m ust be valid during the entire WE# Low pulse.
Symbol Parameter Notes
LH28F016SA-150LH28F016SA-120 Unit
t
AVAV
Write Cycle Time
MaxMax Min
Versions
120 150 ns
t
ELWL
CE# Setup to WE# Going Low
t
AVWL
Address Setup to WE# Going Low
t
DVWH
Data Setup to WE# Going High
t
WLWH
WE# Pulse Width
t
WHDX
Data Hold from WE# High
t
WHAX
Address Hold from WE# High
t
WHEH
CE# Hold from WE# High
t
WHWL
WE# Pulse Width High
t
GHWL
Read Recovery before Write
t
WHGL
Write Recovery before Read
TypTypMin
3
2
2
10
0
75
75
10
10
10
45
0
95 120
0
75
10
10
10
75
50
0
10 ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
Symbol Parameter Notes
LH28F016SA-100LH28F016SA-070 Unit
tAVAV Write Cycle Time
MaxMin
Versions
80 100 ns
tELWL CE# Setup to
WE# Going Low
Typ
0 0 ns
MaxTypMinMaxTypMin
LH28F016SA-080
tAVWL Address Setup to
WE# Going Low
tDVWH Data Setup to
WE# Going High
tWLWH WE# Pulse Width
tWHDX Data Hold from
WE# High
tWHGL Write Recovery
before Read
tWHAX Address Hold
from WE# High
tWHEH CE# Hold from
WE# High
tWHWL WE# Pulse Width
High
tGHWL Read Recovery
before Write
3
2
2
2
70
0
0
50
40
0
10
10
30
0
60
0
50
50
0
10
10
30
0
65
0
50
50
0
10
10
50
0
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
LH28F016SA 16M (1M × 16/2M × 8) F la sh Memory
7-102
t
ELWL
t
WHEH
t
AVWL
t
WLWH
t
WHWL
t
WHAX
t
WHDX
t
DVWH
D
IN
VALID
HIGH Z
CEx#
(E)
WE#
(W)
ADDRESSES
DATA
(D/Q)
Figure 15. Page Buffer Write Timing Waveforms
16M (1M × 16/2M × 8) Flash Memory LH28F016SA
7-103
5.11 Erase and W ord/Byte Write Performance (3)
VCC = 3.3 V ±0.3 V, TA = 0°C to + 70°C
VCC = 5.0 V ±0.5 V, TA = 0°C to + 70°C
NOTES:
1. 25°C, VPP = 12.0 V.
2. Excludes System -Level Overhead.
3. These perf ormance numbers are valid for all speed versions.
Symbol Parameter Notes Units
t
WHRH
1 Word/Byte Write Time 9 µs
MaxTyp(1)
Min
2
t
WHRH
2 Block Write Time
t
WHRH
3 Block Write Time
Block Erase Time
Full Chip Erase Time
Test Conditions
2
2
2
2
0.6
0.3
0.8
25.6
2.1
1.0
10
s
s
s
s
Byte Write Mode
Word Write Mode
Symbol Parameter Notes Units
t
WHRH
1 Word/Byte Write Time 6 µs
MaxTyp(1)
Min
2
t
WHRH
2 Block Write Time
t
WHRH
3 Block Write Time
Block Erase Time
Full Chip Erase Time
Test Conditions
2
2
2
2
0.4
0.2
0.6
19.2
2.1
1.0
10
s
s
s
s
Byte Write Mode
Word Write Mode
LH28F016SA 16M (1M × 16/2M × 8) F la sh Memory
7-104
PACKAGE DIAGRAM
ORD ERING INFORMATION
56
P-0.5TYP.
40-0.2
29
28
0.08
0.10
1
0.125
1.19 MAX.
M
+0.08
–0.08
14.0
+0.2
–0.2
20.0
+0.3
–0.3
18.4
+0.2
–0.2
19.0
+0.3
–0.3
0.125
+0.05
–0.05
PACKAGE BASE PLANE
0.435
+0.05
–0.05
0.995
+0.1
–0.1
0.115
+0.1
–0.1
56- Lead TSO P (Type I )
56-pin TSOP (Type I)
LH28F016SA
Device Type T
Package
FLASH-2
Example: LH28F016SAT-70 (16M Dual Volt (5/12) Flash Memory, 70 ns, 56-pin TSOP (Type I))
16M Dual Volt (5/12) Flash Memory
-##
Speed
70 ns, 5 V Read
100 ns, 5 V Read
120 ns, 3.3 V Read
150 ns, 3.3 V Read
16M (1M × 16/2M × 8) Flash Memory LH28F016SA
7-105
