Copyright ANPEC Electronics Corp.
Rev. A.6 - Dec., 2011 www.anpec.com.tw1
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Stereo Cap-Free Line Driver
APA2174
FeaturesGeneral Description
Applications
•Set-Top Boxes
•CD / DVD Players
•LCD TVs
•HTIBs (Home Theater in Box)
•Operating Voltage: 2.3V-4.5V
•Supply Current
- IDD=5mA at VDD=3.3V
•Low Shutdown Current
- IDD=1µA at VDD=3.3V
•Ground Reference Output
- No Output Capacitor Required (for DC Blocking)
- Save the PCB Space
- Reduce the BOM Costs
- Improve the Low Frequency Response
•Output Voltage Swing Can Reach 2Vrms/Ch into
600Ω at VDD=3.3V
•High PSRR: 90dB at 217Hz
•Fast Start-Up Time: 500µs
•Integrate the De-pop Circuitry
•Separate Shutdown Function for Flexible Applica-
tion
•Thermal Protection
•Surface-Mount Packaging
- TQFN4x4-20B (with Enhanced Thermal Pad)
- TSSOP-16
- SOP-14
•Lead Free and Green Devices Available
(RoHS Compliant)
Simplified Application Circuit
The APA2174 is a stereo, single supply and cap-free line
driver, which is available in TQFN4x4-20B, TSSOP-16,
and SOP-14 packages.
The APA2174 is a ground-reference output and doesn’t
need the output capacitors for DC blocking. The advan-
tages of eliminating the output capacitor are saving the
cost, eliminating component height, and improving the
low frequency response.
The external gain setting is recommended using from
-1V/V to -10V/V. High PSRR provides increased immunity
to noise and RF rectification. The independent shutdown
control of APA2174 is for right channel and left channel.
The APA2174 is capable of driving 2Vrms at 3.3V into
600Ω load, and provides thermal protection.
APA2174 ROUT
RIN
RSD
LIN
LOUT
LSD
Stereo
Input
Signal
Shutdown
Control
Stereo
Line-Out
Signal
Copyright ANPEC Electronics Corp.
Rev. A.6 - Dec., 2011 www.anpec.com.tw2
APA2174
Ordering and Marking Information
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Pin Configuration
APA2174
9 LOUT
10 VDD
11 ROUT
12 LIN
13 RSD
14 RIN
15 GND
16 LSD
PVDD 2
NC 3
CPP 4
PGND 5
CPN 6
CVSS 7
VSS 8
NC 1
=ThermalPad (connected the ThermalPad
to GND plane for better heat dissipation)
TSSOP-16
(Top View)
TQFN4x4-20B
(Top View)
SOP-14
(Top View)
APA2174
GND 17
LSD 18
PVDD 19
NC 20
NC 16
6 NC
7 VSS
8 NC
9 LOUT
10 VDD
CPP 1
PGND 2
CPN 3
NC 4
CVSS 5
15 RIN
14 RSD
13 LIN
12 NC
11 ROUT
CVSS 6
VSS 78 LOUT
9 VDD
CPP 3
PGND 4
CPN 5
10 ROUT
11 LIN
12 RSD
13 RIN
14 GND
LSD 1
PVDD 2
APA2174
APA2174 Package Code
QB : TQFN4x4-20B O : TSSOP-16 K : SOP-14
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
Assembly Material
Handling Code
Temperature Range
Package Code
APA2174 QB :APA2174
XXXXX XXXXX - Date Code
APA2174 O :APA2174
XXXXX XXXXX - Date Code
XXXXX - Date Code
APA2174 K :APA2174
XXXXX
Copyright ANPEC Electronics Corp.
Rev. A.6 - Dec., 2011 www.anpec.com.tw3
APA2174
Absolute Maximum Ratings (Note 1)
Symbol Parameter Rating Unit
VPVDD_VDD PVDD to VDD Voltage -0.3 to 0.3
VPGND_GND PGND to GND Voltage -0.3 to 0.3
VDD Supply Voltage (VDD and PVDD to GND and PGND) -0.3 to 5.5
V
Vcontrol Input Voltage (RSD and LSD to GND) GND-0.3 to VDD+0.3
VSS VSS and CVSS to GND and PGND Voltage -5.5 to 0.3
VOUT ROUT and LOUT to GND Voltage VSS-0.3 to VDD+0.3
VCPP CPP to PGND Voltage PGND-0.3 to VDD+0.3
VCPN CPN to PGND Voltage VSS-0.3 to PGND+0.3
V
TJ Maximum Junction Temperature 150
TSTG Storage Temperature Range -65 to +150
TSDR Maximum Soldering Temperature Range, 10 Seconds 260
οC
PD Power Dissipation Internally Limited W
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom-
mended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Range
Symbol Parameter Min. Max. Unit
VDD Supply Voltage 2.3 4.5
VIH High Level Threshold Voltage RSD, LSD 1 -
VIL Low Level Threshold Voltage RSD, LSD - 0.35
V
Ri Input Resistance 1 47
Rf Feedback Resistance 4.7 100 kΩ
RL Load Resistance 500 - Ω
CL Maximum Capacitive Load - 400 pF
TA Operating Ambient Temperature Range -40 85
TJ Operating Junction Temperature Range -40 125 οC
Recommended Operating Conditions
Thermal Characteristics
Symbol Parameter Typical Value Unit
θJA
Thermal Resistance - Junction to Ambient (Note 2) TQFN4x4-20B
TSSOP-16
SOP-14
45
100
110
oC/W
θJC Thermal Resistance - Junction to Case (Note 3) TQFN4x4-20B
8 oC/W
Note 2: Please refer to “ Layout Recommendation”, the Thermal Pad on the bottom of the IC should soldered directly to the PCB’s
Thermal Pad area that with several thermal vias connect to the ground plan, and the PCB is a 2-layer, 5-inch square area with 2oz
copper thickness.
Note 3: The case temperature is measured at the center of the Thermal Pad on the underside of the TQFN4x4-20B package.
Copyright ANPEC Electronics Corp.
Rev. A.6 - Dec., 2011 www.anpec.com.tw4
APA2174
APA2174
Symbol Parameter Test Conditions Min.
Typ. Max. Unit
IDD Supply Current - 5 10 mA
ISD Shutdown Current VRSD=VLSD=0V - 1 5 µA
Ii Input current RSD, LSD - 0.1 - µA
CHARGE PUMP
fOSC Switching Frequency 400 500 600 kHz
Req Equivalent Resistance - 21 25 Ω
DRIVERS
AVO Open Loop Voltage Gain 80 100 - dB
GBW Unity Gain Bandwidth 8 10 - MHz
RO Output Resistance IO=10mA - - 100 Ω
VSR Slew Rate - 2.5 - V/µs
VOS Output Offset Voltage VDD=2.3V to 4.5V, RL = 600Ω -8 - 8 mV
Vn Noise Output Voltage - 10 20 µVrms
VDD=2.3V to 4.5V, Vrr=200mVrms
fin= 217Hz -90 -70
fin= 1kHz -90 -70
PSRR Power Supply Rejection Ratio
fin= 20kHz
-
-65 -60
dB
Tstart-up Start-up Time - 500 - µs
VESD ESD Protection OUTR, OUTL - 8 - kV
THD+N=1%, fin=1kHz
RL=600Ω 2 2.1 -
RL=100kΩ 2.3
VDD=4.5V, THD+N=1%, fin=1kHz
RL=600Ω - 2.9 -
VO Output Voltage
(Stereo, in Phase)
RL=100kΩ 3.2
Vrms
THD+N Total Harmonic Distortion
Plus Noise
VO=2Vrms, RL=600Ω
fin=20Hz
fin=1kHz
fin=20kHz
-
0.020
0.002
0.020
- %
Crosstalk Channel Separation VO=2Vrms, RL=600Ω
fin=20Hz
fin=1kHz
fin=20kHz
-
100
90
70
-
S/N Signal to Noise Ratio VO=2Vrms, RL=600Ω
With A-weighting Filter - 105 -
dB
Electrical Characteristics
VDD=3.3V, VGND=VPGND=0V, VRSD=VLSD=VDD, CCPF=CCPO=2.2µF, Ci=1µF, Ri=Rf=10kΩ, TA=25oC (unless otherwise noted)
Copyright ANPEC Electronics Corp.
Rev. A.6 - Dec., 2011 www.anpec.com.tw5
APA2174
Typical Operating Characteristics
Crosstalk vs. Frequency
Crosstalk (dB)
Frequency (Hz)
Left to Right
Right to Left
VDD=3.3V
RL=600Ω
AV=-1V/V
Ci=1µF
VO=2Vrms
20 20k100 1k 10k
-140
+0
-120
-100
-80
-60
-40
-20
Crosstalk vs. Frequency
Crosstalk (dB)
Frequency (Hz)
Left to Right
Right to Left
VDD=3.3V
RL=100kΩ
AV=-1V/V
Ci=1µF
VO=2Vrms
20 20k100 1k 10k
-140
+0
-120
-100
-80
-60
-40
-20
THD+N (%)
Output Voltage (V)
THD+N vs. Output Voltage
VDD=3.3V
VDD=4.5V
VDD=2.3V
RL=600Ω
fin=1kHz
AV=-1V/V
0.001
10
0.01
0.1
1
10m 5100m 1
THD+N (%)
THD+N vs. Output Voltage
VDD=3.3V
VDD=4.5V
VDD=2.3V
RL=100kΩ
fin=1kHz
AV=-1V/V
Output Voltage (V)
0.0006
10
0.01
0.1
1
10m 5100m 1
THD+N vs. Frequency
Frequency (Hz)
VDD=3.3V
RL=600Ω
Ci=1µF
AV=-1V/V
BW<80kHz
THD+N (%)
VO=2Vrms
VO=1Vrms
VO=0.1Vrms
20 20k100 1k 10k
0.0006
1
0.001
0.01
0.1
THD+N vs. Frequency
Frequency (Hz)
VDD=3.3V
RL=100kΩ
Ci=1µF
AV=-1V/V
BW<80kHz
THD+N (%)
VO=2Vrms
VO=1Vrms
VO=0.1Vrms
0.0006
1
0.001
0.01
0.1
20 20k100 1k 10k
Copyright ANPEC Electronics Corp.
Rev. A.6 - Dec., 2011 www.anpec.com.tw6
APA2174
Typical Operating Characteristics (Cont.)
Output Noise Voltage vs. Frequency
Output Noise Voltage (Vrms)
Frequency (Hz)
Left channel
Right channel
VDD=3.3V
RL=100kΩ
AV=-1V/V
Ci=1µF
A-Weighting
1µ
50µ
10µ
20 20k100 1k 10k
Output Noise Voltage vs. Frequency
Output Noise Voltage (Vrms)
Frequency (Hz)
Left channel
Right channel
VDD=3.3V
RL=600Ω
AV=-1V/V
Ci=1µF
A-Weighting
1µ
50µ
10µ
20 20k100 1k 10k
Frequency Response
Frequency (Hz)
Gain (dB)
Phase (deg)
VDD=3.3V
Av=-1V/V
RL=600Ω
Ci=1µF
Phase
Gain
-3
+1
-2
-1
+0
10 200k100 1k 10k +140
+220
+160
+180
+200
Frequency Response
Frequency (Hz)
Gain (dB)
Phase (deg)
VDD=3.3V
Av=-1V/V
RL=100kΩ
Ci=1µF
Phase
Gain
-3
+1
-2
-1
+0
10 200k100 1k 10k +140
+220
+160
+180
+200
Frequency (Hz)
PSRR vs. Frequency
Power Supply Rejection Ratio (dB)
VDD=3.3V
RL=600Ω
AV=-1V/V
Ci=1µF
Vrr=0.1Vrms
Left channel
Right channel
-120
+0
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k100 1k 10k Frequency (Hz)
PSRR vs. Frequency
Power Supply Rejection Ratio (dB)
VDD=3.3V
RL=100kΩ
AV=-1V/V
Ci=1µF
Vrr=0.1Vrms
Left channel
Right channel
-120
+0
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k100 1k 10k
Copyright ANPEC Electronics Corp.
Rev. A.6 - Dec., 2011 www.anpec.com.tw7
APA2174
Typical Operating Characteristics (Cont.)
-150
+0
-120
-90
-60
-30
-150
+0
-120
-90
-60
-30
02k400 800 1.2k 1.6k
Supply Voltage (dBV)
Output Voltage (dBV)
Frequency (Hz)
GSM Power Supply Rejection vs.
Frequency GSM Power Supply Rejection vs. Time
VLOUT
VROUT
1
2
3
VDD
Supply Voltage (V)
Supply Current (mA)
Av=-1V/V
No Load
Supply Current vs. Supply Voltage
0
1
2
3
4
5
6
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
Frequency (Hz)
Output Voltage FFT vs. Frequency
Output Voltage FFT (dBr)
VDD=3.3V
RL=600Ω
AV=-1V/V
Vo=-60dB to 2Vrms
-140
+0
-120
-100
-80
-60
-40
-20
020k5k 10k 15k
TIME:2ms/Div
CH2: VLOUT, 20mV/Div, DC
CH3: VROUT, 20mV/Div, DC
CH1: VDD, 500mV/Div, DC, Offset=3.3V
Copyright ANPEC Electronics Corp.
Rev. A.6 - Dec., 2011 www.anpec.com.tw8
APA2174
Operating Waveforms
Refer to the typical application circuit. The test condition is VDD=VSD=3.3V, RL=600Ω, TA= 25oC, unless otherwise specified.
Output Transient at Power OnOutput Transient at Power Off
CH1: VDD, 1V/Div, DC
TIME:2ms/Div
CH2: VLOUT, 20mV/Div, DC
CH3: VROUT, 20mV/Div, DC
CH1: VDD, 1V/Div, DC
TIME:2ms/Div
CH2: VLOUT, 20mV/Div, DC
CH3: VROUT, 20mV/Div, DC
VDD
VLOUT
VROUT
1
2
3
1
2
3
VDD
VLOUT
VROUT
Shutdown Release
1
2
3
VSD
VLOUT
VROUT
CH1: VSD, 1V/Div, DC
TIME:2ms/Div
CH2: VLOUT, 1V/Div, DC
CH3: VROUT, 1V/Div, DC
Load Transient Response
CH1: VSD, 1V/Div, DC
TIME:2ms/Div
CH2: VLOUT, 1V/Div, DC
CH3: VROUT, 1V/Div, DC
1
2
3
VLOUT
VROUT
VSD
Copyright ANPEC Electronics Corp.
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APA2174
Pin Description
PIN
NO.
TQFN4x4-20B
TSSOP-16
SOP-14
NAME I/O/P
FUNCTION
1 4 3 CPP I/O Charge pump flying capacitor positive connection.
2 5 4 PGND P Charge pump’s ground.
3 6 5 CPN I/O Charge pump flying capacitor negative connection.
4,6,8,12,
16,20 1,3 - NC - No Connection.
5 7 6 CVSS O Charge pump output, connect to the “VSS”.
7 8 7 VSS P Line Driver negative power supply.
9 9 8 LOUT
O Left channel output for line driver.
10 10 9 VDD P Power supply.
11 11 10 ROUT O Right channel output for line driver.
13 12 11 LIN I Left channel input terminal.
14 13 12 RSD I Right channel shutdown mode control input signal, pull low for
shutdown the right channel line driver.
15 14 13 RIN I Right channel input terminal.
17 15 14 GND P Ground connection for circuitry.
18 16 1 LSD I Left channel shutdown mode control input signal, pull low for
shutdown the left channel line driver.
19 2 2 PVDD P Charge pump’s power supply.
Block Diagram
ROUT
LOUT
CPP
CPN
PVDD
RIN
RSD
LIN
GND
LSD
VDD CVSS
VSSPGND
Shutdown
Circuit Power
and
Depop
Circuit
Charge
Pump
Copyright ANPEC Electronics Corp.
Rev. A.6 - Dec., 2011 www.anpec.com.tw10
APA2174
Typical Application Circuit
2.2µF
µF
10µF
Shutdown
Control
VDD
VDD VSS
2.2
2.2µF
10kΩRight
Channel
Output
Left
Channel
Output
ROUT
LOUT
AUDIO
DAC
Shutdown
ckt Power
and
Depop
Circuit
ROUT
RIN
RSD Charge
Pump
LIN
LOUT
GND
VDD
CPP
CPN
CVSSVSS
PGND
PVDD
LSD
1µF
1µF10kΩ
10kΩ
10kΩ
CCPB
CCPF
CCPO
CS
Ci1
Ci2
Ri1
Ri2
Rf1
Rf3
1. Inverting Amplifier
2. Secind-Order Active Low-Pass Filter
2.210µF
Shutdown
Control
VDD
2.2
2.2
Right
Channel
Output
ROUT
LOUT
AUDIO
DAC
Shutdown
Circuit
Power
and
Depop
Circuit
ROUT
RIN
RSD Charge
Pump
LIN
LOUT
GND
VDD
CPP
CPN
CVSSVSSPGND
PVDD
LSD
1µF
1µF
CCPB
CCPF
CCPO
CS
Ci1
Ci2
Ri
Ri
Rf1
Rf2
Rf1
Rf2
Cf2
Cf1
Cf2Cf1
VSS
VDD
Left
Channel
Output
220pF
CO
220pF
CO
µF
µF
µF
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Rev. A.6 - Dec., 2011 www.anpec.com.tw11
APA2174
Function Description
Line Driver Operation
Figure 1: Cap-free Line Driver’s Operation
The APA2174’s line drivers use a charge pump to invert
the positive power supply (VDD) to negative power supply
(VSS), see figure1. The line drivers operate at this bipolar
power supply (VDD and VSS) and the outputs reference re-
fers to the ground. This feature eliminates the output ca-
pacitor that is using in conventional single-ended line
drive amplifier. Compare with the single power supply
amplifier, the power supply range has almost doubled.
Thermal Protection
VDD
VDD/2
0
VOUT
VDD
VSS
0
VOUT
Conventional Line Driver
Cap-free Line Driver
The thermal protection circuit limits the junction tempera-
ture of the APA2174. When the junction temperature ex-
ceeds TJ = +150OC, a thermal sensor turns off the driver,
allowing the devices to cool. The thermal sensor allows
the driver to start-up after the junction temperature down
about 125OC. The thermal protection is designed with a
25OC hysteresis to lower the average TJ during continu-
ous thermal overload conditions, increasing lifetime of
the ICs.
Shutdown Function
In order to reduce power consumption while not in use,
the APA2174 contains two shutdown controllers to allow
either channel being independent and externally turns off
the amplifier bias circuitry. LSD controls the left channel
and RSD controls the right channel. This shutdown fea-
ture turns the amplifier off when logic low is placed on the
RSD and LSD pins for the APA2174. The trigger point be-
tween a logic high is 1.0V and logic low level is 0.35V. It is
recommended to switch between ground and the supply
voltage VDD to provide maximum device performance. By
switching the both RSD and LSD pins to a low level, the
amplifier enters a low-consumption current circumstance,
charge pump is disabled, and IDD for the APA2174 is in
shutdown mode. The charge pump is enabled once ei-
ther RSD or LSD pin is pulled to high. In normal operating,
the APA2174’s RSD and LSD pins should be pulled to a
high level to keep the IC out of the shutdown mode. The
RSD and LSD pins should be tied to a definite voltage to
avoid unwanted circumstance change.
Copyright ANPEC Electronics Corp.
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APA2174
Application Information
Second Order Low Pass Filter
Using the APA2174 as a second order, Multi-Feedback
active Butterworth filter for audio DACs. The topology is
like the figure 2.
Figure 2: Active Butterworth Filter
Table 1: The recommended components’ value.
AV
Pass Low
Pass
Ci
Cf1
Cf2
Ri
Rf1
Rf2
-1V/V
16Hz
40kHz
1µF
100pF
680pF
10kΩ
10kΩ
24kΩ
-1.5V/V
19Hz
40kHz
1µF
68pF
680pF
8.2kΩ
12kΩ
30kΩ
-2V/V
11Hz
40kHz
1µF
33pF
330pF
15kΩ
30kΩ
47kΩ
-2V/V
11Hz
30kHz
1µF
47pF
470pF
15kΩ
30kΩ
43kΩ
-3.3V/V
12Hz
30kHz
1µF
33pF
470pF
13kΩ
43kΩ
43kΩ
-10V/V
15Hz
30kHz
2.2µF
22pF
1nF
4.7kΩ
47kΩ
27kΩ
The overall gain is:
The high pass filter’s cutoff frequency is:
(1)
(2)
The low pass filter’s cutoff frequency is:
(3)
Input Capacitor, Ci
CiRiRf
Figure 3: Typical Application Circuit
In the typical application, an input capacitor, Ci, is required
to allow the amplifier to bias the input signal to the proper
DC level for optimum operation. In this case, Ci and the
minimum input impedance Ri from a high-pass filter with
the corner frequency are determined in the following
equation:
(4)
ii
)C(highpass CR21
fπ
=
The value of Ci must be considered carefully because it
directly affects the low frequency performance of the
circuit. Ri is the external input resistance that typical value
is 10kΩ and the specification calls for a flat bass re-
sponse down to 20Hz. Equation is reconfigured as below:
(5)
)C(highpassi
ifR21
Cπ
=
When the input resistance variation is considered, the Ci
is 0.8µF, so a value in the range of 1µF to 2.2µF would be
chosen. A further consideration for this capacitor is the
leakage path from the input source through the input net-
work (Ri + Rf, Ci) to the load.
This leakage current creates a DC offset voltage at the
input to the amplifier that reduces useful headroom, es-
pecially in high gain applications. For this reason, a low
leakage tantalum or ceramic capacitor is the best choice.
When polarized capacitors are used, the negative side of
the capacitor should face the amplifiers’ input in most
applications because the DC level of the amplifiers’ input
is held at GND. Please note that it is important to confirm
the capacitor polarity in the application.
Input Resistor, Ri
The gain of the APA2174 is be set by the external input
resistor (Ri ) and external feedback resistor (Rf). Please
see the figure 3.
ii
)C(highpass CR21
fπ
=
2f1f2f1f
C(lowpass) CCRR21
fπ
=
i
f1
VR
R
A−=
Ci
Cf2
Cf1=Cint+Cext
Cint=internal Capacitance(6pF)
Ri
Rf1Rf2
Cint
Cext
6pF
Cout 220pF
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Rev. A.6 - Dec., 2011 www.anpec.com.tw13
APA2174
Application Information (Cont.)
Input Resistor, Ri (Cont.)
(6)
i
f
VR
R
)Gain(A =
The external gain setting is recommended using from
-1V/V to -10V/V, and the Ri is in the range from 1kΩ to
47kΩ. It’s recommended to use 1% tolerance resistor or
better. Keep the input trace as short as possible to limit
the noise injection. The gain is recommended to set
-1V/V, and Ri is 10kΩ, and Rf is 10kΩ.
Feedback Resistor, Rf
Refer the figure 3, the external gain is setting by Ri and Rf;
and the gain setting is recommended using from -1V/V to
-10V/V. The Rf is in the range from 4.7kΩ to 100kΩ. It’s
recommended to use 1% tolerance resistor or better.
Power Supply Decoupling, Cs
The APA2174 is a high-performance CMOS audio ampli-
fier that requires adequate power supply decoupling to
ensure the output total harmonic distortion (THD+N) is
as low as possible. Power supply decoupling also pre-
vents the oscillations being caused by long lead length
between the amplifier and the speaker.
The optimum decoupling is achieved by using two differ-
ent types of capacitors that target on different types of
noise on the power supply leads. For higher frequency
transients, spikes, or digital hash on the line, a good low
equivalent-series- resistance (ESR) ceramic capacitor,
typically 0.1µF, is placed as close as possible to the de-
vice VDD and PVDD lead for the best performance. For
filtering lower frequency noise signals, a large alumi-
num electrolytic capacitor of 10µF or greater placed near
the audio power amplifier is recommended.
Charge Pump Bypass Capacitor, CCPB
The bypass capacitor (CCPB) relates with the charge
pump switching transient. The capacitor’s value is same
as flying capacitor (2.2µF). Place it close to the PVDD and
PGND.
Charge Pump Flying Capacitor, CCPF
The flying capacitor affects the load transient of the charge
pump. If the capacitor’s value is too small, then that will
degrade the charge pump’s current driver capability and
the performance of line drive amplifier.
Increasing the flying capacitor’s value will improve the
load transient of charge pump. It is recommended using
the low ESR ceramic capacitors (X7R type is
recommended) above 2.2µF.
Charge Pump Output Capacitor, CCPO
The output capacitor’s value affects the power ripple di-
rectly at CVSS (VSS). Increasing the value of output capaci-
tor reduces the power ripple. The ESR of output capacitor
affects the load transient of CVSS (VSS). Lower ESR and
greater than 2.2µF ceramic capacitor is a recommendation.
Layout Consideration
Figure 2: TQFN4x4-20B Land Pattern Recommendation
1. All components should be placed close to the APA2174.
For example, the input capacitor (Ci) should be close to
APA2174’s input pins to avoid causing noise coupling
to APA2174’s high impedance inputs; the decoupling
capacitor (CS) should be placed by the APA2174’s power
pin to decouple the power rail noise.
2. The output traces should be short and wide (>20mil),
3. The input trace should be short and symmetric.
4. The power trace width should be greater than 20mil.
5. The TQFN Thermal PAD should be soldered on PCB,
and the ground plane needs soldered mask (to avoid
short circuit) except the Thermal PAD area.
2.2mm
2.2mm
0.5mm
0.35mm
Ground
Plane for
ThermalPAD
ThermalVia
Diameter
0.3mm X 5
4.9mm
0.9mm
Copyright ANPEC Electronics Corp.
Rev. A.6 - Dec., 2011 www.anpec.com.tw14
APA2174
Package Information
TQFN4x4-20B
0.70
0.098
0.028
0.002
0.50 BSC 0.020 BSC
S
Y
M
B
O
LMIN.MAX.
0.80
0.00
0.18 0.30
2.00 2.70
0.05
2.00
A
A1
b
D
D2
E
E2
e
L
MILLIMETERS
A30.20 REF
TQFN4x4-20B
0.35 0.45
2.70
0.008 REF
MIN.MAX.
INCHES
0.031
0.000
0.008 0.012
0.079 0.098
0.079
0.014 0.018
K0.20 0.008
3.90 4.10 0.154 0.161
3.90 4.10 0.154 0.161
Note : 1. Followed from JEDEC MO-220 VGGD-5.
e
LK E2
Pin 1 Corner
D2
A1
A3
b
A
D
Pin 1
E
NX aaa c
0.08 0.003aaa
Copyright ANPEC Electronics Corp.
Rev. A.6 - Dec., 2011 www.anpec.com.tw15
APA2174
Package Information
TSSOP-16
Note : 1. Follow from JEDEC MO-153 AB.
2. Dimension "D" does not include mold flash, protrusions
or gate burrs. Mold flash, protrusion or gate burrs shall not
exceed 6 mil per side.
3. Dimension "E1" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
A2
A
A1
VIEW A
SEATING PLANE
GAUGE PLANE
0.25
L
SEE VIEW A
C
D
E
E1
b
e
S
Y
M
B
O
LMIN. MAX.
1.20
0.05
0.09 0.20
4.90 5.10
0.15
A
A1
c
D
E
e
L
MILLIMETERS
b0.19 0.30
0.65 BSC
TSSOP-16
0.45 0.75
0.026 BSC
MIN. MAX.
INCHES
0.047
0.002
0.007 0.012
0.004 0.008
0.193 0.201
0.169 0.177
0.018 0.030
6.20 6.60 0.244 0.260
00o8o0o8o
0.006
A2 0.80 1.05
4.30 4.50E1
0.031 0.041
Copyright ANPEC Electronics Corp.
Rev. A.6 - Dec., 2011 www.anpec.com.tw16
APA2174
Package Information
SOP-14
S
Y
M
B
O
LMIN. MAX.
1.75
0.10
0.17 0.25
0.25
A
A1
c
D
E
E1
e
h
L
MILLIMETERS
b0.31 0.51
SOP-14
0.25 0.50
0.40 1.27
MIN. MAX.
INCHES
0.069
0.004
0.012 0.020
0.007 0.010
0.010 0.020
0.016 0.050
0
0.010
1.27 BSC 0.050 BSC
A2 1.25 0.049
0
°
8
°
0
°
8
°
L
VIEW A
0.25
SEATING PLANE
GAUGE PLANE
Note: 1. Follow JEDEC MS-012 AB.
2. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.
3. Dimension “E” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
3.80
5.80
8.55
4.00
6.20
8.75 0.337 0.344
0.228 0.244
0.150 0.157
D
eb
E1
E
SEE VIEW A
c
h X 45
°
A
A1A2
Copyright ANPEC Electronics Corp.
Rev. A.6 - Dec., 2011 www.anpec.com.tw17
APA2174
Carrier Tape & Reel Dimensions
A
E1
A
B
W
F
T
P0
OD0
BA0
P2
K0
B0
SECTION B-B
SECTION A-A
OD1
P1
H
T1
A
d
Application
A H T1 C d D W E1 F
330.0±
2.00
50 MIN. 12.4+2.00
-
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±
0.30
1.75±
0.10
5.5±
0.05
P0 P1 P2 D0 D1 T A0 B0 K0 TQFN4x4-20B
4.0±
0.10
8.0±
0.10
2.0±
0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
4.30±
0.20
4.30±
0.20
1.30±
0.20
Application
A H T1 C d D W E1 F
330.0±
2.00
50 MIN. 12.4+2.00
-
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±
0.30
1.75±
0.10
5.50±
0.05
P0 P1 P2 D0 D1 T A0 B0 K0 TSSOP-16
4.00±
0.10
8.00±
0.10
2.00±
0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
6.90±
0.20
5.40±
0.20
1.60±
0.20
Application
A H T1 C d D W E1 F
330.0±
2.00
50 MIN. 16.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
16.0±
0.30
1.75±
0.10
7.50±
0.10
P0 P1 P2 D0 D1 T A0 B0 K0 SOP-14
4.0±
0.10
8.0±
0.10
2.0±
0.10
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
6.40±
0.20
9.00±
0.20
2.10±
0.20
(mm)
Copyright ANPEC Electronics Corp.
Rev. A.6 - Dec., 2011 www.anpec.com.tw18
APA2174
Package Type Unit Quantity
TQFN4x4-20B Tape & Reel 3000
TSSOP-16 Tape & Reel 2500
SOP-14 Tape & Reel 2500
Taping Direction Information
TQFN4x4-20B
TSSOP-16
USER DIRECTION OF FEED
USER DIRECTION OF FEED
Devices Per Unit
Copyright ANPEC Electronics Corp.
Rev. A.6 - Dec., 2011 www.anpec.com.tw19
APA2174
Classification Profile
SOP-14
USER DIRECTION OF FEED
Taping Direction Information
Copyright ANPEC Electronics Corp.
Rev. A.6 - Dec., 2011 www.anpec.com.tw20
APA2174
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
≥350
<2.5 mm 235 °C 220 °C
≥2.5 mm 220 °C 220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
350-2000 Volume mm3
>2000
<1.6 mm 260 °C 260 °C 260 °C
1.6 mm – 2.5 mm 260 °C 250 °C 245 °C
≥2.5 mm 250 °C 245 °C 245 °C
Reliability Test Program
Test item Method Description
SOLDERABILITY JESD-22, B102 5 Sec, 245°C
HOLT JESD-22, A108 1000 Hrs, Bias @ Tj=125°C
PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C
TCT JESD-22, A104 500 Cycles, -65°C~150°C
HBM MIL-STD-883-3015.7 VHBM≧2KV
MM JESD-22, A115 VMM≧200V
Latch-Up JESD 78 10ms, 1tr≧100mA
Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Average ramp-up rate
(Tsmax to TP) 3 °C/second max. 3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL) 183 °C
60-150 seconds 217 °C
60-150 seconds
Peak package body Temperature
(Tp)* See Classification Temp in table 1 See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc) 20** seconds 30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max. 6 °C/second max.
Time 25°C to peak temperature 6 minutes max. 8 minutes max.
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Classification Reflow Profiles
Copyright ANPEC Electronics Corp.
Rev. A.6 - Dec., 2011 www.anpec.com.tw21
APA2174
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838