©2001 Integrated Device Technology, Inc.
AUGUST 2001
DSC-3026/8
1
HIGH SPEED 3.3V
2K X 8 DUAL-PORT
STATIC RAM WITH INTERRUPTS
IDT71V321S/L
IDT71V421S/L
Features
◆◆
◆◆
◆High-speed access
– Commercial: 25/35/55ns (max.)
– Industrial: 25ns (max.)
◆◆
◆◆
◆Low-power operation
– IDT71V321/IDT71V421S
—Active: 325mW (typ.)
—Standby: 5mW (typ.)
– IDT71V321/V421L
—Active: 325mW (typ.)
—Standby: 1mW (typ.)
◆◆
◆◆
◆Two INT flags for port-to-port communications
Functional Block Diagram
NOTES:
1. IDT71V321 (MASTER): BUSY is an output. IDT71V421 (SLAVE): BUSY is input.
2. BUSY and INT are totem-pole outputs.
◆◆
◆◆
◆MASTER IDT71V321 easily expands data bus width to 16-
or-more-bits using SLAVE IDT71V421
◆◆
◆◆
◆On-chip port arbitration logic (IDT71V321 only)
◆◆
◆◆
◆BUSY output flag on IDT71V321; BUSY input on IDT71V421
◆◆
◆◆
◆Fully asynchronous operation from either port
◆◆
◆◆
◆Battery backup operation—2V data retention (L only)
◆◆
◆◆
◆TTL-compatible, single 3.3V power supply
◆◆
◆◆
◆Available in 52-pin PLCC, 64-pin TQFP and STQFP
packages
◆◆
◆◆
◆Industrial temperature range (–40°C to +85°C) is available
for selected speeds
I/O
Control
Address
Decoder MEMORY
ARRAY
ARBITRATION
and
INTERRUPT
LOGIC
Address
Decoder
I/O
Control
R/WL
CEL
OEL
BUSYL
A10L
A0L
3026 drw 01
I/O0L-I/O
7L
CEL
OEL
R/WL
INTL
BUSYR
I/O0R-I/O7R
A10R
A0R
INTR
CER
OER
(2)
(1,2) (1,2)
(2)
R/WR
CER
OER
11
11
R/WR
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
2
IDT71V321/421J
J52-1(4)
52-Pin PLCC
Top View(5)
INDEX
I/O
A
A
A
A
A
A
A
A
A
I/O
I/O
I/O
1L
2L
3L
4L
5L
6L
7L
8L
9L
0L
1L
3L
2L
OER
A
A
A
A
A
A
A
A
A
A
NC
I/O
0R
1R
2R
3R
4R
5R
6R
7R
8R
9R
7R
4L
5L
6L
7L
NC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0R
1R
2R
3R
4R
6R
5R
A
0L
OE
L
A
10L
INT
L
BUSY
L
R/W
L
CE
L
V
CC
CE
R
R/W
R
BUSY
R
INT
R
A
10R
1
234567474849505152
9
8
10
11
12
13
14
15
16
17
18
19
20 27262524232221 333231302928
35
34
36
37
38
39
40
41
42
43
44
45
46
3026 drw 02
,
Pin Configurations(1,2,3)
Description
The IDT71V321/IDT71V421 are high-speed 2K x 8 Dual-Port
Static RAMs with internal interrupt logic for interprocessor communica-
tions. The IDT71V321 is designed to be used as a stand-alone 8-bit
Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the
IDT71V421 "SLAVE" Dual-Port in 16-or-more-bit memory system ap-
plications results in full speed, error-free operation without the need for
additional discrete logic.
The device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. An automatic power
down feature, controlled by CE, permits the on chip circuitry of each
port to enter a very low standby power mode.
Fabricated using IDT's CMOS high-performance technology, these
devices typically operate on only 325mW of power. Low-power (L)
versions offer battery backup data retention capability, with each Dual-
Port typically consuming 200µW from a 2V battery.
The IDT71V321/IDT71V421 devices are packaged in a 52-pin
PLCC, a 64-pin TQFP (thin quad flatpack), and a 64-pin STQFP
(super thin quad flatpack).
INDEX
IDT71V321/421PF or TF
PP64-1(4)
&
PN64-1(4)
64-Pin STQFP
64-Pin TQFP
Top View(5)
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
46
45
44
43
42
41
40
39
38
37
36
35
34
47
48
33
17
18
19
20
32
31
30
29
28
27
26
25
24
23
22
21
49
50
51
52
63
62
61
60
59
58
57
56
55
54
53
64
I/O6R
N/C
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O7R
OER
N/C
N/C
I/O2L
A0L
OEL
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
N/C
N/C
GND
4L
I/O
5L
I/O
6L
I/O
7L
I/O
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
I/O5R
I/O3L
N/C
N/C
GND
N/C
N/C
A10R
VCC
BUSYL
R/WL
CER
R/WR
BUSYR
CEL
N/C
N/C
A10L
VCC
N/C
INTR
INTL
3026 drw 03
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J52-1 package body is approximately .75 in x .75 in x .17 in.
PP64-1 package body is approximately 10mm x 10mm x 1.4mm.
PN64-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
3
Recommended DC Operating
Conditions
Absolute Maximum Ratings(1) Recommended Operating
Temperature and Supply Voltage(1,2)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTERM must not exceed VCC + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%.
NOTES:
1. VIL (min.) = -1.5V for pulse width less than 20ns.
2. VTERM must not exceed Vcc + 0.3V.
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
Symbol Rating Commercial
& Industrial Unit
VTERM(2) Terminal V olt a ge
with Res p e c t
to GND
-0.5 to +4.6 V
TAOperating
Temperature 0 to + 70 ° C
TBIAS Temperature
Und er B ias -55 to +125 oC
TSTG Storage
Temperature -65 to +150 oC
IOUT DC Output
Current 50 mA
3026 tbl 01
Grade Ambient
Temperature GND Vcc
Commercial 0OC to + 70OC0V3.3V
+ 0.3V
Industrial -40OC to + 85OC0V 3.3V
+ 0.3V
3026 tbl 02
Symbol Parameter Min. Typ. Max. Unit
VCC Sup p ly Vo ltag e 3.0 3.3 3.6 V
GND Ground 0 0 0 V
VIH Input High Voltage 2.0 ____ VCC+0.3(2) V
VIL Inp ut Low Vo ltag e -0. 3(1) ____ 0.8 V
3026 tbl 03
Capacitance(1)
(TA = +25°C, f = 1.0MHz) TQFP Only
Symbol Parameter Conditions(2) Max. Unit
CIN Inp ut Cap ac i tanc e VIN = 3dV 9 pF
COUT Outp ut Cap aci tanc e VOUT = 3d V 10 pF
3026 tbl 04
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dv references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)
Symbol Parameter Test Conditions
71V321S
71V421S 71V321L
71V421L
UnitMin. Max. Min. Max.
|ILI|Input Leakage Current(1) VCC = 3.6V,
VIN = 0V to V CC
___ 10 ___ 5µA
|ILO| Output Leakage Current CE = VIH, VOUT = 0V to V CC
VCC = 3.6V ___ 10 ___ 5µA
VOL Output Low Voltage IOL = 4mA ___ 0.4 ___ 0.4 V
VOH Outp ut Hig h Vo ltag e IOH = -4mA 2.4 ___ 2.4 ___ V
3026 tbl 05
NOTE:
1. At VCC < 2.0V input leakages are undefined.
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
4
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,2) ( VCC = 3.3V ± 0.3V)
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
2. VCC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 70mA (Typ.).
3 . At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t RC and using "AC Test Conditions" of input levels
of GND to 3V.
4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
5. Port "A" may be either left or right port. Port "B" is opposite from port "A".
Symbo l Param eter Test Condition Version
71V321X25
71V421X25
Com'l
& I nd
71V321X35
71V421X35
Com'l Only
71V321X55
71V421X55
Com'l Only
UnitTyp. Max. Typ. Max. Typ. Max.
ICC Dy namic Op erating
Current
(Bo th P orts A ctive )
CE = VIL, Outputs Disabled
SEM = VIH
f = fMAX(3)
COM'L S
L55
55 130
100 55
55 125
95 55
55 115
85 mA
IND S
L55
55 150
130 ___ ___ ___ ___
ISB1 Stand b y Curre nt
(Bo th P orts - TTL
Le v e l Inpu ts)
CE
R = CE
L = VIH
SEMR = SEML = VIH
f = fMAX(3)
COM'L S
L15
15 35
20 15
15 35
20 15
15 35
20 mA
IND S
L15
15 50
35 ___ ___ ___ ___
ISB2 Stand b y Curre nt
(One Po rt - TTL
Le v e l Inpu ts)
CE
"A" = VIL and CE"B" = VIH(5)
Active Port Outputs Disabled,
f=fMAX(3)
SEMR = SEML = VIH
COM'L S
L25
25 75
55 25
25 70
50 25
25 60
40 mA
IND S
L25
25 95
75 ___ ___ ___ ___
ISB3 Full Standb y Current
(Both Ports - A l l
CM OS L e v e l In p uts )
Both Ports CE
L and
CE
R > VCC - 0.2V
VIN > VCC - 0.2V o r
VIN < 0.2V, f = 0(4)
SEMR = SEML > VCC - 0.2V
COM'L S
L1.0
0.2 5
31.0
0.2 5
31.0
0.2 5
3mA
IND S
L1.0
0.2 10
6___ ___ ___ ___
ISB4 Full Standb y Current
(One Po rt - A ll
CM OS L e v e l In p uts )
CE
"A" < 0.2V and
CE
"B" > VCC - 0.2V(5)
SEMR = SEML > VCC - 0.2V
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled
f = fMAX(3)
COM'L S
L25
25 70
55 25
25 65
50 25
25 55
40 mA
IND S
L25
25 85
70 ___ ___ ___ ___
3026 tbl 06
Data Retention Characteristics (L Version Only)
Symbol Parameter Test Condition Min. Typ. (1) Max. Unit
VDR VCC fo r Da ta Rete nti o n 2. 0 ___ 0V
ICCDR Data Rete nti on Curre nt VCC = 2V, CE
> VCC - 0. 2V COM'L. ___ 100 1500 µA
tCDR(3) Chip Des elect to Data
Retentio n Time VIN > VCC - 0 . 2V o r V IN < 0. 2V IND. ___ 100 4000 µA
0___ ___ V
tR(3) Ope ratio n Reco ve ry Time tRC(2) ___ ___ V
3026 t bl 0 7
NOTES:
1. VCC = 2V, TA = +25°C, and is not production tested.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization but not production tested.
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
5
Data Retention Waveform
VCC
CE
3.0V 3.0V
DATA RETENTION MODE
tCDR tR
VIH VIH
VDR
VDR ≥2.0V
3026 drw 04 ,
AC Test Conditions
590Ω
30pF
435Ω
DATAOUT
590Ω
435Ω5pF
DATAOUT
3026 drw 05
3.3V 3.3V
BUSY
INT
Figure 1. AC Output Test Load Figure 2. Output Test Load
(for tHZ, tLZ, tWZ, and tOW)
* Including scope and jig.
Input Pulse Levels
Inp ut Ris e/Fall Time s
Inp ut Timi ng Re fe re nce Le ve ls
Outp ut Refe re nce Le ve ls
Output Load
GND to 3.0V
5ns
1.5V
1.5V
Fi g ures 1 and 2
3026 tbl 08
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range(2)
71V321X25
71V421X25
Com'l
& Ind
71V321X35
71V421X35
Com'l Only
71V321X55
71V421X55
Com'l Only
UnitSymbol Parameter Min. Max. Min. Max. Min. Max.
READ CYCLE
tRC Read Cyc le Time 25 ____ 35 ____ 55 ____ ns
tAA Address Access Time ____ 25 ____ 35 ____ 55 ns
tACE Chip Enable Access Time ____ 25 ____ 35 ____ 55 ns
tAOE Output Enable Acces s Time ____ 12 ____ 20 ____ 25 ns
tOH Output Hold from Address Change 3 ____ 3____ 3____ ns
tLZ Output Low-Z Time(1,2) 0____ 0____ 0____ ns
tHZ Output High-Z Time(1,2) ____ 12 ____ 15 ____ 30 ns
tPU Chip Enab le to Powe r Up Time (2) 0____ 0____ 0____ ns
tPD Chi p Disab le to Powe r Do wn Time(2) ____ 50 ____ 50 ____ 50 ns
3026 t b l 0 9
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. 'X' in part numbers indicates power rating (S or L).
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
6
CE
t
ACE
tHZ
tLZ
tPD
VALID DATA
50%
OE
DATAOUT
CURRENT
ICC
ISS 50%
3026 drw 07
(4)
(1)
(1) (2)
(2)
(4)
tLZ
tHZ
t
AOE
tPU
Timing Waveform of Read Cycle No. 2, Either Side (3)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, OE or CE.
3. R/W = VIH and the address is valid prior to or coincidental with CE transition LOW.
4 . Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
Timing Waveform of Read Cycle No. 1, Either Side(1)
NOTES:
1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.
2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
ADDRESS
DATAOUT
tRC
tOH
PREVIOUS DATA VALID
tAA
tOH
DATA VALID
3026 drw 06
tBDD(2,3)
BUSYOUT
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
7
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but is not production tested.
3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over
voltage and temperature, the actual tDH will always be smaller than the actual tOW.
4. 'X' in part numbers indicates power rating (S or L).
5. For Master/Slave combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA.
Symbol Parameter
71V321X25
71V421X25
Com'l
& I nd
71V321X35
71V421X35
Com'l Only
71V321X55
71V421X55
Com'l Only
UnitMin. Max. Min. Max. Min. Max.
WRI TE CYCL E
tWC Write Cycle Time(5) 25 ____ 35 ____ 55 ____ ns
tEW Chip Enab le to End-o f-Write 20 ____ 30 ____ 40 ____ ns
tAW Address Valid to End-of-Write 20 ____ 30 ____ 40 ____ ns
tAS Address Set-up Time 0 ____ 0____ 0____ ns
tWP Write Pulse Width 20 ____ 30 ____ 40 ____ ns
tWR Write Recovery Time 0 ____ 0____ 0____ ns
tDW Data Valid to End-of-Write 12 ____ 20 ____ 20 ____ ns
tHZ Outp ut High-Z Tim e(1,2) ____ 12 ____ 15 ____ 30 ns
tDH Data Ho ld Time (3) 0____ 0____ 0____ ns
tWZ Write Enable to Output in High-Z(1,2) ____ 15 ____ 15 ____ 30 ns
tOW Outp ut A c tiv e fro m E nd -o f-Write(1,2) 0____ 0____ 0____ ns
3026 t bl 10
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
8
Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)(1,5)
Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)(1,5,8)
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W= VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined to be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test
Load (Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be
placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified tWP.
tWC
ADDRESS
OE
CE
R/W
DATAOUT
DATAIN
tAS tWR
tOW
tDW tDH
tAW
tWP(2)
tHZ
(4) (4)
tWZ
tHZ
3026 drw 08
(6)
(7)
(7)
(3) (7)
tWC
ADDRESS
CE
R/W
DATA IN
tAS tEW tWR
tDW tDH
tAW
3026 drw 09
(6) (2) (3)
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
9
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
NOTES:
1. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY."
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that a write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
71V321X25
71V421X25
Com'l
& I nd
71V321X35
71V421X35
Com'l Only
71V321X55
71V421X55
Com'l Only
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
BUSY Ti ming (For M aster IDT71V 321 Onl y)
tBAA BUSY Access Time from Address ____ 20 ____ 20 ____ 30 ns
tBDA BUSY Disable Time from Address ____ 20 ____ 20 ____ 30 ns
tBAC BUSY Access Time from Chip Enable ____ 20 ____ 20 ____ 30 ns
tBDC BUSY Disable Time from Chip Enable ____ 20 ____ 20 ____ 30 ns
tWH Wri te Ho l d A fte r BUSY(5) 12 ____ 15 ____ 20 ____ ns
tWDD Write Pulse to Data Delay(1) ____ 50 ____ 60 ____ 80 ns
tDDD Write Data Valid to Read Data De lay (1) ____ 35 ____ 45 ____ 65 ns
tAPS Arb itration Priority Se t-up Time(2) 5____ 5____ 5____ ns
tBDD BUSY Disable to Valid Data(3) ____ 30 ____ 30 ____ 45 ns
BUSY Ti ming (For S lave I DT71V421 Only)
tWB BUSY Input to Wri te (4) 0____ 0____ 0____ ns
tWH Wri te Ho l d A fte r BUSY(5) 12 ____ 15 ____ 20 ____ ns
tWDD Write Pulse to Data Delay(1) ____ 50 ____ 60 ____ 80 ns
tDDD Write Data Valid to Read Data De lay (1) ____ 35 ____ 45 ____ 65 ns
3 026 tb l 11
tWC
tWP
tDW tDH
tBDD
tDDD
tBDA
tWDD
ADDR"B"
DATAOUT"B"
DATAIN "A"
ADDR"A" MATCH
VALID
MATCH
VALID
R/W"A"
BUSY"B"
tAPS
3026 drw 10
(1)
tBAA
Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for SLAVE (71V421).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
10
Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)
Timing Waveform of BUSY Arbritration Controlled
by Address Match Timing(1)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (71V321 only).
NOTES:
1. tWH must be met for both BUSY input (71V421, slave) or output (71V321, master).
2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes HIGH.
3. tWB is for the slave version (71V421).
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is oppsite from port "A".
Timing Waveform of Write with BUSY(4)
BUSY"B"
3026 drw 11
R/W"A"
tWP
tWH
tWB
R/W"B" (2)
(1)
(3)
,
tAPS(2)
ADDR
"A" AND "B" ADDRESSES MATCH
tBAC tBDC
CE"B"
CE"A"
BUSY"A"
3026 drw 12
BUSY"B"
ADDRESSES DO NOT MATCH
ADDRESSES MATCH
tAPS
ADDR"A"
ADDR"B"
tRC OR tWC
3026 drw 13
(2)
tBAA tBDA
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
11
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1)
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
71V321X25
71V421X25
Com'l
& Ind
71V321X35
71V421X35
Com'l Only
71V321X55
71V421X55
Com'l Only
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
INTERRUPT TIMING
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
INS
Inte rrup t S e t Tim e
____
25
____
25
____
45 ns
t
INR
Interrupt Re se t Time
____
25
____
25
____
45 ns
3026 t bl 12
Timing Waveform of Interrupt Mode(1)
SET INT
CLEAR INT
NOTES:.
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
tINS
ADDR"A"
INT"B"
INTERRUPT ADDRESS
tWC
tAS
R/W"A"
tWR
3026 drw 14
(3)
(3)
(2)
(4)
tRC
INTERRUPT CLEAR ADDRESS
ADDR"B"
OE"B"
tINR
INT"A" 3026 drw 15
tAS(3)
(3)
(2)
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
12
Table III Address BUSY Arbitration
Table I. Non-Contention
Read/Write Control(4)
NOTES:
1. Pins BUSYL and BUSYR are both outputs for IDT71V321 (master). Both are inputs
for IDT71V421 (slave). BUSYX outputs on the IDT71V321 are totem-pole. On
slaves the BUSYX input internally inhibits writes.
2 . 'L' if the inputs to the opposite port were stable prior to the address and enable
inputs of this port. 'H' if the inputs to the opposite port became stable after the
address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR
= LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW
regardless of actual logic level on the pin. Writes to the right port are internally
ignored when BUSYR outputs are driving LOW regardless of actual logic level
on the pin.
Truth Tables
Table II. Interrupt Flag(1,4)
NOTES:
1. A0L – A10L ≠ A0R – A10R.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = High-impedance.
NOTES:
1. Assumes BUSYL = BUSYR = VIH
2. If BUSYL = VIL, then No Change.
3. If BUSYR = VIL, then No Change.
4. 'H' = HIGH, 'L' = LOW, 'X' = DON’T CARE
Left Port Right Port
FunctionR/WLCE
LOELA10L-A0L INTLR/WRCE
ROERA10R-A0R INTR
LLX7FFXXXX X L
(2) Set Right INTR Flag
XXX X XXLL 7FFH
(3) Re se t Rig ht INTR Flag
XXX X L
(3) L L X 7FE X Set Left INTL Flag
XLL7FEH
(2) X X X X X Reset Left INTL Flag
3 026 tbl 14
Inputs Outputs
Function
CELCERAOL-A10L
AOR-A10R BUSYL(1) BUSYR(1)
X X NO MATCH H H Normal
H X MATCH H H Normal
X H MATCH H H Normal
L L MATCH (2) (2) Write Inhibit(3)
3026 tbl 15
Left or Right Port(1)
R/WCE OE D0-7 Function
XHX Z Port Dese le cte d and in Powe r-
Down Mode. ISB2 or ISB4
XHX Z CE
R = CE
L = VIH, Power-Down Mode ISB1
or ISB3
LLXDATA
IN Da ta on P ort W ri tte n Into M em o ry(2)
HLLDATA
OUT Data in Memory Output on Port(3)
H L H Z High-impedance Outputs
3026 tbl 13
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
13
being expanded in depth, then the BUSY indication for the resulting array
requires the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an SRAM array in width while using BUSY logic, one
master part is used to decide which side of the SRAM array will receive
a BUSY indication. Any number of slaves to be addressed in the same
address range as the master, use the BUSY signal as a write inhibit signal.
Thus on the IDT71V321/IDT71V421 SRAMs the BUSY pin is an output
if the part is Master (IDT71V321), and the BUSY pin is an input if the part
is a Slave (IDT71V421) as shown in Figure 3.
Functional Description
The IDT7V1321/IDT71V421 provides two ports with separate control,
address and I/O pins that permit independent access for reads or writes
to any location in memory. The IDT71V321/IDT71V421 has an automatic
power down feature controlled by CE. The CE controls on-chip power
down circuitry that permits the respective port to go into a standby mode
when not selected (CE = VIH). When a port is enabled, access to the entire
memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 7FE
(HEX), where a write is defined as the CER = R/WR = VIL per Truth Table
II. The left port clears the interrupt by accessing address location 7FE when
CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt
flag (INTR) is asserted when the left port writes to memory location 7FF
(HEX) and to clear the interrupt flag (INTR), the right port must access the
memory location 7FF. The message (8 bits) at 7FE or 7FF is user-defined,
since it is an addressable SRAM location. If the interrupt function is not used,
address locations 7FE and 7FF are not used as mail boxes, but as part
of the random access memory. Refer to Truth Table II for the interrupt
operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “Busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a busy indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY Logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation.
The BUSY outputs on the IDT71V321 RAM master are totem-pole type
outputs and do not require pull-up resistors to operate. If these RAMs are
3026 drw 16
MASTER
Dual Port
RAM
BUSYLBUSYR
CE
MASTER
Dual Port
RAM
BUSYLBUSYR
CE
SLAVE
Dual Port
RAM
BUSYLBUSYR
CE
SLAVE
Dual Port
RAM
BUSYLBUSYR
CE
BUSYL
BUSYR
DECODER
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT71V321 (Master) and (Slave) IDT71V421 RAMs.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.
The BUSY arbitration, on a Master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with either the R/W signal or the byte enables. Failure
to observe this timing can result in a glitched internal write inhibit signal and
corrupted data in the slave.
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
14
Ordering Information
NOTE:
1. Contact your sales office Industrial temperature range is available for selected speeds, packages and powers.
52-pin PLCC (J52-1)
64-pin TQFP (PN64-1)
64-pin STQFP (PP64-1)
XXXXIDT Device Type A 999 A A
Power Speed Package Process/
Temperature
Range
16K (2K x 8-Bit) MASTER 3.3V
Dual-Port RAM w/ Interrupt
16K (2K x 8-Bit) SLAVE 3.3V
Dual-Port RAM w/ Interrupt
Speed in nanoseconds
3026 drw 17
Blank
I(1)
J
PF
TF
25
35
55
L
S
71V321
71V421
Low Power
Standard Power
Commercial (0°Cto+70°C)
Industrial (-40°Cto+85°C)
Commercial & Industrial
Commercial Only
Commercial Only
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
03/24/99: Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Page 2 Added additional notes to pin configurations
06/15/99: Changed drawing format
10/15/99: Page 12 Changed open drain to totem-pole in Table III, note 1
10/21/99: Page 13 Deleted 'does not' in copy from Busy Logic
11/12/99: Replaced IDT logo
01/12/01: Pages 1 & 2 Moved full "Description" to page 2 and adjusted page layouts
Page 3 Increased storage temperature parameters
Clarified TA parameter
Page 4 DC Electrical parameters–changed wording from "open" to "disabled"
Changed ±200mV to 0mV in notes
08/22/01: Pages 4, 5, 7, 9 & 11 Industrial temp range offering removed from DC & AC Electrical Characteristics for 35 and 55ns
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