PI2EQX3421 3.2Gbps, 1:2 Port Switch, SATA2/SAS ReDriverTM Features Description IITwo 3.2Gbps differential signal Pericom Semiconductor's PI2EQX3421 is a low power, signal ReDriver. The device provides programmable equalization, to optimize performance over a variety of physical mediums by reducing Inter-Symbol Interference. PI2EQX3421 supports two 100-Ohm Differential CML data I/O's between the Protocol ASIC to a switch fabric, across a backplane, or to extend the signals across other distant data pathways on the user's platform. IIAdjustable Receiver Equalization II100-Ohm Differential CML I/O's IIIndependent output level control IIInput signal level detect and squelch for each channel IIOOB support The integrated equalization circuitry provides flexibility with signal integrity of the signal input to ReDriver. IILow Power (100mW per Channel) IIStand-by Mode - Power Down State A low-level input signal detection and output squelch function is provided for each channel. Each channel operates fully independently. When the channels are enabled (CE=1) and operating, that channels input signal level (on XIN+/-) determines whether the output is enabled. If the input signal level of the channel falls below the active threshold level (Vth-) then the outputs are driven to the common mode voltage. IIVDD Operating Range: 1.5V to 1.8V IIPackaging: -- 28-TQFN (3.5x 5.5mm) In addition to signal conditioning, Pericom's PI2EQX3421 also provides power management Stand-by mode operated by the Chip Enable (CE) pin. F_SD FA_OUT+ FA_OUT- F_IN+ EQUALIZER FA_ES VDD F_IN+ F_IN- SIGNAL DETECT EQUALIZER SIGNAL DETECT LOGIC R_OUT+ R_OUT- RA_IN- R_ES SIGNAL DETECT RB_SD VDD VDD R_OUT+ R_OUTRB_SD RA_IN+ RA_EQ EQUALIZER RB_INRB_EQ All trademarks are property of their respective owners. 10-0114 5 GND 6 7 8 1 20 19 18 17 16 9 11 12 13 14 15 10 RB_EQ RB_IN+ 1 28 27 26 25 24 23 2 22 3 21 4 FA_OUT+ FA_OUTVDD RA_IN+ RA_INFB_OUT+ FB_OUTVDD RB_IN+ RB_IN- CH_SEL F_SD FB_ES RA_SD CONTROL LOGIC RA_SD FB_OUT- F_EQ R_ES FB_OUT+ FB_ES F_IN- CH_SEL TEST# CE CE F_EQ SIGNAL DETECT FA_ES Pin Description (Top Side View) RA_EQ Block Diagram www.pericom.com PS8972D 02/04/10 PI2EQX3421 3.2Gbps, 1:2 Port Switch, SATA2/SAS ReDriverTM Pin Description Pin # Pin Name Type Description 25 CE Input Chip Enable "high" provides normal operation. "Low" for power down mode. With internal 50K-Ohm pull-up resistor. 14 CH_SEL Input Channel Select "high" selects path A. "Low" selects path B. With internal 50KOhm pull-up resistor. 28 F_EQ Input Selection pin for equalizer of Fin. "Low" means 2.5dB, "high" means 6.5dB. With internal 50K-Ohm pull-up resistor. 4 F_IN+ 5 F_IN- Input CML input channel F with internal 50-Ohm pull down. 2 F_SD Output Channel Fin Signal detector output. Provides "high" when a signal is detected. 26 FA_ES Input "High" means FA_OUT operates to the SATA i/m standard. "Low" means FA_ OUT support SATAx standard. With internal 50K-Ohm pull-up resistor. 24 FA_OUT+ 23 FA_OUT- Output CML output channel FA with internal 50-Ohm pull up. 12 FB_ES Input "High" means FB_OUT operates to the SATA i/m standard. "Low" means FB_ OUT support SATAx standard. With internal 50K-Ohm pull-up resistor. 19 FB_OUT+ 18 FB_OUT- Output CML output channel FB with internal 50-Ohm pull up. Center Pad GND GND Supply ground. 13 R_ES Input "High" means Rout operates to the SATA i/m standard. "Low" means Rout support SATAx standard. With internal 50K-Ohm pull-up resistor. 27 RA_EQ Input Selection pin for equalizer of RA_IN. "Low" means 2.5dB, "high" means 6.5dB. With internal 50K-Ohm pull-up resistor. 21 RA_IN+ 20 RA_IN- Input CML input channel RA with internal 50-Ohm pull down. 1 RA_SD Output Signal detector for Channel RA_IN. Provides "high" when signal is detected. 11 RB_EQ Input Selection pin for equalizer of RB_IN. "Low" means 2.5dB, "high" means 6.5dB. With internal 50K-Ohm pull-up resistor. 16 RB_IN+ 15 RB_IN- Input CML input channel RB with internal 50-Ohm pull down. 10 RB_SD Output Signal detector for Channel RB_IN. Provides "high" when signal is detected. 8 R_OUT+ 9 R_OUT- Output CML output channel R with internal 50-Ohm pull up. 3,6,7,17,22 VDD Power Positive Supply Voltage, 1.5V to 1.8V (0.1V) All trademarks are property of their respective owners. 10-0114 2 www.pericom.com PS8972D 02/04/10 PI2EQX3421 3.2Gbps, 1:2 Port Switch, SATA2/SAS ReDriverTM Equalizer Selection x_EQ Compliance Channel @ 1.6 GHz 0 1.5dB 1.0dB 1 5.5dB 1.0dB Output CML Buffer CE CH_SEL X_ES FA_OUT FB_OUT R_OUT 0 X X VDD VDD VDD 1 0 0 VDD VDD-0.6V VDD-0.6V 1 0 1 VDD VDD-0.3V VDD-0.3V 1 1 0 VDD-0.6V VDD VDD-0.6V 1 1 1 VDD-0.3V VDD VDD-0.3V All trademarks are property of their respective owners. 10-0114 3 www.pericom.com PS8972D 02/04/10 PI2EQX3421 3.2Gbps, 1:2 Port Switch, SATA2/SAS ReDriverTM Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature........................................................... -65C to +150C Supply Voltage to Ground Potential....................................-0.5V to +2.5V DC SIG Voltage........................................................... -0.5V to VDD +0.5V Current Output .................................................................-25mA to +25mA Power Dissipation Continous...........................................................500mW Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating Temperature................................................................ 0 to +70C AC/DC Electrical Characteristics (VDD = 1.4V to 1.9V) Symbol Parameter Conditions Min. Typ. Max. Units PSTANDBY Supply Power CE = LVCMOS Low 0.1 PACTIVE Active Supply Power CE = LVCMOS High 0.3 Tpd Latency Input to Output 1.0 ns TSW Switch time, idle to active CH_Sel toggles 50 ns W CML Receiver Input VRX-DIFFP-P Differential Input Peak-topeak Voltage VRX-CM-ACP AC Peak Common Mode Input Voltage ZRX-DC DC Input Impedance 40 50 60 ZRX-DIFF-DC DC Differential Input Impedance 85 100 115 Equalization JRS JRM Residual Jitter(1,2) Random Jitter(1,2) 0.200 150 Total Jitter 0.3 1.5 Signal Detector Performance VTH Threshold TEN Enable/disable time V 65(3) CE = 1 mV Ohm Ulp-p psrms 200 (3) mVppd 16 ns Notes 1. K28.7 pattern is applied differentially at point A as shown in Figure 1. 2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 x RJ + DJ) where RJ is random RMS jitter and DJ is maximum deterministic jitter. Signal source is a K28.5 pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or equivalent for random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or its equivalent. The deterministic jitter at point B must be from media-induced loss, and not from clock source modulation. JItter is measured at 0V at point C of Figure 1. 3. Using Compliance test at 1.5Gbps and 3Gbps. Also using OOB (OOB is formed by ALIGNp primitive or D24.3) test patterns at 1.5Gbps. The ALIGN primitive (K28.5+D10.2+D27.3 = 0011111010+0101010101+0010011100). The D24.3 = 00110011001100110011 All trademarks are property of their respective owners. 10-0114 4 www.pericom.com PS8972D 02/04/10 PI2EQX3421 3.2Gbps, 1:2 Port Switch, SATA2/SAS ReDriverTM AC/DC Electrical Characteristics Symbol Parameter Conditions Min. Typ. Max. Units CML Transmitter Output (100-Ohm differential) VDIFFP Output Voltage Swing x_ES=1 200 375 Differential Swing | VTX-D+ - VTX-D- | x_ES=0 550 650 (1) mVp-p Differential Peak-to-peak Ouput Voltage(1) VTX-DIFFP-P = 2 * | VTX-D+ - VTX-D- | x_ES=1 400 750 x_ES=0 1000 1300 Common-Mode Voltage(1) x_ES=1 VDD-0.6 | VTX-D+ + VTX-D- | / 2 x_ES=0 VDD-0.3 tF, tR Transition Time 20% to 80% 150 ps tF-tR / tF+tR Transition Mismatch Time 20% to 80% 20 % ZOUT Output resistance Single ended ZTX-DIFF-DC DC Differential TX Impedance 80 100 120 Ohm CTX AC Coupling Capacitor 0.3 4.7 12 nF VTX-DIFFP-P VTX-C mV mV 50 Ohm LVCMOS Control Pins 0.65 x VDD VIH Input High Voltage VIL Input Low Voltage 0.35 x VDD IIH Input High Current 250 IIL Input Low Current 500 VOH DC Output Logic High IOH = 4mA VOL DC Output Logic Low IOL = 4mA V A VDD 0.45 V 0.4 Note: 1. When x_ES=0, select SATAx standard. When x_ES=1, select SATAI/m standard. FR4 Signal Source A B SmA Connector SmA Connector Pericom PI2EQX3421 In C Out 30IN Figure 1. Test Condition Referenced in the Electrical Characteristic Table All trademarks are property of their respective owners. 10-0114 5 www.pericom.com PS8972D 02/04/10 PI2EQX3421 3.2Gbps, 1:2 Port Switch, SATA2/SAS ReDriverTM Packaging Mechanical: 28-contact TQFN (ZH) DATE: 01/26/09 DESCRIPTION: 28-Contact, Very Thin Quad Flat No-Lead, TQFN PACKAGE CODE: ZH28 REVISION: B DOCUMENT CONTROL #: PD-2034 09-0066 Note: For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php Ordering Information Ordering Number Package Code Package Description PI2EQX3421ZHE ZH Pb-Free and Green 28-contact TQFN Notes: * Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ * E = Pb-free and Green * X suffix = Tape/Reel Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com All trademarks are property of their respective owners. 10-0114 6 www.pericom.com PS8972D 02/04/10