70-0100-1070-3 - 3M - Datasheet.Live

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Features

 Two 3.2Gbps dierential signal

 Adjustable Receiver Equalization

 100-Ohm Dierential CML I/O’s

 Independent output level control

 Input signal level detect and squelch for each channel

 OOB support

 Low Power (100mW per Channel)

 Stand-by Mode – Power Down State

 VDD Operating Range: 1.5V to 1.8V

 Packaging: — 28-TQFN (3.5x 5.5mm)

Description

Pericom Semiconductor’s PI2EQX3421 is a low power, signal

ReDriver. e device provides programmable equalization, to

optimize performance over a variety of physical mediums by

reducing Inter-Symbol Interference. PI2EQX3421 supports two

100-Ohm Dierential CML data I/O’s between the Protocol

ASIC to a switch fabric, across a backplane, or to extend the sig-

nals across other distant data pathways on the user’s platform.

e integrated equalization circuitry provides exibility with

signal integrity of the signal input to ReDriver.

A low-level input signal detection and output squelch function is

provided for each channel. Each channel operates fully indepen-

dently. When the channels are enabled (CE=1) and operating,

that channels input signal level (on XIN+/-) determines whether

the output is enabled. If the input signal level of the channel

falls below the active threshold level (Vth-) then the outputs are

driven to the common mode voltage.

In addition to signal conditioning, Pericom’s PI2EQX3421 also

provides power management Stand-by mode operated by the

Chip Enable (CE) pin.

Block Diagram Pin Description (Top Side View)

10 11

F_SD

VDD

F_IN+

VDD

R_OUT+

R_OUT-

FA_OUT-

VDD

RA_IN+

RA_IN-

FB_OUT+

FB_OUT-

VDD

RB_IN+

FB_ES

R_ES

GND

RA_SD

RB_SD

RB_EQ

CH_SEL

FA_OUT+

RB_IN-

RA_EQ

FA_ES

F_EQ

F_IN-

F_IN+

F_IN-

F_EQ

EQUALIZER

SIGNAL

DETECT

FA_OUT+

FA_OUT-

FB_OUT+

FB_OUT-

FA_ES

FB_ES

EQUALIZER

SIGNAL

DETECT

LOGIC

SIGNAL

DETECT

SIGNAL

DETECT

R_OUT+

R_OUT-

R_ES

RA_IN+

RA_IN-

RA_EQ

RB_IN+

RB_IN-

RB_EQ

CONTROL

LOGIC

CH_SEL

TEST#

F_SD

RA_SD

RB_SD

PI2EQX3421

3.2Gbps, 1:2 Port Switch, SATA2/SAS ReDriver™

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PI2EQX3421

3.2Gbps, 1:2 Port Switch, SATA2/SAS ReDriver™

Pin Description

Pin # Pin Name Type Description

25 CE Input Chip Enable "high" provides normal operation. "Low" for power down mode.

With internal 50K-Ohm pull-up resistor.

14 CH_SEL Input Channel Select "high" selects path A. "Low" selects path B. With internal 50K-

Ohm pull-up resistor.

28 F_EQ Input Selection pin for equalizer of Fin. "Low" means 2.5dB, "high" means 6.5dB. With

internal 50K-Ohm pull-up resistor.

F_IN+

F_IN- Input CML input channel F with internal 50-Ohm pull down.

2 F_SD Output Channel Fin Signal detector output. Provides "high" when a signal is detected.

26 FA_ES Input "High" means FA_OUT operates to the SATA i/m standard. "Low" means FA_

OUT support SATAx standard. With internal 50K-Ohm pull-up resistor.

FA_OUT+

FA_OUT- Output CML output channel FA with internal 50-Ohm pull up.

12 FB_ES Input "High" means FB_OUT operates to the SATA i/m standard. "Low" means FB_

OUT support SATAx standard. With internal 50K-Ohm pull-up resistor.

FB_OUT+

FB_OUT- Output CML output channel FB with internal 50-Ohm pull up.

Center Pad GND GND Supply ground.

13 R_ES Input "High" means Rout operates to the SATA i/m standard. "Low" means Rout sup-

port SATAx standard. With internal 50K-Ohm pull-up resistor.

27 RA_EQ Input Selection pin for equalizer of RA_IN. "Low" means 2.5dB, "high" means 6.5dB.

With internal 50K-Ohm pull-up resistor.

RA_IN+

RA_IN- Input CML input channel RA with internal 50-Ohm pull down.

1 RA_SD Output Signal detector for Channel RA_IN. Provides "high" when signal is detected.

11 RB_EQ Input Selection pin for equalizer of RB_IN. "Low" means 2.5dB, "high" means 6.5dB.

With internal 50K-Ohm pull-up resistor.

RB_IN+

RB_IN- Input CML input channel RB with internal 50-Ohm pull down.

10 RB_SD Output Signal detector for Channel RB_IN. Provides "high" when signal is detected.

R_OUT+

R_OUT- Output CML output channel R with internal 50-Ohm pull up.

3,6,7,17,22 VDD Power Positive Supply Voltage, 1.5V to 1.8V (±0.1V)

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PI2EQX3421

3.2Gbps, 1:2 Port Switch, SATA2/SAS ReDriver™

Equalizer Selection

x_EQ Compliance Channel @ 1.6 GHz

0 1.5dB ± 1.0dB

1 5.5dB ± 1.0dB

Output CML Buffer

CE CH_SEL X_ES FA_OUT FB_OUT R_OUT

0 X X VDD VDD VDD

1 0 0 VDD VDD-0.6V VDD-0.6V

1 0 1 VDD VDD-0.3V VDD-0.3V

1 1 0 VDD-0.6V VDD VDD-0.6V

1 1 1 VDD-0.3V VDD VDD-0.3V

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PI2EQX3421

3.2Gbps, 1:2 Port Switch, SATA2/SAS ReDriver™

Storage Temperature .......................................................... –65°C to +150°C

Supply Voltage to Ground Potential ...................................–0.5V to +2.5V

DC SIG Voltage ..........................................................–0.5V to VDD +0.5V

Current Output ................................................................-25mA to +25mA

Power Dissipation Continous ..........................................................500mW

Operating Temperature ............................................................... 0 to +70°C

Note:

Stresses greater than those listed under MAXIMUM RAT-

INGS may cause permanent damage to the device. is is a

stress rating only and functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this specication is not implied. Ex-

posure to absolute maximum rating conditions for extended

periods may aect reliability.

Maximum Ratings

(Above which useful life may be impaired. For user guidelines, not tested.)

AC/DC Electrical Characteristics (VDD = 1.4V to 1.9V)

Symbol Parameter Conditions Min. Typ. Max. Units

PSTANDBY Supply Power CE = LVCMOS Low 0.1 W

ACTIVE

Active Supply Power CE = LVCMOS High 0.3

Latency Input to Output 1.0 ns

Switch time, idle to active CH_Sel toggles 50 ns

CML Receiver Input

VRX-DIFFP-P Dierential Input Peak-to-

peak Voltage 0.200 V

VRX-CM-ACP AC Peak Common Mode

Input Voltage 150 mV

ZRX-DC DC Input Impedance 40 50 60

Ohm

ZRX-DIFF-DC DC Dierential Input

Impedance 85 100 115

Equalization

Residual Jitter(1,2) Total Jitter 0.3 Ulp-p

Random Jitter

(1,2)

1.5 psrms

Signal Detector Performance

VTH reshold CE = 1 65

(3)

200

(3)

mVppd

Enable/disable time 16 ns

Notes

1. K28.7 pattern is applied dierentially at point A as shown in Figure 1.

2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 × RJ + DJ) where RJ is random RMS jitter and DJ is maximum deterministic jitter.

Signal source is a K28.5 ± pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or equivalent for random jitter test. Re-

sidual jitter is that which remains aer equalizing media-induced losses of the environment of Figure 1 or its equivalent. e deterministic jitter at point B must

be from media-induced loss, and not from clock source modulation. JItter is measured at 0V at point C of Figure 1.

3. Using Compliance test at 1.5Gbps and 3Gbps. Also using OOB (OOB is formed by ALIGNp primitive or D24.3) test patterns at 1.5Gbps. e ALIGN primitive

(K28.5+D10.2+D27.3 = 0011111010+0101010101+0010011100). e D24.3 = 00110011001100110011

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PI2EQX3421

3.2Gbps, 1:2 Port Switch, SATA2/SAS ReDriver™

AC/DC Electrical Characteristics

Symbol Parameter Conditions Min. Typ. Max. Units

CML Transmitter Output (100-Ohm dierential)

VDIFFP

Output Voltage Swing

Dierential Swing(1) | VTX-D+

- VTX-D- |

x_ES=1 200 375

mVp-p

x_ES=0 550 650

VTX-DIFFP-P

Dierential Peak-to-peak Ou-

put Voltage(1) VTX-DIFFP-P = 2

* | VTX-D+ - VTX-D- |

x_ES=1 400 750 mV

x_ES=0 1000 1300

VTX-C

Common-Mode Voltage(1)

| VTX-D+ + VTX-D- | / 2

x_ES=1 VDD-0.6 mV

x_ES=0 VDD-0.3

tF, tRTransition Time 20% to 80% 150 ps

tF-tR / tF+tRTransition Mismatch Time 20% to 80% 20 %

ZOUT Output resistance Single ended 50 Ohm

ZTX-DIFF-DC DC Dierential TX Imped-

ance 80 100 120 Ohm

CTX AC Coupling Capacitor 0.3 4.7 12 nF

LVCMOS Control Pins

VIH Input High Voltage 0.65 ×

VDD V

VIL Input Low Voltage 0.35 ×

VDD

IIH Input High Current 250 µA

IIL Input Low Current 500

VOH DC Output Logic High IOH = 4mA VDD -

0.45 V

VOL DC Output Logic Low IOL = 4mA 0.4

Note:

1. When x_ES=0, select SATAx standard. When x_ES=1, select SATAI/m standard.

Pericom

PI2EQX3421

Signal

Source

SmA

Connector In Out

SmA

Connector

B C

FR4

30IN

Figure 1. Test Condition Referenced in the Electrical Characteristic Table

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PI2EQX3421

3.2Gbps, 1:2 Port Switch, SATA2/SAS ReDriver™

Packaging Mechanical: 28-contact TQFN (ZH)

Ordering Information

Ordering Number Package Code Package Description

PI2EQX3421ZHE ZH Pb-Free and Green 28-contact TQFN

Notes:

• ermal characteristics can be found on the company web site at www.pericom.com/packaging/

• E = Pb-free and Green

• X sux = Tape/Reel

Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com

DESCRIPTION: 28-Contact, Very Thin Quad Flat No-Lead, TQFN

PACKAGE CODE: ZH28

DOCUMENT CONTROL #: PD-2034 REVISION: B

DATE: 01/26/09

09-0066 Note: For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php

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