551600142-002/NOPB - Texas Instruments

SW L

LM3150

VCC

PGND

SGND

BST

ILIM

CIN

CSS

VIN VIN

RON

COUT

VOUT

CBST

CVCC VIN

RLIM RFB2

RFB1

LM3150

www.ti.com

SNVS561D –SEPTEMBER 2008–REVISED MARCH 2011

LM3150 SIMPLE SWITCHER

CONTROLLER, 42V Synchronous Step-Down

Check for Samples: LM3150

1FEATURES DESCRIPTION

The LM3150 SIMPLE SWITCHER®Controller is an

2• PowerWise®Step-down Controller easy to use and simplified step down power controller

• 6V to 42V Wide Input Voltage Range capable of providing up to 12A of output current in a

• Adjustable Output Voltage Down to 0.6V typical application. Operating with an input voltage

range of 6V-42V, the LM3150 features an adjustable

• Programmable Switching Frequency up to 1 output voltage down to 0.6V. The switching frequency

MHz is adjustable up to 1 MHz and the synchronous

• No Loop Compensation Required architecture provides for highly efficient designs. The

• Fully WEBENCH®Enabled LM3150 controller employs a Constant On-Time

(COT) architecture with a proprietary Emulated Ripple

• Low External Component Count Mode (ERM) control that allows for the use of low

• Constant On-Time Control ESR output capacitors, which reduces overall solution

• Ultra-fast Transient Response size and output voltage ripple. The Constant On-Time

(COT) regulation architecture allows for fast transient

• Stable with Low ESR Capacitors response and requires no loop compensation, which

• Output Voltage Pre-bias Startup reduces external component count and reduces

• Valley Current Limit design complexity.

• Programmable Soft-start Fault protection features such as thermal shutdown,

under-voltage lockout, over-voltage protection, short-

TYPICAL APPLICATIONS circuit protection, current limit, and output voltage pre-

bias startup allow for a reliable and robust solution.

• Telecom

• Networking Equipment The LM3150 SIMPLE SWITCHER®concept provides

for an easy to use complete design using a minimum

• Routers number of external components and TI’s WEBENCH®

• Security Surveillance online design tool. WEBENCH®provides design

• Power Modules support for every step of the design process and

includes features such as external component

calculation with a new MOSFET selector, electrical

simulation, thermal simulation, and Build-It boards for

prototyping.

Typical Application

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

411

VCC

SGND

PGND

RON

SGND

ILIM

BST

VIN

LM3150

SNVS561D –SEPTEMBER 2008–REVISED MARCH 2011

www.ti.com

Connection Diagram

Figure 1. TSSOP-14

PIN DESCRIPTIONS

Pin Name Description Function

Supply Voltage for FET Nominally regulated to 5.95V. Connect a 1.0 µF to 4.7 µF decoupling capacitor from

1 VCC Drivers this pin to ground.

2 VIN Input Supply Voltage Supply pin to the device. Nominal input range is 6V to 42V.

To enable the IC apply a logic high signal to this pin greater than 1.26V typical or leave

3 EN Enable floating. To disable the part, ground the EN pin.

Internally connected to the regulation, over-voltage, and short-circuit comparators. The

4 FB Feedback regulation setting is 0.6V at this pin. Connect to feedback resistor divider between the

output and ground to set the output voltage.

Ground for all internal bias and reference circuitry. Should be connected to PGND at a

5,9 SGND Signal Ground single point.

An internal 7.7 µA current source charges an external capacitor to provide the soft-start

6 SS Soft-Start function.

7 RON On-time Control An external resistor from VIN to this pin sets the high-side switch on-time.

Monitors current through the low-side switch and triggers current limit operation if the

8 ILIM Current Limit inductor valley current exceeds a user defined value that is set by RLIM and the Sense

current, ILIM-TH, sourced out of this pin during operation.

Switch pin of controller and high-gate driver lower supply rail. A boost capacitor is also

10 SW Switch Node connected between this pin and BST pin

Gate drive signal to the high-side NMOS switch. The high-side gate driver voltage is

11 HG High-Side Gate Drive supplied by the differential voltage between the BST pin and SW pin.

High-gate driver upper supply rail. Connect a 0.33 µF-0.47 µF capacitor from SW pin to

Connection for Bootstrap

12 BST this pin. An internal diode charges the capacitor during the high-side switch off-time. Do

Capacitor not connect to an external supply rail.

Gate drive signal to the low-side NMOS switch. The low-side gate driver voltage is

13 LG Low-Side Gate Drive supplied by VCC.

Synchronous rectifier MOSFET source connection. Tie to power ground plane. Should

14 PGND Power Ground be tied to SGND at a single point.

Exposed die attach pad should be connected directly to SGND. Also used to help

EP EP Exposed Pad dissipate heat out of the IC.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Product Folder Links: LM3150

LM3150

www.ti.com

SNVS561D –SEPTEMBER 2008–REVISED MARCH 2011

Absolute Maximum Ratings(1)(2)

VIN, RON to GND -0.3V to 47V

SW to GND -3V to 47V

BST to SW -0.3V to 7V

BST to GND -0.3V to 52V

All Other Inputs to GND -0.3V to 7V

ESD Rating(3) 2 kV

Storage Temperature Range -65°C to +150°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and conditions,

see the Electrical Characteristics.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(3) The human body model is a 100 pF capacitor discharged through a 1.5 kΩresistor into each pin. Test Method is per JESD-22-A114.

Operating Ratings(1)

VIN 6V to 42V

Junction Temperature Range (TJ)−40°C to + 125°C

EN 0V to 5V

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and conditions,

see the Electrical Characteristics.

Electrical Characteristics

Limits in standard type are for TJ= 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C

to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent

the most likely parametric norm at TJ= 25°C, and are provided for reference purposes only. Unless otherwise stated the

following conditions apply: VIN = 18V.

Symbol Parameter Conditions Min Typ Max Units

Start-Up Regulator, VCC

VCC CVCC = 1 µF, 0 mA to 40 mA 5.65 5.95 6.25 V

IVCC = 2 mA, VIN = 5.5V 40

VIN - VCC VIN - VCC Dropout Voltage mV

IVCC = 30 mA, VIN = 5.5V 330

IVCCL VCC Current Limit(1) VCC = 0V 65 100 mA

VCC Under-Voltage Lockout Threshold

VCCUVLO VCC Increasing 4.75 5.1 5.40 V

(UVLO)

VCCUVLO-HYS VCC UVLO Hysteresis VCC Decreasing 475 mV

tCC-UVLO-D VCC UVLO Filter Delay 3 µs

IIN Input Operating Current No Switching, VFB = 1V 3.5 5mA

IIN-SD Input Operating Current, Device Shutdown VEN = 0V 32 55 µA

GATE Drive

IQ-BST Boost Pin Leakage VBST – VSW = 6V 2 nA

RDS-HG-Pull-Up HG Drive Pull–Up On-Resistance IHG Source = 200 mA 5 Ω

RDS-HG-Pull-Down HG Drive Pull–Down On-Resistance IHG Sink = 200 mA 3.4 Ω

RDS-LG-Pull-Up LG Drive Pull–Up On-Resistance ILG Source = 200 mA 3.4 Ω

RDS-LG-Pull-Down LG Drive Pull–Down On-Resistance ILG Sink = 200 mA 2 Ω

Soft-Start

ISS SS Pin Source Current VSS = 0V 5.9 7.7 9.5 µA

ISS-DIS SS Pin Discharge Current 200 µA

Current Limit

ILIM-TH Current Limit Sense Pin Source Current 75 85 95 µA

(1) VCC provides self bias for the internal gate drive and control circuits. Device thermal limitations limit external loading.

Product Folder Links: LM3150

LM3150

SNVS561D –SEPTEMBER 2008–REVISED MARCH 2011

www.ti.com

Electrical Characteristics (continued)

Limits in standard type are for TJ= 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C

to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent

the most likely parametric norm at TJ= 25°C, and are provided for reference purposes only. Unless otherwise stated the

following conditions apply: VIN = 18V.

Symbol Parameter Conditions Min Typ Max Units

ON/OFF Timer

VIN = 10V, RON = 100 kΩ,1.02

VFB = 0.6V

VIN = 18V, RON = 100 kΩ,

tON ON Timer Pulse Width 0.62 µs

VFB = 0.6V

VIN = 42V, RON = 100 kΩ,0.36

VFB = 0.6V

tON-MIN ON Timer Minimum Pulse Width See(2) 200 ns

tOFF OFF Timer Minimum Pulse Width 370 525 ns

Enable Input

VEN EN Pin Input Threshold Trip Point VEN Rising 1.14 1.20 1.26 V

VEN-HYS EN Pin Threshold Hysteresis VEN Falling 120 mV

Regulation and Over-Voltage Comparator

VFB In-Regulation Feedback Voltage VSS > 0.6V 0.588 0.600 0.612 V

VFB-OV Feedback Over-Voltage Threshold 0.690 0.720 0.748 V

IFB Feedback Bias Current 20 nA

Boost Diode

Forward Voltage IBST = 2 mA 0.7

VfV

IBST = 30 mA 1

Thermal Characteristics

Thermal Shutdown Rising 165 °C

TSD Thermal Shutdown Hysteresis Falling 15 °C

4 Layer JEDEC Printed Circuit 40

Board, 9 Vias, No Air Flow

θJA Junction to Ambient °C/W

2 Layer JEDEC Printed Circuit 140

Board. No Air Flow

θJC Junction to Case No Air Flow 4 °C/W

(2) See Theory of Operation section for minimum on-time when using MOSFETs connected to gate drivers.

Product Folder Links: LM3150

CBST

BST

ON TIMER

Ron START

COMPLETE

UVLO THERMAL

SHUTDOWN

LEVEL

SHIFT L

LM3150

AVDD

DRIVER

REGULATION

COMPARATOR

VDD

LOGIC DrvH

DrvL

CURRENT LIMIT

COMPARATOR

DRIVER

GND

Vbias

VDD

toff

OFF TIMER

PMOS

input

VIN

RON

VIN

CVCC

VCC

PGND

CIN

RON

VCC

CSS

SGND

VDD

ILIM

ERM CONTROL

Zero

Current

Detect

VCC

1.20V

6V LDO 0.72V

0.6V

VIN

VOUT

COUT

RFB1

RFB2

RLIM

ILIM-TH

START

COMPLETE

0.72V

ISS

VFB-OV and

SHORT

CIRCUIT

PROTECTION

1.20V

GND

0.36V

1 M5

Vref = 0.6V

LM3150

www.ti.com

SNVS561D –SEPTEMBER 2008–REVISED MARCH 2011

Simplified Block Diagram

Product Folder Links: LM3150

LM3150

SNVS561D –SEPTEMBER 2008–REVISED MARCH 2011

www.ti.com

Typical Performance Characteristics

Boost Diode Forward Voltage ILIM-TH

vs. vs.

Temperature Temperature

Figure 2. Figure 3.

Quiescent Current Soft-Start Current

vs. vs.

Temperature Temperature

Figure 4. Figure 5.

tON tON

vs. vs.

Temperature Temperature

Figure 6. Figure 7.

Product Folder Links: LM3150

LM3150

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SNVS561D –SEPTEMBER 2008–REVISED MARCH 2011

Typical Performance Characteristics (continued)

tON VCC Current Limit

vs. vs.

Temperature Temperature

Figure 8. Figure 9.

VCC Dropout VCC

vs. vs.

Temperature Temperature

Figure 10. Figure 11.

Product Folder Links: LM3150

VOUT = VFB x (RFB1 + RFB2)

RFB1

fS = VOUT

K x RON

D = tON

tON + tOFF = tON x fS |VOUT

VIN

RON = K x fS

VOUT

tON = K x RON

VIN

LM3150

SNVS561D –SEPTEMBER 2008–REVISED MARCH 2011

www.ti.com

THEORY OF OPERATION

The LM3150 synchronous step-down SIMPLE SWITCHER®Controller utilizes a Constant On-Time (COT)

architecture which is a derivative of the hysteretic control scheme. COT relies on a fixed switch on-time to

regulate the output. The on-time of the high-side switch can be set manually by adjusting the size of an external

resistor (RON). To maintain a relatively constant switching frequency as VIN varies, the LM3150 automatically

adjusts the on-time inversely with the input voltage. Assuming an ideal system and VIN is much greater than 1V,

the following approximations can be made:

The on-time, tON:

where

• constant K = 100 pC (1)

The RON resistance value can be calculated as follows:

where

• fsis the desired switching frequency (2)

Control is based on a comparator and the on-timer, with the output voltage feedback (FB) compared with an

internal reference of 0.6V. If the FB level is below the reference, the high-side switch is turned on for a fixed time,

tON, which is determined by the input voltage and the resistor RON. Following this on-time, the switch remains off

for a minimum off-time, tOFF, as specified in the Electrical Characteristics table or until the FB pin voltage is below

the reference, then the switch turns on again for another on-time period. The switching will continue in this

fashion to maintain regulation. During continuous conduction mode (CCM), the switching frequency ideally

depends on duty-cycle and on-time only. In a practical application however, there is a small delay in the time that

the HG goes low and the SW node goes low that also affects the switching frequency that is accounted for in the

typical application curves. The duty-cycle and frequency can be approximated as:

(3)

(4)

Typical COT hysteretic controllers need a significant amount of output capacitor ESR to maintain a minimum

amount of ripple at the FB pin in order to switch properly and maintain efficient regulation. The LM3150 however,

utilizes a proprietary Emulated Ripple Mode control scheme (ERM) that allows the use of low ESR output

capacitors. Not only does this reduce the need for high output capacitor ESR, but also significantly reduces the

amount of output voltage ripple seen in a typical hysteretic control scheme. The output ripple voltage can

become so low that it is comparable to voltage-mode and current-mode control schemes.

Programming the Output Voltage

The output voltage is set by two external resistors (RFB1,RFB2). The regulated output voltage is calculated as

follows:

where

• RFB2 is the top resistor connected between VOUT and FB

• RFB1 is the bottom resistor connected between FB and GND (5)

Regulation Comparator

The feedback voltage at FB is compared to the internal reference voltage of 0.6V. In normal operation (the output

voltage is regulated), an on-time period is initiated when the voltage at FB falls below 0.6V. The high-side switch

stays on for the on-time, causing the FB voltage to rise above 0.6V. After the on-time period, the high-side switch

stays off until the FB voltage falls below 0.6V.

Product Folder Links: LM3150

'IL = (VIN - VOUT) x tON

Ivalley = IOUT - 'IL

RLIM = ICL x RDS(ON)max

ILIM-TH

ICL = IOCL - 'IL

LM3150

www.ti.com

SNVS561D –SEPTEMBER 2008–REVISED MARCH 2011

Over-Voltage Comparator

The over-voltage comparator is provided to protect the output from over-voltage conditions due to sudden input

line voltage changes or output loading changes. The over-voltage comparator continuously monitors the voltage

at the FB pin and compares it to a 0.72V internal reference. If the voltage at FB rises above 0.72V, the on-time

pulse is immediately terminated. This condition can occur if the input or the output load changes suddenly. Once

the over-voltage protection is activated, the HG and LG signals remain off until the voltage at FB pin falls below

0.72V.

Current Limit

Current limit detection occurs during the off-time by monitoring the current through the low-side switch using an

external resistor, RLIM. If during the off-time the current in the low-side switch exceeds the user defined current

limit value, the next on-time cycle is immediately terminated. Current sensing is achieved by comparing the

voltage across the low side FET with the voltage across the current limit set resistor RLIM. If the voltage across

RLIM and the voltage across the low-side FET are equal then the current limit comparator will terminate the next

on-time cycle.

The RLIM value can be approximated as follows:

(6)

where

• IOCL is the user-defined average output current limit value

• RDS(ON)max is the resistance value of the low-side FETat the expected maximum FET junction temperature

• ILIM-TH is an internal current supply of 85 µA typical (7)

Figure 12 illustrates the inductor current waveform. During normal operation, the output current ripple is dictated

by the switching of the FETs. The current through the low-side switch, Ivalley, is sampled at the end of each

switching cycle and compared to the current limit, ICL, current. The valley current can be calculated as follows:

where

• IOUT is the average output current

•ΔILis the peak-to-peak inductor ripple current (8)

If an overload condition occurs, the current through the low-side switch will increase which will cause the current

limit comparator to trigger the logic to skip the next on-time cycle. The IC will then try to recover by checking the

valley current during each off-time. If the valley current is greater than or equal to ICL, then the IC will keep the

low-side FET on and allow the inductor current to further decay.

Throughout the whole process, regardless of the load current, the on-time of the controller will stay constant and

thereby the positive ripple current slope will remain constant. During each on-time the current ramps-up an

amount equal to:

(9)

The valley current limit feature prevents current runaway conditions due to propagation delays or inductor

saturation since the inductor current is forced to decay following any overload conditions.

Current sensing is achieved by either a low value sense resistor in series with the low-side FET or by utilizing the

RDS(ON) of the low-side FET. The RDS(ON) sensing method is the preferred choice for a more simplified design and

lower costs. The RDS(ON) value of a FET has a positive temperature coefficient and will increase in value as the

FET’s temperature increases. The LM3150 controller will maintain a more stable current limit that is closer to the

original value that was set by the user, by positively adjusting the ILIM-TH value as the IC temperature increases.

This does not provide an exact temperature compensation but allows for a more tightly controlled current limit

when compared to traditional RDS(ON) sensing methods when the RDS(ON) value can change typically 140% from

room to maximum temperature and cause other components to be over-designed. The temperature

compensated ILIM-TH is shown below where TJis the die temperature of the LM3150 in Celsius:

Product Folder Links: LM3150

ICL

IPK

IOCL

IOUT

Inductor Current

Load Current

Increases

Normal Operation Current Limited

tSS = Vref x CSS

ISS

LM3150

SNVS561D –SEPTEMBER 2008–REVISED MARCH 2011

www.ti.com

ILIM-TH(TJ) = ILIM-TH x [1 + 3.3 x 10-3 x (TJ- 27)] (10)

To calculate the RLIM value with temperature compensation, substitute equation (10) into ILIM-TH in equation (7).

Short-Circuit Protection

The LM3150 will sense a short-circuit on the output by monitoring the output voltage. When the feedback voltage

has fallen below 60% of the reference voltage, Vref x 0.6 (≈0.36V), short-circuit mode of operation will start.

During short-circuit operation, the SS pin is discharged and the output voltage will fall to 0V. The SS pin voltage,

VSS, is then ramped back up at the rate determined by the SS capacitor and ISS until VSS reaches 0.7V. During

this re-ramp phase, if the short-circuit fault is still present the output current will be equal to the set current limit.

Once the soft-start voltage reaches 0.7V the output voltage is sensed again and if the VFB is still below Vref x 0.6

then the SS pin is discharged again and the cycle repeats until the short-circuit fault is removed.

Soft-Start

The soft-start (SS) feature allows the regulator to gradually reach a steady-state operating point, which reduces

start-up stresses and current surges. At turn-on, while VCC is below the under-voltage threshold, the SS pin is

internally grounded and VOUT is held at 0V. The SS capacitor is used to slowly ramp VFB from 0V to 0.6V. By

changing the capacitor value, the duration of start-up can be changed accordingly. The start-up time can be

calculated using the following equation:

where

• tSS is measured in seconds

• Vref = 0.6V

• ISS is the soft-start pin source current, which is typically 7.7 µA (refer to Electrical Characteristics table) (11)

An internal switch grounds the SS pin if VCC is below the under-voltage lockout threshold, if a thermal shutdown

occurs, or if the EN pin is grounded. By using an externally controlled switch, the output voltage can be shut off

by grounding the SS pin.

During startup the LM3150 will operate in diode emulation mode, where the low-side gate LG will turn off and

remain off when the inductor current falls to zero. Diode emulation mode will allow start-up into a pre-biased

output voltage. When soft-start is greater than 0.7V, the LM3150 will remain in continuous conduction mode.

During diode emulation mode at current limit the low-gate will remain off when the inductor current is off.

Figure 12. Inductor Current - Current Limit Operation

The soft-start time should be greater than the input voltage rise time and also satisfy the following equality to

maintain a smooth transition of the output voltage to the programmed regulation voltage during startup.

tSS ≥(VOUT x COUT) / (IOCL - IOUT) (12)

Product Folder Links: LM3150

VOUT = VFB x (RFB1 + RFB2)

RFB1

LM3150

www.ti.com

SNVS561D –SEPTEMBER 2008–REVISED MARCH 2011

Enable/Shutdown

The EN pin can be activated by either leaving the pin floating due to an internal pull up resistor to VIN or by

applying a logic high signal to the EN pin of 1.26V or greater. The LM3150 can be remotely shut down by taking

the EN pin below 1.02V. Low quiescent shutdown is achieved when VEN is less than 0.4V. During low quiescent

shutdown the internal bias circuitry is turned off.

The LM3150 has certain fault conditions that can trigger shutdown, such as over-voltage protection, current limit,

under-voltage lockout, or thermal shutdown. During shutdown, the soft-start capacitor is discharged. Once the

fault condition is removed, the soft-start capacitor begins charging, allowing the part to start-up in a controlled

fashion. In conditions where there may be an open drain connection to the EN pin, it may be necessary to add a

1 nF bypass capacitor to this pin. This will help decouple noise from the EN pin and prevent false disabling.

Thermal Protection

The LM3150 should be operated such that the junction temperature does not exceed the maximum operating

junction temperature. An internal thermal shutdown circuit, which activates at 165°C (typical), takes the controller

to a low-power reset state by disabling the buck switch and the on-timer, and grounding the SS pin. This feature

helps prevent catastrophic failures from accidental device overheating. When the junction temperature falls back

below 150°C the SS pin is released and device operation resumes.

Design Guide

The design guide provides the equations required to design with the LM3150 SIMPLE SWITCHER®Controller.

WEBENCH®design tool can be used with or in place of this section for a more complete and simplified design

process.

1. Define Power Supply Operating Conditions

a. Required Output Voltage

b. Maximum and Minimum DC Input Voltage

c. Maximum Expected Load Current during Normal Operation

d. Soft-Start Time

2. Set Output Voltage With Feedback Resistors

where

• RFB1 is the bottom resistor

• RFB2 is the top resistor (13)

3. Determine RON and fs

The available frequency range for a given input voltage range, is determined by the duty-cycle, D = VOUT/VIN, and

the minimum tON and tOFF times as specified in the Electrical Characteristics table. The maximum frequency is

thus, fsmax = Dmin/tON-MIN. Where Dmin=VOUT/VIN-MAX, is the minimum duty-cycle. The off-time will need to be less

than the minimum off-time tOFF as specified in the Electrical Characteristics table plus any turn off and turn on

delays of the MOSFETs which can easily add another 200 ns. The minimum off-time will occur at maximum duty

cycle Dmax and will determine if the frequency chosen will allow for the minimum desired input voltage. The

requirement for minimum off-time is tOFF= (1–Dmax)/fs≥(tOFF-MIN + 200 ns). If tOFF does not meet this requirement

it will be necessary to choose a smaller switching frequency fS.

Choose RON so that the switching frequency at your typical input voltage matches your fSchosen above using

the following formula:

RON = [(VOUT x VIN)-VOUT] / (VIN x K x fS) + ROND (14)

ROND = - [(VIN - 1) x (VIN x 16.5 + 100)] - 1000 (15)

Use Figure 13 to determine if the calculated RON will allow for the minimum desired input voltage. If the minimum

desired input voltage is not met, recalculate RON for a lower switching frequency.

Product Folder Links: LM3150

ET = (Vinmax ± VOUT) x Vinmax

VOUT xfS

1000 (V x Ps)

LM3150

SNVS561D –SEPTEMBER 2008–REVISED MARCH 2011

www.ti.com

Figure 13. Minimum VIN vs. VOUT

IOUT = 10 A

4. Determine Inductor Required Using Figure 14

To use the nomograph in Figure 14, calculate the inductor volt-microsecond constant ET from the following

formula:

where

• fsis in kHz units (16)

The intersection of the Load Current and the Volt-microseconds lines on the chart below will determine which

inductors are capable for use in the design. The chart shows a sample of parts that can be used. The offline

calculator tools and WEBENCH®will fully calculate the requirements for the components needed for the design.

Product Folder Links: LM3150

L36

L35

MAXIMUM LOAD CURRENT (A)

4 5 6 7 8 9 10 12

100 L01

L02

L03

L04

L05

L06

L07

L08

L09

L10

L11

L12

L13

L14

L15

L16

L17

L18

L19

L20

L21

L22

L23

L24

L34

L33

L32

L25

L26

L27

L28

L29

L30

L31

L48

L47

L46

L45

L44

L37

L38

L39

L40

L41

L42

L43

E À T (V À Ps)

47 PH

33 PH

22 PH

15 PH

10 PH

6.8 PH

4.7 PH

3.3 PH

2.2 PH

1.5 PH

1.0 PH

0.68 PH

0.47 PH

0.33 PH

LM3150

www.ti.com

SNVS561D –SEPTEMBER 2008–REVISED MARCH 2011

Figure 14. Inductor Nomograph

Table 1. Inductor Selection Table

Inductor Designator Inductance Current Part Name Vendor

(µH) (A)

L01 47 7-9

L02 33 7-9 SER2817H-333KL COILCRAFT

L03 22 7-9 SER2814H-223KL COILCRAFT

L04 15 7-9 7447709150 WURTH

L05 10 7-9 RLF12560T-100M7R5 TDK

L06 6.8 7-9 B82477-G4682-M EPCOS

L07 4.7 7-9 B82477-G4472-M EPCOS

L08 3.3 7-9 DR1050-3R3-R COOPER

L09 2.2 7-9 MSS1048-222 COILCRAFT

L10 1.5 7-9 SRU1048-1R5Y BOURNS

L11 1 7-9 DO3316P-102 COILCRAFT

L12 0.68 7-9 DO3316H-681 COILCRAFT

L13 33 9-12

L14 22 9-12 SER2918H-223 COILCRAFT

L15 15 9-12 SER2814H-153KL COILCRAFT

L16 10 9-12 7447709100 WURTH

L17 6.8 9-12 SPT50H-652 COILCRAFT

L18 4.7 9-12 SER1360-472 COILCRAFT

L19 3.3 9-12 MSS1260-332 COILCRAFT

L20 2.2 9-12 DR1050-2R2-R COOPER

L21 1.5 9-12 DR1050-1R5-R COOPER

L22 1 9-12 DO3316H-102 COILCRAFT

L23 0.68 9-12

L24 0.47 9-12

L25 22 12-15 SER2817H-223KL COILCRAFT

Product Folder Links: LM3150

LM3150

SNVS561D –SEPTEMBER 2008–REVISED MARCH 2011

www.ti.com

Table 1. Inductor Selection Table (continued)

Inductor Designator Inductance Current Part Name Vendor

(µH) (A)

L26 15 12-15

L27 10 12-15 SER2814L-103KL COILCRAFT

L28 6.8 12-15 7447709006 WURTH

L29 4.7 12-15 7447709004 WURTH

L30 3.3 12-15

L31 2.2 12-15

L32 1.5 12-15 MLC1245-152 COILCRAFT

L33 1 12-15

L34 0.68 12-15 DO3316H-681 COILCRAFT

L35 0.47 12-15

L36 0.33 12-15 DR73-R33-R COOPER

L37 22 15-

L38 15 15- SER2817H-153KL COILCRAFT

L39 10 15- SER2814H-103KL COILCRAFT

L40 6.8 15-

L41 4.7 15- SER2013-472ML COILCRAFT

L42 3.3 15- SER2013-362L COILCRAFT

L43 2.2 15-

L44 1.5 15- HA3778–AL COILCRAFT

L45 1 15- B82477-G4102-M EPCOS

L46 0.68 15-

L47 0.47 15-

L48 0.33 15-

5. Determine Output Capacitance

Typical hysteretic COT converters similar to the LM3150 require a certain amount of ripple that is generated

across the ESR of the output capacitor and fed back to the error comparator. Emulated Ripple Mode control built

into the LM3150 will recreate a similar ripple signal and thus the requirement for output capacitor ESR will

decrease compared to a typical Hysteretic COT converter. The emulated ripple is generated by sensing the

voltage signal across the low-side FET and is then compared to the FB voltage at the error comparator input to

determine when to initiate the next on-time period.

COmin = 70 / (fs2x L) (17)

The maximum ESR allowed to prevent over-voltage protection during normal operation is:

ESRmax = (80 mV x L x Af) / ETmin (18)

ETmin is calculated using VIN-MIN

Af= VOUT / 0.6 if there is no feed-forward capacitor used

Af= 1 if there is a feed-forward capacitor used

The minimum ESR must meet both of the following criteria:

ESRmin ≥(15 mV x L x Af) / ETmax (19)

ESRmin ≥[ ETmax / (VIN - VOUT) ] x (Af/ CO) (20)

ETmax is calculated using VIN-MAX.

Any additional parallel capacitors should be chosen so that their effective impedance will not negatively attenuate

the output ripple voltage.

6. Determine The Use of Feed-Forward Capacitor

Certain applications may require a feed-forward capacitor for improved stability and easier selection of available

output capacitance. Use the following equation to calculate the value of Cff.

Product Folder Links: LM3150

CIN = Iomax x D x (1-D)

fs x 'VIN-MAX

RLIM (Tj) = ICL x RDS(ON)max

ILIM-TH (Tj)

LM3150

www.ti.com

SNVS561D –SEPTEMBER 2008–REVISED MARCH 2011

ZFB = (RFB1 x RFB2)/(RFB1 + RFB2) (21)

Cff = VOUT/(VIN-MIN x fSx ZFB) (22)

7. MOSFET and RLIM Selection

The high-side and low-side FETs must have a drain to source (VDS) rating of at least 1.2 x VIN.

Use the following equations to calculate the desired target value of the low-side FET RDS(ON) for current limit.

(23)

ILIM-TH(Tj) = ILIM-TH x [1 + 3.3 x 10-3 x (Tj- 27)] (24)

The gate drive current from VCC must not exceed the minimum current limit of VCC. The drive current from VCC

can be calculated with:

IVCCdrive = Qgtotal x fS

where

• Qgtotal is the combined total gate charge of the high-side and low-side FETs (25)

The plateau voltage of the FET VGS vs Qgcurve, as shown in Figure 15, must be less than VCC - 750 mV.

Figure 15. Typical MOSFET Gate Charge Curve

See following design example for estimated power dissipation calculation.

8. Calculate Input Capacitance

The main parameters for the input capacitor are the voltage rating, which must be greater than or equal to the

maximum DC input voltage of the power supply, and its rms current rating. The maximum rms current is

approximately 50% of the maximum load current.

where

•ΔVIN-MAX is the maximum allowable input ripple voltage (26)

A good starting point for the input ripple voltage is 5% of VIN.

When using low ESR ceramic capacitors on the input of the LM3150 a resonant circuit can be formed with the

impedance of the input power supply and parasitic impedance of long leads/PCB traces to the LM3150 input

capacitors. It is recommended to use a damping capacitor under these circumstances, such as aluminum

electrolytic that will prevent ringing on the input. The damping capacitor should be chosen to be approximately 5

times greater than the parallel ceramic capacitors combination. The total input capacitance should be greater

than 10 times the input inductance of the power supply leads/pcb trace. The damping capacitor should also be

chosen to handle its share of the rms input current which is shared proportionately with the parallel impedance of

the ceramic capacitors and aluminum electrolytic at the LM3150 switching frequency.

The CBYP capacitor should be placed directly at the VIN pin. The recommended value is 0.1 µF.

Product Folder Links: LM3150

RFB2 = 4.99 k:3.3V

0.6V-1

RFB2 = RFB1 VOUT

VFB -1

SW L

LM3150

VCC

PGND

SGND

BST

ILIM

CBYP

CSS

VIN VIN

RON

COUT

VOUT

CBST

CVCC

VIN

RLIM

RFB2

RFB1

CEN

CFF

CIN

CSS = ISS x tSS

Vref

LM3150

SNVS561D –SEPTEMBER 2008–REVISED MARCH 2011

www.ti.com

9. Calculate Soft-Start Capacitor

where

• tss is the soft-start time in seconds

• Vref = 0.6V (27)

10. CVCC, CBST and CEN

CVCC should be placed directly at the VCC pin with a recommended value of 1 µF to 4.7 µF. CBST creates a

voltage used to drive the gate of the high-side FET. It is charged during the SW off-time. The recommended

value for CBST is 0.47 µF. The EN bypass capacitor, CEN, recommended value is 1000 pF when driving the EN

pin from open drain type of signal.

Design Example

Figure 16. Design Example Schematic

1.Define Power Supply Operating Conditions

a. VOUT = 3.3V

b. VIN-MIN = 6V, VIN-TYP = 12V, VIN-MAX = 24V

c. Typical Load Current = 12A, Max Load Current = 15A

d. Soft-Start time tSS = 5 ms

2. Set Output Voltage with Feedback Resistors

RFB2 = 22.455 kΩ

RFB2 = 22.6 kΩ, nearest 1% standard value.

3. Determine RON and fS

Dmin = VOUT/VIN-MAX

Dmin = 3.3V/24V = 0.137

Dmax = 3.3V / 6V = 0.55

fsmax = 0.137/ 200 ns = 687 kHz

Dmax = VOUT/VIN-MIN

Product Folder Links: LM3150

Irmsco = 12 x 12

0.3

Irmsco = IOUT x 12

LM3150

www.ti.com

SNVS561D –SEPTEMBER 2008–REVISED MARCH 2011

tOFF = (1-0.55)/687 kHz = 654 ns

tOFF should meet the following criteria:

tOFF > tOFF-MIN + 200 ns

tOFF > 725 ns

At the maximum switching frequency of 687 kHz, which is limited by the minimum on-time, the off-time of 654 ns

is less than 725 ns. Therefore the switching frequency should be reduced and meet the following criteria:

fs< (1 - D)/725 ns

fS< (1 - 0.55)/725 ns = 620 kHz

A switching frequency is arbitrarily chosen at 500 kHz which should allow for reasonable size components and

satisfies the requirements above.

fS= 500 kHz

Using fS= 500 kHz RON can be calculated as follows:

RON = [(VOUT x VIN)-VOUT] / (VIN x K x fS) + ROND

ROND = - [(VIN - 1) x (VIN x 16.5 + 100)] - 1000

ROND = - [(12 - 1) x (12 x 16.5 + 100)] -1000

ROND = -4.3 kΩ

RON = [(3.3 x 12) - 3.3] / (12 x 100 pC x 500 kHz) - 4.3 kΩ

RON = 56.2 kΩ

Next, check the desired minimum input voltage for RON using Figure 13. This design will meet the desired

minimum input voltage of 6V.

4. Determine Inductor Required

a. ET = (24-3.3) x (3.3/24) x (1000/500) = 5.7 V µs

b. From the inductor nomograph a 12A load and 5.7 V µs calculation corresponds to a L44 type of inductor.

c. Using the inductor designator L44 in Table 1 the Coilcraft HA3778–AL 1.65 µH inductor is chosen.

5. Determine Output Capacitance

The voltage rating on the output capacitor should be greater than or equal to the output voltage. As a rule of

thumb most capacitor manufacturers suggests not to exceed 90% of the capacitor rated voltage. In the case of

multilayer ceramics the capacitance will tend to decrease dramatically as the applied voltage is increased

towards the capacitor rated voltage. The capacitance can decrease by as much as 50% when the applied

voltage is only 30% of the rated voltage. The chosen capacitor should also be able to handle the rms current

which is equal to:

For this design the chosen ripple current ratio, r = 0.3, represents the ratio of inductor peak-to-peak current to

load current IOUT. A good starting point for ripple ratio is 0.3 but it is acceptable to choose r between 0.25 to 0.5.

The nomographs in this datasheet all use 0.3 as the ripple current ratio.

Irmsco = 1A

tON = (3.3V/12V)/500 kHz = 550 ns

Minimum output capacitance is:

COmin = 70 / (fs2x L)

COmin = 70 / (500 kHz2x 1.65 µH) = 169 µF

The maximum ESR allowed to prevent over-voltage protection during normal operation is:

ESRmax = (80 mV x L x Af) / ET

Af= VOUT / 0.6 without a feed-forward capacitor

Af= 1 with a feed-forward capacitor

Product Folder Links: LM3150

Pdh = 0.396 + 0.278 = 0.674W

Pcond = Iout2 x RDS(ON) x D

8.5

Vcc - Vth +6.8

Vth

2x Vin x Iout x Qgd x fs x

Psw =

Pdh = Pcond + Psw

Pcond = 122 x 0.01 x 0.275 = 0.396W

8.5

6 ± 2.5 +6.8

2.5

2x 12 x 12 x 1.5 nC x 500 kHz x

Psw = = 0.278W

Cff = VIN-MIN x fs

VOUT xRFB1 + RFB2

RFB1 x RFB2

Cff = 6V x 500 kHz

3.3V x4.99 k: + 22.6 k:

4.99 k: x 22.6 k:= 269 pF

LM3150

SNVS561D –SEPTEMBER 2008–REVISED MARCH 2011

www.ti.com

For this design a feed-forward capacitor will be used to help minimize output ripple.

ESRmax = (80 mV x 1.65 µH x 1) / 5.7 V µs

ESRmax = 23 mΩ

The minimum ESR must meet both of the following criteria:

ESRmin ≥(15 mV x L x Af) / ET

ESRmin ≥[ ET / (VIN - VOUT) ] x (Af/ CO)

ESRmin ≥(15 mV x 1.65 µH x 1) / 5.7 V µs = 4.3 mΩ

ESRmin ≥[5.7 V µs / (12 - 3.3) ] x (1 / 169 µF) = 3.9 mΩ

Based on the above criteria two 150 µF polymer aluminum capacitors with a ESR = 12 mΩeach for a effective

ESR in parallel of 6 mΩwas chosen from Panasonic. The part number is EEF-UE0J101P.

6. Determine Use of Feed-Forward Capacitor

From step 5 the capacitor chosen in ESR is small enough that we should use a feed-forward capacitor. This is

calculated from:

Let Cff = 270 pF, which is the closest next standard value.

7. MOSFET and RLIM Selection

The LM3150 is designed to drive N-channel MOSFETs. For a maximum input voltage of 24V we should choose

N-channel MOSFETs with a maximum drain-source voltage, VDS, greater than 1.2 x 24V = 28.8V. FETs with

maximum VDS of 30V will be the first option. The combined total gate charge Qgtotal of the high-side and low-side

FET should satisfy the following:

Qgtotal ≤IVCCL / fs

Qgtotal ≤65 mA / 500 kHz

Qgtotal ≤130 nC

Where IVCCL is the minimum current limit of VCC, over the temperature range, specified in the Electrical

Characteristics table. The MOSFET gate charge Qgis gathered from reading the VGS vs Qgcurve of the

MOSFET datasheet at the VGS = 5V for the high-side, M1, MOSFET and VGS = 6V for the low-side, M2,

MOSFET.

The Renesas MOSFET RJK0305DPB has a gate charge of 10 nC at VGS = 5V, and 12 nC at VGS = 6V. This

combined gate charge for a high-side, M1, and low-side, M2, MOSFET 12 nC + 10 nC = 22 nC is less than 130

nC calculated Qgtotal.

The calculated MOSFET power dissipation must be less than the max allowed power dissipation, Pdmax, as

specified in the MOSFET datasheet. An approximate calculation of the FET power dissipated Pd, of the high-side

and low-side FET is given by:

High-Side MOSFET

Product Folder Links: LM3150

LM3150

www.ti.com

SNVS561D –SEPTEMBER 2008–REVISED MARCH 2011

The max power dissipation of the RJK0305DPB is rated as 45W for a junction temperature that is 125°C higher

than the case temperature and a thermal resistance from the FET junction to case, θJC, of 2.78°C/W. When the

FET is mounted onto the PCB, the PCB will have some additional thermal resistance such that the total system

thermal resistance of the FET package and the PCB, θJA, is typically in the range of 30°C/W for this type of FET

package. The max power dissipation, Pdmax, with the FET mounted onto a PCB with a 125°C junction

temperature rise above ambient temperature and θJA = 30°C/W, can be estimated by:

Pdmax = 125°C / 30°C/W = 4.1W

The system calculated Pdh of 0.674W is much less than the FET Pdmax of 4.1W and therefore the

RJK0305DPB max allowable power dissipation criteria is met.

Low-Side MOSFET

Primary loss is conduction loss given by:

Pdl = Iout2x RDS(ON) x (1-D) = 122x 0.01 x (1-0.275) = 1W

Pdl is also less than the Pdmax specified on the RJK0305DPB MOSFET datasheet.

However, it is not always necessary to use the same MOSFET for both the high-side and low-side. For most

applications it is necessary to choose the high-side MOSFET with the lowest gate charge and the low-side

MOSFET is chosen for the lowest allowed RDS(ON). The plateau voltage of the FET VGS vs Qgcurve must be less

than VCC - 750 mV.

The current limit resistor, RLIM, is calculated by estimating the RDS(ON) of the low-side FET at the maximum

junction temperature of 100°C. By choosing to go into current limit when the average output load current is 20%

higher than the output load current of 12A while the inductor ripple current ratio is 1/3 of the load current will

make ICL= 10.4A. Then the following calculation of RLIM is:

RLIM = (10.4 x 0.014) / (75 x 10-6) = 1.9 kΩ

Let RLIM = 1.91 kΩwhich is the next standard value.

8. Calculate Input Capacitance

The input capacitor should be chosen so that the voltage rating is greater than the maximum input voltage which

for this example is 24V. Similar to the output capacitor, the voltage rating needed will depend on the type of

capacitor chosen. The input capacitor should also be able to handle the input rms current, which is a maximum

of approximately 0.5 x IOUT. For this example the rms input current is approximately 0.5 x 12A = 6A.

The minimum capacitance with a maximum 5% input ripple ΔVIN-MAX = (0.05 x 12) = 0.6V:

CIN = [12 x 0.275 x (1-0.275)] / [500 kHz x 0.6] = 8 µF

To handle the large input rms current 2 ceramic capacitors are chosen at 10 µF each with a voltage rating of 50V

and case size of 1210. Each ceramic capacitor is capable of handling 3A of rms current. A aluminum electrolytic

of 5 times the combined input capacitance, 5 x 20 µF = 100 µF, is chosen to provide input voltage filter damping

because of the low ESR ceramic input capacitors.

CBYP = 0.1µF ceramic with a voltage rating greater than maximum VIN

9. Calculate Soft-Start Capacitor

The soft start-time should be greater than the input voltage rise time and also satisfy the following equality to

maintain a smooth transition of the output voltage to the programmed regulation voltage during startup. The

desired soft-start time, tss, of 5 ms also needs to satisfy the equality in equation 12, by using the chosen

component values through the previous steps as shown below:

5 ms > (3.3V x 300 µF) / (1.2 x 12A - 12A)

5 ms > 0.412 ms

Since the desired soft-start time satisfies the equality in equation 12, the soft start capacitor is calculated as:

CSS = (7.7 µA x 5 ms) / 0.6V = 0.064 µF

Let CSS = 0.068 µF, which is the next closest standard value. This should be a ceramic cap with a voltage rating

greater than 10V.

Product Folder Links: LM3150

LM3150

SNVS561D –SEPTEMBER 2008–REVISED MARCH 2011

www.ti.com

10. CVCC, CEN, and CBST

CVCC = 4.7 µF ceramic with a voltage rating greater than 10V

CEN = 1000 pF ceramic with a voltage rating greater than 10V

CBST = 0.47 µF ceramic with a voltage rating greater than 10V

Bill of Materials

Designator Value Parameters Manufacturer Part Number

CBST 0.47 µF Ceramic, X7R, 16V, 10% TDK C2012X7R1C474K

CBYP 0.1 µF Ceramic, X7R, 50V, 10% TDK C2012X7R1H104K

CEN 1000 pF Ceramic, X7R, 50V, 10% TDK C1608X7R1H102K

CFF 270 pF Ceramic, C0G, 50V, 5% Vishay-Bccomponents VJ0805A271JXACW1BC

CIN1, CIN2 10 µF Ceramic, X5R, 35V, 20% Taiyo Yuden GMK325BJ106KN-T

COUT1, COUT2 150 µF Polymer Aluminum, , 6.3V, 20% Panasonic EEF-UE0J151R

CSS 0.068 µF Ceramic, 0805, 25V, 10% Vishay VJ0805Y683KXXA

CVCC 4.7 µF Ceramic, X7R, 16V, 10% Murata GRM21BR71C475KA73L

L1 1.65 µH Shielded Drum Core, 2.53 mΩCoilcraft HA3778–AL

M1, M2 30V 8 nC, RDS(ON) @4.5V=10 mΩRenesas RJK0305DPB

RFB1 4.99 kΩ1%, 0.125W Vishay-Dale CRCW08054k99FKEA

RFB2 22.6 kΩ1%, 0.125W Vishay-Dale CRCW080522k6FKEA

RLIM 1.91 kΩ1%, 0.125W Vishay-Dale CRCW08051K91FKEA

RON 56.2 kΩ1%, 0.125W Vishay-Dale CRCW080556K2FKEA

U1 LM3150 Texas Instruments LM3150MH

PCB Layout Considerations

It is good practice to layout the power components first, such as the input and output capacitors, FETs, and

inductor. The first priority is to make the loop between the input capacitors and the source of the low-side FET to

be very small and tie the grounds of the low-side FET and input capacitor directly to each other and then to the

ground plane through vias. As shown in Figure 17 when the input capacitor ground is tied directly to the source

of the low-side FET, parasitic inductance in the power path, along with noise coupled into the ground plane, are

reduced.

The switch node is the next item of importance. The switch node should be made only as large as required to

handle the load current. There are fast voltage transitions occurring in the switch node at a high frequency, and if

the switch node is made too large it may act as an antennae and couple switching noise into other parts of the

circuit. For high power designs, it is recommended to use a multi-layer board. The FETs are going to be the

largest heat generating devices in the design, and as such, care should be taken to remove the heat. On multi-

layer boards using exposed-pad packages for the FETs such as the power-pak SO-8, vias should be used under

the FETs to the same plane on the interior layers to help dissipate the heat and cool the FETs. For the typical

single FET Power-Pak type FETs, the high-side FET DAP is VIN. The VIN plane should be copied to the other

interior layers to the bottom layer for maximum heat dissipation. Likewise, the DAP of the low-side FET is

connected to the SW node and the SW node shape should be duplicated to the other PCB layers for maximum

heat dissipation.

See the Evaluation Board application note AN-1900 (SNVA371) for an example of a typical multi-layer board

layout, and the Demonstration Board Reference Design Application Note for a typical 2 layer board layout. Each

design allows for single sided component mounting.

Product Folder Links: LM3150

LM3150

VIN VOUT

COUT

CIN

x x

vias to

ground plane

PGND

x x

VIN

CIN

COUT

LM3150

www.ti.com

SNVS561D –SEPTEMBER 2008–REVISED MARCH 2011

Figure 17. Schematic of Parasitics

Figure 18. PCB Placement of Power Stage

Product Folder Links: LM3150

PACKAGE OPTION ADDENDUM

www.ti.com 24-Jan-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package Qty Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

(3)

Op Temp (°C) Top-Side Markings

(4)

Samples

LM3150MH/NOPB ACTIVE HTSSOP PWP 14 94 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM3150

LM3150MHE/NOPB ACTIVE HTSSOP PWP 14 250 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM3150

LM3150MHX/NOPB ACTIVE HTSSOP PWP 14 2500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM3150

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) Only one of markings shown within the brackets will appear on the physical device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LM3150MHE/NOPB HTSSOP PWP 14 250 178.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1

LM3150MHX/NOPB HTSSOP PWP 14 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 21-Mar-2013

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM3150MHE/NOPB HTSSOP PWP 14 250 210.0 185.0 35.0

LM3150MHX/NOPB HTSSOP PWP 14 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 21-Mar-2013

Pack Materials-Page 2

MECHANICAL DATA

PWP0014A

www.ti.com

MXA14A (Rev A)

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anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of

non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products Applications

Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive

Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications

Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers

DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps

DSP dsp.ti.com Energy and Lighting www.ti.com/energy

Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial

Interface interface.ti.com Medical www.ti.com/medical

Logic logic.ti.com Security www.ti.com/security

Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense

Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video

RFID www.ti-rfid.com

OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com

Wireless Connectivity www.ti.com/wirelessconnectivity

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