MC7447RX1000LB - Motorola / Freescale Semiconductor

This document describes part-number-speciﬁc changes to recommended operating conditions

and revised electrical speciﬁcations, as applicable, from those described in the general

MPC7457 RISC Microprocessor Hardware Speciﬁcations

(Order No. MPC7457EC). The

MPC7457 and MPC7447 are implementations of the PowerPC™ microprocessor family of

reduced instruction set computer (RISC) microprocessors.

Speciﬁcations provided in this document supersede those in the

MPC7457 RISC

Microprocessor Hardware Speciﬁcations

, Rev. 2 or later, for the part numbers listed in

Table A only. This document is primarily concerned with the MPC7457; however, unless

otherwise noted, all information herein also applies to the MPC7447 part numbers listed in

Table A. Speciﬁcations not addressed herein are unchanged. Because this document is

frequently updated, refer to http://www.motorola.com/semiconductors or to your Motorola

sales ofﬁce for the latest version.

Note that headings and table numbers in this document are not consecuti vely numbered. They

are intended to correspond to the heading or table affected in the general hardware

speciﬁcation.

Advance Information

MPC7457RXNXPNS

Rev. 2 , 10/2003

MPC7457 Part Number

Speciﬁcation for the

MPC74x7RXnnnnNx Series

Motorola Part

Numbers Af fected:

PPC7457RX1000NB

PPC7457RX867NB

PPC7457RX733NB

PPC7457RX600NB

PPC7447RX1000NB

PPC7447RX867NB

MC7447RX1000NB

MC7447RX867NB

MC7447RX733NB

MC7447RX600NB

MPC7457 Part Number Speciﬁcation for the MPC74x7RXnnnnNx Series

MO TOR OLA

Part numbers addressed in this document are listed in Table A.

Table A. Part Numbers Addressed by this Data Sheet

Motorola

Part Number

Operating Conditions

Signiﬁcant Differences from

Hardware Speciﬁcation

CPU

Frequency

(MHz) V

(°C)

PPC7457RX1000NB 1000 1.1 V ± 50 mV 0 to 105 Modiﬁed core frequency and voltage to reduce

power consumption, modiﬁed processor bus AC

timing.

PPC7447RX1000NB

MC7447RX1000NB

PPC7457RX867NB 867

PPC7447RX867NB

MC7447RX867NB

PPC7457RX733NB 733

MC7447RX733NB

PPC7457RX600NB 600

MC7447RX600NB

Note:

The P preﬁx in a Motorola part number designates a “Pilot Production Prototype” as deﬁned by Motorola SOP

3-13. These parts have only preliminary reliability and characterization data. Before pilot production prototypes may

be shipped, written authorization from the customer must be on ﬁle in the applicable sales ofﬁce acknowledging the

qualiﬁcation status and the fact that product changes may still occur while shipping pilot production prototypes.

MOTOROLA

MPC7457 Part Number Speciﬁcation for the MPC74x7RXnnnnNx Series

Features

1.2 Features

This section summarizes changes to the features of the MPC7457 described in the

MPC7457 RISC

Microprocessor Hardware

Speciﬁcations

• Power management

— 1.1-V processor core

1.3 General Parameters

• Core power supply: 1.1 V ± 50 mV DC nominal

1.5.1 DC Electrical Characteristics

Table 4 provides the recommended operating conditions for the MPC7457 part numbers described herein.

Table 4. Recommended Operating Conditions

Characteristic Symbol Recommended

Value Unit

Core supply voltage V

1.1 V ± 50 mV V

PLL supply voltage AV

1.1 V ± 50 mV V

Note:

These are the recommended and tested operating conditions. Proper device operation outside of these

conditions is not guaranteed.

MPC7457 Part Number Speciﬁcation for the MPC74x7RXnnnnNx Series

MO TOR OLA

General Parameters General Parameters

Table 7 provides the power consumption for the MPC7457 part numbers described herein.

Table 7. Power Consumption for MPC7457

Processor (CPU) Frequency Unit Notes

600 MHz 733 MHz 867 MHz 1000 MHz

Full-Power Mode

Typical 5.3 6.3 7.3 8.3 W 1, 3

Maximum 7.9 9.1 10.3 11.5 W 1, 2

Doze Mode

Typical ————W4

Nap Mode

Typical 1.3 1.3 1.3 1.3 W 1, 2

Sleep Mode

Typical 1.2 1.2 1.2 1.2 W 1, 2

Deep Sleep Mode (PLL Disabled)

Typical 1.1 1.1 1.1 1.1 W 1, 3

Notes:

1. These values apply for all valid processor bus and L3 bus ratios. The values do not include I/O supply power

(OV

and GV

) or PLL supply power (AV

). O V

and GV

power is system dependent, b ut is typically <5%

of V

power. Worst case power consumption for AV

< 3 mW.

2. Maximum power is the maximum measured at nominal V

and maximum operating junction temperature (see

Table 4) while running an entirely cache-resident, contrived sequence of instructions which keep all the e xecution

units maximally busy.

3. Typical power is an average value measured at the nominal recommended V

(see Table 4) and 65

C while

running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz.

4. Doze mode is not a user-deﬁnable state; it is an intermediate state between full-power and either nap or sleep

mode. As a result, power consumption for this mode is not tested.

MOTOROLA

MPC7457 Part Number Speciﬁcation for the MPC74x7RXnnnnNx Series

General Parameters

Table 8 provides the clock AC timing speciﬁcations for the MPC7457 part numbers described herein.

Table 8. Clock AC Timing Speciﬁcations

At recommended operating conditions. See Table 4.

Characteristic Symbol

Maximum Processor Core Frequency

Unit Notes600 MHz 733 MHz 867 MHz 1000 MHz

Min Max Min Max Min Max Min Max

Processor frequency f

core

500 600 500 733 500 867 500 1000 MHz 1

VCO frequency f

VCO

1000 1200 1000 1466 1000 1733 1000 2000 MHz 1

SYSCLK frequency f

SYSCLK

33 167 33 167 33 167 33 167 MHz

SYSCLK cycle time t

SYSCLK

6.0 30 6.0 30 6.0 30 6.0 30 ns

Note:

Caution

: The SYSCLK frequency, PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus)

frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respectiv e maximum or minim um

operating frequencies. Ref er to the PLL_CFG[0:4] signal description in Section 1.9.1, “PLL Conﬁgur ation,” for v alid

PLL_CFG[0:4] settings.

MPC7457 Part Number Speciﬁcation for the MPC74x7RXnnnnNx Series

MO TOR OLA

General Parameters General Parameters

1.5.2.2 Processor Bus AC Speciﬁcations

Table 9 provides the processor bus AC timing speciﬁcations for the MPC7457 part numbers described

herein.

Table 9. Processor Bus AC Timing Speciﬁcations

At recommended operating conditions. See Table 4.

Parameter Symbol

All Speed Grades Unit Notes

Min Max

Input setup times:

A[0:35], AP[0:4]

D[0:63], DP[0:7]

AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,

HIT, TT[0:3], QACK, TA, TBEN, TEA, TS,

EXT_QUAL, PMON_IN, SHD[0:1], BMODE[0:1],

BMODE[0:1], BVSEL, L3VSEL

AVKH

DVKH

IVKH

MVKH

2.0

—

Input hold times:

A[0:35], AP[0:4]

D[0:63], DP[0:7]

AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,

HIT, TT[0:3], QACK, TA, TBEN, TEA, TS,

EXT_QUAL, PMON_IN, SHD[0:1]

BMODE[0:1], BVSEL, L3VSEL

AXKH

DXKH

IXKH

MXKH

—

Output valid times:

A[0:35], AP[0:4]

D[0:63], DP[0:7]

AACK, ARTRY, BR, CI, CKSTP_IN, DRDY, DTI[0:3],

GBL, PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3],

TS, SHD[0:1], WT

KHAV

KHDV

KHOV

—

2.0

Output hold times:

A[0:35], AP[0:4]

D[0:63], DP[0:7]

AACK, ARTRY, BR, CI, CKSTP_IN, DRDY, DTI[0:3],

GBL, PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3],

TS, SHD[0:1], WT

KHAX

KHDX

KHOX

0.5

—

SYSCLK to output enable t

KHOE

0.5 — ns

SYSCLK to output high impedance (all e xcept TS , AR TRY,

SHD0, SHD1) t

KHOZ

— 3.5 ns

SYSCLK to TS high impedance after precharge t

KHTSPZ

—1t

SYSCLK

3, 4, 5

Maximum delay to ARTRY/SHD0/SHD1 precharge t

KHARP

—1t

SYSCLK

3, 5,

6, 7

MOTOROLA

MPC7457 Part Number Speciﬁcation for the MPC74x7RXnnnnNx Series

General Parameters

SYSCLK to ARTRY/SHD0/SHD1 high impedance after

precharge t

KHARPZ

—2t

SYSCLK

3, 5

6, 7

Notes:

1. All input speciﬁcations are measured from the midpoint of the signal in question to the midpoint of the rising edge

of the input SYSCLK. All output speciﬁcations are measured from the midpoint of the rising edge of SYSCLK to the

midpoint of the signal in question. All output timings assume a purely resistive 50-

Ω

load (see Figure 4 in the

MPC7457 RISC Microprocessor Hardware Speciﬁcations)

. Input and output timings are measured at the pin;

time-of-ﬂight delays must be added for trace lengths, vias, and connectors in the system.

2. The symbology used f or timing speciﬁcations herein follo ws the pattern of t

(signal)(state)(reference)(state)

f or inputs and

(reference)(state)(signal)(state)

f or outputs. For e xample , t

IVKH

symbolizes the time input signals (I) reach the v alid state

(V) relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And t

KHOV

symbolizes the

time from SYSCLK(K) going high (H) until outputs (O) are valid (V) or output v alid time. Input hold time can be read

as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH) (note the position of

the ref erence and its state for inputs) and output hold time can be read as the time from the rising edge (KH) until

the output went invalid (OX).

3. t

SYSCLK

is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by

the period of SYSCLK to compute the actual time duration (in ns) of the parameter in question.

4. According to the bus protocol, TS is driven only by the currently active bus master. It is asserted low then

precharged high bef ore returning to high impedance, as shown in Figure 6 in the

MPC7457 RISC Microprocessor

Hardware Speciﬁcations

. The nominal precharge width for TS is 0.5

SYSCLK

, that is, less than the minimum

SYSCLK

period, to ensure that another master asserting TS on the following clock will not contend with the

precharge. Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for

precharge. The high-impedance behavior is guaranteed by design.

5. Guaranteed by design and not tested.

6. According to the bus protocol, AR TRY can be driven by m ultiple bus masters through the cloc k period immediately

following AACK. Bus contention is not an issue because any master asserting ARTRY will be driving it low. Any

master asserting it low in the ﬁrst clock following AACK will then go to high impedance for one clock before

precharging it high during the second cycle after the assertion of AACK. The nominal precharge width for ARTRY

is 1.0 t

SYSCLK

; that is, it should be high impedance, as shown in Figure 6 in the

MPC7457 RISC Microprocessor

Hardware Speciﬁcations,

before the ﬁrst opportunity for another master to assert ARTRY. Output valid and output

hold timing is tested for the signal asserted.The high-impedance behavior is guaranteed by design.

7. According to the MPX bus protocol, SHD0 and SHD1 can be driv en by m ultiple bus masters beginning the cycle of

TS. Timing is the same as ARTRY, that is, the signal is high impedance for a fraction of a cycle, then negated for

up to an entire cycle (crossing a bus cycle boundary) before being three-stated again. The nominal precharge width

for SHD0 and SHD1 is 1.0 t

SYSCLK

. The edges of the precharge vary depending on the programmed ratio of core

to bus (PLL conﬁgurations).

8. BMODE[0:1] and BVSEL are mode select inputs and are sampled before and after HRESET negation. These

parameters represent the input setup and hold times f or each sample. These v alues are guaranteed b y design and

not tested. These inputs must remain stable after the second sample. See Figure 5 in the

MPC7457 RISC

Microprocessor Hardware Speciﬁcations

for sample timing.

Table 9. Processor Bus AC Timing Speciﬁcations

(continued)

At recommended operating conditions. See Table 4.

Parameter Symbol

All Speed Grades Unit Notes

Min Max

MPC7457 Part Number Speciﬁcation for the MPC74x7RXnnnnNx Series

MO TOR OLA

General Parameters General Parameters

1.5.2.3 L3 Clock AC Speciﬁcations

Devices described by this part number speciﬁcation conform to the L3 clock AC timing speciﬁcations

provided in the

MPC7457 RISC Microprocessor Hardware Speciﬁcations

. Refer to the hardware

speciﬁcations for additional information.

1.5.2.4 L3 Bus AC Speciﬁcations

Devices described by this part number speciﬁcation conform to the L3 clock AC timing speciﬁcations

provided in the

MPC7457 RISC Microprocessor Hardware Speciﬁcations

. Refer to the hardware

speciﬁcations for additional information.

MOTOROLA

MPC7457 Part Number Speciﬁcation for the MPC74x7RXnnnnNx Series

Ordering Information

1.11 Ordering Information

1.11.1 Part Numbers Addressed by This Speciﬁcation

Table 22 provides the ordering information for the MPC7457 parts described in this document.

Table 22. Part Marking Nomenclature

xxx 74x7RXnnnn x x

Product

Code Part

Identiﬁer Package Processor

Frequency 1Application Modiﬁer Revision Level

PPC 27457 RX = CBGA 1000 N: 1.1 V ± 50 mV

0° to 105°CB: 1.1: PVR = 8002 0101

867

733

600

7447 1000

867

MC 7447 1000

867

733

600

Notes:

1. Processor core frequencies supported by parts addressed by this speciﬁcation only. Parts addressed by other

speciﬁcations may support other maximum core frequencies.

2. The P preﬁx in a Motorola part number designates a “Pilot Production Prototype” as deﬁned by Motorola SOP

3-13. These parts have only preliminary reliability and characterization data. Before pilot production prototypes

may be shipped, written authorization from the customer must be on ﬁle in the applicable sales ofﬁce

acknowledging the qualiﬁcation status and the fact that product changes may still occur while shipping pilot

production prototypes.

10 MPC7457 Part Number Speciﬁcation for the MPC74x7RXnnnnNx Series MO TOROLA

Ordering Information Ordering Information

1.11.3 Part Marking

Parts are marked as the example shown in Figure 29.

Figure 29. Motorola Part Marking for BGA Devices

BGA

Notes:

CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States.

MMMMMM is the 6-digit mask number.

ATWLYYWWA is the traceability code.

PPC7457

RX1000NB

MMMMMM

ATWLYYWWA

7457

BGA

MC7447

RX1000NB

MMMMMM

ATWLYYWWA

7447

CCCCC

MOTOROLA MPC7457 Part Number Speciﬁcation for the MPC74x7RXnnnnNx Series 11

Document Revision History

Table B provides a revision history for this part number speciﬁcation.

Table B. Document Revision History

Rev. No. Substantive Change(s)

0 Initial release.

0.1 Edited introductory paragraphs to clarify which part numbers are affected by this speciﬁcation.

1 Corrected product code in part numbers on page 1 and in Table A.

Updated power consumption speciﬁcations in Table 7.

Corrected product code in Section 1.11 and Table 21.

2 Added “MC7447...” part numbers to reﬂect qualiﬁcation status.

Table 8: Increased maximum system bus frequency (fSYSCLK) to 167 MHz.

Table 9: Corrected numerous errors in lists of pins associated with tKHOV, tKHOX, tIVKH, and tIXKH.

Updated (improved) AC timing parameters based on latest characterization data.

Added 867, 733, and 600 MHz speed grades.

Remov ed Tables 10, 13, and 14: de vices described by this speciﬁcation conform to the A C timing found

in the MPC7457 hardware speciﬁcations.

Corrected typo in Figure 29: 7447 device was incorrectly marked...RX10000NB.

MPC7457RXNXPNS

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