(S) MOTOROLA MC14536B PROGRAMMABLE TIMER The MC14536B programmable timer fs a 24-stage binary ripple counter with 16 stages selectable by a binary code. Provisions for an on-chip RC oscillator or an external clock are provided. An on-chip monostable circuit incorporating a pulse-type output has been included, By selecting the ap- propriate counter stage in conjunction with the appropriate input clock fre- quency, a variety of timing can be achieved: 24 Flip-Fiop Stages - Will Count From 29 to 224 Last 16 Stages Selectable By Four-Bit Select Code 8-Bypass Input Allows Bypassing of First Eight Stages Set and Reset Inputs Clock Inhibit and Oscillator Inhibit inputs On-Chip RC Oscillator Provisions . On-Chip Monostable Output Provisions Clock Conditioning Circuit Permits Operation With Very Long Rise and Fall Times #eee#ees* Test Mode Allows Fast Tst Sequence Supply Voltage Range = 3.0 Vde to 18 Vde Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range MAXIMUM RATINGS (Voitages Referenced to Vss) L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648 DW SUFFIX SOIC CASE 7516 & Symbol Parameter Value Unit Voo OC Supply Voltage -90.5 to +180 v Vin: Vi Input or Output Voltage (DC or Transient -0.5 to V +05 Vv ine Vout | oP P s } DD ORDERING INFORMATION lin lout _jfnput or Output Current (DC or Transient), per Pin 10 mA P P Dissipatl Pack 500 mW MC14XXXBCP_ Plastic 7 B {Power Dissipation, per Packaget MC14XXXBCL Ceramic ne Fstg Storage Temperature -65 to +150 C MC14XXXBDW Saic Th Lead Temperature (8-Second Soldering) 260 C Ta = -55 to 125C Jor ali packages. Maximum Ratings are those values beyond which damage to the device may occur. tTemperature Derating: Plastic "P and D/DW Packages: 7.0 mWPC From 65C To 125% Ceramic L" Packagas: - 12 mW/C From 100C To 125C - BLOCK DIAGRAM Clock Ink, Reset Set 8 Bypass 7 29 19 69 Osc. inhibit 14 - ny Stages 9 thru 24 _. . 3 a aa ag eaacaanaoanaoaa a T T T 1 T 13.16 17 = 18 7 29.21 22 23 1 4 5 A 90+ - Out} Gut2 B 100- C tlo Decoder BD i120 Voo = Pin 16 Vssr Pins | Monostable Decode M | onoln 15 0 Multivibrator 13 Out Boo. oe ett mom 6-354MC14536B ELECTRICAL CHARACTERISTICS (Voltages Referenced to Vss) 25C 125C Characteristi symbot | \BP ~ 85C Unit aracteristic y Vdc |win | Max | Min | Typ# | Max | Min { Max Output Voltage 0 Level 5.0 _ 0.05 _ 0 0.05 _ 0.05 Vin = Vpp or 0 VOL 10 _- 0.05 _ 0 0.05 _ 0.05 | Vde 15 _ 0.05 _ 0 0.05 0.05 1 Level 50 | 495 _ 4.95 5.0 4.95 Vin = O or Vpp VOH 10 9.95 _ 9.95 10 - 9.95 -| Vde 15 14.95 _ 14.95 15 _ 14.95 _- Input Voltage. 0 Level (Vo = 4.5 or 0.5 Vde) VIL 5.0 = 15 2.25 1.5 _ 15 | Ve (Vo = 9.0 or 1.0 Vdc) 10 _ 3.0 = 450 . 3.0 _ 3.0 (Vo = 13.5 or 1.5 Vde) 15 _ 4.0 6.75 4.0 _ 4.0 1" Level (Vo = 0.5 of 4.5 Vde) Vin 5.0 3.5 _- 3.5 2.75 _ 3.5 _ Vde (Vo = 1.0'or 9.0 Vdc) 10 70 _ 7.0 5.50 _ 7.0 _- (Vo = 1.5 or 13.5 Vdc) 15 W _ W 8.25 - 11 _-- Output Drive Current Le loH ' mAdc (VoH = 2.5 Vde) Source 5.0 -1.2 _ ~1.0 -1.7 _ -0.7 _ (VOH = 4.6 Vde) Pins 4&5 5.0 ~0.25 _ ~0.2 ~0.36 _ - 0,14 _ (VOH = 9.5 Vdc) 10 ~ 0.62 _ -0.5 ~0.9 _ -0.35} (VoH = 13.5 Vde) 15 -18 _ -1.5 -3.5 _ -1.1 - (VOH = 2.5 Vde) Source 5.0 3.0 _ -2.4 -42 _ -1.7 | mAdc (VOH = 4.6 Vdc) Pin 13 5.0 - 0.64 _ -0.51 0.88 _ -0.36| - (VoH = 9.5 Vde) 10 ~ 1.6 - -13 ~ 2.25 _ -0.9 _ (VOH = 13.5 Vde) 15 -4.2 -3.4 -8.8 ~24) (Von = 0.4 Vde} Sink loL 5.0 0.64 _ 0.51 0.88 _ 0.36 | mAdc (VoL = 0.5 Vde} 10 1.6 _- 1.3 2.25 - 09 _ (WoL_= 1.5 Vde) 15 4.2 3.4 8.8 _ 2.4 = Input Current lin 15 - +0.1, -_ +0,00001| +0.1 - +1.0 | wAde Input Capacitance Cin _ - _ _ 5.0 75 _ _ pF (Vin = 9) - Quiescent Current lop 5.0 - 5.0 _ 0.010 5.0 -| 180 | Ade (Per Package) 10 - 10 0.020 10 - 300 15 _ 20 _ 0,030 . 20 600 Total Supply Current**t+ tr 5.0 I7 = (1.50 wA/kHz) f + Ipp wAdC (Dynamic plus Quiescent, 10 IT = (2.30 pA/KHz) f + Ipp Per Package) . 15 ly = (3.55 wA/KHz)f + IDD (Cl, = 50 pF on all outputs, all buffers switching) #Data labelled Typ is not to be used for.design purposes but is intended as an indication of the ICs potential performance. _ **The formulas given are for the typical characteristics only at 25C. +To calculate total supply current at loads. other than 50 pF: I7(CL) = I7(50 pF) + (CL - 50) Vik where: {7 is in A (per package), CL in pF, V = f in KHz is input frequency, and k = 0.003. (Vpp - Vgs) in volts, 6-355MC14536B SWITCHING CHARACTERISTICS* {C1 = 50 pF, Ta = 25C) oe SE Max ____._ Characteristic _ _ Symbol Vpp Min Typ # Unit Output Rise and Fall Time (Pin 13) 'TLH: ns 'TLH TTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 - 100 200 tree: ttHLe = (0.75 ns/pF) CL + 42.5 ns 10 - 50 300 'TLH tTHL = (0.55 ns/pF) CL + 9.5 ns 18 - 40 80 Propagation Delay Time . 'PLH, ns Clock to Q1, 8-Bypass (Pin 6) High tPHL tPLH, tPHL = (1.7 ns/pF) Cy + 1715 ns 5.0 - 1800 3600 tPLH, tPHL = (0.66 ns/oF) Cy +617 ns 10 - 650 1300 TPLH, tPHL = (0.5 ns/pF)C, +425 ns 15 - 450 10060 Clock to Q1, 8-Bypass (Pin 6) Low tPLH, us tPLH, tPHE = (1.7 ns/pF) Cy + 3715 ns PHL 5.0 - 38 7.6 tPLH, tPHL = (0.66 ns/pF) C, + 1467 ns 10 - 15 3.0 tPLH, tPHL = (0.5 ns/pF) CL + 1075 ns 15 - 14 2.3 Clock. to 016 - 2 tPLH, us tPHL, tPLH = (1.7 ns/pF) C_ +6915 ns tPHL 5.0 - 7.0 14 PHL, tPLH = (0.66 ns/pF) C_ + 2967 ns 10 _ 3.0 6.0 tPHL, tPLH = (0.5 ns/pF) Cy + 2175 ns 16 - 2.2 45 Reset to OQ, PHL ng tPHL = (1.7 ns/pF) Cy, + 1415 ns 5.0 - 1500 3000 tPHL = (0.66 ns/pF) CL + 567 ns 10 - 600 1200 tHe ~ (0.5 ns/pF) C_ +425 ns 15 - 4s0 900 Clock Putse Width tWH 5.0 600 300 - ns 10 200 100 - eee = es 15 170 85 - Clock Pulse Frequency fol 5.0 - 1.2 0.4 MHz {50% Duty Cycle) 10 - 3.0 15 we a is | 5.0 2.0 Clock Rise and Fail Time TTLH, 5.0 ~ 'THL 10 No Limit eee 15 Reset Pulse Width twH 5.0 1000 500 - ns 10 400 200 - ee ae ee 15 300 150 - "The formulas given are for the typical characteristics only at 25C. #Data labelled Typ is not to be used for design purpeses but is intended as an indication of the {Cs Potential performance. PIN ASSIGNMENT This device contains protection circuitry to Tn guard against damage due to high static 1ccySet Vop ke 16 voltages or electric fields. However, precau- tions must be taken to avoid applications of 2cjReset Mono Inf 15 any voltage higher than maximum rated 3cini Osc Inne&o14 voltages to this high-impedance circuit. For Proper operation, Vin and Voyt should be 4C{Outt = Dacodef4 13 vena e vny to the range Vgg = (Vin or 5 colour 2 Dir 12 out Dp- Unused inputs must always be tied to an ap- 6 C4 8-Bypass Cpa propriate logic voltage level (e.g., either Vss 7 C24 Clock Inh BE 410 or Vpp). Unused outputs must be left open. 8 vgs atsg9 6-356MC14536B PIN DESCRIPTIONS INPUTS SET (Pin 1) A high on Set asynchronously forces Decode Out to a high level. This is accomplished by set- ting an output conditioning latch to a high level while at the same time resetting the 24 flip-flop stages. After Set goes low (inactive), the occurrence of the first negative clock transition on IN; causes Decede Out to go low. The counters flip-flop stages begin counting on the sec- ~ ond negative clock transition of IN;. When Set is high, the on-chip RC oscillator is disabled: This allows for very low-power standby operation. : - RESET (Pin 2) -A high on Reset asynchronously forces Decode Out to a low level; all 24 flip-flop stages are also reset to a low level. Like the Set input, Reset disables the on-chip RC oscillator for standby operation. IN, (Pin 3} The device's internal counters advance on the negative-going edge of this input. IN; may be used as an external clock input or used in conjunction with OUT, and OUT2 to form an RC oscillater. When an external clock is used, both OUT, and OUT2 may be left unconnected or used to drive 1 LSTTL or several CMOS loads. first 8 flip-flop stages to be bypassed. This device es- sentially becomes a 16-stage counter with all 16 stages selectable. Selection is accomplished by the A, B, C, and D inputs. (See the truth tables.) CLOCK INHIBIT (Pin 7) A high on this input dis- connects the first counter stage from the clocking source, This holds the present count and inhibits further counting. However, the clocking source may continue to run. Therefore, when Clock inhibit is brought low, no os- cillator start-up time is required. When Clock inhibit is low, the counter will start counting on the occurrence of _ the first negative edge of the clocking source at IN; _ OSC INHIBIT (Pin 14) A high level on this pin stops the RC oscillator which allows for very low-power 8-BYPASS (Pin 6) A high on this input causes the standby operation. May also be used, in conjunction with an external clock, with essentially the same results as the Clock Inhibit input. MONO-IN (Pin 15) Used as the timing pin for the on-chip monostable multivibrator. !f the Mono-in input is connected to.Vgg, the monstable circuit is disabled, and Decode Out is directly connected to the selected Q out- put. The monostable circuit is enabled if a resistor is connected between Mono-tn and Vpp. This resistor and the device's internal capacitance will determine the minimum output pulse widths. With the addition of an ex- ternal capacitor to Vgg, the pulse width range may be extended. For reliable operation the resistor value should be limited to the range of 5 kX to 100 kQ and the capacitor value should be limited to a maximum of 1000 - pf. (See figures 3, 4, 5, and 10). A, B, C, D (Pins 9, 10, 11, 12) These inputs se- lect the flip-flop stage to be connected to Decode Out. (See the truth tables.) OUTPUTS OUT,, OUT, (Pin 4, 5) Outputs used in conjunc- tion with IN, to form an RC oscillator. These outputs are buffered and may be used for 20 frequency division of an external clock. DECODE OUT (Pin 13) Output function depends on configuration. When the monostable circuit is dis- abled, this output is a 50% duty cycle square wave dur- ing free run. TEST MODE The test mode configuration divides the 24 flip-flop stages into three 8-stage sections to facilitate a fast test sequence. The test mode is enabled when 8-Bypass, Set and Reset are at a high level. (See Figure 8.) 6-3570 0 Qo 0 9 0 0 9 0 0 Qo oO oO G G MC14536B TRUTH TABLES Stage Selected For Decode Out FUNCTION TABLE Clock | OSC Decode in; Set | Reset] Inh Inh | Out 1 ]Out 2 Out No 0 Q 0 Qo Sf Sf Change Advance ~\ 0 0 0 0 ~\ S/S to next state x 1 0 0 0 0 1 1 x 0 t 0 0 0 1 0 x |olo 1 o}/ | No Change No x 9 a 0 1 6 1 Change No 9 o 0 0 x Qo 1 Change Advance 1 0 Q 0 Sf. \ Sf to next state X = Don't Care 6-358 Stage Selected For Decode Out SOia inion [aia jo [rw la ~afofoqjoaga fos fo Qian form /= loB Ug = SSA 91 lg = Ap, waryuy: 41D ing Et " LF sponeg p-o p poco ws ' [ w ugp- sspossg MC14536B 4 } Gj ve} [ose | b seins 3D yo 3 2? t pote avayes ibd L{ reeis ijt PTL en i A Gh UqIYU; 250 z 1080H wVYOVIG 51507 6-359MC14536B TYPICAL RC OSCILLATOR CHARACTERISTICS (For Circuit Diagram See Figure 11 In Application) FIGURE 2 - RC OSCILLATOR FREQUENCY AS A FIGURE 1 RC OSCILLATOR STABILITY FUNCTION OF Rrc AND GC tose 1D = Vop: 15V = O OV - FJ = z = fasa = B of Arc < = ip {C = 1000 pF) - a Ss (Rg = 9 eee Ba. iri 50 fasa function - & = of s e 2.07 (Are = $6 ki) 3 e a J pk tAs > 20K) nu ao = ow oo -12 ~ Rro= 56 {=r fs 20.12 10.18 kt @ Von = V.TaA= 0.2 peLOZ NOD PE lam Rg = 120 ke, f= 7.8 KHz @ Von = 10 V, Ta = 25C a1 ~55 25 0 25 50 5 100 125 , Te, RESISTANCE Device Only. Ta, AMBIENT TEMPERATURE {OC} 0.000! 001 0.0} 0.1 C, CAPACITANCE (uF} MONOSTABLE CHARACTERISTICS (For Circult Diagram See Figure 10 in Application) FIGURE 3 TYPICAL Cy versus PULSE WIDTH @ Vop = 5.0 V FIGURE 4 TYPICAL Cy versus PULSE WIDTH @ Vopp = 10 V ; toa = - 100 . Formula for calculating Win microseconds is as follows: Forrmufa for cafenrang an 2 W * 0.00247 Ry Cx0.85 CW = B00247 Ay CxO85 & Where Rx isin k&2, Cx in pF. = = 10 3 10 Where Ry is in k&2, CX in pF, 5 = Fs = EF x 5 ~ 8 = 3 Ry = 100 kt a Rx = 100 ka " SDK 2 Rx = 50 ka # to WEN x We - oie RX = 10k2 - = Ta = 25C Ry = 6.0kO 2 _ Ta = 25C Voo=5V ---Vop tov at 01 1.0 10 100 i000 1.0 . 10 190 1000 Cx, EXTERNAL CAPACITANCE (pF) Cx, EXTERNAL CAPACITANCE (pF) FIGURE 5 TYPICAL Cy versus PULSE WIDTH @ Vpop = 15 V 106 0 fee for 0 microseconds is as follows. tw = 0.00247 Rx = Cx9-85 Where 1s it kS2, Cx in Rx = HOOkN Ry = 5K tW , PULSE WIDTH (us} e Ry = 16 = a LE Rx = Sksz - /.- TAP -4- ---Vop*18 1 4 19 10 100 1000 Cx, EXTERNAL CAPACITANCE (pF) 6-360MC14536B FIGURE 6 POWER DISSIPATION TEST CIRCUIT AND WAVEFORM FIGURE 7 SWITCHING TIME TEST CIRCUIT AND WAVEFORMS 500 1 F d -O-] Set Vop @O-JReset Out ror _= 4 CL -_O-+ 8 Bypass tT Pulse I = ~ oO- Set Generator at Out 1-0 0-4 C tnh \ O --O- Reset | Mone Ingar Pune f 04 3-Bypass e-OfOsc inh 2 roo. cL Generator OF Iny Ha t $-_O7Cinh 4$_o}8 0 Mono In af oe OH1 6 Decode ~~~O7] Ose inh olp Out ore, _ Co A = oe }+0-/ 8 | \y 12] Secose ourbo-go SS oo . ecode Out +. - b--_o| D = CL 20ns I Vss ~ - - 0% 7 oo Duty Cycle FIGURE 6 FUNCTIONAL TEST CIRCUIT g Voo FUNCTIONAL TEST SEQUENCE Set Lo Pulse Te Reset Our! Test function (Figure 8) has been included for the re- Generator 8 Bypass duction of test time required to exercise all 24 counter ny stages. This test function divides the counter into three -O Inh 8-stage sections and 255 counts are loaded in each of {4 Mono In ous bo the 8-stage sections in parallel. All flip-flops are now at @-C4 Ose Inh a 1". The counter is now returned to the normal 24- eA stages in series configuration. One more pulse is en- . 4-18 tered into Inj which will cause the counter to ripple from t ole Decode iq tips ci an all 1" state to an all 0" state. | } olo our |? ; vss FUNCTIONAL TEST SEQUENCE INPUTS OUTPUTS . __ _ _COMMENTS_ Decade Out Inq Set Reset 8-Bypass O1 thru 024 All 24 stages are in Reset mode. 1 0 1 1 0 os . ~ 1 1 t 1 Oo Counter 1s im three 8 stage sections in paraliel mode 0 1 1 1 Oo First t" to O" transition of clack a F = oO - 1 1 1 265 1" to 'O" transitions are clocked in the counter 0 1 1 1 1 The 255 "1" to O" transition Counter converted back to 24 stages in series mode. 9 0 a Qa 1 Set and Reset must be connected together and simultaneously go from "i" to O" 1 6 0 1 Inz Switches toa "1". o oO o 0 0 Counter Ripples from an all ''1" state to an all "0" state 6-361MC14536B FIGURE 9 TIME INTERVAL CONFIGURATION USING AN EXTERNAL CLOCK, SET, AND CLOCK INHIBIT FUNCTIONS (DIVIDE-BY-2 CONFIGURED) +V 16 Vv 8-Bypass DD 9 A Out i = 10 B 11 Gc 12 0 2 Reset- Out 2 +S. 14 OSC INH is Mono-In Pulse 1 Sat Gen. 7 Clock INH Pulse 3 INy Decode Out p32 _ Gen. Ves Clock 8 In; | | Set - | Clock INH | - T _ Decode Out | | Power Up Note: When power is first applied to the device, Decode Out can be either at a high or low state. On the rising edge of a Set pulse the output goes high if initially at a low state. The output remains high if initially at a high state. Because Clock Inh is heid high, the clock source on the input pin has no effect on the output. Once Clock Inh is taken fow, the output goes low on the first negative clock transition. The output returns high depending on the 8-Bypass, A, B, C, and D inputs, and the clock input period. A 2n frequency division (where n = the number of stages selected from the truth table) is obtainable at Decode Out. A 20 -divided output of IN, can be obtained at OUT, and OUT). 6-362MC14536B FIGURE 10 TIME INTERVAL CONFIGURATION USING AN EXTERNAL CLOCK, RESET, AND OUTPUT MONOSTABLE TO ACHIEVE A PULSE OUTPUT. (DIVIDE-BY-4 CONGIFURED). Pulse +V 16 *S 8-Bypass A B Cc D Reset Set Glock INH 15 Mono-In 14] ogc INH Clock (Ny Ypp OUT tt OT 2 _ Decode Out 13 IN; _| Reset Decode Out To Power Up Is PLI uu Ly -}--- tw +| | TL M ty 00247 Ry + C285 ty in psec Ry in ka Cy in pF Note: When Power is first applied to the device with the Reset input going high, Decode Out initializes low. Bringing the Reset input low enables the chip's internal counters. After Reset goes low, the 2/2 negative transition of the clock input causes Decode Out to go high. Since the Mono-In input is being used, the output becomes monostabie. The pulse width of the output is dependent on the external timing components. The second and all subsequent pulses occur at 29 x (the clock period) intervals where n = the number of stages selected from the truth table, 6-363MC14536B FIGURE 11 TIME INTERVAL CONFIGURATION USING ON-CHIP RC OSCILLATOR AND RESET INPUT TO INITIATE TIME INTERVAL (DIVIDE-BY-2 CONFIGURED) + 16 6 Vpp 8-Bypass 2) a OUT 1 19 i 12 B c D Puls 2 Reset . OUT 2 Gen. 14 MONO-IN 1 Set z Clock INH 3 INi Decode Out 12 Vss to | Reset _ OUT 1 OUT 2 - | 1 Decode Out : ~~~ tose 2.3 Rig C = Hz = Ohms = FARADS a # Ww Power Up | lw \ ayaa i Note: This circuit is designed to use the on-chip oscillation function. The oscillator frequency Is determined by the external R and C components. When power is first applied to the device, Decode Out initializes to a high state. Because this output is tied directly to the Osc-Inh input, the oscillator is disabled. This puts the device in a low-current standby condition. The rising edge of the Reset pulse wil! cause the output to go low. This in turn causes Ose-Inh to go low. However, while Reset is high, the oscillator is still disabled (i.e.: standy condition). After Reset goes low, the output remains low for 21/2 of the oscillators period. After the part times out, the output again goes high. 6-364 OSC INH : :