MF1151-05 S1D13505F00A Technicl Manual Embedded RAMDAC LCD/CRT Controller S1D13505F00A Technical Manual S1D13505F00A Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ This manual was made with recycle papaer, and printed using soy-based inks. First issue February,1999 M Printed April, 2001 in Japan C B NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. MS-DOS and Windows are registered trademarks of Microsoft Corporation, U.S.A. PC-DOS, PC/AT, VGA, EGA and IBM are registered trademarks of International Business Machines Corporation, U.S.A. All other product names mentioned herein are trademarks and/or registered trademarks of their respective owners. (c) SEIKO EPSON CORPORATION 2001, All rights reserved. The information of the product number change Starting April 1, 2001, the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative. Configuration of product number Devices S1 D 13706 F 00A0 00 Packing specification Specification Package (B: CSP, F: QFP) Corresponding model number Model name (D: driver, digital products) Product classification (S1: semiconductor) Evaluation Board S5U 13705 P00C Specification Corresponding model number (13705: for S1D13705) Product classification (S5U: development tool for semiconductor) Comparison table between new and previous number * S1D13305 Series Previous No. SED1335 Series SED1335D0A SED1335F0A SED1335F0B * S1D1370x Series New No. S1D13305 Series S1D13305D00A S1D13305F00A S1D13305F00B * S1D1350x Series Previous No. New No. SED135x Series SED1353D0A SED1353F0A SED1353F1A S1D1350x Series S1D13503D00A S1D13503F00A S1D13503F01A SED1354F0A SED1354F1A SED1354F2A S1D13504F00A S1D13504F01A S1D13504F02A SED1355F0A S1D13505F00A SED1356F0A S1D13506F00A * S1D1380x Series New No. Previous No. SED137x Series SED1374F0A S1D1370x Series S1D13704F00A SED1375F0A S1D13705F00A SED1376B0A SED1376F0A S1D13706B00A S1D13706F00A SED1378 Series S1D13708 Series New No. Previous No. SED138x Series SED1386F0A S1D1380x Series S1D13806F00A * S1D13A0x Series Previous No. New No. SED13Ax Series SED13A3F0A SED13A3B0B S1D13A0x Series S1D13A03F00A S1D13A03B00B SED13A4B0B S1D13A04B00B Comparison table between new and previous number of Evaluation Boards * S1D1350x Series Previous No. * S1D1370x Series New No. * S1D1380x Series New No. Previous No. SDU1353#0C S5U13503P00C SDU1374#0C S5U13704P00C SDU1354#0C S5U13504P00C SDU1375#0C S5U13705P00C SDU1355#0C S5U13505P00C SDU1356#0C S5U13506P00C SDU1376#0C SDU1376BVR S5U13706P00C S5U13706B32R SDU1378#0C S5U13708P00C * S1D13A0x Series Previous No. SDU13A3#0C SDU13A4#0C New No. S5U13A03P00C S5U13A04P00C Previous No. SDU1386#0C New No. S5U13806P00C TOBIRA.fm Page 1 Sunday, April 15, 2001 6:24 PM S1D13505F00A Technical Manual HARDWARE FUNCTIONAL SPECIFICATION PROGRAMMING NOTES AND EXAMPLES UTILITIES S5U13505P00C ISA BUS EVALUATION BOARD USER'S MANUAL APPLICATION NOTES WINDOWS(R) CE DISPLAY DRIVERS ll er ro t n A Co 0 0 T l t c F n u 5 /CR F 0 e ion 5 r D a t 3 LC a w 1 c rd cifi D a C H pe S1 DA S i d e d Em d e b M A R a n o CONTENTS Contents Table of Contents 1 INTRODUCTION .........................................................................................................................1-1 1.1 Scope ............................................................................................................................................1-1 1.2 Overview Description ....................................................................................................................1-1 2 FEATURES ...............................................................................................................................1-2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Memory Interface ..........................................................................................................................1-2 CPU Interface ................................................................................................................................1-2 Display Support .............................................................................................................................1-2 Display Modes ...............................................................................................................................1-3 Display Features ...........................................................................................................................1-3 Clock Source .................................................................................................................................1-3 Miscellaneous................................................................................................................................1-3 3 TYPICAL SYSTEM IMPLEMENTATION DIAGRAMS ...........................................................................1-4 4 INTERNAL DESCRIPTION ............................................................................................................1-9 4.1 Block Diagram Showing Datapaths ...............................................................................................1-9 4.2 Block Descriptions .........................................................................................................................1-9 Register......................................................................................................................................1-9 Host Interface.............................................................................................................................1-9 CPU R/W ...................................................................................................................................1-9 Memory Controller......................................................................................................................1-9 Display FIFO ..............................................................................................................................1-9 Cursor FIFO .............................................................................................................................1-10 Look-Up Tables........................................................................................................................1-10 CRTC .......................................................................................................................................1-10 LCD Interface ...........................................................................................................................1-10 DAC .........................................................................................................................................1-10 Power Save..............................................................................................................................1-10 Clocks ......................................................................................................................................1-10 5 PINS .....................................................................................................................................1-11 5.1 Pinout Diagram............................................................................................................................1-11 5.2 Pin Description ............................................................................................................................1-12 Host Interface...........................................................................................................................1-13 Memory Interface .....................................................................................................................1-17 LCD Interface ...........................................................................................................................1-18 CRT Interface...........................................................................................................................1-18 Miscellaneous ..........................................................................................................................1-19 5.3 Summary of Configuration Options .............................................................................................1-20 5.4 Multiple Function Pin Mapping .................................................................................................... 1-20 5.5 CRT Interface ..............................................................................................................................1-23 6 D.C. CHARACTERISTICS .........................................................................................................1-24 7 A.C. CHARACTERISTICS .........................................................................................................1-26 7.1 CPU Interface Timing ..................................................................................................................1-26 SH-4 Interface Timing ..............................................................................................................1-26 SH-3 Interface Timing ..............................................................................................................1-28 MC68K Bus 1 Interface Timing (e.g. MC68000) ......................................................................1-30 MC68K Bus 2 Interface Timing (e.g. MC68030) ......................................................................1-32 PC Card Interface Timing ........................................................................................................1-34 Generic Interface Timing..........................................................................................................1-36 MIPS/ISA Interface Timing.......................................................................................................1-38 Philips Interface Timing (e.g. PR31500/PR31700) ..................................................................1-40 Toshiba Interface Timing (e.g. TX3912) ..................................................................................1-42 PowerPC Interface Timing (e.g. MPC8xx, MC68040, Coldfire) ...............................................1-45 S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-i CONTENTS 7.2 Clock Input Requirements ...........................................................................................................1-46 7.3 Memory Interface Timing.............................................................................................................1-47 EDO-DRAM Read/Write/Read-Write Timing............................................................................1-47 EDO-DRAM CAS Before RAS Refresh Timing........................................................................1-49 EDO-DRAM Self-Refresh Timing.............................................................................................1-50 FPM-DRAM Read / Write / Read - Write Timing......................................................................1-51 FPM-DRAM CAS Before RAS Refresh Timing ........................................................................1-53 FPM-DRAM Self-Refresh Timing .............................................................................................1-54 7.4 Power Sequencing ......................................................................................................................1-55 LCD Power Sequencing...........................................................................................................1-55 Power Save Status ..................................................................................................................1-56 7.5 Display Interface..........................................................................................................................1-57 4-Bit Single Monochrome Passive LCD Panel Timing .............................................................1-57 8-Bit Single Monochrome Passive LCD Panel Timing .............................................................1-59 4-Bit Single Color Passive LCD Panel Timing .........................................................................1-61 8-Bit Single Color Passive LCD Panel Timing (Format 1)........................................................1-63 8-Bit Single Color Passive LCD Panel Timing (Format 2)........................................................1-65 16-Bit Single Color Passive LCD Panel Timing .......................................................................1-67 8-Bit Dual Monochrome Passive LCD Panel Timing................................................................1-69 8-Bit Dual Color Passive LCD Panel Timing ............................................................................1-71 16-Bit Dual Color Passive LCD Panel Timing ..........................................................................1-73 16-Bit TFT/D-TFD Panel Timing ..............................................................................................1-75 CRT Timing ..............................................................................................................................1-77 8 REGISTERS ............................................................................................................................1-79 8.1 Register Mapping ........................................................................................................................1-79 8.2 Register Descriptions ..................................................................................................................1-80 Revision Code Register ...........................................................................................................1-80 Memory Configuration Registers .............................................................................................1-80 Panel/Monitor Configuration Registers ....................................................................................1-81 Display Configuration Registers...............................................................................................1-86 Clock Configuration Register ...................................................................................................1-90 Power Save Configuration Registers .......................................................................................1-91 Miscellaneous Registers ..........................................................................................................1-92 Look-Up Table Registers .........................................................................................................1-97 Ink/Cursor Registers ................................................................................................................1-98 9 DISPLAY BUFFER .................................................................................................................1-101 9.1 Image Buffer ..............................................................................................................................1-102 9.2 Ink/Cursor Buffers .....................................................................................................................1-102 9.3 Half Frame Buffer ......................................................................................................................1-102 10 DISPLAY CONFIGURATION .....................................................................................................1-103 10.1 Display Mode Data Format........................................................................................................1-103 10.2 Image Manipulation ...................................................................................................................1-105 11 LOOK-UP TABLE ARCHITECTURE...........................................................................................1-106 11.1 Monochrome Modes..................................................................................................................1-106 1 Bit-Per-Pixel Monochrome Mode ..................................................................................1-106 2 Bit-Per-Pixel Monochrome Mode ..................................................................................1-106 4 Bit-Per-Pixel Monochrome Mode ..................................................................................1-107 11.2 Color Display Modes .................................................................................................................1-108 1 Bit-Per-Pixel Color Mode...............................................................................................1-108 2 Bit-Per-Pixel Color Mode...............................................................................................1-109 4 Bit-Per-Pixel Color Mode...............................................................................................1-110 8 Bit-Per-Pixel Color Mode...............................................................................................1-111 12 INK/CURSOR ARCHITECTURE .................................................................................................1-113 12.1 Ink/Cursor Buffers .....................................................................................................................1-113 12.2 Ink/Cursor Data Format .............................................................................................................1-113 1-ii EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) CONTENTS 12.3 Ink/Cursor Image Manipulation .................................................................................................1-114 Ink Image ...............................................................................................................................1-114 Cursor Image .........................................................................................................................1-114 13 SWIVELVIEWTM ....................................................................................................................1-115 13.1 Concept .....................................................................................................................................1-115 13.2 Image Manipulation in SwivelViewTM ........................................................................................1-116 13.3 Physical Memory Requirement..................................................................................................1-117 13.4 Limitations .................................................................................................................................1-118 14 CLOCKING ...........................................................................................................................1-119 14.1 Maximum MCLK: PCLK Ratios .................................................................................................1-119 14.2 Frame Rate Calculation.............................................................................................................1-120 14.3 Bandwidth Calculation ...............................................................................................................1-122 15 POWER SAVE MODES ...........................................................................................................1-125 16 MECHANICAL DATA ..............................................................................................................1-126 S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-iii CONTENTS List of Figures Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5 Figure 3-6 Figure 3-7 Figure 3-8 Figure 3-9 Figure 3-10 Figure 4-1 Figure 5-1 Figure 5-2 Figure 7-1 Figure 7-2 Figure 7-3 Figure 7-4 Figure 7-5 Figure 7-6 Figure 7-7 Figure 7-8 Figure 7-9 Figure 7-10 Figure 7-11 Figure 7-12 Figure 7-13 Figure 7-14 Figure 7-15 Figure 7-16 Figure 7-17 Figure 7-18 Figure 7-19 Figure 7-20 Figure 7-21 Figure 7-22 Figure 7-23 Figure 7-24 Figure 7-25 Figure 7-26 Figure 7-27 Figure 7-28 Figure 7-29 Figure 7-30 Figure 7-31 Figure 7-32 Figure 7-33 Figure 7-34 Figure 7-35 1-iv Typical System Diagram (SH-4 Bus, 256Kx16 FPM/EDO-DRAM) ...................................... 1-4 Typical System Diagram (SH-3 Bus, 256Kx16 FPM/EDO-DRAM) ...................................... 1-4 Typical System Diagram (MC68K Bus 1, 16-Bit 68000, 256Kx16 FPM/EDO-DRAM)......... 1-5 Typical System Diagram (MC68K Bus 2, 32-Bit 68030, 256Kx16 FPM/EDO-DRAM)......... 1-5 Typical System Diagram (Generic Bus, 1Mx16 FPM/EDO-DRAM) ..................................... 1-6 Typical System Diagram (NEC VR41xx (MIPS) Bus, 1Mx16 FPM/EDO-DRAM)................. 1-6 Typical System Diagram (Philips PR31500/PR31700 Bus, 1Mx16 FPM/EDO-DRAM) ....... 1-7 Typical System Diagram (Toshiba TX3912 Bus, 1Mx16 FPM/EDO-DRAM) ....................... 1-7 Typical System Diagram (Power PC Bus, 256Kx16 FPM/EDO-DRAM) .............................. 1-8 Typical System Diagram (PC Card (PCMCIA) Bus, 1Mx16 FPM/EDO-DRAM) .................. 1-8 System Block Diagram Showing Datapaths ........................................................................ 1-9 Pinout Diagram .................................................................................................................. 1-11 External Circuitry for CRT Interface ................................................................................... 1-23 SH-4 Timing ....................................................................................................................... 1-26 SH-3 Timing ....................................................................................................................... 1-28 MC68000 Timing................................................................................................................ 1-30 MC68030 Timing................................................................................................................ 1-32 PC Card Interface Timing .................................................................................................. 1-34 Generic Timing................................................................................................................... 1-36 MIPS/ISA Timing................................................................................................................ 1-38 Philips Timing..................................................................................................................... 1-40 Clock Input Requirements for BUSCLK Using Philips Local Bus ...................................... 1-41 Toshiba Timing .................................................................................................................. 1-42 Clock Input Requirements.................................................................................................. 1-44 PowerPC Timing ................................................................................................................ 1-45 Clock Input Requirements.................................................................................................. 1-46 EDO-DRAM Read/Write Timing......................................................................................... 1-47 EDO-DRAM Read-Write Timing......................................................................................... 1-47 EDO-DRAM CAS Before RAS Refresh Write Timing ........................................................ 1-49 EDO-DRAM Self-Refresh Timing....................................................................................... 1-50 FPM-DRAM Read/Write Timing ......................................................................................... 1-51 FPM-DRAM Read-Write Timing......................................................................................... 1-51 FPM-DRAM CAS before RAS Refresh Timing .................................................................. 1-53 FPM-DRAM Self-Refresh Timing ....................................................................................... 1-54 LCD Panel Power Off / Power On Timing. Drawn with LCDPWR Set to Active High Polarity155 Power Save Status and Local Bus Memory Access Relative to Power Save Mode.......... 1-56 4-Bit Single Monochrome Passive LCD Panel Timing ....................................................... 1-57 4-Bit Single Monochrome Passive LCD Panel A.C. Timing ............................................... 1-58 8-Bit Single Monochrome Passive LCD Panel Timing ....................................................... 1-59 8-Bit Single Monochrome Passive LCD Panel A.C. Timing ............................................... 1-60 4-Bit Single Color Passive LCD Panel Timing ................................................................... 1-61 4-Bit Single Color Passive LCD Panel A.C.Timing ............................................................ 1-62 8-Bit Single Color Passive LCD Panel Timing (Format 1).................................................. 1-63 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 1).......................................... 1-64 8-Bit Single Color Passive LCD Panel Timing (Format 2).................................................. 1-65 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 2).......................................... 1-66 16-Bit Single Color Passive LCD Panel Timing ................................................................. 1-67 16-Bit Single Color Passive LCD Panel A.C. Timing ......................................................... 1-68 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) CONTENTS Figure 7-36 Figure 7-37 Figure 7-38 Figure 7-39 Figure 7-40 Figure 7-41 Figure 7-42 Figure 7-43 Figure 7-44 Figure 7-45 Figure 9-1 Figure 10-1 Figure 10-2 Figure 10-3 Figure 11-1 Figure 11-2 Figure 11-3 Figure 11-4 Figure 11-5 Figure 11-6 Figure 11-7 Figure 12-1 Figure 12-2 Figure 13-1 Figure 16-1 8-Bit Dual Monochrome Passive LCD Panel Timing..........................................................1-69 8-Bit Dual Monochrome Passive LCD Panel A.C. Timing..................................................1-70 8-Bit Dual Color Passive LCD Panel Timing ......................................................................1-71 8-Bit Dual Color Passive LCD Panel A.C. Timing ..............................................................1-72 16-Bit Dual Color Passive LCD Panel Timing ....................................................................1-73 16-Bit Dual Color Passive LCD Panel A.C. Timing ............................................................1-74 16-Bit TFT/D-TFD Panel Timing.........................................................................................1-75 16-Bit TFT/D-TFD A.C. Timing...........................................................................................1-76 CRT Timing ........................................................................................................................1-77 CRT A.C. Timing ................................................................................................................1-78 Display Buffer Addressing ................................................................................................1-101 1/2/4/8 Bit-Per-Pixel Format Memory Organization..........................................................1-103 15/16 Bit-Per-Pixel Format Memory Organization............................................................1-104 Image Manipulation ..........................................................................................................1-105 1 Bit-per-pixel Monochrome Mode Data Output Path ......................................................1-106 2 Bit-per-pixel Monochrome Mode Data Output Path ......................................................1-106 4 Bit-per-pixel Monochrome Mode Data Output Path ......................................................1-107 1 Bit-per-pixel Color Mode Data Output Path...................................................................1-108 2 Bit-per-pixel Color Mode Data Output Path...................................................................1-109 4 Bit-per-pixel Color Mode Data Output Path...................................................................1-110 8 Bit-per-pixel Color Mode Data Output Path...................................................................1-111 Ink/Cursor Data Format....................................................................................................1-113 Cursor Positioning ............................................................................................................1-114 Relationship Between the Screen Image and the Image Residing in the Display Buffer .1-115 Mechanical Drawing QFP15.............................................................................................1-126 S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-v CONTENTS List of Tables Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 5-5 Table 5-6 Table 5-7 Table 5-8 Table 5-9 Table 6-1 Table 6-2 Table 6-3 Table 6-4 Table 6-5 Table 7-1 Table 7-2 Table 7-3 Table 7-4 Table 7-5 Table 7-6 Table 7-7 Table 7-8 Table 7-9 Table 7-10 Table 7-11 Table 7-12 Table 7-13 Table 7-14 Table 7-15 Table 7-16 Table 7-17 Table 7-18 Table 7-19 Table 7-20 Table 7-21 Table 7-22 Table 7-23 Table 7-24 Table 7-25 Table 7-26 Table 7-27 Table 7-28 Table 7-29 Table 7-30 Table 7-31 Table 7-32 Table 7-33 Table 8-1 Table 8-2 Table 8-3 Table 8-4 Table 8-5 Table 8-6 1-vi Host Interface Pin Descriptions.......................................................................................... 1-13 Memory Interface Pin Descriptions .................................................................................... 1-17 LCD Interface Pin Descriptions .......................................................................................... 1-18 Clock Input Pin Description ................................................................................................ 1-18 Miscellaneous Interface Pin Descriptions .......................................................................... 1-19 Summary of Power On / Reset Options ............................................................................. 1-20 CPU Interface Pin Mapping ............................................................................................... 1-20 Memory Interface Pin Mapping .......................................................................................... 1-21 LCD Interface Pin Mapping ................................................................................................ 1-22 Absolute Maximum Ratings ............................................................................................... 1-24 Recommended Operating Conditions ................................................................................ 1-24 Electrical Characteristics for VDD = 5.0V Typical ............................................................... 1-24 Electrical Characteristics for VDD = 3.3V Typical ............................................................... 1-24 Electrical Characteristics for VDD = 3.0V Typical ............................................................... 1-25 SH-4 Timing ....................................................................................................................... 1-27 SH-3 Timing ....................................................................................................................... 1-29 MC68000 Timing................................................................................................................ 1-31 MC68030 Timing................................................................................................................ 1-33 PC Card Interface Timing .................................................................................................. 1-35 Generic Timing................................................................................................................... 1-37 MIPS/ISA Timing................................................................................................................ 1-39 Philips Timing..................................................................................................................... 1-41 Clock Input Requirements for BUSCLK Using Philips Local Bus ...................................... 1-41 Toshiba Timing .................................................................................................................. 1-43 Clock Input Requirements for BUSCLK Using Toshiba Local Bus .................................... 1-44 PowerPC Timing ................................................................................................................ 1-45 Clock Input Requirements for CLKI Divided Down Internally (MCLK = CLKI/2) ................ 1-46 Clock Input Requirements for CLKI ................................................................................... 1-46 EDO DRAM Read Timing .................................................................................................. 1-48 EDO DRAM CAS Before RAS Refresh Write Timing......................................................... 1-49 EDO-DRAM Self-Refresh Timing....................................................................................... 1-50 FPM-DRAM Read/Write/Read-Write Timing...................................................................... 1-52 FPM-DRAM CAS before RAS Refresh Timing .................................................................. 1-53 FPM DRAM Self-Refresh Timing ....................................................................................... 1-54 LCD Panel Power Off/ Power On....................................................................................... 1-55 Power Save Status and Local Bus Memory Access Relative to Power Save Mode.......... 1-56 4-Bit Single Monochrome Passive LCD Panel A.C. Timing ............................................... 1-58 8-Bit Single Monochrome Passive LCD Panel A.C. Timing ............................................... 1-60 4-Bit Single Color Passive LCD Panel A.C.Timing ............................................................ 1-62 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 1).......................................... 1-64 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 2).......................................... 1-66 16-Bit Single Color Passive LCD Panel A.C. Timing ......................................................... 1-68 8-Bit Dual Monochrome Passive LCD Panel A.C. Timing.................................................. 1-70 8-Bit Dual Color Passive LCD Panel A.C. Timing .............................................................. 1-72 16-Bit Dual Color Passive LCD Panel A.C. Timing ............................................................ 1-74 16-Bit TFT/D-TFD A.C. Timing........................................................................................... 1-76 CRT A.C. Timing ................................................................................................................ 1-78 S1D13505 Addressing ....................................................................................................... 1-79 DRAM Refresh Rate Selection .......................................................................................... 1-80 Panel Data Width Selection ............................................................................................... 1-81 FPLINE Polarity Selection.................................................................................................. 1-83 FPFRAME Polarity Selection ............................................................................................. 1-85 Simultaneous Display Option Selection ............................................................................. 1-86 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) CONTENTS Table 8-7 Table 8-8 Table 8-9 Table 8-10 Table 8-11 Table 8-12 Table 8-13 Table 8-14 Table 8-15 Table 8-16 Table 8-17 Table 8-18 Table 8-19 Table 9-1 Table 12-1 Table 12-2 Table 13-1 Table 14-1 Table 14-2 Table 14-3 Table 14-4 Table 14-5 Table 14-6 Table 15-1 Table 15-2 Bits-Per-Pixel Selection......................................................................................................1-87 Pixel Panning Selection......................................................................................................1-89 PCLK Divide Selection .......................................................................................................1-90 Suspend Refresh Selection................................................................................................1-91 MA/GPIO Pin Functionality.................................................................................................1-93 Minimum Memory Timing Selection ...................................................................................1-95 RAS#-to-CAS# Delay Timing Select ..................................................................................1-95 RAS# Precharge Timing Select..........................................................................................1-95 Optimal NRC, NRP, and NRCD Values at Maximum MCLK Frequency ................................1-96 Minimum Memory Timing Selection ...................................................................................1-96 Ink/Cursor Selection ...........................................................................................................1-98 Ink/Cursor Start Address Encoding ..................................................................................1-100 Recommended Alternate FRM Scheme...........................................................................1-100 S1D13505 Addressing .....................................................................................................1-101 Ink/Cursor Data Format....................................................................................................1-113 Ink/Cursor Color Select ....................................................................................................1-113 Minimum DRAM Size Required for SwivleViewTM .................................................................................. 1-118 Maximum PCLK Frequency with EDO-DRAM .................................................................1-119 Maximum PCLK Frequency with FPM-DRAM..................................................................1-120 Example Frame Rates with Ink Disabled .........................................................................1-121 Number of MCLKs Required for Various Memory Access ...............................................1-122 Total # MCLKs Taken for Display Refresh .......................................................................1-123 Theoretical Maximum Bandwidth M byte/sec, Cursor/Ink Disabled .................................1-124 Power Save Mode Function Summary.............................................................................1-125 Pin States in Power-Save Modes.....................................................................................1-125 S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-vii 1: INTRODUCTION 1 INTRODUCTION 1.1 Scope This is the Hardware Functional Specification for the S1D13505 Embedded RAMDAC LCD/CRT Controller. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. This document is intended for two audiences: Video Subsystem Designers and Software Developers. 1.2 Overview Description The S1D13505 is a color/monochrome LCD/CRT graphics controller interfacing to a wide range of CPUs and display devices. The S1D13505 architecture is designed to meet the low cost, low power requirements of the embedded markets, such as Mobile Communications, Hand-Held PCs, and Office Automation. The S1D13505 supports multiple CPUs, all LCD panel types, CRT, and additionally provides a number of differentiating features. Products requiring a "Portrait" mode display can take advantage of the SwivelViewTM feature. Simultaneous, Virtual and Split Screen Display are just some of the display modes supported, while the Hardware Cursor, Ink Layer, and the Memory Enhancement Registers offer substantial performance benefits. These features, combined with the S1D13505's Operating System independence, make it an ideal display solution for a wide variety of applications. S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-1 2: FEATURES 2 FEATURES 2.1 Memory Interface * 16-bit DRAM interface: - EDO-DRAM up to 40MHz data rate (80M bytes per second). - FPM-DRAM up to 25MHz data rate (50M bytes per second). * Memory size options: - 512K bytes using one 256Kx16 device. - 2M bytes using one 1Mx16 device. * Performance Enhancement Register to tailor the memory control output timing for the DRAM device. 2.2 CPU Interface * Supports the following interfaces: - 8/16-bit SH-4 bus interface. - 8/16-bit SH-3 bus interface. - 8/16-bit interface to 8/16/32-bit MC68000 microprocessors/microcontrollers. - 8/16-bit interface to 8/16/32-bit MC68030 microprocessors/microcontrollers. - Philips PR31500/PR31700 (MIPS). - Toshiba TX3912 (MIPS). - Philips PR31500/PR31700. - 16-bit Power PC (MPC821) microprocessor. - 16-bit Epson E0C33 microprocessor. - PC Card (PCMCIA). - StrongARM (PC Card). - NEC VR41xx (MIPS). - ISA bus. * Supports the following interface with external logic: - GX486 microprocessor. * One-stage write buffer for minimum wait-state CPU writes. * Registers are memory-mapped - the M/R# pin selects between the display buffer and register address space. * The complete 2M byte display buffer address space is addressable as a single linear address space through the 21-bit address bus. 2.3 Display Support * 4/8-bit monochrome passive LCD interface. * 4/8/16-bit color passive LCD interface. * Single-panel, single-drive displays. * Dual-panel, dual-drive displays. * Direct support for 9/12-bit TFT/D-TFD; 18-bit TFT/D-TFD is supported up to 64K color depth (16-bit data). * Embedded RAMDAC (DAC)with direct analog CRT drive. * Simultaneous display of CRT and passive or TFT/D-TFD panels. 1-2 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 2: FEATURES 2.4 Display Modes * 1/2/4/8/15/16 bit-per-pixel (bpp) support on LCD/CRT. * Up to 16 shades of gray using FRM on monochrome passive LCD panels. * Up to 4096 colors on passive LCD panels; three 256x4 Look-Up Tables (LUT) are used to map 1/ 2/4/8 bpp modes into these colors, 15/16 bpp modes are mapped directly using the 4 most significant bits of the red, green and blue colors. * Up to 64K colors on TFT/D-TFD LCD panels and CRT; three 256x4 Look-Up Tables are used to map 1/2/4/8 bpp modes into 4096 colors, 15/16 bpp modes are mapped directly. 2.5 Display Features * SwivelViewTM: direct hardware 90 rotation of display image for "portrait" mode display. * Split Screen Display: allows two different images to be simultaneously viewed on the same display. * Virtual Display Support: displays images larger than the display size through the use of panning. * Double Buffering/multi-pages: provides smooth animation and instantaneous screen update. * Acceleration of screen updates by allocating full display memory bandwidth to CPU (see REG[23h] bit 7). * Hardware 64x64 pixel 2-bit cursor or full screen 2-bit ink layer. * Simultaneous display of CRT and passive panel or TFT/D-TFD panel. * Normal mode for cases where LCD and CRT screen sizes are identical. * Line-doubling for simultaneous display of 240-line images on 240-line LCD and 480-line CRT. * Even-scan or interlace modes for simultaneous display of 480-line images on 240-line LCD and 480-line CRT. 2.6 Clock Source * Single clock input for both the pixel and memory clocks. * Memory clock can be input clock or (input clock/2), providing flexibility to use CPU bus clock as input. * Pixel clock can be the memory clock, (memory clock/2), (memory clock/3) or (memory clock/4). 2.7 Miscellaneous * The memory data bus, MD[15:0], is used to configure the chip at power-on. * Three General Purpose Input/Output pins, GPIO[3:1], are available if the upper Memory Address pins are not required for asymmetric DRAM support. * Suspend power save mode can be initiated by either hardware or software. * The SUSPEND# pin is used either as an input to initiate Suspend mode, or as a General Purpose Output that can be used to control the LCD backlight. Power-on polarity is selected by an MD configuration pin. * Operating voltages from 2.7 volts to 5.5 volts are supported * 128-pin QFP15 surface mount package S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-3 3: TYPICAL SYSTEM IMPLEMENTATION DIAGRAMS 3 TYPICAL SYSTEM IMPLEMENTATION DIAGRAMS Power Management Oscillator CSn# M/R# CS# A[20:0] AB[20:0] D[15:0] DB[15:0] CLKI A[21] SUSPEND# SH-4 BUS FPDAT[15:8] UD[7:0] FPDAT[7:0] LD[7:0] FPSHIFT FPSHIFT 4/8/16-bit FPFRAME FPFRAME LCD Display FPLINE DRDY WE1# BS# RD/WR# RD# WE1# S1D13505F00A BS# RD/WR# RD# WE0# WE0# WAIT# WAIT# FPLINE MOD LCDPWR RED,GREEN,BLUE CRT Display HRTC UCAS# UCAS# RAS# LCAS# WE# LCAS# RAS# MD[15:0] WE# MA[8:0] BUSCLK RESET# A[11:0] CKIO RESET# D[15:0] VRTC IREF IREF 256Kx16 FPM/EDO-DRAM Power Management Oscillator SUSPEND# CLKI Figure 3-1 Typical System Diagram (SH-4 Bus, 256Kx16 FPM/EDO-DRAM) SH-3 BUS A[21] CSn# M/R# CS# A[20:0] AB[20:0] D[15:0] DB[15:0] WE1# BS# RD/WR# RD# FPDAT[15:8] UD[7:0] FPDAT[7:0] LD[7:0] FPSHIFT FPSHIFT 4/8/16-bit FPFRAME FPFRAME LCD Display FPLINE DRDY WE1# BS# FPLINE MOD S1D13505F00A LCDPWR RD/WR# RD# WE# RAS# LCAS# UCAS# RAS# LCAS# UCAS# BUSCLK RESET# VRTC WE# CKIO RESET# MD[15:0] HRTC MA[8:0] RED,GREEN,BLUE WAIT# A[8:0] WE0# D[15:0] WE0# WAIT# IREF CRT Display IREF 256Kx16 FPM/EDO-DRAM Figure 3-2 Typical System Diagram (SH-3 Bus, 256Kx16 FPM/EDO-DRAM) 1-4 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) Power Management Oscillator SUSPEND# CLKI 3: TYPICAL SYSTEM IMPLEMENTATION DIAGRAMS MC68000 BUS A[23:21] FC0, FC1 Decoder Decoder M/R# CS# A[20:1] AB[20:1] D[15:0] DB[15:0] FPDAT[15:8] UD[7:0] FPDAT[7:0] LD[7:0] FPSHIFT FPSHIFT 4/8/16-bit FPFRAME FPFRAME LCD Display FPLINE DRDY LDS# AB0# UDS# WE1# AS# FPLINE MOD S1D13505F00A LCDPWR BS# R/W# RED,GREEN,BLUE RD/WR# DTACK# RAS# LCAS# UCAS# LCAS# UCAS# WE# RAS# MD[15:0] VRTC WE# MA[8:0] A[8:0] BUSCLK RESET# D[15:0] BCLK RESET# CRT Display HRTC WAIT# IREF IREF 256Kx16 FPM/EDO-DRAM Figure 3-3 Typical System Diagram (MC68K Bus 1, 16-Bit 68000, 256Kx16 FPM/EDO-DRAM) Power Management Oscillator Decoder Decoder M/R# CS# A[20:0] AB[20:0] D[31:16] DB[15:0] CLKI A[31:21] FC0, FC1 SUSPEND# MC68030 BUS FPDAT[15:8] UD[7:0] FPDAT[7:0] LD[7:0] FPSHIFT FPSHIFT 4/8/16-bit FPFRAME FPFRAME LCD Display FPLINE DS# WE1# AS# BS# R/W# RD/WR# DRDY S1D13505F00A WE0# RED,GREEN,BLUE WAIT# HRTC LCAS# UCAS# LCAS# UCAS# RAS# RAS# WE# VRTC WE# A[8:0] D[15:0] BUSCLK RESET# MD[15:0] SIZ0 DSACK1# MA[8:0] RD# BCLK MOD LCDPWR SIZ1 RESET# FPLINE IREF CRT Display IREF 256Kx16 FPM/EDO-DRAM Figure 3-4 Typical System Diagram (MC68K Bus 2, 32-Bit 68030, 256Kx16 FPM/EDO-DRAM) S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-5 3: TYPICAL SYSTEM IMPLEMENTATION DIAGRAMS Power Management Oscillator M/R# Decoder CSn# CS# A[20:0] AB[20:0] D[15:0] DB[15:0] CLKI A[27:21] SUSPEND# Generic BUS FPDAT[15:8] UD[7:0] FPDAT[7:0] LD[7:0] FPSHIFT FPSHIFT 4/8/16-bit FPFRAME FPFRAME LCD Display FPLINE DRDY WE0# WE0# WE1# WE1# RD# FPLINE MOD S1D13505F00A LCDPWR RD# RED,GREEN,BLUE RD/WR# WAIT# RAS# LCAS# UCAS# LCAS# UCAS# WE# RAS# MD[15:0] VRTC WE# MA[11:0] A[11:0] BUSCLK RESET# D[15:0] BCLK RESET# CRT Display HRTC WAIT# IREF IREF 1Mx16 FPM/EDO-DRAM Figure 3-5 Typical System Diagram (Generic Bus, 1Mx16 FPM/EDO-DRAM) Power Management Oscillator M/R# Decoder CSn# CS# A[20:0] AB[20:0] D[15:0] DB[15:0] CLKI A[25:21] SUSPEND# MIPS BUS FPDAT[15:8] UD[7:0] FPDAT[7:0] LD[7:0] FPSHIFT FPSHIFT 4/8/16-bit FPFRAME FPFRAME LCD Display FPLINE DRDY MEMW# WE0# SBHE# WE1# MEMR# RD# MOD S1D13505F00A LCDPWR RED,GREEN,BLUE VDD WE# RAS# LCAS# UCAS# RAS# LCAS# UCAS# BUSCLK RESET# WE# BCLK RESET MD[15:0] VRTC MA[11:0] HRTC WAIT# A[11:0] RD/WR# D[15:0] RDY FPLINE IREF CRT Display IREF 1Mx16 FPM/EDO-DRAM Figure 3-6 Typical System Diagram (NEC VR41xx (MIPS) Bus, 1Mx16 FPM/EDO-DRAM) 1-6 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 3: TYPICAL SYSTEM IMPLEMENTATION DIAGRAMS . Power Management A[12:0] AB[12:0] D[31:16] DB[15:0] CLKI M/R# CS# BS# AB[16:13] SUSPEND# Philips PR31500 /PR31700 BUS Oscillator FPDAT[15:8] UD[7:0] FPDAT[7:0] LD[7:0] FPSHIFT FPSHIFT 4/8/16-bit FPFRAME FPFRAME LCD Display ALE /CARDREG AB20 FPLINE AB19 DRDY /CARDIORD AB18 /CARDIOWR AB17 /CARDxCSH WE1# /CARDxCSL RD/WR# FPLINE MOD S1D13505F00A LCDPWR RAS# LCAS# UCAS# LCAS# UCAS# WE# VRTC RAS# BUSCLK RESET# RESET# MD[15:0] DCLKOUT CRT Display HRTC WAIT# WE# /CARDxWAIT RED,GREEN,BLUE MA[11:0] WE0# A[11:0] RD# D[15:0] /RD /WE IREF IREF 1Mx16 FPM/EDO-DRAM Figure 3-7 Typical System Diagram (Philips PR31500/PR31700 Bus, 1Mx16 FPM/EDO-DRAM) . Power Management CLKI M/R# CS# BS# AB[16:13] SUSPEND# Toshiba TX3912 BUS Oscillator AB[12:0] DB[15:8] A[12:0] D[23:16] DB[7:0] D[31:24] ALE CARDREG* UD[7:0] FPDAT[7:0] LD[7:0] FPSHIFT FPSHIFT 4/8/16-bit FPFRAME FPFRAME LCD Display AB20 FPLINE AB19 DRDY AB18 CARDIORD* FPDAT[15:8] CARDIOWR* AB17 CARDxCSH* WE1# CARDxCSL* RD/WR# FPLINE MOD S1D13505F00A LCDPWR WE# RAS# LCAS# UCAS# RAS# LCAS# UCAS# BUSCLK RESET# RESET# VRTC WE# DCLKOUT CRT Display HRTC MD[15:0] WAIT# CARDxWAIT* RED,GREEN,BLUE MA[11:0] WE0# A[11:0] RD# D[15:0] RD* WE* IREF IREF 1Mx16 FPM/EDO-DRAM Figure 3-8 Typical System Diagram (Toshiba TX3912 Bus, 1Mx16 FPM/EDO-DRAM) S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-7 3: TYPICAL SYSTEM IMPLEMENTATION DIAGRAMS Oscillator Power Management Decoder Decoder M/R# CS# A[11:31] AB[20:0] D[0:15] DB[15:0] CLKI A[0:10] SUSPEND# PowerPC BUS FPDAT[15:8] UD[7:0] FPDAT[7:0] LD[7:0] FPSHIFT FPSHIFT 4/8/16-bit FPFRAME FPFRAME LCD Display FPLINE BI# TS# BS# RD/WR# S1D13505F00A RD/WR# WE0# RED,GREEN,BLUE TA# WAIT# HRTC CRT Display UCAS# UCAS# RAS# LCAS# LCAS# WE# WE# VRTC RAS# A[8:0] D[15:0] BUSCLK RESET# MD[15:0] TSIZ1 MA[8:0] RD# RESET# MOD LCDPWR TSIZ0 CLKOUT FPLINE DRDY WE1# IREF IREF 256Kx16 FPM/EDO-DRAM Figure 3-9 Typical System Diagram (Power PC Bus, 256Kx16 FPM/EDO-DRAM) Power Management Decoder Decoder M/R# CS# A[20:0] AB[20:0] D[15:0] DB[15:0] CLKI A[25:21] SUSPEND# PC Card (PCMCIA) BUS Oscillator FPDAT[15:8] UD[7:0] FPDAT[7:0] LD[7:0] FPSHIFT FPSHIFT 4/8/16-bit FPFRAME FPFRAME LCD Display FPLINE DRDY WE# WE0# CE2# WE1# LCDPWR RD# RED,GREEN,BLUE RD/WR# WE# RAS# LCAS# UCAS# WE# LCAS# UCAS# VRTC RAS# MD[15:0] BUSCLK RESET# MA[11:0] BCLK RESET# CRT Display HRTC WAIT# A[11:0] CE1# WAIT# MOD S1D13505F00A D[15:0] OE# FPLINE IREF IREF 1Mx16 FPM/EDO-DRAM Figure 3-10 Typical System Diagram (PC Card (PCMCIA) Bus, 1Mx16 FPM/EDO-DRAM) 1-8 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 4: INTERNAL DESCRIPTION 4 INTERNAL DESCRIPTION 4.1 Block Diagram Showing Datapaths 16-bit FPM/EDO-DRAM Memory Controller Register CPU R/W Display FIFO Host CPU/MPU LCD I/F LookUp Tables DAC Cursor FIFO Power Save LCD I/F CRT CRTC Clocks Figure 4-1 System Block Diagram Showing Datapaths 4.2 Block Descriptions Register The Register block contains all the register latches. Host Interface The Host Interface (I/F) block provides the means for the CPU/MPU to communicate with the display buffer and internal registers via one of the supported bus interfaces. CPU R/W The CPU R/W block synchronizes the CPU requests for display buffer access. If SwivelViewTM is enabled, the data is rotated in this block. Memory Controller The Memory Controller block arbitrates between CPU accesses and display refresh accesses as well as generates the necessary signals to interface to one of the supported 16-bit memory devices (FPMDRAM or EDO-DRAM). Display FIFO The Display FIFO block fetches display data from the Memory Controller for display refresh. S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-9 4: INTERNAL DESCRIPTION Cursor FIFO The Cursor FIFO block fetches Cursor/ink data from the Memory Controller for display refresh. Look-Up Tables The Look-Up Tables block contains three 256x4 Look-Up Tables (LUT), one for each primary color. In monochrome mode, only the green LUT is selected and used. This block contains anti-sparkle circuitry. The cursor/ink and display data are merged in this block. CRTC The CRTC generates the sync timing for the LCD and CRT, defining the vertical and horizontal display periods. LCD Interface The LCD Interface block performs Frame Rate Modulation (FRM) for passive LCD panels and generates the correct data format and timing control signals for various LCD and TFT/D-TFD panels. DAC The DAC is the Digital to Analog converter for analog CRT support. Power Save The Power Save block contains the power save mode circuitry. Clocks The Clocks module is the source of all clocks in the chip. 1-10 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 5: PINS 5 PINS 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VSS FPDAT15 FPDAT14 FPDAT13 FPDAT12 FPDAT11 FPDAT10 FPDAT9 FPDAT8 VSS FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3 FPDAT2 FPDAT1 FPDAT0 VSS FPSHIFT DRDY LCDPWR FPLINE FPFRAME VDD SUSPEND# TESTEN CLKI VSS MA3 MA4 MA2 5.1 Pinout Diagram 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 S1D13505F00A 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 MA5 MA1 MA6 MA0 MA7 MA10 MA8 MA11 MA9 VDD RAS# WE# UCAS# LCAS# VSS MD7 MD8 MD6 MD9 MD5 MD10 MD4 MD11 MD3 MD12 MD2 MD13 MD1 MD14 MD0 MD15 VDD AB2 AB1 AB0 CS# M/R# BS# RD# WE0# WE1# RD/WR# RESET# VDD BUSCLK VSS WAIT# DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD DACVSS DACVDD RED IREF DACVDD GREEN DACVDD BLUE DACVSS HRTC VRTC VDD VSS AB20 AB19 AB18 AB17 AB16 AB15 AB14 AB13 AB12 AB11 AB10 AB9 AB8 AB7 AB6 AB5 AB4 AB3 Figure 5-1 Pinout Diagram 128-pin QFP15 surface mount package S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-11 5: PINS 5.2 Pin Description Key: I O I/O A P C CD CS COx TSx TSxD CNx 1-12 = Input = Output = Bi-Directional (Input/Output) = Analog = Power pin = CMOS level input = CMOS level input with pull down resistor (typical values of 100K/180K at 5V/3.3V respectively) = CMOS level Schmitt input = CMOS output driver, x denotes driver type (see tables 6-3, 6-4, 6-5 for details) = Tri-state CMOS output driver, x denotes driver type (see tables 6-3, 6-4, 6-5 for details) = Tri-state CMOS output driver with pull down resistor (typical values of 100K/180K at 5V/3.3V respectively), x denotes driver type (see tables 6-3, 6-4, 6-5 for details) = CMOS low-noise output driver, x denotes driver type (see tables 6-3, 6-4, 6-5 for details) EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 5: PINS Host Interface Pin Name Type Pin # AB0 I 3 AB[12:1] I 119-128, 1, 2 AB[16:13] I 115-118 AB17# I 114 AB18 I 113 AB19 I 112 Table 5-1 Host Interface Pin Descriptions Reset# Driver Description State * For SH-3/SH-4 Bus, this pin inputs system address bit 0 (A0). * For MC68K Bus 1, this pin inputs the lower data strobe (LDS#). * For MC68K Bus 2, this pin inputs system address bit 0 (A0). * For Generic Bus, this pin inputs system address bit 0 (A0). * For MIPS/ISA Bus, this pin inputs system address bit 0 (SA0). * For Philips PR31500/31700 Bus, this pin inputs system address bit 0 CS Hi-Z (A0). * For Toshiba TX3912 Bus, this pin inputs system address bit 0 (A0). * For PowerPC Bus, this pin inputs system address bit 31 (A31). * For PC Card (PCMCIA) Bus, this pin inputs system address bit 0 (A0). See "Table 5-7 CPU Interface Pin Mapping" for summary. See the respective AC Timing diagram for detailed functionality. * For PowerPC Bus, these pins input the system address bits 19 through 30 (A[19:30]). * For all other busses, these pins input the system address bits 12 through C Hi-Z 1 (A[12:1]). See "Table 5-7 CPU Interface Pin Mapping" for summary. See the respective AC Timing diagram for detailed functionality. * For Philips PR31500/31700 Bus, these pins are connected to VDD. * For Toshiba TX3912 Bus, these pins are connected to VDD. * For PowerPC Bus, these pins input the system address bits 15 through 18 (A[15:18]). C Hi-Z * For all other busses, these pins input the system address bits 16 through 13 (A[16:13]). See "Table 5-7 CPU Interface Pin Mapping" for summary. See the respective AC Timing diagram for detailed functionality. * For Philips PR31500/31700 Bus, this pin inputs the I/O write command (/CARDIOWR). * For Toshiba TX3912 Bus, this pin inputs the I/O write command (CARDIOWR*). C Hi-Z * For PowerPC Bus, this pin inputs the system address bit 14 (A14). * For all other busses, this pin inputs the system address bit 17 (A17). See "Table 5-7 CPU Interface Pin Mapping" for summary. See the respective AC Timing diagram for detailed functionality. * For Philips PR31500/31700 Bus, this pin inputs the I/O read command (/ CARDIORD). * For Toshiba TX3912 Bus, this pin inputs the I/O read command (CARDIORD*). C Hi-Z * For PowerPC Bus, this pin inputs the system address bit 13 (A13). * For all other busses, this pin inputs the system address bit 18 (A18). See "Table 5-7 CPU Interface Pin Mapping" for summary. See the respective AC Timing diagram for detailed functionality. * For Philips PR31500/31700 Bus, this pin inputs the card control register access (/CARDREG). * For Toshiba TX3912 Bus, this pin inputs the card control register (CARDREG*). C Hi-Z * For PowerPC Bus, this pin inputs the system address bit 12 (A12). * For all other busses, this pin inputs the system address bit 19 (A19). See "Table 5-7 CPU Interface Pin Mapping" for summary. See the respective AC Timing diagram for detailed functionality. S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-13 5: PINS Pin Name Type Pin # AB20 I 111 DB[15:0] IO 16-31 WE1# IO 9 M/R# I 5 CS# I 4 1-14 Table 5-1 Host Interface Pin Descriptions Reset# Driver Description State * For the MIPS/ISA Bus, this pin inputs system address bit 20. Note that for the ISA Bus, the unlatched LA20 must first be latched before input to AB20. * For Philips PR31500/31700 Bus, this pin inputs the address latch enable (ALE). C Hi-Z * For Toshiba TX3912 Bus, this pin inputs the address latch enable (ALE). * For PowerPC Bus, this pin inputs the system address bit 11 (A11). * For all other busses, this pin inputs the system address bit 20 (A20). See "Table 5-7 CPU Interface Pin Mapping" for summary. See the respective AC Timing diagram for detailed functionality. These pins are the system data bus. For 8-bit bus modes, unused data pins should be tied to VDD. * For SH-3/SH-4 Bus, these pins are connected to D[15:0]. * For MC68K Bus 1, these pins are connected to D[15:0]. * For MC68K Bus 2, these pins are connected to D[31:16] for 32-bit devices (e.g. MC68030) or D[15:0] for 16-bit devices (e.g. MC68340). * For Generic Bus, these pins are connected to D[15:0]. * For MIPS/ISA Bus, these pins are connected to SD[15:0]. C/TS2 Hi-Z * For Philips PR31500/31700 Bus, these pins are connected to D[31:16]. * For Toshiba TX3912 Bus, pins [15:8] are connected to D[23:16] and pins [7:0] are connected to D[31:24]. * For PowerPC Bus, these pins are connected to D[0:15]. * For PC Card (PCMCIA) Bus, these pins are connected to D[15:0]. See "Table 5-7 CPU Interface Pin Mapping" for summary. See the respective AC Timing diagram for detailed functionality. This is a multi-purpose pin: * For SH-3/SH-4 Bus, this pin inputs the write enable signal for the upper data byte (WE1#). * For MC68K Bus 1, this pin inputs the upper data strobe (UDS#). * For MC68K Bus 2, this pin inputs the data strobe (DS#). * For Generic Bus, this pin inputs the write enable signal for the upper data byte (WE1#). * For MIPS/ISA Bus, this pin inputs the system byte high enable signal (SBHE#). CS/TS2 Hi-Z * For Philips PR31500/31700 Bus, this pin inputs the odd byte access enable signal (/CARDxCSH). * For Toshiba TX3912 Bus, this pin inputs the odd byte access enable signal (CARDxCSH*). * For PowerPC Bus, this pin outputs the burst inhibit signal (BI#). * For PC Card (PCMCIA) Bus, this pin inputs the card enable 2 signal (-CE2). See "Table 5-7 CPU Interface Pin Mapping" for summary. See the respective AC Timing diagram for detailed functionality. * For Philips PR31500/31700 Bus, this pin is connected to VDD. * For Toshiba TX3912 Bus, this pin is connected to VDD. * For all busses, this input pin is used to select between the display buffer C Hi-Z and register address spaces of the S1D13505. M/R# is set high to access the display buffer and low to access the registers. See Register Mapping. See "Table 5-7 CPU Interface Pin Mapping" on page 1-20. * For Philips PR31500/31700 Bus, this pin is connected to VDD. * For Toshiba TX3912 Bus, this pin is connected to VDD. C Hi-Z * For all busses, this is the Chip Select input. See "Table 5-7 CPU Interface Pin Mapping" on page 1-20. See the respective AC Timing diagram for detailed functionality. EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 5: PINS Pin Name Type Pin # BUSCLK I 13 BS# I 6 RD/WR# I 10 RD# I 7 Table 5-1 Host Interface Pin Descriptions Reset# Driver Description State This pin inputs the system bus clock. It is possible to apply a 2x clock and divide it by 2 internally - see MD12 in Summary of Configuration Options. * For SH-3/SH-4 Bus, this pin is connected to CKIO. * For MC68K Bus 1, this pin is connected to CLK. * For MC68K Bus 2, this pin is connected to CLK. * For Generic Bus, this pin is connected to BCLK. C Hi-Z * For MIPS/ISA Bus, this pin is connected to CLK. * For Philips PR31500/31700 Bus, this pin is connected to DCLKOUT. * For Toshiba TX3912 Bus, this pin is connected to DCLKOUT. * For PowerPC Bus, this pin is connected to CLKOUT. * For PC Card (PCMCIA) Bus, this pin is connected to the input clock (CLKI, pin 69). See "Table 5-7 CPU Interface Pin Mapping" for summary. See the respective AC Timing diagram for detailed functionality. This is a multi-purpose pin: * For SH-3/SH-4 Bus, this pin inputs the bus start signal (BS#). * For MC68K Bus 1, this pin inputs the address strobe (AS#). * For MC68K Bus 2, this pin inputs the address strobe (AS#). * For Generic Bus, this pin is connected to VDD. * For MIPS/ISA Bus, this pin is connected to VDD. CS Hi-Z * For Philips PR31500/31700 Bus, this pin is connected to VDD. * For Toshiba TX3912 Bus, this pin is connected to VDD. * For PowerPC Bus, this pin inputs the Transfer Start signal (TS#). * For PC Card (PCMCIA) Bus, this pin is connected to VDD. See "Table 5-7 CPU Interface Pin Mapping" for summary. See the respective AC Timing diagram for detailed functionality. This is a multi-purpose pin: * For SH-3/SH-4 Bus, this pin inputs the read write signal (RD/WR#). The S1D13505 needs this signal for early decode of the bus cycle. * For MC68K Bus 1, this pin inputs the read write signal (R/W#). * For MC68K Bus 2, this pin inputs the read write signal (R/W#). * For Generic Bus, this pin inputs the read command for the upper data byte (RD1#). * For MIPS/ISA Bus, this pin is connected to VDD. CS Hi-Z * For Philips PR31500/31700 Bus, this pin inputs the even byte access enable signal (/CARDxCSL). * For Toshiba TX3912 Bus, this pin inputs the even byte access enable signal (CARDxCSL*). * For PowerPC Bus, this pin inputs the read write signal (RD/WR#). * For PC Card (PCMCIA) Bus, this pin inputs the card enable 1 signal (-CE1). See "Table 5-7 CPU Interface Pin Mapping" for summary. See the respective AC Timing diagram for detailed functionality. This is a multi-purpose pin: * For SH-3/SH-4 Bus, this pin inputs the read signal (RD#). * For MC68K Bus 1, this pin is connected to VDD. * For MC68K Bus 2, this pin inputs the bus size bit 1 (SIZ1). * For Generic Bus, this pin inputs the read command for the lower data byte (RD0#). * For MIPS/ISA Bus, this pin inputs the memory read signal (MEMR#). * For Philips PR31500/31700 Bus, this pin inputs the memory read comCS Hi-Z mand (/RD). * For Toshiba TX3912 Bus, this pin inputs the memory read command (RD*). * For PowerPC Bus, this pin inputs the transfer size 0 signal (TSIZ0). * For PC Card (PCMCIA) Bus, this pin inputs the output enable signal (-OE). See "Table 5-7 CPU Interface Pin Mapping" for summary. See the respective AC Timing diagram for detailed functionality. S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-15 5: PINS Pin Name Type Pin # WE0# I 8 WAIT# O 15 RESET# I 11 1-16 Table 5-1 Host Interface Pin Descriptions Reset# Driver Description State This is a multi-purpose pin: * For SH-3/SH-4 Bus, this pin inputs the write enable signal for the lower data byte (WE0#). * For MC68K Bus 1, this pin must be connected to VDD * For MC68K Bus 2, this pin inputs the bus size bit 0 (SIZ0). * For Generic Bus, this pin inputs the write enable signal for the lower data byte (WE0#). * For MIPS/ISA Bus, this pin inputs the memory write signal (MEMW#). CS Hi-Z * For Philips PR31500/31700 Bus, this pin inputs the memory write command (/WE). * For Toshiba TX3912 Bus, this pin inputs the memory write command (WE*). * For PowerPC Bus, this pin inputs the Transfer Size 1 signal (TSIZ1). * For PC Card (PCMCIA) Bus, this pin inputs the write enable signal (-WE). See "Table 5-7 CPU Interface Pin Mapping" for summary. See the respective AC Timing diagram for detailed functionality. The active polarity of the WAIT# output is configurable; the state of MD5 on the rising edge of RESET# defines the active polarity of WAIT# - see "Summary of Configuration Options". * For SH-3 Bus, this pin outputs the wait request signal (WAIT#); MD5 must be pulled low during reset by the internal pull-down resistor. * For SH-4 Bus, this pin outputs the ready signal (RDY#); MD5 must be pulled high during reset by an external pull-up resistor. * For MC68K Bus 1, this pin outputs the data transfer acknowledge signal (DTACK#); MD5 must be pulled high during reset by an external pullup resistor. * For MC68K Bus 2, this pin outputs the data transfer and size acknowledge bit 1 (DSACK1#); MD5 must be pulled high during reset by an external pull-up resistor. * For Generic Bus, this pin outputs the wait signal (WAIT#); MD5 must be pulled high during reset by an external pull-up resistor. TS2 Hi-Z * For MIPS/ISA Bus, this pin outputs the IO channel ready signal (IOCHRDY); MD5 must be pulled low during reset by the internal pulldown resistor. * For Philips PR31500/31700 Bus, this pin outputs the wait state signal (/CARDxWAIT); MD5 must be pulled low during reset by the internal pull-down resistor. * For Toshiba TX3912 Bus, this pin outputs the wait state signal (CARDxWAIT*); MD5 must be pulled low during reset by the internal pull-down resistor. * For PowerPC Bus, this pin outputs the transfer acknowledge signal (TA#); MD5 must be pulled high during reset by an external pull-up resistor. * For PC Card (PCMCIA) Bus, this pin outputs the wait signal (-WAIT); MD5 must be pulled low during reset by the internal pull-down resistor. See "Table 5-7 CPU Interface Pin Mapping" for summary. See the respective AC Timing diagram for detailed functionality. Active low input that clears all internal registers and forces all outputs to CS - their inactive states. Note that active high RESET signals must be inverted before input to this pin. EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 5: PINS Memory Interface Pin Name Type Pin # LCAS# O 51 UCAS# O 52 WE# O 53 RAS# O 54 MD[15:0] IO 34, 36, 38, 40, 42, 44, 46, 48, 49, 47, 45, 43, 41, 39, 37, 35 MA[8:0] O 58, 60, 62, 64, 66, 67, 65, 63, 61 Table 5-2 Memory Interface Pin Descriptions Reset# Driver Description State * For dual-CAS# DRAM, this is the column address strobe for the lower byte (LCAS#). CO1 1 * For single-CAS# DRAM, this is the column address strobe (CAS#). See "Table 5-8 Memory Interface Pin Mapping" for summary. See Memory Interface Timing for detailed functionality. This is a multi-purpose pin: * For dual-CAS# DRAM, this is the column address strobe for the upper byte (UCAS#). CO1 1 * For single-CAS# DRAM, this is the write enable signal for the upper byte (UWE#). See "Table 5-8 Memory Interface Pin Mapping" for summary. See Memory Interface Timing for detailed functionality. * For dual-CAS# DRAM, this is the write enable signal (WE#). * For single-CAS# DRAM, this is the write enable signal for the lower CO1 1 byte (LWE#). See "Table 5-8 Memory Interface Pin Mapping" for summary. See Memory Interface Timing for detailed functionality. Row address strobe - see Memory Interface Timing for detailed functionCO1 1 ality. * Bi-Directional memory data bus. * During reset, these pins are inputs and their states at the rising edge of RESET# are used to configure the chip - see Summary of Configuration C/TS1D Hi-Z Options. Internal pull-down resistors (typical values of 100K/180 at 5V/3.3V respectively) pull the reset states to 0. External pull-up resistors can be used to pull the reset states to 1. See Memory Interface Timing for detailed functionality. Multiplexed memory address - see Memory Interface Timing for functionCO1 Output ality. MA9 IO 56 C/TS1 Output MA10 IO 59 C/TS1 Output MA11 IO 57 C/TS1 Output S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) This is a multi-purpose pin: * For 2M byte DRAM, this is memory address bit 9 (MA9). * For asymmetrical 512K byte DRAM, this is memory address bit 9 (MA9). * For symmetrical 512K byte DRAM, this pin can be used as general purpose IO pin 3 (GPIO3). Note that unless configured otherwise, this pin defaults to an input and must be driven to a valid logic level. See "Table 5-8 Memory Interface Pin Mapping" for summary. See Memory Interface Timing for detailed functionality. This is a multi-purpose pin: * For asymmetrical 2M byte DRAM this is memory address bit 10 (MA10). * For symmetrical 2M byte DRAM and all 512K byte DRAM this pin can be used as general purpose IO pin 1 (GPIO1). Note that unless configured otherwise, this pin defaults to an input and must be driven to a valid logic level. See "Table 5-8 Memory Interface Pin Mapping" for summary. See Memory Interface Timing for detailed functionality. This is a multi-purpose pin: * For asymmetrical 2M byte DRAM this is memory address bit 11 (MA11). * For symmetrical 2M byte DRAM and all 512K byte DRAM this pin can be used as general purpose IO pin 2 (GPIO2). Note that unless configured otherwise, this pin defaults to an input and must be driven to a valid logic level. See "Table 5-8 Memory Interface Pin Mapping" for summary. See Memory Interface Timing for detailed functionality. EPSON 1-17 5: PINS LCD Interface Pin Name Type FPDAT[15:0] O FPFRAME FPLINE FPSHIFT Pin # Cell O O O 95-88, 86-79 73 74 77 CN3 CN3 CO3 LCDPWR O 75 CO1 DRDY O 76 CN3 CN3 Table 5-3 LCD Interface Pin Descriptions RESET# Description State Panel data bus. Not all pins are used for some panels - see "Table 5-9 Output LCD Interface Pin Mapping" for details. Unused pins are driven low. Output Frame pulse Output Line pulse Output Shift clock Output LCD power control output. The active polarity of this output is if MD[10]=0 selected by the state of MD10 at the rising edge of RESET# - see "5.3 1 Summary of Configuration Options". This output is controlled by the if MD[10]=1 power save mode circuitry - see "15 Power Save Modes" for details. This is a multi-purpose pin: * For TFT/D-TFD panels this is the display enable output (DRDY). * For passive LCD with Format 1 interface this is the 2nd Shift Clock Output (FPSHIFT2). * For all other LCD panels this is the LCD backplane bias signal (MOD). See "Table 5-9 LCD Interface Pin Mapping" and REG[02h] for details. CRT Interface Pin Name Type Pin # Cell HRTC VRTC RED GREEN BLUE IO IO O O O 107 108 100 103 105 CN3 CN3 A A A IREF I 101 A 1-18 Table 5-4 Clock Input Pin Description RESET# Description State Output Horizontal retrace signal for CRT Output Vertical retrace signal for CRT Analog output for CRT color Red Analog output for CRT color Green Analog output for CRT color Blue Current reference for DAC - see Analog Pins. This pin must be left unconnected if the DAC is not needed. EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 5: PINS Miscellaneous Table 5-5 Miscellaneous Interface Pin Descriptions Cell RESET# State Description This pin can be used as a power-down input (SUSPEND#) or as an output possibly used for controlling the LCD backlight power: * When MD9 = 0 at rising edge of RESET#, this pin is an activeHi-Z if MD[9]=0 low Schmitt input used to put the S1D13505 into Hardware susHigh pend mode - see "15 Power Save Modes" for details. IO 71 CS/TS1 if MD[10:9]=01 * When MD[10:9] = 01 at rising edge of RESET#, this pin is an Low output (GPO) with a reset state of 1. Its state is controlled by if MD[10:9]=11 REG[21h] bit 7. * When MD[10:9] = 11 at rising edge of RESET#, this pin is an output (GPO) with a reset state of 0. Its state is controlled by REG[21h] bit 7. Input clock for the internal pixel clock (PCLK) and memory clock (MCLK). PCLK and MCLK are derived from CLKI - see REG[19h] I 69 C for details. Test Enable. This pin should be connected to VSS for normal operaI 70 CD Hi-Z tion. 12, 33, 55, VDD P P 72, 97, 109 99, 102, DAC VDD P P 104 14, 32, 50, VSS P 68, 78, 87, P 96, 110 P 98, 106 P DAC VSS Pin Name Type SUSPEND# CLKI TESTEN VDD DACVDD VSS DACVSS Pin # S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-19 5: PINS 5.3 Summary of Configuration Options Pin Name MD0 MD[3:1] MD4 MD5 MD[7:6] MD8 MD9 MD10 MD11 MD12 MD[15:13] Table 5-6 Summary of Power On / Reset Options Value on this pin at rising edge of RESET# is used to configure: (1/0) 1 0 8-bit host bus interface 16-bit host bus interface Select host bus interface:MD[11] = 0: 000 = SH-3/SH-4 bus interface 001 = MC68K Bus 1 010 = MC68K Bus 2 011 = Generic 100 = Reserved 101 = MIPS/ISA 110 = PowerPC 111 = PC Card (when MD11 = 1Philips PR31500/PR31700 or Toshiba TX3912 Bus) Little Endian Big Endian WAIT# is active high (1 = insert wait state) WAIT# is active low (0 = insert wait state) Memory Address/GPIO configuration: 00 = symmetrical 256Kx16 DRAM. MA[8:0] = DRAM address. MA[11:9] = GPIO2,1,3 pins. 01 = symmetrical 1Mx16 DRAM. MA[9:0] = DRAM address. MA[10:11] = GPIO2,1 pins. 10 = asymmetrical 256Kx16 DRAM. MA[9:0] = DRAM address. MA[10:11] = GPIO2,1 pins. 11 = asymmetrical 1Mx16 DRAM. MA[11:0] = DRAM address. Not used SUSPEND# pin configured as GPO output SUSPEND# pin configured as SUSPEND# input Active low LCDPWR and GPO polarities Active high LCDPWR and GPO polarities Alternate Host Bus Interface Selected Primary Host Bus Interface Selected BUSCLK input divided by 2 BUSCLK input not divided Not used 5.4 Multiple Function Pin Mapping Table 5-7 CPU Interface Pin Mapping Philips S1D13505 SH-3 MC68K MC68K Generic MIPS/ISA PR31500 Toshiba PowerPC PC Card SH-4 (PCMCIA) Pin Name Bus 1 Bus 2 TX3912 /PR31700 AB20 A20 A20 A20 A20 A20 LatchA20 ALE ALE A11 A20 AB19 A19 A19 A19 A19 A19 SA19 /CARCARA12 A19 DREG DREG* AB18 A18 A18 A18 A18 A18 SA18 /CARCARA13 A18 DIORD DIORD* AB17 A17 A17 A17 A17 A17 SA17 /CARCARA14 A17 DIOWR DIOWR* AB[16:13] A[16:13] A[16:13] A[16:13] A[16:13] A[16:13] SA[16:13] VDD VDD A[15:18] A[16:13] AB[12:1] A[12:1] A[12:1] A[12:1] A[12:1] A[12:1] SA[12:1] A[12:1] A[12:1] A[19:30] A[12:1] AB0 A0 A0 LDS# A0 A0 SA0 A0 A0 A31 A0 DB[15:8] D[15:8] D[15:8] D[15:8] D[31:24] D[15:8] SD[15:8] D[31:24] D[31:24] D[0:7] D[15:8] DB[7:0] D[7:0] D[7:0] D[7:0] D[23:16] D[7:0] SD[7:0] D[23:16] D[23:16] D[8:15] D[7:0] WE1# WE1# WE1# UDS# DS# WE1# SBHE# /CARD CARD BI# -CE2 xCSH xCSH* M/R# External Decode VDD External Decode CS# External Decode VDD External Decode BUSCLK CKIO CKIO CLK CLK BCLK CLK DCLKDCLK- CLKOUT CLKI OUT OUT BS# BS# BS# AS# AS# VDD VDD VDD VDD TS# VDD RD/WR# RD/WR# RD/WR# R/W# R/W# RD1# VDD /CARD CARD RD/WR# -CE1 xCSL xCSL* RD# RD# RD# VDD SIZ1 RD0# MEMR# /RD RD* TSIZ0 -OE WE0# WE0# WE0# VDD SIZ0 WE0# MEMW# /WE WE* TSIZ1 -WE WAIT# WAIT# RDY DTACK# DSACK1# WAIT# IOCHRD /CARD x CARD x TA# -WAIT Y WAIT WAIT* RESET# RESET# RESET# RESET# RESET# RESET# inverted RESET# PON* RESET# inverted RESET RESET 1-20 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 5: PINS S1D13505 Pin Name MD[15:0] MA[8:0] MA9 MA10 MA11 UCAS# LCAS# WE# RAS# Sym 256Kx16 2-CAS# 2-WE# GPIO3 UCAS# LCAS# WE# UWE# CAS# LWE# Table 5-8 Memory Interface Pin Mapping FPM/EDO-DRAM Asym 256Kx16 Sym 1Mx16 2-CAS# 2-WE# 2-CAS# 2-WE# D[15:0] A[8:0] A9 GPIO1 GPIO2 UCAS# UWE# UCAS# UWE# LCAS# CAS# LCAS# CAS# WE# LWE# WE# LWE# RAS# Asym 1Mx16 2-CAS# 2-WE# A9 A10 A11 UCAS# LCAS# WE# UWE# CAS# LWE# Notes: * All GPIO pins default to input on reset and unless programmed otherwise, should be connected to either VSS or IO VDD if not used. * The bus signal A0 is not used by the S1D13505 internally. S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-21 5: PINS Table 5-9 LCD Interface Pin Mapping S1D13505 Pin Name Monochrome Passive Panel Single 4-bit FPFRAME FPLINE FPSHIFT DRDY FPDAT0 FPDAT1 FPDAT2 FPDAT3 FPDAT4 FPDAT5 FPDAT6 FPDAT7 FPDAT8 FPDAT9 FPDAT10 FPDAT11 FPDAT12 FPDAT13 FPDAT14 FPDAT15 1-22 8-bit Color Passive Panel D0 D1 D2 D3 D4 D5 D6 D7 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 Single Format 1 Format 2 Single 8-bit 4-bit 8-bit driven 0 driven 0 driven 0 driven 0 D0 D1 D2 D3 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 FPSHIFT 2 D0 D1 D2 D3 D4 D5 D6 D7 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 MOD driven 0 driven 0 driven 0 driven 0 D0 D1 D2 D3 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 Single Dual LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 Color TFT/D-TFD Panel Single Dual 8-bit 16-bit 8-bit FPFRAME FPLINE FPSHIFT MOD D0 D1 D2 D3 D4 D5 D6 D7 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 EPSON D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 16-bit 9-bit 12-bit 18-bit DRDY LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 LD4 LD5 LD6 LD7 UD4 UD5 UD6 UD7 R2 R1 R0 G2 G1 G0 B2 B1 B0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 R3 R2 R1 G3 G2 G1 B3 B2 B1 R0 driven 0 G0 driven 0 driven 0 B0 driven 0 R5 R4 R3 G5 G4 G3 B5 B4 B3 R2 R1 G2 G1 G0 B2 B1 S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 5: PINS 5.5 CRT Interface The following figure shows the external circuitry for the CRT interface. DAC VDD = 3.3V DAC VDD = 2.7V to 5.5V OR 1.5k 1% 4.6mA IREF 4.6mA 1F 4.6mA V+ 2N2222 R 140 1% 1k 1% DAC VSS V- DAC VSS 290 1% 29 1% DAC VSS R G B } 150 1% 150 1% DAC VSS DAC VSS LM334 1N457 DAC VSS To CRT 150 1% DAC VSS Figure 5-2 External Circuitry for CRT Interface S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-23 6: D.C. CHARACTERISTICS 6 D.C. CHARACTERISTICS Symbol VDD DAC VDD VIN VOUT TSTG TSOL Parameter Supply Voltage Supply Voltage Input Voltage Output Voltage Storage Temperature Solder Temperature/Time Symbol VDD VIN TOPR Parameter Supply Voltage Input Voltage Operating Temperature Symbol IDDS IIZ IOZ VOH VOL VIH VIL VT+ VTVH1 RPD CI CO CIO Symbol IDDS IIZ IOZ VOH VOL VIH VIL VT+ VTVH1 RPD CI CO CIO 1-24 Table 6-1 Absolute Maximum Ratings Rating VSS - 0.3 to 6.0 VSS - 0.3 to 6.0 VSS - 0.3 to VDD + 0.5 VSS - 0.3 to VDD + 0.5 -65 to 150 260 for 10 sec. max at lead Table 6-2 Recommended Operating Conditions Condition Min. VSS = 0V 2.7 VSS -40 Typ. 3.0/3.3/5.0 25 Table 6-3 Electrical Characteristics for VDD = 5.0V Typical Parameter Condition Min. Typ. Quiescent Current Quiescent Conditions Input Leakage Current -1 Output Leakage Current -1 High Level Output Voltage VDD = min VDD - 0.4 IOL = -4mA (Type1), -8mA (Type2), -12mA (Type3) Low Level Output Voltage VDD = min IOL = 4mA (Type1), 8mA (Type2), 12mA (Type3) High Level Input Voltage CMOS level, VDD = max 3.5 Low Level Input Voltage CMOS level, VDD = min High Level Input Voltage CMOS Schmitt, VDD = 5.0V Low Level Input Voltage CMOS Schmitt, VDD = 5.0V 0.8 Hysteresis Voltage CMOS Schmitt, VDD = 5.0V 0.3 Pull Down Resistance VI = VDD 50 100 Input Pin Capacitance Output Pin Capacitance Bi-Directional Pin Capacitance Table 6-4 Electrical Characteristics for VDD = 3.3V Typical Parameter Condition Min. Typ. Quiescent Current Quiescent Conditions Input Leakage Current -1 Output Leakage Current -1 High Level Output Voltage VDD = min VDD - 0.3 IOL = -2mA (Type1), -4mA (Type2), -6mA (Type3) Low Level Output Voltage VDD = min IOL = 2mA (Type1), 4mA (Type2), 6mA (Type3) High Level Input Voltage CMOS level, VDD = max 2.2 Low Level Input Voltage CMOS level, VDD = min High Level Input Voltage CMOS Schmitt, VDD = 3.3V Low Level Input Voltage CMOS Schmitt, VDD = 3.3V 0.6 Hysteresis Voltage CMOS Schmitt, VDD = 3.3V 0.1 Pull Down Resistance VI = VDD 90 180 Input Pin Capacitance Output Pin Capacitance Bi-Directional Pin Capacitance EPSON Units V V V V C C Max. 5.5 VDD 85 Units V V C Max. 400 1 1 Units A A A V 0.4 V 1.0 4.0 200 12 12 12 V V V V V k pF pF pF Max. 290 1 1 Units A A A V 0.3 V 0.8 2.4 360 12 12 12 V V V V V k pF pF pF S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 6: D.C. CHARACTERISTICS Symbol IDDS IIZ IOZ VOH VOL VIH VIL VT+ VTVH1 RPD CI CO CIO Table 6-5 Electrical Characteristics for VDD = 3.0V Typical Parameter Condition Min. Typ. Quiescent Current Quiescent Conditions Input Leakage Current -1 Output Leakage Current -1 High Level Output Voltage VDD = min VDD - 0.3 IOL = -1.8mA (Type1), -3.5mA (Type2), -5mA (Type3) Low Level Output Voltage VDD = min IOL = 1.8mA (Type1), 3.5mA (Type2), 5mA (Type3) High Level Input Voltage CMOS level, VDD = max 2.0 Low Level Input Voltage CMOS level, VDD = min High Level Input Voltage CMOS Schmitt, VDD = 3.0V Low Level Input Voltage CMOS Schmitt, VDD = 3.0V 0.5 Hysteresis Voltage CMOS Schmitt, VDD = 3.0V 0.1 Pull Down Resistance VI = VDD 100 200 Input Pin Capacitance Output Pin Capacitance Bi-Directional Pin Capacitance S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON Max. 260 1 1 Units A A A V 0.3 V 0.8 2.3 400 12 12 12 V V V V V k pF pF pF 1-25 7: A.C. CHARACTERISTICS 7 A.C. CHARACTERISTICS Conditions: Conditions: VDD = 3.0V 10% and VDD = 5.0V 10% TA = -40C to 85C Trise and Tfall for all inputs must be 5 nsec (10% to 90%) CL = 50pF (CPU Interface), unless noted CL = 100pF (LCD Panel Interface) CL = 10pF (Display Buffer Interface) CL = 10pF (CRT Interface) 7.1 CPU Interface Timing SH-4 Interface Timing t1 t2 t3 CKIO t4 t5 A[20:0], M/R# RD/WR# t6 t7 BS# t8 t12 CSn# t10 t9 WEn# RD# t12 t11 RDY# t14 t13 D[15:0](write) t15 t16 D[15:0](read) Figure 7-1 SH-4 Timing Notes: * The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected. * The SH-4 Wait State Control Register for the area in which the S1D13505 resides must be set to a non-zero value. The SH-4 read-to-write cycle transition must be set to a non-zero value (with reference to BUSCLK). 1-26 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 7: A.C. CHARACTERISTICS Table 7-1 SH-4 Timing Symbol 3.0Va Parameter Min. 15 6 6 3 0 4 1 4 Max. 5.0Vb Min. Max. 15 6 6 3 0 4 1 4 Units t1 t2 t3 t4 t5 t6 t7 t8 Clock period Clock pulse width high Clock pulse width low A[20:0], M/R#, RD/WR# setup to CKIO A[20:0], M/R#, RD/WR# hold from CS# BS# setup BS# hold CSn# setup t9#2 Falling edge RD# to DB[15:0] driven 0 t10 Rising edge CSn# to RDY# tri-state Falling edge CSn# to RDY# driven 5 0 25 15 2.5 0 10 10 ns ns CKIO to WAIT# delay 4 10 20 3.6 10 12 ns ns t11#1 t12 t13 t14 t15 t16 DB[15:0] setup to 2nd CKIO after BS# (write cycle) DB[15:0] hold (write cycle) DB[15:0] valid to RDY# falling edge (read cycle) Rising edge RD# to DB[15:0] tri-state (read cycle) 0 0 5 0 25 0 0 2.5 ns ns ns ns ns ns ns ns ns 10 ns ns ns a Two Software WAIT States Required b One Software WAIT State Required #1. If the S1D13505 host interface is disabled, the timing for RDY# driven is relative to the falling edge of CSn# or the first positive edge of CKIO after A[20:0], M/R# becomes valid, whichever one is later. #2. If the S1D13505 host interface is disabled, the timing for D[15:0] driven is relative to the falling edge of RD# or the first positive edge of CKIO after A[20:0], M/R# becomes valid, whichever one is later. S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-27 7: A.C. CHARACTERISTICS SH-3 Interface Timing t1 t2 t3 CKIO t4 t5 A[20:0], M/R# RD/WR# t6 t7 BS# t8 t12 CSn# t9 t10 WEn# RD# t12 t11 WAIT# t14 t13 D[15:0](write) t15 t16 D[15:0](read) Figure 7-2 SH-3 Timing Notes: * The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected. * The SH-3 Wait State Control Register for the area in which the S1D13505 resides must be set to a non-zero value. 1-28 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 7: A.C. CHARACTERISTICS Table 7-2 SH-3 Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9#2 t10 t11#1 t12 t13 t14 t15 t16 Parameter Clock period Clock pulse width high Clock pulse width low A[20:0], M/R#, RD/WR# setup to CKIO A[20:0], M/R#, RD/WR# hold from CS# BS# setup BS# hold CSn# setup Falling edge RD# to DB[15:0] driven Rising edge CSn# to WAIT# tri-state Falling edge CSn# to WAIT# driven CKIO to WAIT# delay DB[15:0] setup to 2nd CKIO after BS# (write cycle) DB[15:0] hold (write cycle) DB[15:0] valid to WAIT# rising edge (read cycle) Rising edge RD# to DB[15:0] tri-state (read cycle) 3.0Va Min. Max. 16.6 6 6 3 0 4 1 4 0 5 25 0 15 4 20 10 0 0 5 25 5.0Vb Min. Max. 16.6 6 6 3 0 4 1 4 0 2.5 10 0 10 3.6 12 10 0 0 2.5 10 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns a Two Software WAIT States Required b One Software WAIT State Required #1. If the S1D13505 host interface is disabled, the timing for WAIT# driven is relative to the falling edge of CSn# or the first positive edge of CKIO after A[20:0], M/R# becomes valid, whichever one is later. #2. If the S1D13505 host interface is disabled, the timing for D[15:0] driven is relative to the falling edge of RD# or the first positive edge of CKIO after A[20:0], M/R# becomes valid, whichever one is later. S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-29 7: A.C. CHARACTERISTICS MC68K Bus 1 Interface Timing (e.g. MC68000) t1 t2 t3 CLK t5 t4 A[20:1] M/R# t6 CS# t17 AS# t11 UDS# LDS# t8 t7 R/W# t9 t10 DTACK# t12 t13 D[15:0](write) t14 t15 t16 D[15:0](read) Figure 7-3 MC68000 Timing Note: The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected. 1-30 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 7: A.C. CHARACTERISTICS Table 7-3 MC68000 Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9#1 t10 t11 t12 t13 t14#2 t15 t16 t17 3.3V Parameter Clock period Clock pulse width high Clock pulse width low A[20:1], M/R# setup to first CLK where CS# = 0 AS# = 0, and either UDS# = 0 or LDS# = 0 A[20:1], M/R# hold from AS# CS# hold from AS# R/W# setup to before to either UDS# = 0 or LDS# = 0 R/W# hold from AS# AS# = 0 and CS# = 0 to DTACK# driven high AS# high to DTACK# high First BCLK where AS# = 1 to DTACK# high impedance D[15:0] valid to third CLK where CS# = 0 AS# = 0, and either UDS# = 0 or LDS# = 0 (write cycle) D[15:0] hold from falling edge of DTACK# (write cycle) Falling edge of UDS# = 0 or LDS# = 0 to DB driven (read cycle) D[15:0] valid to DTACK# falling edge (read cycle) UDS# and LDS# high to D[15:0] invalid/high impedance (read cycle) AS# high setup to CLK Min. 20 6 6 10 0 0 10 0 0 3 5.0V Max. Min. 20 6 6 10 Units ns ns ns ns 10 10 ns ns ns ns ns ns ns ns 0 0 0 5 2 0 0 0 2.5 2 ns ns ns ns ns 18 25 25 0 0 10 0 0 3 Max. 12 10 10 #1. If the S1D13505 host interface is disabled, the timing for DTACK# driven high is relative to the falling edge of CS#, AS# or the first positive edge of CLK after A[20:1], M/R# becomes valid, whichever one is later. #2. If the S1D13505 host interface is disabled, the timing for D[15:0] driven is relative to the falling edge of UDS#, LDS# or the first positive edge of CLK after A[20:1], M/R# becomes valid, whichever one is later. S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-31 7: A.C. CHARACTERISTICS MC68K Bus 2 Interface Timing (e.g. MC68030) t1 t2 t3 CLK t5 t4 A[20:0] SIZ[1:0] M/R# t6 CS# t17 AS# t11 DS# t7 t8 R/W# t9 t10 DSACK1# t12 t13 D[31:16](write) t14 t15 t16 D[31:16](read) Figure 7-4 MC68030 Timing Note: The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected. 1-32 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 7: A.C. CHARACTERISTICS Table 7-4 MC68030 Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9#1 t10 t11 t12 t13 t14#2 t15 t16 t17 3.3V Parameter Clock period Clock pulse width high Clock pulse width low A[20:1], M/R# setup to first CLK where CS# = 0 AS# = 0, and either UDS# = 0 or LDS# = 0 A[20:1], M/R# hold from AS# CS# hold from AS# R/W# setup to before to either UDS# = 0 or LDS# = 0 R/W# hold from AS# AS# = 0 and CS# = 0 to DTACK# driven high AS# high to DTACK# high First BCLK where AS# = 1 to DTACK# high impedance D[15:0] valid to third CLK where CS# = 0 AS# = 0, and either UDS# = 0 or LDS# = 0 (write cycle) D[15:0] hold from falling edge of DTACK# (write cycle) Falling edge of UDS# = 0 or LDS# = 0 to DB driven (read cycle) D[15:0] valid to DTACK# falling edge (read cycle) UDS# and LDS# high to D[15:0] invalid/high impedance (read cycle) AS# high setup to CLK Min. 20 6 6 10 0 0 10 0 0 3 5.0V Max. Min. 20 6 6 10 Units ns ns ns ns 10 10 ns ns ns ns ns ns ns ns 0 0 0 5 2 0 0 0 2.5 2 ns ns ns ns ns 18 25 25 0 0 10 0 0 3 Max. 12 10 10 #1. If the S1D13505 host interface is disabled, the timing for DSACK1# driven high is relative to the falling edge of CS#, AS# or the first positive edge of CLK after A[20:0], M/R# becomes valid, whichever one is later. #2. If the S1D13505 host interface is disabled, the timing for D[31:16] driven is relative to the falling edge of UDS#, LDS# or the first positive edge of CLK after A[20:0], M/R# becomes valid, which ever one is later. S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-33 7: A.C. CHARACTERISTICS PC Card Interface Timing t1 t2 t3 CLK t5 t4 A[20:0] M/R# CE#[1:0] t6 CS# OE# WE# t7 t8 WAIT# t10 t9 D[15:0](write) t11 t12 t13 D[15:0](read) Figure 7-5 PC Card Interface Timing Note: The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected. 1-34 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 7: A.C. CHARACTERISTICS Table 7-5 PC Card Interface Timing Symbol t1 t2 t3 t4 t5 t6 t7#1 t8 t9 t10 t11#2 t12 t13 3.0V Parameter Clock period Clock pulse width high Clock pulse width low A[20:0], M/R# setup to first CLK where CE# = 0 and either OE# = 0 or WE# = 0 A[20:0], M/R# hold from rising edge of either OE# or WE# CE# hold from rising edge of either OE# or WE# Falling edge of either OE# or WE# to -WAIT driven low Rising edge of either OE# or WE# to -WAIT tri-state D[15:0] setup to third CLK where CE# = 0 and WE# = 0 (write cycle) D[15:0] hold (write cycle) Falling edge OE# toD[15:0] driven (read cycle) D[15:0] setup to rising edge WAIT# (read cycle) Rising edge of OE# to D[15:0] tri-state (read cycle) Min. 20 6 6 10 0 0 0 5 10 0 0 0 5 5.0V Max. 15 25 25 Min. 20 6 6 10 0 0 0 2.5 10 0 0 0 5 Max. Units ns ns ns ns 10 10 10 ns ns ns ns ns ns ns ns ns #1. If the S1D13505 host interface is disabled, the timing for WAIT# driven low is relative to the falling edge of OE#, WE# or the first positive edge of CLK after A[20:0], M/R# becomes valid, whichever one is later. #2. If the S1D13505 host interface is disabled, the timing for D[15:0] driven is relative to the falling edge of OE# or the first positive edge of CLK after A[20:0], M/R# becomes valid, whichever one is later. S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-35 7: A.C. CHARACTERISTICS Generic Interface Timing t1 t2 t3 CLK t5 t4 A[20:0] M/R# t6 CS# RD0#, RD1# WE0#, WE1# t7 t8 WAIT# t10 t9 D[15:0](write) t11 t12 t13 D[15:0](read) Figure 7-6 Generic Timing Note: The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected. 1-36 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 7: A.C. CHARACTERISTICS Table 7-6 Generic Timing Symbol t1 t2 t3 t4 t5 t6 t7#1 t8 t9 t10 t11#2 t12 t13 3.0V Parameter Clock period Clock pulse width high Clock pulse width low A[20:0], M/R# setup to first CLK where CS# = 0 and either RD0#, RD1#, WE0# or WE1# = 0 A[20:0], M/R# hold from rising edge of either RD0#, RD1#, WE0# or WE1# CS# hold from rising edge of either RD0#, RD1#, WE0# or WE1# Falling edge of either RD0#, RD1#, WE0# or WE1# to WAIT# driven low Rising edge of either RD0#, RD1#, WE0# or WE1# to WAIT# tri-state D[15:0] setup to third CLK where CS# = 0 and WE0#, WE1# = 0 (write cycle) D[15:0] hold (write cycle) Falling edge RD0#, RD1# toD[15:0] driven (read cycle) D[15:0] setup to rising edge WAIT# (read cycle) Rising edge of RD0#, RD#1 to D[15:0] tri-state (read cycle) Min. 20 6 6 10 5.0V Max. 0 0 0 5 10 0 0 0 5 Min. 20 6 6 10 Max. ns ns ns ns 0 15 25 25 0 0 2.5 10 0 0 0 5 Units ns 10 10 10 ns ns ns ns ns ns ns ns #1. If the S1D13505 host interface is disabled, the timing for WAIT# driven low is relative to the falling edge of RD0#, RD1#, WE0#, WE1# or the first positive edge of CLK after A[20:0], M/R# becomes valid, whichever one is later. #2. If the S1D13505 host interface is disabled, the timing for D[15:0] driven is relative to the falling edge of RD0#, RD1# or the first positive edge of CLK after A[20:0], M/R# becomes valid, whichever one is later. S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-37 7: A.C. CHARACTERISTICS MIPS/ISA Interface Timing t1 t2 t3 BUSCLK t5 t4 LatchA20 SA[19:0] M/R#, SBHE# t6 CS# MEMR# MEMW# t7 t8 IOCHRDY t9 t10 SD[15:0](write) t11 t12 t13 SD[15:0](read) Figure 7-7 MIPS/ISA Timing Note: The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected. 1-38 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 7: A.C. CHARACTERISTICS Table 7-7 MIPS/ISA Timing Symbol t1 t2 t3 t4 t5 t6 t7#1 t8 t9 t10 t11#2 t12 t13 3.0V Parameter Clock period Clock pulse width high Clock pulse width low LatchA20, SA[19:0], M/R#, SBHE# setup to first BUSCLK where CS# = 0 and either MEMR# = 0 or MEMW# = 0 LatchA20, SA[19:0], M/R#, SBHE# hold from rising edge of either MEMR# or MEMW# CS# hold from rising edge of either MEMR# or MEMW# Falling edge of either MEMR# or MEMW# to IOCHRDY# driven low Rising edge of either MEMR# or MEMW# to IOCHRDY# tri-state SD[15:0] setup to third BUSCLK where CS# = 0 MEMW# = 0 (write cycle) SD[15:0] hold (write cycle) Falling edge MEMR# toSD[15:0] driven (read cycle) SD[15:0] setup to rising edge IOCHRDY# (read cycle) Rising edge of MEMR# toSD[15:0] tri-state (read cycle) Min. 20 6 6 10 5.0V Max. Min. 20 6 6 10 Max. Units ns ns ns ns 0 0 ns 0 0 5 10 0 0 2.5 10 ns ns ns ns 0 0 0 5 25 25 0 0 0 5 10 10 ns ns ns ns #1. If the S1D13505 host interface is disabled, the timing for IOCHRDY driven low is relative to the falling edge of MEMR#, MEMW# or the first positive edge of BUSCLK after LatchA20, SA[19:0], M/R# becomes valid, whichever one is later. #2. If the S1D13505 host interface is disabled, the timing for SD[15:0] driven is relative to the falling edge of MEMR# or the first positive edge of BUSCLK after LatchA20, SA[19:0], M/R# becomes valid, whichever one is later. S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-39 7: A.C. CHARACTERISTICS Philips Interface Timing (e.g. PR31500/PR31700) t1 t3 t2 DCLKOUT t5 t4 ADDR[12:0] t6 t7 ALE t8 CARDREG# CARDxCSH# CARDxCSL# CARDIORD# CARDIOWR# WE# RD# t9 t10 CARDxWAIT# t11 t12 D[31:16](write) t13 t14 t15 D[31:16](read) Figure 7-8 Philips Timing 1-40 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 7: A.C. CHARACTERISTICS Table 7-8 Philips Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9#1 t10 t11 t12 t13#2 t14 t15 3.0V Min. Max. 13.3 6 6 10 0 10 5 0 0 15 5 25 10 0 1 0 5 25 Parameter Clock period Clock pulse width low Clock pulse width high ADDR[12:0] setup to first CLK of cycle ADDR[12:0] hold from command invalid ADDR[12:0] setup to falling edge ALE ADDR[12:0] hold from falling edge ALE CARDREG# hold from command invalid Falling edge of chip select to CARDxWAIT# driven Command invalid to CARDxWAIT# tri-state D[31:16] valid to first CLK of cycle (write cycle) D[31:16] hold from rising edge of CARDxWAIT# Chip select to D[31:16] driven (read cycle) D[31:16] setup to rising edge CARDxWAIT# (read cycle) Command invalid to D[31:16] tri-state (read cycle) 5.0V Min. Max. 13.3 6 6 10 0 10 5 0 0 9 2.5 10 10 0 1 0 2.5 10 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns #1. If the S1D13505 host interface is disabled, the timing for CARDxWAIT# driven is relative to the falling edge of chip select or the second positive edge of DCLKOUT after ADDR[12:0] becomes valid, which ever one is later. #2. If the S1D13505 host interface is disabled, the timing for D[31:16] driven is relative to the falling edge of chip select or the second positive edge of DCLKOUT after ADDR[12:0] becomes valid, whichever one is later. Note: The Philips interface has different clock input requirements as follows: t t PWH PWL 90% V IH VIL 10% t tr T f OSC Figure 7-9 Clock Input Requirements for BUSCLK Using Philips Local Bus Symbol TOSC tPWH tPWL tf tr Table 7-9 Clock Input Requirements for BUSCLK Using Philips Local Bus Parameter Min. Max. Input Clock Period 13.3 Input Clock Pulse Width High 6 Input Clock Pulse Width Low 6 Input Clock Fall Time (10%-90%) 5 Input Clock Rise Time (10%-90%) 5 S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON Units ns ns ns ns ns 1-41 7: A.C. CHARACTERISTICS Toshiba Interface Timing (e.g. TX3912) t1 t3 t2 DCLKOUT t4 t5 ADDR[12:0] t6 t7 ALE t8 CARDREG* CARDxCSH* CARDxCSL* CARDIORD* CARDIOWR* WE* RD* t9 t10 CARDxWAIT* t11 t12 D[31:16](write) t13 t14 t15 D[31:16](read) Figure 7-10 Toshiba Timing 1-42 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 7: A.C. CHARACTERISTICS Table 7-10 Toshiba Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9#1 t10 t11 t12 t13#2 t14 t15 Parameter Clock period Clock pulse width low Clock pulse width high ADDR[12:0] setup to first CLK of cycle ADDR[12:0] hold from command invalid ADDR[12:0] setup to falling edge ALE ADDR[12:0] hold from falling edge ALE CARDREG* hold from command invalid Falling edge of chip select to CARDxWAIT* driven Command invalid to CARDxWAIT* tri-state D[31:16] valid to first CLK of cycle (write cycle) D[31:16] hold from rising edge of CARDxWAIT* Chip select to D[31:16] driven (read cycle) D[31:16] setup to rising edge CARDxWAIT* (read cycle) Command invalid to D[31:16] tri-state (read cycle) 3.0V Min. Max. 13.3 5.4 5.4 10 0 10 5 0 0 15 5 25 10 0 1 0 5 25 5.0V Min. Max. 13.3 5.4 5.4 10 0 10 5 0 0 9 2.5 10 10 0 1 0 2.5 10 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns #1. If the S1D13505 host interface is disabled, the timing for CARDxWAIT* driven is relative to the falling edge of chip select or the second positive edge of DCLKOUT after ADDR[12:0]becomes valid, whichever one is later. #2. If the S1D13505 host interface is disabled, the timing for D[31:16] driven is relative to thefalling edge of chip select or the second positive edge of DCLKOUT after ADDR[12:0] becomes valid, whichever one is later. S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-43 7: A.C. CHARACTERISTICS Note: The Toshiba interface has different clock input requirements as follows: t t PWH PWL 90% V IH VIL 10% t tr f T OSC Figure 7-11 Clock Input Requirements Symbol TOSC tPWH tPWL tf tr 1-44 Table 7-11 Clock Input Requirements for BUSCLK Using Toshiba Local Bus Parameter Min. Max. Input Clock Period 13.3 Input Clock Pulse Width High 5.4 Input Clock Pulse Width Low 5.4 Input Clock Fall Time (10%-90%) 5 Input Clock Rise Time (10%-90%) 5 EPSON Units ns ns ns ns ns S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 7: A.C. CHARACTERISTICS PowerPC Interface Timing (e.g. MPC8xx, MC68040, Coldfire) t1 t2 t3 CLKOUT t4 t5 A[11:31], RD/WR# TSIZ[0:1], M/R# t7 t6 CS# t8 t9 TS# t11 t10 t12 t13 t15 t16 TA# t14 BI# t17 t18 D[0:15](write) t20 t19 t21 D[0:15](read) Figure 7-12 PowerPC Timing Note: The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected. Table 7-12 PowerPC Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 3.0V Parameter Clock period Clock pulse width high Clock pulse width low AB[11:31], RD/WR#, TSIZ[0:1], M/R# setup AB[11:31], RD/WR#, TSIZ[0:1], M/R# hold CS# setup CS# hold TS# setup TS# hold CLKOUT to TA# driven CLKOUT to TA# low CLKOUT to TA# high negative edge CLKOUT to TA# tri-state CLKOUT to BI# driven CLKOUT to BI# high negative edge CLKOUT to BI# tri-state DB[15:0] setup to 2nd CLKOUT after TS# = 0 (write cycle) DB[15:0] hold (write cycle) CLKOUT to DB driven (read cycle) DB[15:0] valid to TA# falling edge (read cycle) CLKOUT to DB[15:0] tri-state (read cycle) S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON Min. 25 6 6 10 0 10 0 7 5 0 3 3 5 0 3 5 10 0 0 0 5 5.0V Max. 19 19.7 25 18 16 25 25 Min. 20 6 6 10 0 10 0 10 0 0 3 3 2.5 0 3 2.5 10 0 0 0 2.5 Max. 12 13 10 11 10 10 10 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1-45 7: A.C. CHARACTERISTICS 7.2 Clock Input Requirements t t PWH PWL 90% V IH VIL 10% t tr T f OSC Figure 7-13 Clock Input Requirements Table 7-13 Clock Input Requirements for CLKI Divided Down Internally (MCLK = CLKI/2) Symbol TOSC tPWH tPWL tf tr Parameter Input Clock Period Input Clock Pulse Width High Input Clock Pulse Width Low Input Clock Fall Time (10% - 90%) Input Clock Rise Time (10% - 90%) Min. 12.5 5.6 5.6 Max. 5 5 Units ns ns ns ns ns Table 7-14 Clock Input Requirements for CLKI Symbol TOSC tPWH tPWL tf tr Parameter Input Clock Period Input Clock Pulse Width High Input Clock Pulse Width Low Input Clock Fall Time (10% - 90%) Input Clock Rise Time (10% - 90%) Min. 25 11.3 11.3 Max. 5 5 Units ns ns ns ns ns Note: When CLKI is more than 40MHz, REG[19h] bit 2 must be set to 1 (MCLK = CLKI/2). 1-46 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 7: A.C. CHARACTERISTICS 7.3 Memory Interface Timing EDO-DRAM Read/Write/Read-Write Timing t1 Memory Clock t2 RAS# t3 t5 t4 t6 t1 t7 CAS# t8 MA t9 t10 t11 t10 t11 C1 R C2 C3 t12 t13 WE# (read) t15 t14 MD (read) t16 d1 d2 t17 d3 t18 t19 WE#(write) t20 t21 MD(write) d1 t22 d2 d3 Figure 7-14 EDO-DRAM Read/Write Timing t1 Memory Clock RAS# t3 t5 t4 t6 t1 t7 CAS# t8 MA t9 t10 t11 C1 R C2 C3 t12 C2 C1 t23 C3 t19 t24 WE# t15 t14 MD(Read) d1 t25 d2 t26 d3 t20 t21 MD(Write) d1 t22 d2 d3 Figure 7-15 EDO-DRAM Read-Write Timing S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-47 7: A.C. CHARACTERISTICS Table 7-15 EDO DRAM Read Timing Symbol Parameter t1 Internal memory clock period t2 Random read cycle REG[22h] bits 6-5 = 00 Random read cycle REG[22h] bits 6-5 = 01 Random read cycle REG[22h] bits 6-5 = 10 t3 RAS# precharge time (REG[22h] bits 3-2 = 00) RAS# precharge time (REG[22h] bits 3-2 = 01) RAS# precharge time (REG[22h] bits 3-2 = 10) t4 RAS# to CAS# delay time (REG[22h] bit 4 = 0 and bits 3-2 = 00 or 10) RAS# to CAS# delay time (REG[22h] bit 4 = 1 and bits 3-2 = 00 or 10) RAS# to CAS# delay time (REG[22h] bits 3-2 = 01) t5 CAS# precharge time t6 CAS# pulse width t7 RAS# hold time t8 Row address setup time (REG[22h] bits 3-2 = 00) Row address setup time (REG[22h] bits 3-2 = 01) Row address setup time (REG[22h] bits 3-2 = 10) t9 Row address hold time (REG[22h] bits 3-2 = 00 or 10) Row address hold time (REG[22h] bits 3-2 = 01) t10 Column address setup time t11 Column address hold time t12 Read Command Setup (REG[22h] bit 4 = 0 and bits 3-2 = 00) Read Command Setup (REG[22h] bit 4 = 0 and bits 3-2 = 10) Read Command Setup (REG[22h] bit 4 = 1 and bits 3-2 = 00) Read Command Setup (REG[22h] bit 4 = 1 and bits 3-2 = 10) Read Command Setup (REG[22h] bits 3-2 = 01) t13 Read Command Hold (REG[22h] bit 4 = 0 and bits 3-2 = 00) Read Command Hold (REG[22h] bit 4 = 0 and bits 3-2 = 10) Read Command Hold (REG[22h] bit 4 = 1 and bits 3-2 = 00) Read Command Hold (REG[22h] bit 4 = 1 and bits 3-2 = 10) Read Command Hold (REG[22h] bits 3-2 = 01) t14 Read Data Setup referenced from CAS# t15 Read Data Hold referenced from CAS# t16 Last Read Data Setup referenced from RAS# t17 Bus Turn Off from RAS# t18 Write Command Setup t19 Write Command Hold t20 Write Data Setup t21 Write Data Hold t22 MD Tri-state t23 CAS# to WE# active during Read-Write cycle t24 Write Command Setup during Read-Write cycle t25 Last Read Data Setup referenced from WE# during Read-Write cycle t26 Bus Tri-state from WE# during Read-Write cycle 1-48 EPSON Min. 25 5 t1 4 t1 3 t1 2 t1 - 3 1.45 t1 - 3 1 t1 - 3 2 t1 - 3 1 t1 - 3 1.45 t1 - 3 0.45 t1 - 3 0.45 t1 - 3 1 t1 - 3 2.45 t1 2 t1 1.45 t1 0.45 t1 - 3 1 t1 - 3 0.45 t1 - 3 0.45 t1 - 3 4.45 t1 - 3 3.45 t1 - 3 3.45 t1 - 3 2.45 t1 - 3 3.45 t1 - 3 3.45 t1 - 3 2.45 t1 - 3 2.45 t1 - 3 1.45 t1 - 3 2.45 t1 - 3 5 3 5 3 0.45 t1 - 3 0.45 t1 - 3 0.45 t1 - 3 0.45 t1 - 3 0.45 t1 1 t1 - 3 1.45 t1 - 3 10 0 Max. t1 - 5 0.45 t1 + 21 t1 - 5 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 7: A.C. CHARACTERISTICS EDO-DRAM CAS Before RAS Refresh Timing t1 Memory Clock t2 t3 RAS# t4 t5 t6 CAS# Figure 7-16 EDO-DRAM CAS Before RAS Refresh Write Timing Table 7-16 EDO DRAM CAS Before RAS Refresh Write Timing Symbol Parameter Min. t1 Internal memory clock period 25 t2 RAS# precharge time (REG[22h] bits 3-2 = 00) 2 t1 - 3 RAS# precharge time (REG[22h] bits 3-2 = 01) 1.45 t1 - 3 RAS# precharge time (REG[22h] bits 3-2 = 10) 1 t1 - 3 t3 RAS# pulse width (REG[22h] bits 6-5 = 00 and bits 3-2 = 00) 3 t1 - 3 RAS# pulse width (REG[22h] bits 6-5 = 00 and bits 3-2 = 01) 3.45 t1 - 3 RAS# pulse width (REG[22h] bits 6-5 = 00 and bits 3-2 = 10) 4 t1 - 3 RAS# pulse width (REG[22h] bits 6-5 = 01 and bits 3-2 = 00) 2 t1 - 3 RAS# pulse width (REG[22h] bits 6-5 = 01 and bits 3-2 = 01) 2.45 t1 - 3 RAS# pulse width (REG[22h] bits 6-5 = 01 and bits 3-2 = 10) 3 t1 - 3 RAS# pulse width (REG[22h] bits 6-5 = 10 and bits 3-2 = 00) 1 t1 - 3 RAS# pulse width (REG[22h] bits 6-5 = 10 and bits 3-2 = 01) 1.45 t1 - 3 RAS# pulse width (REG[22h] bits 6-5 = 10 and bits 3-2 = 10) 2 t1 - 3 t4 CAS# pulse width t2 t5 CAS# setup time (REG[22h] bits 3-2 = 00 or 10) 0.45 t1 - 3 CAS# setup time (REG[22h] bits 3-2 = 01) 1 t1 - 3 t6 CAS# Hold to RAS# (REG[22h] bits 6-5 = 00 and bits 3-2 = 00) 2.45 t1 - 3 CAS# Hold to RAS# (REG[22h] bits 6-5 = 00 and bits 3-2 = 01) 3 t1 - 3 CAS# Hold to RAS# (REG[22h] bits 6-5 = 00 and bits 3-2 = 10) 3.45 t1 - 3 CAS# Hold to RAS# (REG[22h] bits 6-5 = 01 and bits 3-2 = 00) 1.45 t1 - 3 CAS# Hold to RAS# (REG[22h] bits 6-5 = 01 and bits 3-2 = 01) 2 t1 - 3 CAS# Hold to RAS# (REG[22h] bits 6-5 = 01 and bits 3-2 = 10) 2.45 t1 - 3 CAS# Hold to RAS# (REG[22h] bits 6-5 = 10 and bits 3-2 = 00) 0.45 t1 - 3 CAS# Hold to RAS# (REG[22h] bits 6-5 = 10 and bits 3-2 = 01) 1 t1 - 3 CAS# Hold to RAS# (REG[22h] bits 6-5 = 10 and bits 3-2 = 10) 1.45 t1 - 3 S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON Max. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1-49 7: A.C. CHARACTERISTICS EDO-DRAM Self-Refresh Timing Restarted for active mode Stopped for suspend mode t1 Memory Clock t2 RAS# t3 t4 t5 CAS# Figure 7-17 EDO-DRAM Self-Refresh Timing Table 7-17 EDO-DRAM Self-Refresh Timing Symbol Parameter t1 Internal memory clock period t2 RAS# precharge time (REG[22h] bits 3-2 = 00) RAS# precharge time (REG[22h] bits 3-2 = 01) RAS# precharge time (REG[22h] bits 3-2 = 10) t3 RAS# to CAS# precharge time (REG[22h] bits 3-2 = 00) RAS# to CAS# precharge time (REG[22h] bits 3-2 = 01 or 10) t4 CAS# setup time (REG[22h] bits 3-2 = 00 or 10) CAS# setup time (REG[22h] bits 3-2 = 01) t5 CAS# precharge time (REG[22h] bits 3-2 = 00) CAS# precharge time (REG[22h] bits 3-2 = 01 or 10) 1-50 EPSON Min. 25 2 t1 - 3 1.45 t1 - 3 1 t1 - 3 1.45 t1 - 3 0.45 t1 - 3 0.45 t1 - 3 1 t1 - 3 2 t1 - 3 1 t1 - 3 Max. Units ns ns ns ns ns ns ns ns ns ns S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 7: A.C. CHARACTERISTICS FPM-DRAM Read / Write / Read - Write Timing t1 Memory Clock t2 RAS# t5 t4 t3 t6 t1 t7 CAS# t8 MA t9 t11 t10 t11 t10 R C1 C2 C3 t12 t13 WE#(read) t14 MD(read) d1 d2 t15 d3 t16 t17 WE#(write) t18 t19 MD(write) d1 t20 d2 d3 Figure 7-18 FPM-DRAM Read/Write Timing t1 Memory Clock RAS# t4 t3 t5 t6 t7 t1 CAS# t8 MA t9 R t10 t11 C2 C1 C3 C1 t21 t12 C2 C3 t16 t17 t18 t19 t20 WE# t14 MD(read) d1 t15 d2 MD(write) d3 d1 d2 d3 Figure 7-19 FPM-DRAM Read-Write Timing S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-51 7: A.C. CHARACTERISTICS Table 7-18 FPM-DRAM Read/Write/Read-Write Timing Symbol Parameter Min. t1 Internal memory clock period 40 t2 Random read cycle REG[22h] bits 6-5 = 00 5 t1 Random read cycle REG[22h] bits 6-5 = 01 4 t1 Random read cycle REG[22h] bits 6-5 = 10 3 t1 t3 RAS# precharge time (REG[22h] bits 3-2 = 00) 2 t1 - 3 RAS# precharge time (REG[22h] bits 3-2 = 01) 1.45 t1 - 3 RAS# precharge time (REG[22h] bits 3-2 = 10) 1 t1 - 3 t4 RAS# to CAS# delay time (REG[22h] bit 4 = 1 and bits 3-2 = 00 or 10) 1.45 t1 - 3 RAS# to CAS# delay time (REG[22h] bit 4 = 0 and bits 3-2 = 00 or 10) 2.45 t1 - 3 RAS# to CAS# delay time (REG[22h] bit 4 = 1 and bits 3-2 = 01) 1 t1 - 3 RAS# to CAS# delay time (REG[22h] bit 4 = 0 and bits 3-2 = 01) 2 t1 - 3 t5 CAS# precharge time 0.45 t1 - 3 t6 CAS# pulse width 0.45 t1 - 3 t7 RAS# hold time 0.45 t1 - 3 t8 Row address setup time (REG[22h] bits 3-2 = 00) 2 t1 - 3 Row address setup time (REG[22h] bits 3-2 = 01) 1.45 t1 - 3 Row address setup time (REG[22h] bits 3-2 = 10) 1 t1 - 3 t9 Row address hold time (REG[22h] bits 3-2 = 00 or 10) t1 - 3 Row address hold time (REG[22h] bits 3-2 = 01) 0.45 t1 - 3 t10 Column address setup time 0.45 t1 - 3 t11 Column address hold time 0.45 t1 - 3 t12 Read Command Setup (REG[22h] bit 4 = 0 and bits 3-2 = 00) 4.45 t1 - 3 Read Command Setup (REG[22h] bit 4 = 0 and bits 3-2 = 01 or 10) 3.45 t1 - 3 Read Command Setup (REG[22h] bit 4 = 1 and bits 3-2 = 00) 3.45 t1 - 3 Read Command Setup (REG[22h] bit 4 = 1 and bits 3-2 = 01 or 10) 2.45 t1 - 3 t13 Read Command Hold (REG[22h] bit 4 = 0 and bits 3-2 = 00) 4 t1 - 3 Read Command Hold (REG[22h] bit 4 = 0 and bits 3-2 = 01 or 10) 3 t1 - 3 Read Command Hold (REG[22h] bit 4 = 1 and bits 3-2 = 00) 3 t1 - 3 Read Command Hold (REG[22h] bit 4 = 1 and bits 3-2 = 01 or 10) 2 t1 - 3 t14 Read Data Setup referenced from CAS# 5 t15 Bus Tri-State 3 t16 Write Command Setup 0.45 t1 - 3 t17 Write Command Hold 0.45 t1 - 3 t18 Write Data Setup 0.45 t1 - 3 t19 Write Data Hold 0.45 t1 - 3 t20 MD Tri-state 0.45 t1 t21 CAS# to WE# active during Read-Write cycle 0.45 t1 - 3 1-52 EPSON Max. t1 - 5 0.45 t1 + 21 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 7: A.C. CHARACTERISTICS FPM-DRAM CAS Before RAS Refresh Timing t1 Memory Clock t2 t3 RAS# t4 t5 t6 CAS# Figure 7-20 FPM-DRAM CAS before RAS Refresh Timing Table 7-19 FPM-DRAM CAS before RAS Refresh Timing Symbol Parameter Min. t1 Internal memory clock period 40 t2 RAS# precharge time (REG[22h] bits 3-2 = 00) 2.45 t1 - 3 RAS# precharge time (REG[22h] bits 3-2 = 01 or 10) 1.45 t1 - 3 t3 RAS# pulse width (REG[22h] bits 6-5 = 00 and bits 3-2 = 00) 2.45 t1 - 3 RAS# pulse width (REG[22h] bits 6-5 = 00 and bits 3-2 = 01 or 10) 3.45 t1 - 3 RAS# pulse width (REG[22h] bits 6-5 = 01 and bits 3-2 = 00) 1.45 t1 - 3 RAS# pulse width (REG[22h] bits 6-5 = 01 and bits 3-2 = 01 or 10) 2.45 t1 - 3 RAS# pulse width (REG[22h] bits 6-5 = 10 and bits 3-2 = 00) 0.45 t1 - 3 RAS# pulse width (REG[22h] bits 6-5 = 10 and bits 3-2 = 01 or 10) 1.45 t1 - 3 t4 CAS# pulse width (REG[22h] bits 3-2 = 00) 2 t1 - 3 CAS# pulse width (REG[22h] bits 3-2 = 01 or 10) 1 t1 - 3 t5 CAS# Setup to RAS# 0.45 t1 - 3 t6 CAS# Hold to RAS# (REG[22h] bits 6-5 = 00 and bits 3-2 = 00) 2.45 t1 - 3 CAS# Hold to RAS# (REG[22h] bits 6-5 = 00 and bits 3-2 = 01 or 10) 3.45 t1 - 3 CAS# Hold to RAS# (REG[22h] bits 6-5 = 01 and bits 3-2 = 00) 1.45 t1 - 3 CAS# Hold to RAS# (REG[22h] bits 6-5 = 01 and bits 3-2 = 01 or 10) 2.45 t1 - 3 CAS# Hold to RAS# (REG[22h] bits 6-5 = 10 and bits 3-2 = 00) 0.45 t1 - 3 CAS# Hold to RAS# (REG[22h] bits 6-5 = 10 and bits 3-2 = 01 or 10) 1.45 t1 - 3 S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON Max. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1-53 7: A.C. CHARACTERISTICS FPM-DRAM Self-Refresh Timing Restarted for active mode Stopped for suspend mode t1 Memory Clock t2 RAS# t3 t4 CAS# Figure 7-21 FPM-DRAM Self-Refresh Timing Table 7-20 FPM DRAM Self-Refresh Timing Symbol Parameter Min. t1 Internal memory clock 40 t2 RAS# precharge time (REG[22h] bits 3-2 = 00) 2.45 t1 - 1 RAS# precharge time (REG[22h] bits 3-2 = 01 or 10) 1.45 t1 - 1 t3 RAS# to CAS# precharge time (REG[22h] bits 3-2 = 00) 2 t1 RAS# to CAS# precharge time (REG[22h] bits 3-2 = 01 or 10) 1 t1 t4 CAS# setup time (CAS# before RAS# refresh) 0.45 t1 - 2 1-54 EPSON Max. Units ns ns ns ns ns ns S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 7: A.C. CHARACTERISTICS 7.4 Power Sequencing LCD Power Sequencing SUSPEND# or LCD Enable Bit t1 t5 t6 LCDPWR t2 t3 FPFRAME FPLINE FPSHIFT FPDATA DRDY t4 t7 CLKI Figure 7-22 LCD Panel Power Off / Power On Timing. Drawn with LCDPWR Set to Active High Polarity Symbol t1 t2 t3 t4 t5 t6 t7 Table 7-21 LCD Panel Power Off/ Power On Parameter Min. SUSPEND# or LCD ENABLE BIT low to LCDPWR off SUSPEND# or LCD ENABLE BIT low to FPFRAME inactive FPFRAME inactive to FPLINE, FPSHIFT, FPDATA, DRDY inactive SUSPEND# to CLKI inactive SUSPEND# or LCD ENABLE BIT high to FPLINE, FPSHIFT, FPDATA, DRDY active FPLINE, FPSHIFT, FPDATA, DRDY active to LCDPWR, on and FPFRAME active CLKI active to SUSPEND# inactive Max. 2TFPFRAME + 8TPCLK 1 128 130 TFPFRAME + 8TPCLK Units ns Frames Frames Frames ns 128 Frames 0 ns Note: Where TFPFRAME is the period of FPFRAME and TPCLK is the period of the pixel clock. S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-55 7: A.C. CHARACTERISTICS Power Save Status Power Save t2 t1 Power Save Status Bit t3 Memory Access allowed not allowed allowed Figure 7-23 Power Save Status and Local Bus Memory Access Relative to Power Save Mode Note: Power Save can be initiated through either the SUSPEND# pin or Software Suspend Enable Bit. Symbol t1 t2 t3 Table 7-22 Power Save Status and Local Bus Memory Access Relative to Power Save Mode Parameter Min. Max. Power Save initiated to rising edge of Power Save Status and the last 129 130 time memory access by the local bus may be performed Power Save deactivated to falling edge of Power Save Status 12 Falling edge of Power Save Status to the earliest time the local bus may 8 perform a memory access Units Frames MCLK MCLK Note: It is recommended that memory access not be performed after a Power Save Mode has been initiated. 1-56 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 7: A.C. CHARACTERISTICS 7.5 Display Interface 4-Bit Single Monochrome Passive LCD Panel Timing VDP VNDP FPFRAME FPLINE MOD UD[3:0] LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 LINE1 LINE2 FPLINE MOD HDP HNDP FPSHIFT UD3 1-1 1-5 UD2 1-2 1-6 1-318 UD1 1-3 1-7 1-319 UD0 1-4 1-8 1-320 1-317 * Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320x240 panel Figure 7-24 4-Bit Single Monochrome Passive LCD Panel Timing VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = ((REG[05h] bits [4:0]) + 1)*8Ts EPSON 1-57 7: A.C. CHARACTERISTICS t1 t2 Sync Timing FPFRAME t4 t3 FPLINE t5 MOD Data Timing FPLINE t6 t7 t9 t8 t10 t11 t12 FPSHIFT t13 t14 1 UD[3:0] 2 Figure 7-25 4-Bit Single Monochrome Passive LCD Panel A.C. Timing Table 7-23 4-Bit Single Monochrome Passive LCD Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Parameter FPFRAME setup to FPLINE pulse trailing edge FPFRAME hold from FPLINE pulse trailing edge FPLINE pulse width FPLINE period MOD transition to FPLINE pulse trailing edge FPSHIFT falling edge to FPLINE pulse leading edge FPLINE pulse trailing edge to FPSHIFT falling edge FPSHIFT period FPSHIFT falling edge to FPLINE pulse trailing edge FPLINE pulse trailing edge to FPSHIFT rising edge FPSHIFT pulse width high FPSHIFT pulse width low UD[3:0] setup to FPSHIFT falling edge UD[3:0] hold to FPSHIFT falling edge Notes: 1. Ts 2. 3. 4. 5. 6. 1-58 t1min t4min t5min t6min t9min Min. note 2 14 9 note 3 1 note 5 t10 + t11 4 note 6 20 2 2 2 2 Typ. Max. Units Ts (note 1) Ts note 4 Ts Ts Ts Ts Ts Ts Ts = pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = t4min - 14Ts = [((REG[04h] bits [6:0])+1)8 + ((REG[05h] bits [4:0]) + 1)8] + 33 Ts = [(((REG[04h] bits [6:0])+1)8 + ((REG[05h] bits [4:0]) + 1)8)-1] Ts = [((REG[05h] bits [4:0]) + 1)8 - 27] Ts = [((REG[05h] bits [4:0]) + 1)8 - 18] Ts EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 7: A.C. CHARACTERISTICS 8-Bit Single Monochrome Passive LCD Panel Timing VDP VNDP FPFRAME FPLINE MOD LINE1 UD[3:0], LD[3:0] LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPLINE MOD HDP HNDP FPSHIFT UD3 1-1 1-9 UD2 1-2 1-10 1-634 UD1 1-3 1-11 1-635 UD0 1-4 1-12 1-636 LD3 1-5 1-13 1-637 LD2 1-6 1-14 1-638 LD1 1-7 1-15 1-639 LD0 1-8 1-16 1-640 1-633 * Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7-26 8-Bit Single Monochrome Passive LCD Panel Timing VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = ((REG[05h] bits [4:0]) + 1)*8Ts EPSON 1-59 7: A.C. CHARACTERISTICS t1 t2 Sync Timing FPFRAME t4 t3 FPLINE t5 MOD Data Timing FPLINE t6 t7 t9 t8 t10 t11 t12 FPSHIFT t13 UD[3:0] LD[3:0] t14 1 2 Figure 7-27 8-Bit Single Monochrome Passive LCD Panel A.C. Timing Table 7-24 8-Bit Single Monochrome Passive LCD Panel A.C. Timing Symbol Parameter Min. Typ. t1 FPFRAME setup to FPLINE pulse trailing edge note 2 t2 FPFRAME hold from FPLINE pulse trailing edge 14 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 FPLINE pulse width FPLINE period MOD transition to FPLINE pulse trailing edge FPSHIFT falling edge to FPLINE pulse leading edge FPLINE pulse trailing edge to FPSHIFT falling edge FPSHIFT period FPSHIFT falling edge to FPLINE pulse trailing edge FPLINE pulse trailing edge to FPSHIFT rising edge FPSHIFT pulse width high FPSHIFT pulse width low UD[3:0], LD[3:0] setup to FPSHIFT falling edge UD[3:0], LD[3:0] hold to FPSHIFT falling edge Notes: 1. Ts 2. 3. 4. 5. 6. 1-60 t1min t4min t5min t6min t9min 9 note 3 1 note 5 t10 + t11 8 note 6 20 4 4 4 4 Max. Units Ts (note 1) Ts note 4 Ts Ts Ts Ts Ts Ts Ts = pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = t4min - 14Ts = [((REG[04h] bits [6:0])+1)8 + ((REG[05h] bits [4:0]) + 1)8] + 33 Ts = [(((REG[04h] bits [6:0])+1)8 + ((REG[05h] bits [4:0]) + 1)8)-1] Ts = [((REG[05h] bits [4:0]) + 1)8 - 25] Ts = [((REG[05h] bits [4:0]) + 1)8 - 16] Ts EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 7: A.C. CHARACTERISTICS 4-Bit Single Color Passive LCD Panel Timing VNDP VDP FPFRAME FPLINE MOD UD[3:0] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPLINE MOD HDP HNDP FPSHIFT UD3 1-R1 1-G2 1-B3 1-B319 UD2 1-G1 1-B2 1-R4 1-R320 UD1 1-B1 1-R3 1-G4 1-G320 UD0 1-R2 1-G3 1-B4 1-B320 * Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7-28 4-Bit Single Color Passive LCD Panel Timing VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = ((REG[05h] bits [4:0]) + 1)*8Ts EPSON 1-61 7: A.C. CHARACTERISTICS t1 t2 Sync Timing FPFRAME t4 t3 FPLINE t5 MOD Data Timing FPLINE t6 t7 t9 t8 t10 t11 t12 FPSHIFT t13 t14 1 UD[3:0] 2 Figure 7-29 4-Bit Single Color Passive LCD Panel A.C.Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Table 7-25 4-Bit Single Color Passive LCD Panel A.C.Timing Parameter Min. Typ. FPFRAME setup to FPLINE pulse trailing edge note 2 FPFRAME hold from FPLINE pulse trailing edge 14 FPLINE pulse width 9 FPLINE period note 3 MOD transition to FPLINE pulse trailing edge 1 FPSHIFT falling edge to FPLINE pulse leading edge note 5 FPLINE pulse trailing edge to FPSHIFT falling edge t10 + t11 FPSHIFT period 4 FPSHIFT falling edge to FPLINE pulse trailing edge note 6 FPLINE pulse trailing edge to FPSHIFT rising edge 21 FPSHIFT pulse width high 2 FPSHIFT pulse width low 2 UD[3:0], setup to FPSHIFT falling edge 2 UD[3:0], hold from FPSHIFT falling edge 2 Notes: 1. Ts 2. 3. 4. 5. 6. 1-62 t1min t4min t5min t6min t9min Max. Units Ts (note 1) Ts note 4 Ts Ts Ts Ts Ts Ts Ts = pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = t4min - 14Ts = [((REG[04h] bits [6:0]) + 1)8 + ((REG[05h] bits [4:0]) + 1)8] + 33 Ts = [(((REG[04h] bits [6:0])+1)8 + ((REG[05h] bits [4:0]) + 1)8)-1] Ts = [((REG[05h] bits [4:0]) + 1)8 - 28] Ts = [((REG[05h] bits [4:0]) + 1)8 - 19] Ts EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 7: A.C. CHARACTERISTICS 8-Bit Single Color Passive LCD Panel Timing (Format 1) VNDP VDP FPFRAME FPLINE UD[3:0], LD[3:0] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPLINE HDP HNDP FPSHIFT FPSHIFT2 UD3 1-R1 1-G1 1-G6 1-B6 1-B11 1-R12 1-R636 UD2 1-B1 1-R2 1-R7 1-G7 1-G12 1-B12 1-B636 UD1 1-G2 1-B2 1-B7 1-R8 1-R13 1-G13 1-G637 UD0 1-R3 1-G3 1-G8 1-B8 1-B13 1-R14 1-R638 LD3 1-B3 1-R4 1-R9 1-G9 1-G14 1-B14 1-B638 LD2 1-G4 1-B4 1-B9 1-R10 1-R15 1-G15 1-G639 LD1 1-R5 1-G5 1-G10 1-B10 1-B15 1-R16 1-R640 LD0 1-B5 1-R6 1-R11 1-G11 1-G16 1-B16 1-B640 * Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7-30 8-Bit Single Color Passive LCD Panel Timing (Format 1) VDP = Vertical Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 VNDP = Vertical Non-Display Period = (REG[0Ah] bits [5:0]) + 1 HDP = Horizontal Display Period = ((REG[04h] bits [6:0]) + 1)*8Ts HNDP = Horizontal Non-Display Period = ((REG[05h] bits [4:0]) + 1)*8Ts S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-63 7: A.C. CHARACTERISTICS t1 t2 Sync Timing FPFRAME t4 t3 FPLINE Data Timing FPLINE t5a t5b t6 t8a t7 t9 t10 t11 FPSHIFT t8b FPSHIFT2 t12 UD[3:0] LD[3:0] t13 1 2 Figure 7-31 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 1) Symbol t1 t2 t3 t4 t5a t5b t6 t7 t8a t8b t9 t10 t11 t12 t13 Table 7-26 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 1) Parameter Min. Typ. FPFRAME setup to FPLINE pulse trailing edge note 2 FPFRAME hold from FPLINE pulse trailing edge 14 FPLINE pulse width 9 FPLINE period note 3 FPSHIFT2 falling edge to FPLINE pulse leading edge note 4 FPSHIFT falling edge to FPLINE pulse leading edge note 5 FPLINE pulse trailing edge to FPSHIFT2 rising, FPSHIFT falling t9 + t10 edge FPSHIFT2, FPSHIFT period 4 FPSHIFT falling edge to FPLINE pulse trailing edge note 6 FPSHIFT2 falling edge to FPLINE pulse trailing edge note 7 FPLINE pulse trailing edge to FPSHIFT rising edge 20 FPSHIFT2, FPSHIFT pulse width high 2 FPSHIFT2, FPSHIFT pulse width low 2 UD[3:0], LD[3:0] setup to FPSHIFT2 rising, FPSHIFT falling edge 1 UD[3:0], LD[3:0] hold from FPSHIFT2 rising, FPSHIFT falling edge 1 Notes: 1. Ts 2. 3. 4. 5. 6. 7. 1-64 t1min t4min t5min t5min t8min t8min Max. Units Ts (note 1) Ts Ts Ts Ts Ts Ts Ts Ts = pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = t4min - 14Ts = [((REG[04h] bits [6:0])+1)8 + ((REG[05h] bits [4:0]) + 1)8] Ts = [((REG[05h] bits [4:0]) + 1)8 - 27] Ts = [((REG[05h] bits [4:0]) + 1)8 - 29] Ts = [((REG[05h] bits [4:0]) + 1)8 - 20] Ts = [((REG[05h] bits [4:0]) + 1)8 - 18] Ts EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 7: A.C. CHARACTERISTICS 8-Bit Single Color Passive LCD Panel Timing (Format 2) VDP VNDP FPFRAME FPLINE MOD UD[3:0], LD[3:0] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPLINE MOD HDP HNDP FPSHIFT UD3 1-R1 1-B3 1-G6 1-G638 UD2 1-G1 1-R4 1-B6 1-B638 UD1 1-B1 1-G4 1-R7 1-R639 UD0 1-R2 1-B4 1-G7 1-G639 LD3 1-G2 1-R5 1-B7 1-B639 LD2 1-B2 1-G5 1-R8 1-R640 LD1 1-R3 1-B5 1-G8 1-G640 LD0 1-G3 1-R6 1-B8 1-B640 * Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7-32 8-Bit Single Color Passive LCD Panel Timing (Format 2) VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = ((REG[05h] bits [4:0]) + 1)*8Ts EPSON 1-65 7: A.C. CHARACTERISTICS t1 Sync Timing t2 FPFRAME t3 t4 FPLINE t5 MOD Data Timing FPLINE t6 t8 t7 t9 t14 t11 t10 FPSHIFT t12 UD[3:0] LD[3:0] t13 1 2 Figure 7-33 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 2) Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Table 7-27 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 2) Parameter Min. Typ. FPFRAME setup to FPLINE pulse trailing edge note 2 FPFRAME hold from FPLINE pulse trailing edge 14 FPLINE period note 3 FPLINE pulse width 9 MOD transition to FPLINE pulse trailing edge 1 FPSHIFT falling edge to FPLINE pulse leading edge note 5 FPSHIFT falling edge to FPLINE pulse trailing edge note 6 FPLINE pulse trailing edge to FPSHIFT falling edge t14 + 2 FPSHIFT period 2 FPSHIFT pulse width low 1 FPSHIFT pulse width high 1 UD[3:0], LD[3:0] setup to FPSHIFT falling edge 1 UD[3:0], LD[3:0] hold to FPSHIFT falling edge 1 FPLINE pulse trailing edge to FPSHIFT rising edge 20 Notes: 1. Ts 2. 3. 4. 5. 6. 1-66 t1min t3min t5min t6min t7min Max. Units Ts (note 1) Ts note 4 Ts Ts Ts Ts Ts Ts = pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = t3min - 14Ts = [((REG[04h] bits [6:0])+1)8 + ((REG[05h] bits [4:0]) + 1)8] + 33 Ts = [(((REG[04h] bits [6:0])+1)8 + ((REG[05h] bits [4:0]) + 1)8)-1] Ts = [((REG[05h] bits [4:0]) + 1)8 - 28] Ts = [((REG[05h] bits [4:0]) + 1)8 - 19] Ts EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 7: A.C. CHARACTERISTICS 16-Bit Single Color Passive LCD Panel Timing VDP VNDP FPFRAME FPLINE MOD UD[7:0], LD[7:0] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPLINE MOD HDP HNDP FPSHIFT UD7 1-G6 1-B11 1-G635 1-B1 1-R7 1-G12 1-G636 UD5 1-G2 1-B7 1-R13 1-R637 UD4 1-R3 1-G8 1-B13 1-B637 UD3 1-B3 1-R9 1-G14 1-G638 UD2 1-G4 1-B9 1-R15 1-R639 UD1 1-R5 1-G10 1-B15 1-B639 UD0 1-B5 1-R11 1-G16 1-G640 UD6 1-R1 LD7 1-G1 1-B6 1-R12 1-R636 LD6 1-R2 1-G7 1-B12 1-B636 LD5 1-B2 1-R8 1-G13 1-G637 LD4 1-G3 1-B8 1-R14 1-R638 LD3 1-R4 1-G9 1-B14 1-B638 LD2 1-B4 1-R10 1-G15 1-G639 LD1 1-G5 1-B10 1-R16 1-R640 LD0 1-R6 1-G11 1-B16 1-B640 * Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7-34 16-Bit Single Color Passive LCD Panel Timing VDP = Vertical Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 VNDP = Vertical Non-Display Period = (REG[0Ah] bits [5:0]) + 1 HDP = Horizontal Display Period = ((REG[04h] bits [6:0]) + 1)*8Ts HNDP = Horizontal Non-Display Period = ((REG[05h] bits [4:0]) + 1)*8Ts S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-67 7: A.C. CHARACTERISTICS t1 Sync Timing t2 FPFRAME t3 t4 FPLINE t5 MOD Data Timing FPLINE t6 t8 t7 t9 t14 t10 t11 FPSHIFT t12 t13 1 UD[7:0] LD[7:0] 2 Figure 7-35 16-Bit Single Color Passive LCD Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Table 7-28 16-Bit Single Color Passive LCD Panel A.C. Timing Parameter Min. Typ. FPFRAME setup to FPLINE pulse trailing edge note 2 FPFRAME hold from FPLINE pulse trailing edge 14 FPLINE period note 3 FPLINE pulse width 9 MOD transition to FPLINE pulse trailing edge 1 FPSHIFT falling edge to FPLINE pulse leading edge note 5 FPSHIFT falling edge to FPLINE pulse trailing edge note 6 FPLINE pulse trailing edge to FPSHIFT falling edge t14 + 3 FPSHIFT period 5 FPSHIFT pulse width low 2 FPSHIFT pulse width high 2 UD[7:0], LD[7:0] setup to FPSHIFT falling edge 2 UD[7:0], LD[7:0] hold to FPSHIFT falling edge 2 FPLINE pulse trailing edge to FPSHIFT rising edge 20 Notes: 1. Ts 2. 3. 4. 5. 6. 1-68 t1min t3min t5min t6min t7min Max. Units Ts (note 1) Ts note 4 Ts Ts Ts Ts Ts Ts Ts = pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = t3min - 14Ts = [((REG[04h] bits [6:0])+1)8 + ((REG[05h] bits [4:0]) + 1)8] + 33 Ts = [(((REG[04h] bits [6:0])+1)8 + ((REG[05h] bits [4:0]) + 1)8)-1] Ts = [(REG[05h] bits [4:0]) + 1)8 - 27] Ts = [((REG[05h] bits [4:0]) + 1)8 - 18] Ts EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 7: A.C. CHARACTERISTICS 8-Bit Dual Monochrome Passive LCD Panel Timing VNDP VDP FPFRAME FPLINE MOD UD[3:0], LD[3:0] LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 LINE 1/241 LINE 2/242 FPLINE MOD HNDP HDP FPSHIFT UD3 1 -1 1 -5 1 -63 7 UD2 1 -2 1 -6 1 -63 8 UD1 1 -3 1 -7 1 -63 9 UD0 1 -4 1 -8 1 -64 0 LD3 2 41 -1 2 41 -5 24 1 -63 7 LD2 2 41 -2 2 41 -6 24 1 -63 8 LD1 2 41 -3 2 41 -7 24 1 -63 9 LD0 2 41 -4 2 41 -8 24 1 -64 0 * Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7-36 8-Bit Dual Monochrome Passive LCD Panel Timing VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = ((REG[05h] bits [4:0]) + 1)*8Ts EPSON 1-69 7: A.C. CHARACTERISTICS t1 Sync Timing t2 FPFRAME t4 t3 FPLINE t5 MOD Data Timing FPLINE t6 t8 t7 t9 t14 t10 t11 FPSHIFT t12 t13 1 UD[3:0] LD[3:0] 2 Figure 7-37 8-Bit Dual Monochrome Passive LCD Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Table 7-29 8-Bit Dual Monochrome Passive LCD Panel A.C. Timing Parameter Min. Typ. FPFRAME setup to FPLINE pulse trailing edge note 2 FPFRAME hold from FPLINE pulse trailing edge 14 FPLINE period note 3 FPLINE pulse width 9 MOD transition to FPLINE pulse trailing edge 1 FPSHIFT falling edge to FPLINE pulse leading edge note 5 FPSHIFT falling edge to FPLINE pulse trailing edge note 6 FPLINE pulse trailing edge to FPSHIFT falling edge t14 + 2 FPSHIFT period 4 FPSHIFT pulse width low 2 FPSHIFT pulse width high 2 UD[3:0], LD[3:0] setup to FPSHIFT falling edge 2 UD[3:0], LD[3:0] hold to FPSHIFT falling edge 2 FPLINE pulse trailing edge to FPSHIFT rising edge 12 Notes: 1. Ts 2. 3. 4. 5. 6. 1-70 t1min t3min t5min t6min t7min Max. Units Ts (note 1) Ts note 4 Ts Ts Ts Ts Ts Ts Ts = pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = t3min - 14Ts = [((REG[04h] bits [6:0])+1)8 + ((REG[05h] bits [4:0]) + 1)8] + 33 Ts = [(((REG[04h] bits [6:0])+1)8 + ((REG[05h] bits [4:0]) + 1)8)-1] Ts = [((REG[05h] bits [4:0]) + 1)8 - 19] Ts = [((REG[05h] bits [4:0]) + 1)8 - 10] Ts EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 7: A.C. CHARACTERISTICS 8-Bit Dual Color Passive LCD Panel Timing VNDP VDP FPFRAME FPLINE MOD UD[3:0], LD[3:0] LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 LINE 1/241 LINE 2/242 FPLINE MOD HNDP HDP FPSHIFT FPDAT7 (UD3) 1 -R 1 1 -G 2 1 -B3 1 -R 5 1 -G 6 1 -B7 1 -B6 3 9 FPDAT6 (UD2) 1 -G 1 1 -B2 1 -R 4 1 -G 5 1 -B6 1 -R 8 1 -R 6 4 0 FPDAT5 (UD1) 1 -B1 1 -R 3 1 -G 4 1 -B5 1 -R 7 1-G8 1 -G 6 4 0 1 -R 2 1 -G 3 1 -B4 1 -R 6 1 -G 7 1-B8 1 -B6 4 0 FPDAT4 (UD0) FPDAT3 (LD3) 2 4 1 -R 1 2 4 1 -G 2 2 4 1-B3 2 4 1 -R 5 2 4 1 -G 6 2 4 1 -B7 2 41B6 3 9 FPDAT2 (UD2) 2 4 1 -G1 2 4 1 -B2 2 4 1 -R 4 2 4 1 -G 5 2 4 1 -B6 2 4 1 -R 8 241R640 FPDAT1 (UD1) 2 4 1 -B1 2 4 1 -R 3 2 41 -G 4 2 4 1 -B5 2 4 1 -R 7 2 41 -G 8 2 41 G640 FPDAT0 (UD0) 2 4 1 -R 2 2 4 1 -G 3 24 1-B4 2 4 1 -R 6 2 41 -G 7 2 41-B8 241B6 4 0 * Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7-38 8-Bit Dual Color Passive LCD Panel Timing VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = ((REG[05h] bits [4:0]) + 1)*8Ts EPSON 1-71 7: A.C. CHARACTERISTICS t1 t2 Sync Timing FPFRAME t4 t3 FPLINE t5 MOD Data Timing FPLINE t6 t8 t7 t9 t14 t11 t10 FPSHIFT t12 UD[3:0] LD[3:0] t13 1 2 Figure 7-39 8-Bit Dual Color Passive LCD Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Table 7-30 8-Bit Dual Color Passive LCD Panel A.C. Timing Parameter Min. Typ. FPFRAME setup to FPLINE pulse trailing edge note 2 FPFRAME hold from FPLINE pulse trailing edge 14 FPLINE period note 3 FPLINE pulse width 9 MOD transition to FPLINE pulse trailing edge 1 FPSHIFT falling edge to FPLINE pulse leading edge note 5 FPSHIFT falling edge to FPLINE pulse trailing edge note 6 FPLINE pulse trailing edge to FPSHIFT falling edge t14 + t11 FPSHIFT period 1 FPSHIFT pulse width low 0.45 FPSHIFT pulse width high 0.45 UD[3:0], LD[3:0] setup to FPSHIFT falling edge 0.45 UD[3:0], LD[3:0] hold to FPSHIFT falling edge 0.45 FPLINE pulse trailing edge to FPSHIFT rising edge 13 Notes: 1. Ts 2. 3. 4. 5. 6. 1-72 t1min t3min t5min t6min t7min Max. Units Ts (note 1) Ts note 4 Ts Ts Ts Ts Ts Ts Ts = pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = t3min - 14Ts = [((REG[04h] bits [6:0])+1)8 + ((REG[05h] bits [4:0]) + 1)8] + 33 Ts = [(((REG[04h] bits [6:0])+1)8 + ((REG[05h] bits [4:0]) + 1)8)-1] Ts = [((REG[05h] bits [4:0]) + 1)8 - 20] Ts = [((REG[05h] bits [4:0]) + 1)8 - 11] Ts EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 7: A.C. CHARACTERISTICS 16-Bit Dual Color Passive LCD Panel Timing VNDP VDP FPFRAME FPLINE MOD UD[7:0], LD[7:0] LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 LINE 1/241 LINE 2/242 FPLINE MOD HNDP HDP FPSHIFT UD7, LD7 1-R1, 241-R 1 1-B3, 2 41-B 3 1-G 63 8, 2 41 -G 6 3 8 UD6, LD6 1-G1, 24 1-G 1 1-R 4 , 2 41 -R 4 1-B63 8, 24 1-B638 UD5, LD5 1-B1, 2 4 1-B 1 1-G 4, 2 41-G 4 1-R 639 , 24 1 -R 639 UD4, LD4 1-R2, 2 41 -R 2 1-B4, 2 41-B 4 1-G 63 9, 2 41 -G 6 3 9 UD3, LD3 1-G2, 24 1-G 2 1-R 5 , 2 41 -R 5 1 -B63 9, 2 4 1-B6 3 9 UD2, LD2 1-B2, 2 4 1-B 2 1-G 5, 2 41-G 5 1-R 640 , 24 1 -R6 40 UD1, LD1 1-R3, 2 41 -R 3 1-B5, 2 41-B5 1-G 6 40, 2 4 1-G 64 0 UD0, LD0 1-G3, 24 1-G 3 1-R 6 , 2 41 -R 6 1 -B64 0, 2 4 1-B6 4 0 * Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7-40 16-Bit Dual Color Passive LCD Panel Timing VDP = Vertical Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 VNDP = Vertical Non-Display Period = (REG[0Ah] bits [5:0]) + 1 HDP = Horizontal Display Period = ((REG[04h] bits [6:0]) + 1)*8Ts HNDP = Horizontal Non-Display Period = ((REG[05h] bits [4:0]) + 1)*8Ts S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-73 7: A.C. CHARACTERISTICS t1 t2 Sync Timing FPFRAME t4 t3 FPLINE t5 MOD Data Timing FPLINE t6 t8 t7 t9 t14 t11 t10 FPSHIFT t12 UD[7:0] LD[7:0] t13 1 2 Figure 7-41 16-Bit Dual Color Passive LCD Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Table 7-31 16-Bit Dual Color Passive LCD Panel A.C. Timing Parameter Min. Typ. FPFRAME setup to FPLINE pulse trailing edge note 2 FPFRAME hold from FPLINE pulse trailing edge 14 FPLINE period note 3 FPLINE pulse width 9 MOD transition to FPLINE pulse trailing edge 1 FPSHIFT falling edge to FPLINE pulse leading edge note 5 FPSHIFT falling edge to FPLINE pulse trailing edge note 6 FPLINE pulse trailing edge to FPSHIFT falling edge t14 + 2 FPSHIFT period 2 FPSHIFT pulse width low 1 FPSHIFT pulse width high 1 UD[7:0], LD[7:0] setup to FPSHIFT falling edge 1 UD[7:0], LD[7:0] hold to FPSHIFT falling edge 1 FPLINE pulse trailing edge to FPSHIFT rising edge 12 Notes: 1. Ts 2. 3. 4. 5. 6. 1-74 t1min t3min t5min t6min t7min Max. Units Ts (note 1) Ts note 4 Ts Ts Ts Ts Ts Ts = pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = t3min - 14Ts = [((REG[04h] bits [6:0])+1)8 + ((REG[05h] bits [4:0]) + 1)8] +33 Ts = [(((REG[04h] bits [6:0])+1)8 + ((REG[05h] bits [4:0]) + 1)8)-1] Ts = [((REG[05h] bits [4:0]) + 1)8 - 20] Ts = [((REG[05h] bits [4:0]) + 1)8 - 11] Ts EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 7: A.C. CHARACTERISTICS 16-Bit TFT/D-TFD Panel Timing VNDP VDP FPFRAME FPLINE R [5:1], G [5:0], B [5:1] LINE480 LINE1 LINE480 DRDY FPLINE HDP HNDP1 HNDP2 FPSHIFT DRDY R [5:1] G [5:0] B [5:1] 1-1 1-2 1-640 1-1 1-2 1-640 1-1 1-2 1-640 Note: DRDY is used to indicate the first pixel Example Timing for 640x480 panel Figure 7-42 16-Bit TFT/D-TFD Panel Timing VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = HNDP1 + HNDP2= ((REG[05h] bits [4:0]) + 1)*8Ts EPSON 1-75 7: A.C. CHARACTERISTICS t8 t9 FPFRAME t12 FPLINE t6 FPLINE t15 t7 t17 DRDY t14 t1 t2 t3 t11 t13 t16 FPSHIFT t4 R[5:1] G[5:0] B[5:1] t5 1 2 639 640 t10 Note: DRDY is used to indicate the first pixel Figure 7-43 16-Bit TFT/D-TFD A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 Table 7-32 16-Bit TFT/D-TFD A.C. Timing Parameter Min. FPSHIFT period 1 FPSHIFT pulse width high 0.45 FPSHIFT pulse width low 0.45 data setup to FPSHIFT falling edge 0.45 data hold from FPSHIFT falling edge 0.45 FPLINE cycle time note 2 FPLINE pulse width low note 3 FPFRAME cycle time note 4 FPFRAME pulse width low note 5 horizontal display period note 6 FPLINE setup to FPSHIFT falling edge 0.45 FPFRAME pulse leading edge to FPLINE pulse leading edge phase note 7 difference DRDY to FPSHIFT falling edge setup time 0.45 DRDY pulse width note 8 DRDY falling edge to FPLINE pulse leading edge note 9 DRDY hold from FPSHIFT falling edge 0.45 FPLINE pulse leading edge to DRDY active note 10 Typ. Max. Units Ts (note 1) Ts Ts Ts Ts Ts Ts 250 Ts Ts Notes: 1. Ts = pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) 2. t6min = [((REG[04h] bits [6:0])+1)8 + ((REG[05h] bits [4:0])+1)8] Ts 3. t7min = [((REG[07h] bits [3:0])+1)8] Ts 4. t8 min = [((REG[09h] bits [1:0], REG[08h] bits [7:0])+1) + ((REG[0Ah] bits [5:0])+1)] lines 5. t9min = [((REG[0Ch] bits [2:0])+1)] lines 6. t10min = [((REG[04h] bits [6:0])+1)8] Ts 7. t12min = [((REG[06h] bits [4:0])*8)+1] Ts 8. t14min = [((REG[04h] bits [6:0])+1)8] Ts 9. t15min = [((REG[06h] bits [4:0])+1)8 - 2] Ts 10. t17min = [((REG[05h] bits [4:0])+1)8 - ((REG[06h] bits [4:0])+1)8 + 2] 1-76 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 7: A.C. CHARACTERISTICS CRT Timing VNDP VDP VRTC HRTC RED, GREEN, BLUE LINE480 LINE1 LINE480 HRTC HDP HNDP1 RED, GREEN, BLUE 1-1 1-2 HNDP2 1-640 Example Timing for 640x480 CRT Figure 7-44 CRT Timing VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = HNDP1 + HNDP2 = ((REG[05h] bits [4:0]) + 1)*8Ts Note: The signals RED, GREEN and BLUE are analog signals from the embedded DAC and represent the color components which make up each pixel. S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-77 7: A.C. CHARACTERISTICS t1 t2 VRTC t3 HRTC Figure 7-45 CRT A.C. Timing Symbol t1 t2 t3 Table 7-33 CRT A.C. Timing Parameter Min. VRTC cycle time VRTC pulse width low VRTC falling edge to FPLINE falling edge phase difference Typ. note 1 note 2 Max. Units note 3 Notes: 1. t1min = [((REG[09h] bits 1:0, REG[08h] bits 7:0)+1) + ((REG[0Ah] bits 6:0)+1)] lines 2. t2min = [((REG[0Ch] bits 2:0)+1)] lines 3. t3min = [((REG[06h] bits 4:0)+1)8] Ts 1-78 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 8: REGISTERS 8 REGISTERS 8.1 Register Mapping The S1D13505 registers are memory mapped. The system addresses the registers through the CS#, M/R#, and AB[5:0] input pins. When CS# = 0 and M/R# = 0, the registers are mapped by address bits AB[5:0], e.g. REG[00h] is mapped to AB[5:0] = 000000, REG[01h] is mapped to AB[5:0] = 000001. See the table below: Table 8-1 S1D13505 Addressing CS# M/R# 0 0 0 1 1 x S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) Access Register access: * REG[00h] is addressed when AB[5:0] = 0 * REG[01h] is addressed when AB[5:0] = 1 * REG[n] is addressed when AB[5:0] = n Memory access: the 2M byte display buffer is addressed by AB[20:0] S1D13505 not selected EPSON 1-79 8: REGISTERS 8.2 Register Descriptions Unless specified otherwise, all register bits are reset to 0 during power up. Reserved bits should be written 0 when programming unless otherwise noted. Revision Code Register Revision Code Register REG[00h] Product Code Product Code Bit 5 Bit 4 Product Code Bit 3 Product Code Bit 2 Product Code Bit 1 Product Code Bit 0 RO Revision Code Revision Code Bit 1 Bit 0 bits 7-2 Product Code Bits [5:0] This is a read-only register that indicates the product code of the chip. The product code for the S1D13505F00A is 000011. bits 1-0 Revision Code Bits [1:0] This is a read-only register that indicates the revision code of the chip. The revision code for the S1D13505F00A is 00. Memory Configuration Registers Memory Configuration Register REG[01h] Refresh Rate Refresh Rate n/a Bit 2 Bit 1 RW Refresh Rate Bit 0 n/a WE# Control n/a Memory Type bits 6-4 DRAM Refresh Rate Select Bits [2:0] These bits specify the divisor used to generate the DRAM refresh rate from the input clock (CLKI). Table 8-2 DRAM Refresh Rate Selection DRAM Refresh Rate Select Bits [2:0] CLKI Frequency Divisor Example Refresh Rate for CLKI = 33MHz 000 001 010 011 100 101 110 111 64 128 256 512 1024 2048 4096 8192 520 kHz 260 kHz 130 kHz 65 kHz 33 kHz 16 kHz 8 kHz 4 kHz bit 2 WE# Control When this bit = 1, 2-WE# DRAM is selected. When this bit = 0, 2-CAS# DRAM is selected. bit 0 Memory Type When this bit = 1, FPM-DRAM is selected. When this bit = 0, EDO-DRAM is selected. Example period for 256 refresh cycles at CLKI = 33MHz 0.5 ms 1 ms 2 ms 4 ms 8 ms 16 ms 32 ms 64 ms This bit should be changed only when there are no read/write DRAM cycles. This condition occurs when all of the following are true: the Display FIFO is disabled (REG[23h] bit 7 = 1), and the Half Frame Buffer is disabled (REG[1Bh] bit 0 = 1), and the Ink/Cursor is inactive(Reg[27h] bits 7-6 = 00). This condition also occurs when the CRT and LCD enable bits (Reg[0Dh] bits 1-0) have remained 0 since chip reset. For further programming information, see "S1D13505 Programming Notes and Examples", document number X23A-G-003-05. 1-80 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 8: REGISTERS Panel/Monitor Configuration Registers Panel Type Register REG[02h] EL Panel Enable bit 7 n/a Panel Data Width Bit 1 Panel Data Width Bit 0 Panel Data Format Select Color/Mono Panel Select Dual/Single Panel Select RW TFT/Passive LCD Panel Select EL Panel Mode Enable When this bit = 1, EL Panel support mode is enabled. Every 262143 frames (approximately 1 hour at 60Hz frame rate) the identical panel data is sent to two consecutive frames, i.e. the frame rate modulation circuitry is frozen for one frame. bits 5-4 Panel Data Width Bits [1:0] These bits select the LCD interface data width as shown in the following table. Table 8-3 Panel Data Width Selection Panel Data Width Bits [1:0] Passive LCD Panel Data Width Size 00 01 10 11 4-bit 8-bit 16-bit Reserved TFT/D-TFD Panel Data Width Size 9-bit 12-bit 16-bit Reserved bit 3 Panel Data Format Select When this bit = 1, color passive LCD panel data format 2 is selected. When this bit = 0, passive LCD panel data format 1 is selected. bit 2 Color/Mono Panel Select When this bit = 1, color passive LCD panel is selected. When this bit = 0, monochrome passive LCD panel is selected. bit 1 Dual/Single Panel Select When this bit = 1, dual passive LCD panel is selected. When this bit = 0, single passive LCD panel is selected. bit 0 TFT/Passive LCD Panel Select When this bit = 1, TFT/D-TFD panel is selected. When this bit = 0, passive LCD panel is selected. MOD Rate Register REG[03h] n/a n/a RW MOD Rate Bit MOD Rate Bit MOD Rate Bit MOD Rate Bit MOD Rate Bit MOD Rate Bit 5 4 3 2 1 0 bits 5-0 MOD Rate Bits [5:0] When the DRDY pin is configured as MOD, this register controls the toggle rate of the MOD output. When this register is zero, the MOD output signal toggles every FPFRAME. When this register is non-zero, its value represents the number of FPLINE pulses between toggles of the MOD output signal. S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-81 8: REGISTERS Horizontal Display Width Register REG[04h] RW Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal n/a Display Width Display Width Display Width Display Width Display Width Display Width Display Width Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 bits 6-0 Horizontal Display Width Bits [6:0] These bits specify the horizontal display width. Horizontal display width (pixels) = (Horizontal Display Width Bits [6:0] + 1) x 8 The maximum horizontal display width is 1024 pixels. Notes: * This register must be programmed such that REG[04h] 3 (32 pixels). * When setting a horizontal resolution greater than 767 pixels, with a color depth of 15/16 bpp, the Memory Offset Registers (REG[16h], REG[17h]) must be set to a virtual horizontal pixelresolution of 1024. Horizontal Non-Display Period Register REG[05h] n/a n/a n/a Horizontal Non-Display Period Bit 4 Horizontal Non-Display Period Bit 3 Horizontal Non-Display Period Bit 2 Horizontal Non-Display Period Bit 1 RW Horizontal Non-Display Period Bit 0 bits 4-0 Horizontal Non-Display Period Bits [4:0] These bits specify the horizontal non-display period. Horizontal non-display period (pixels) = (Horizontal Non-Display Period Bits [4:0] + 1) x 8 The recommended minimum value which should be programmed into this register is 3 (32 pixels). The maximum value which can be programmed into this register is 1Fh, which gives a horizontal non-display period of 256 pixels. Note: This register must be programmed such that REG[05h] 3 and (REG[05h] + 1) (REG[06h] + 1) + (REG[07h] bits [3:0] + 1) HRTC/FPLINE Start Position Register REG[06h] RW HRTC/FPLINE HRTC/FPLINE HRTC/FPLINE HRTC/FPLINE HRTC/FPLINE n/a n/a n/a Start Position Start Position Start Position Start Position Start Position Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 bits 4-0 HRTC/FPLINE Start Position Bits [4:0] For CRT and TFT/D-TFD, these bits specify the delay from the start of the horizontal non-display period to the leading edge of the HRTC pulse and FPLINE pulse respectively. HRTC/FPLINE start position (pixels) = (HRTC/FPLINE Start Position Bits [4:0] + 1) x 8 - 2 Note: This register must be programmed such that (REG[05h] + 1) (REG[06h] + 1) + (REG[07h] bits [3:0] + 1) 1-82 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 8: REGISTERS HRTC/FPLINE Pulse Width Register REG[07h] HRTC FPLINE Polarity Select Polarity Select n/a RW HRTC/FPLINE HRTC/FPLINE HRTC/FPLINE HRTC/FPLINE Pulse Width Bit Pulse Width Bit Pulse Width Bit Pulse Width Bit 3 2 1 0 n/a bit 7 HRTC Polarity Select This bit selects the polarity of the HRTC pulse to the CRT. When this bit = 1, the HRTC pulse is active high. When this bit = 0, the HRTC pulse is active low. bit 6 FPLINE Polarity Select This bit selects the polarity of the FPLINE pulse to TFT/D-TFD or passive LCD. When this bit = 1, the FPLINE pulse is active high for TFT/D-TFD and active low for passive LCD. When this bit = 0, the FPLINE pulse is active low for TFT/D-TFD and active high for passive LCD. FPLINE Polarity Select 0 1 Table 8-4 FPLINE Polarity Selection Passive LCD FPLINE Polarity TFT/D-TFD FPLINE Polarity active high active low active low active high bits 3-0 HRTC/FPLINE Pulse Width Bits [3:0] For CRT and TFT/D-TFD, these bits specify the pulse width of HRTC and FPLINE respectively. For passive LCD, FPLINE is automatically created and these bits have no effect. HRTC/FPLINE pulse width (pixels) = (HRTC/FPLINE Pulse Width Bits [3:0] + 1) x 8 The maximum HRTC pulse width is 128 pixels. Note: This register must be programmed such that (REG[05h] + 1) (REG[06h] + 1) + (REG[07h] bits [3:0] + 1) Vertical Display Height Register 0 REG[08h] Vertical Display Height Bit 7 Vertical Display Height Bit 6 Vertical Display Height Bit 5 RW Vertical Display Height Bit 4 Vertical Display Height Bit 3 Vertical Display Height Bit 2 Vertical Display Height Bit 1 Vertical Display Height Bit 0 Vertical Display Height Register 1 REG[09h] n/a n/a n/a RW n/a n/a n/a Vertical Display Height Bit 9 Vertical Display Height Bit 8 REG[08h] bits 7-0 Vertical Display Height Bits [9:0] REG[09h] bits 1-0 These bits specify the vertical display height. Vertical display height (lines) = Vertical Display Height Bits [9:0] + 1 * For CRT, TFT/D-TFD, and single passive LCD panel this register is programmed to: (vertical resolution of the display) - 1, e.g. EFh for a 240-line display. * For dual-panel passive LCD not in simultaneous display mode, this register is programmed to: ((vertical resolution of the display)/2) - 1, e.g. EFh for a 480-line display. * For all simultaneous display modes, this register is programmed to: (vertical resolution of the CRT) - 1, e.g. 1DFh for a 480-line CRT. S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-83 8: REGISTERS Vertical Non-Display Period Register REG[0Ah] RW Vertical Nonn/a Vertical Non- Vertical Non- Vertical Non- Vertical Non- Vertical Non- Vertical NonDisplay Period Display Period Display Period Display Period Display Period Display Period Display Period Status (RO) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 bit 7 Vertical Non-Display Period Status This is a read-only status bit. When this bit = 1, a vertical non-display period is indicated. When this bit = 0, a vertical display period is indicated. bits 5-0 Vertical Non-Display Period Bits [5:0] These bits specify the vertical non-display period. Vertical non-display period (lines) = Vertical Non-Display Period Bits [5:0] Note: This register must be programmed such that REG[0Ah] 1 and (REG[0Ah] bits [5:0] + 1) (REG[0Bh] + 1) + (REG[0Ch] bits [2:0] + 1) VRTC/FPFRAME Start Position Register REG[0Bh] VRTC/ FPFRAME n/a n/a Start Position Bit 5 VRTC/ FPFRAME Start Position Bit 4 VRTC/ FPFRAME Start Position Bit 3 VRTC/ FPFRAME Start Position Bit 2 VRTC/ FPFRAME Start Position Bit 1 RW VRTC/ FPFRAME Start Position Bit 0 bits 5-0 VRTC/FPFRAME Start Position Bits [5:0] For CRT and TFT/D-TFD, these bits specify the delay in lines from the start of the vertical non-display period to the leading edge of the VRTC pulse and FPFRAME pulse respectively. For passive LCD, FPFRAME is automatically created and these bits have no effect. VRTC/FPFRAME start position (lines) = VRTC/FPFRAME Start Position Bits [5:0] + 1 The maximum start delay is 64 lines. Note: This register must be programmed such that (REG[0Ah] bits [5:0] + 1) (REG[0Bh] + 1) + (REG[0Ch] bits [2:0] + 1) For exact timing please use the timing diagrams in section 7.5 1-84 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 8: REGISTERS VRTC/FPFRAME Pulse Width Register REG[0Ch] VRTC PolarFPFRAME n/a ity Select Polarity Select n/a n/a VRTC/ FPFRAME Pulse Width Bit 2 VRTC/ FPFRAME Pulse Width Bit 1 RW VRTC/ FPFRAME Pulse Width Bit 0 bit 7 VRTC Polarity Select This bit selects the polarity of the VRTC pulse to the CRT. When this bit = 1, the VRTC pulse is active high. When this bit = 0, the VRTC pulse is active low. bit 6 FPFRAME Polarity Select This bit selects the polarity of the FPFRAME pulse to the TFT/D-TFD or passive LCD. When this bit = 1, the FPFRAME pulse is active high for TFT/D-TFD and active low for passive. When this bit = 0, the FPFRAME pulse is active low for TFT/D-TFD and active high for passive. FPFRAME Polarity Select 0 1 Table 8-5 FPFRAME Polarity Selection Passive LCD FPFRAME Polarity TFT/D-TFD FPFRAME Polarity active high active low active low active high bits 2-0 VRTC/FPFRAME Pulse Width Bits [2:0] For CRT and TFT/D-TFD, these bits specify the pulse width of VRTC and FPFRAME respectively. For passive LCD, FPFRAME is automatically created and these bits have no effect. VRTC/FPFRAME pulse width (lines) = VRTC/FPFRAME Pulse Width Bits [2:0] + 1 Note: This register must be programmed such that (REG[0Ah] bits [5:0] + 1) (REG[0Bh] + 1) + (REG[0Ch] bits [2:0] + 1) S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-85 8: REGISTERS Display Configuration Registers Display Mode Register REG[0Dh] SwivelViewTM Simultaneous Simultaneous Display Option Display Option Enable Select Bit 1 Select Bit 0 bit 7 Bit-per-pixel Select Bit 2 Bit-per-pixel Select Bit 1 Bit-per-pixel Select Bit 0 CRT Enable RW LCD Enable SwivelViewTM Enable When this bit = 1, all CPU accesses to the display buffer are translated to provide clockwise 90 hardware rotation of the display image. Refer to Section 13, "SwivelViewTM" for application and limitations. bits 6-5 Simultaneous Display Option Select Bits [1:0] These bits are used to select one of four different simultaneous display mode options: Normal, Line Doubling, Interlace, or Even Scan Only. The purpose of these modes is to manipulate the vertical resolution of the image so that it fits on both the CRT, typically 640x480, and LCD. The following table describes the four modes using a 640x480 CRT as an example: Table 8-6 Simultaneous Display Option Selection Simultaneous Display Option Select Bits [1:0] 00 01 10 11 Simultaneous Display Mode Mode Description The image is not manipulated. This mode is used when the CRT and LCD have the same resolution, e.g. 480 lines. It is necessary to suit the vertical retrace period to the CRT. This results in a lower LCD duty Normal cycle (1/525 compared to the usual 1/481). This reduced duty cycle may result in lower contrast on the LCD. Each line is replicated on the CRT. This mode is used to display a 240-line image on a 240-line LCD and stretch it to a 480-line image on the CRT. The CRT has a heightened aspect ratio. Line Doubling It is necessary to suit the vertical retrace period to the CRT. This results in a lower LCD duty cycle (2/525 compared to the usual 1/241). This reduced duty cycle is not extreme and the contrast of the LCD image should not be greatly reduced. The odd and even fields of a 480-line image are interlaced on the LCD. This mode is used to display a 480-line image on the CRT and squash it onto a 240-line LCD. The full image is viewed on the LCD but the interlacing may create flicker. The LCD has a shortened aspect Interlace ratio. It is necessary to suit the vertical retrace period to the CRT. This results in a lower LCD duty cycle (2/525 compared to the usual 1/241). This reduced duty cycle is not extreme and the contrast of the LCD image should not be greatly reduced. Only the even field of a 480-line image is displayed on the LCD. This is an alternate method to display a 480-line image on the CRT and squash it onto a 240-line LCD. Only the even scans are viewed on the LCD. The LCD has a shortened aspect ratio. Even Scan Only It is necessary to suit the vertical retrace period to the CRT. This results in a lower LCD duty cycle (2/525 compared to the usual 1/241). This reduced duty cycle is not extreme and the contrast of the LCD image should not be greatly reduced. Notes: 1. Dual Panel Considerations: When configured for a dual LCD panel and using Simultaneous Display, the Half Frame Buffer Disable, REG[1Bh] bit 0, must be set to 1. This results in a lower contrast on the LCD panel, which may require adjustment. 2. The Line doubling option is not supported with dual panel. 1-86 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 8: REGISTERS bits 4-2 Bit-Per-Pixel Select Bits [2:0] These bits select the color depth (bpp) for the displayed data. See Section 10.1, "Display Mode Data Format" for details of how the pixels are mapped into the image buffer. Table 8-7 Bits-Per-Pixel Selection Bit-per-pixel Select Bits [2:0] Color Depth (bpp) 000 1 bpp 001 2 bpp 010 4 bpp 011 8 bpp 100 15 bpp 101 16 bpp Reserved 110 - 111 bit 1 CRT Enable This bit enables the CRT monitor. When this bit = 1, the CRT is enabled. When this bit = 0, the CRT is disabled. bit 0 LCD Enable This bit enables the LCD panel. Programming this bit from a 0 to a 1 starts the LCD power-on sequence. Programming this bit from a 1 to a 0 starts the LCD power-off sequence. Screen 1 Line Compare Register 0 REG[0Eh] RW Screen 1 Line Screen 1 Line Screen 1 Line Screen 1 Line Screen 1 Line Screen 1 Line Screen 1 Line Screen 1 Line Compare Bit 7 Compare Bit 6 Compare Bit 5 Compare Bit 4 Compare Bit 3 Compare Bit 2 Compare Bit 1 Compare Bit 0 Screen 1 Line Compare Register 1 REG[0Fh] n/a n/a n/a n/a n/a n/a RW Screen 1 Line Screen 1 Line Compare Bit 9 Compare Bit 8 REG[0Eh] bits 7-0 Screen 1 Line Compare Bits [9:0] REG[0Fh] bits 1-0 These bits are set to 1 during power-on. The display can be split into two images: Screen 1 and Screen 2, with Screen 1 above Screen 2. This 10-bit value specifies the height of Screen 1. Height of Screen 1 (lines) = Screen 1 Line Compare Bits [9:0] + 1 If the height of Screen 1 is less than the display height then the remainder of the display is taken up by Screen 2. For normal operation (no split screen) this register must be set greater than the Vertical Display Height register (e.g. set to the reset value of 3FFh). See Section 10, "Display Configuration" for details. Screen 1 Display Start Address Register 0 REG[10h] Start Address Start Address Start Address Start Address Bit 7 Bit 6 Bit 5 Bit 4 Start Address Bit 3 Start Address Bit 2 Start Address Bit 1 RW Start Address Bit 0 Screen 1 Display Start Address Register 1 REG[11h] Start Address Start Address Start Address Start Address Bit 15 Bit 14 Bit 13 Bit 12 Start Address Bit 11 Start Address Bit 10 Start Address Bit 9 RW Start Address Bit 8 Start Address Bit 19 Start Address Bit 18 Start Address Bit 17 RW Start Address Bit 16 Screen 1 Display Start Address Register 2 REG[12h] n/a n/a n/a S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) n/a EPSON 1-87 8: REGISTERS REG[10h] bits 7-0 REG[11h] bits 7-0 Screen 1 Start Address Bits [19:0] These registers form the 20-bit address for the starting word of the Screen 1 image in the display buffer. REG[12h] bits 3-0 Note that this is a word address. A combination of this register and the Pixel Panning register (REG[18h]) can be used to uniquely identify the start (top left) pixel within the Screen 1 image stored in the display buffer. See Section 10, "Display Configuration" for details. Screen 2 Display Start Address Register 0 REG[13h] Start Address Start Address Start Address Start Address Bit 7 Bit 6 Bit 5 Bit 4 Start Address Bit 3 Start Address Bit 2 Start Address Bit 1 RW Start Address Bit 0 Screen 2 Display Start Address Register 1 REG[14h] Start Address Start Address Start Address Start Address Bit 15 Bit 14 Bit 13 Bit 12 Start Address Bit 11 Start Address Bit 10 Start Address Bit 9 RW Start Address Bit 8 Start Address Bit 19 Start Address Bit 18 Start Address Bit 17 RW Start Address Bit 16 Screen 2 Display Start Address Register 2 REG[15h] n/a n/a REG[13h] bits 7-0 REG[14h] bits 7-0 n/a n/a Screen 2 Start Address Bits [19:0] These registers form the 20-bit address for the starting word of the Screen 2 image in the display buffer. REG[15h] bits 3-0 Note that this is a word address. A combination of this register and the Pixel Panning register (REG[18h]) can be used to uniquely identify the start (top left) pixel within the Screen 2 image stored in the display buffer. See Section 10, "Display Configuration" for details. Memory Address Offset Register 0 REG[16h] Memory Memory Memory Address Address Address Offset Bit 7 Offset Bit 6 Offset Bit 5 Memory Address Offset Bit 4 Memory Address Offset Bit 3 Memory Address Offset Bit 2 Memory Address Offset Bit 1 RW Memory Address Offset Bit 0 n/a Memory Address Offset Bit 10 Memory Address Offset Bit 9 RW Memory Address Offset Bit 8 Memory Address Offset Register 1 REG[17h] n/a n/a n/a n/a REG[16h] bits 7-0 REG[17h] bits 2-0 Memory Address Offset Bits [10:0] These bits form the 11-bit address offset from the starting word of line n to the starting word of line n+1. This value is applied to both Screen 1 and Screen 2. Note that this value is in words. A virtual image can be formed by setting this register to a value greater than the width of the display. The displayed image is a window into the larger virtual image. See Section 10, "Display Configuration" for details. 1-88 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 8: REGISTERS Pixel Panning Register REG[18h] RW Screen 2 Pixel Screen 2 Pixel Screen 2 Pixel Screen 2 Pixel Screen 1 Pixel Screen 1 Pixel Screen 1 Pixel Screen 1 Pixel Panning Bit 3 Panning Bit 2 Panning Bit 1 Panning Bit 0 Panning Bit 3 Panning Bit 2 Panning Bit 1 Panning Bit 0 This register is used to control the horizontal pixel panning of Screen 1 and Screen 2. Each screen can be independently panned to the left by programming its respective Pixel Panning Bits to a non-zero value. The value represents the number of pixels panned. The maximum pan value is dependent on the display mode. Display Mode 1 bpp 2 bpp 4 bpp 8 bpp 15/16 bpp Table 8-8 Pixel Panning Selection Maximum Pan Value 16 8 4 1 0 Pixel Panning Bits Active Bits [3:0] Bits [2:0] Bits [1:0] Bit 0 none Smooth horizontal panning can be achieved by a combination of this register and the Display Start Address registers. See Section 10, "Display Configuration" for details. bits 7-4 Screen 2 Pixel Panning Bits [3:0] Pixel panning bits for screen 2. bits 3-0 Screen 1 Pixel Panning Bits [3:0] Pixel panning bits for screen 1. S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-89 8: REGISTERS Clock Configuration Register Clock Configuration Register REG[19h] Reserved n/a n/a n/a n/a MCLK Divide Select PCLK Divide Select Bit 1 RW PCLK Divide Select Bit 0 bit 7 Reserved This bit must be set to 0. bit 2 MCLK Divide Select When this bit = 1 the MCLK frequency is half of its source frequency. When this bit = 0 the MCLK frequency is equal to its source frequency. The MCLK frequency should always be set to the maximum frequency allowed by the DRAM; this provides maximum performance and minimum overall system power consumption. bits 1-0 PCLK Divide Select Bits [1:0] These bits select the MCLK: PCLK frequency ratio. Table 8-9 PCLK Divide Selection PCLK Divide Select Bits [1:0] MCLK : PCLK Frequency Ratio 00 1:1 01 2:1 10 3:1 11 4:1 See Section on "Maximum MCLK: PCLK Ratios" for selection of clock ratios. 1-90 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 8: REGISTERS Power Save Configuration Registers Power Save Configuration Register REG[1Ah] Power Save Status n/a n/a RO n/a LCD Power Disable RW Suspend Suspend Software Refresh Select Refresh Select Suspend Mode Bit 1 Bit 0 Enable bit 7 Power Save Status This is a read-only status bit. This bit indicates the power-save state of the chip. When this bit = 1, the panel has been powered down and the memory controller is either in self refresh mode or is performing only CAS-before-RAS refresh cycles. When this bit = 0, the chip is either powered up, in transition of powering up, or in transition of powering down. See Section 15, "Power Save Modes" for details. bit 3 LCD Power Disable This bit is used to override the panel on/off sequencing logic. When this bit = 0 the LCDPWR output is controlled by the panel on/off sequencing logic. When this bit = 1 the LCDPWR output is directly forced to the off state. The LCDPWR "On/Off" polarity is configured by MD10 at the rising edge of RESET# (MD10 = 0 configures LCDPWR = 0 as the Off state; MD10 = 1 configures LCDPWR = 1 as the Off state). bits 2-1 Suspend Refresh Select Bits [1:0] These bits specify the type of DRAM refresh to use in Suspend mode. Table 8-10 Suspend Refresh Selection Suspend Refresh Select Bits [1:0] DRAM Refresh Type 00 CAS-before-RAS (CBR) refresh 01 Self-Refresh 1x No Refresh Note: bit 0 These bits should not be changed when suspend mode is active. Software Suspend Mode Enable When this bit = 1 software Suspend mode is enabled. When this bit = 0 software Suspend mode is disabled. See Section 15, "Power Save Modes" for details. S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-91 8: REGISTERS Miscellaneous Registers Miscellaneous Disable Register REG[1Bh] Host Interface n/a Disable n/a n/a n/a n/a n/a RW Half Frame Buffer Disable bit 7 Host Interface Disable This bit is set to 1 during power-on/reset. This bit must be programmed to 0 to enable the Host Interface. When this bit is high, all memory and all registers except REG[1Ah] (read-only) and REG[1Bh] are inaccessible. bit 0 Half Frame Buffer Disable This bit is used to disable the Half Frame Buffer. When this bit = 1, the Half Frame Buffer is disabled. When this bit = 0, the Half Frame Buffer is enabled. When a single panel is selected, the Half Frame Buffer is automatically disabled and this bit has no effect. The half frame buffer is needed to fully support dual panels. Disabling the Half Frame Buffer reduces memory bandwidth requirements and increases the supportable pixel clock frequency, but results in reduced contrast on the LCD panel (the duty cycle of the LCD is halved). This mode is not normally used except under special circumstances such as simultaneous display on a CRT and dual panel LCD. When this mode is used the Alternate Frame Rate Modulation scheme should be used (see REG[31h]). For details on Frame Rate calculation see Section 14.2, "Frame Rate Calculation". MD Configuration Readback Register 0 REG[1Ch] MD[7] Status MD[6] Status MD[5] Status MD[1] Status RO MD[0] Status MD Configuration Readback Register 1 REG[1Dh] MD[15] Status MD[14] Status MD[13] Status MD[12] Status MD[11] Status MD[10] Status MD[9] Status RO MD[8] Status 1-92 MD[4] Status MD[3] Status MD[2] Status REG[1Ch] bits 7-0 MD[15:0] Configuration Status REG[1Dh] bits 7-0 These are read-only status bits for the MD[15:0] pins configuration status at the rising edge of RESET#. MD[15:0] are used to configure the chip at the rising edge of RESET# - see "Pin Descriptions and Summary of Configuration Options" for details. EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 8: REGISTERS General IO Pins Configuration Register 0 REG[1Eh] n/a n/a n/a RO n/a GPIO3 Pin IO Config. GPIO2 Pin IO Config. GPIO1 Pin IO Config. n/a Pins MA9, MA10, MA11 are multi-functional - they can be DRAM address outputs or general purpose IO dependent on the DRAM type. MD[7:6] are used to identify the DRAM type and configure these pins as follows: Table 8-11 MA/GPIO Pin Functionality Pin Function MD[7:6] at Rising Edge of RESET# MA9 MA10 MA11 00 GPIO3 GPIO1 GPIO2 01 MA9 GPIO1 GPIO2 10 MA9 GPIO1 GPIO2 11 MA9 MA10 MA11 These bits are used to control the direction of these pins when they are used as general purpose IO. These bits have no effect when the pins are used as DRAM address outputs. bit 3 GPIO3 Pin IO Configuration When this bit = 1, the GPIO3 pin is configured as an output pin. When this bit = 0 (default), the GPIO3 pin is configured as an input pin. bit 2 GPIO2 Pin IO Configuration When this bit = 1, the GPIO2 pin is configured as an output pin. When this bit = 0 (default), the GPIO2 pin is configured as an input pin. bit 1 GPIO1 Pin IO Configuration When this bit = 1, the GPIO1 pin is configured as an output pin. When this bit = 0 (default), the GPIO1 pin is configured as an input pin. General IO Pins Configuration Register 1 REG[1Fh] n/a n/a n/a RW n/a n/a n/a n/a GPIO2 Pin IO Status GPIO1 Pin IO Status n/a This register position is reserved for future use. General IO Pins Control Register 0 REG[20h] n/a n/a n/a RW n/a GPIO3 Pin IO Status n/a bit 3 GPIO3 Pin IO Status When GPIO3 is configured as an output (see REG[1Eh]), a "1" in this bit drives GPIO3 high and a "0" in this bit drives GPIO3 low. When GPIO3 is configured as an input, a read from this bit returns the status of GPIO3. bit 2 GPIO2 Pin IO Status When GPIO2 is configured as an output (see REG[1Eh]), a "1" in this bit drives GPIO2 high and a "0" in this bit drives GPIO2 low. When GPIO2 is configured as an input, a read from this bit returns the status of GPIO2. bit 1 GPIO1 Pin IO Status When GPIO1 is configured as an output (see REG[1Eh]), a "1" in this bit drives GPIO1 high and a "0" in this bit drives GPIO1 low. When GPIO1 is configured as an input, a read from this bit returns the status of GPIO1. S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-93 8: REGISTERS GPIO Status / Control Register 1 REG[21h] GPO n/a n/a Control bit 7 RW n/a n/a n/a n/a n/a GPO Control This bit is used to control the state of the SUSPEND# when it is configured as GPO. The SUSPEND# pin can be used as a power-down input (SUSPEND#) or as an output (GPO) possibly used for controlling the LCD backlight power: *When MD9 = 0 at rising edge of RESET#, SUSPEND#/GPO is an active-low Schmitt input used to put the S1D13505 into suspend mode - see "Power Save Modes" for details. *When MD[10:9] = 01 at rising edge of RESET#, SUSPEND#/GPO is an output with a reset state of 0. *When MD[10:9] = 11 at rising edge of RESET#, SUSPEND#/GPO is an output with a reset state of 1. When this bit = 1 the GPO output is set to the reset state. When this bit = 0 the GPO output pin is set to the inverse of the reset state. Performance Enhancement Register 0 REG[22h] Reserved RC Timing Value Bit 1 RC Timing Value Bit 0 RW RAS#-toCAS# Delay Value RAS# PreRAS# Precharge Timing charge Timing Value Bit 1 Value Bit 0 Reserved Reserved Note: Changing this register to non-zero value, or to a different non-zero value, should be done only when there are no read/write DRAM cycles. This condition occurs when all of the following are true: the Display FIFO is disabled (REG[23h] bit 7 = 1), and the Half Frame Buffer is disabled (REG[1Bh] bit 0 = 1), and the Ink/Cursor is inactive (Reg[27h] bits 7-6 = 00). This condition also occurs when the CRT and LCD enable bits (Reg[0Dh] bits 1-0) have remained 0 since chip reset. For further programming information, see "S1D13505 Programming Notes and Examples", document number X23A-G-003-05. bit 7 Reserved bits 6-5 RC Timing Value (NRC) Bits [1:0] These bits select the DRAM random-cycle timing parameter, tRC. These bits specify the number (NRC) of MCLK periods (TM) used to create tRC. NRC should be chosen to meet tRC as well as tRAS, the RAS pulse width. Use the following two formulae to calculate NRC then choose the larger value. Note, these formulae assume an MCLK duty cycle of 50 +/- 5%. NRC = Round-Up (tRC/TM) NRC = Round-Up (tRAS/TM + NRP)if NRP = 1 or 2 = Round-Up (tRAS/TM + 1.55)if NRP = 1.5 The resulting tRC is related to NRC as follows: tRC = (NRC) TM 1-94 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 8: REGISTERS REG[22h] Bits [6:5] 00 01 10 11 bit 4 Table 8-12 Minimum Memory Timing Selection NRC Minimum Random Cycle Width (tRC) 5 5 TM 4 4 TM 3 3 TM Reserved Reserved RAS#-to-CAS# Delay Value (NRCD) This bit selects the DRAM RAS#-to-CAS# delay parameter, tRCD. This bit specifies the number (NRCD) of MCLK periods (TM) used to create tRCD. NRCD must be chosen to satisfy the RAS# access time, tRAC. Note, these formulae assume an MCLK duty cycle of 50 5%. NRCD = Round-Up ((tRAC + 5)/TM - 1) =2 = Round-Up (tRAC/TM - 1) = Round-Up (tRAC/TM - 0.45) if EDO and NRP = 1 or 2 if EDO and NRP = 1.5 if FPM and NRP = 1 or 2 if FPM and NRP = 1.5 Note that for EDO-DRAM and NRP = 1.5, this bit is automatically forced to 0 to select 2 MCLK for NRCD. This is done to satisfy the CAS# address setup time, tASC. The resulting tRCD is related to NRCD as follows: tRCD tRCD tRCD tRCD = (NRCD) TM = (1.5) TM = (NRCD + 0.5) TM = (NRCD) TM REG[22h] Bit 4 0 1 if EDO and NRP = 1 or 2 if EDO and NRP = 1.5 if FPM and NRP = 1 or 2 if FPM and NRP = 1.5 Table 8-13 RAS#-to-CAS# Delay Timing Select RAS#-to-CAS# Delay (tRCD) NRCD 2 2 1 1 bits 3-2 RAS# Precharge Timing Value (NRP) Bits [1:0] Minimum Memory Timing for RAS# precharge These bits select the DRAM RAS# Precharge timing parameter, tRP. These bits specify the number (NRP) of MCLK periods (TM) used to create tRP - see the following formulae. Note, these formulae assume an MCLK duty cycle of 50 +/- 5%. NRP = 1 = 1.5 =2 if (tRP/TM) < 1 if 1 (tRP/TM) < 1.45 if (tRP/TM) 1.45 The resulting tRP is related to NRP as follows: tRP = (NRP + 0.5) TM tRP = (NRP) TM if FPM refresh cycle and NRP = 1 or 2 for all other bits 1-0 Reserved These bits must be set to 0. REG[22h] Bits [3:2] 00 01 10 11 S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) Table 8-14 RAS# Precharge Timing Select NRP RAS# Precharge Width (tRP) 2 2 1.5 1.5 1 1 Reserved Reserved EPSON 1-95 8: REGISTERS Optimal DRAM Timing The following table contains the optimally programmed values of NRC, NRP, and NRCD for different DRAM types, at maximum MCLK frequencies. Table 8-15 Optimal NRC, NRP, and NRCD Values at Maximum MCLK Frequency DRAM Speed TM NRC NRP NRCD DRAM Type (ns) (ns) (#MCLK) (#MCLK) (#MCLK) 50 25 4 1.5 2 EDO 60 30 4 1.5 2 70 33 5 2 2 60 40 4 1.5 2 FPM 70 50 3 1.5 1 bits 1-0 Reserved This reserved bit must be set to 0. Performance Enhancement Register 1 REG[23h] Display FIFO CPU to Mem- CPU to MemDisable ory Wait State ory Wait State Bit 1 Bit 0 bit 7 Display FIFO Threshold Bit 4 Display FIFO Threshold Bit 3 Display FIFO Threshold Bit 2 Display FIFO Threshold Bit 1 RW Display FIFO Threshold Bit 0 Display FIFO Disable When this bit = 1 the display FIFO is disabled and all data outputs are forced to zero (i.e., the screen is blanked). This accelerates screen updates by allocating more memory bandwidth to CPU accesses. When this bit = 0 the display FIFO is enabled. Note: For further performance increase in dual panel mode disable the half frame buffer (see "Miscellaneous Registers") and disable the cursor (see "Ink/Cursor Registers"). bits 6-5 CPU to Memory Wait State Bits [1:0] These bits are used to optimize the handshaking between the host interface and the memory controller. The bits should be set according to the relationship between BCLK and MCLK - see the table below where TB and TM are the BCLK and MCLK periods respectively. Table 8-16 Minimum Memory Timing Selection Wait State Bits [1:0] Condition 00 no restrictions (default) 01 2TM - 4ns > TB 10 undefined 11 undefined bits 4-0 1-96 Display FIFO Threshold Bits [4:0] These bits specify the display FIFO depth required to sustain uninterrupted display fetches. When these bits are all 0s, the display FIFO depth is calculated automatically. These bits should always be set to 0, except in the following configurations: Landscape mode at 15/16 bpp (with MCLK=PCLK), Portrait mode at 8/16 bpp (with MCLK=PCLK). When in the above configurations, a value of 1Bh should be used. EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 8: REGISTERS Look-Up Table Registers Look-Up Table Address Register REG[24h] LUT Address LUT Address LUT Address Bit 7 Bit 6 Bit 5 LUT Address Bit 4 LUT Address Bit 3 LUT Address Bit 2 LUT Address Bit 1 RW LUT Address Bit 0 bits 7-0 LUT Address Bits [7:0] These 8 bits control a pointer into the Look-Up Tables (LUT). The S1D13505 has three 256-position, 4-bit wide LUTs, one for each of red, green, and blue - refer to "Look-Up Table Architecture" for details. This register selects which LUT entry is read/write accessible through the LUT Data Register (REG[26h]). Writing the LUT Address Register automatically sets the pointer to the Red LUT. Accesses to the LUT Data Register automatically increment the pointer. For example, writing a value 03h into the LUT Address Register sets the pointer to R[3]. A subsequent access to the LUT Data Register accesses R[3] and moves the pointer onto G[3]. Subsequent accesses to the LUT Data Register move the pointer onto B[3], R[4], G[4], B[4], R[5], etc. Note that the RGB data is inserted into the LUT after the Blue data is written, i.e. all three colors must be written before the LUT is updated. Look-Up Table Data Register REG[26h] LUT Data LUT Data LUT Data Bit 3 Bit 2 Bit 1 RW LUT Data Bit 0 n/a n/a n/a n/a bits 7-4 LUT Data This register is used to read/write the RGB Look-Up Tables. This register accesses the entry at the pointer controlled by the Look-Up Table Address Register (REG[24h]) - see above. Accesses to the Look-Up Table Data Register automatically increment the pointer. Note that the RGB data is inserted into the LUT after the Blue data is written, i.e. all three colors must be written before the LUT is updated. S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-97 8: REGISTERS Ink/Cursor Registers Ink/Cursor Control Register REG[27h] Ink/Cursor Ink/Cursor Mode Mode Bit 1 Bit 0 n/a Cursor High Threshold Bit 3 n/a Cursor High Threshold Bit 2 Cursor High Threshold Bit 1 RW Cursor High Threshold Bit 0 bits 7-6 Ink/Cursor Control Bits [1:0] These bits select the operating mode of the Ink/Cursor circuitry. See table below. Table 8-17 Ink/Cursor Selection REG[27h] Operating Mode Bit 6 0 inactive 1 Cursor 0 Ink 1 reserved Bit 7 0 0 1 1 bits 3-0 Ink/Cursor FIFO Threshold Bits [3:0] These bits specify the Ink/Cursor FIFO depth required to sustain uninterrupted display fetches. When these bits are all 0, the Ink/Cursor FIFO depth is calculated automatically. Cursor X Position Register 0 REG[28h] Cursor X Cursor X Cursor X Position Bit 7 Position Bit 6 Position Bit 5 Cursor X Position Bit 4 Cursor X Position Bit 3 Cursor X Position Bit 2 Cursor X Position Bit 1 RW Cursor X Position Bit 0 n/a n/a n/a Cursor X Position Bit 9 RW Cursor X Position Bit 8 Cursor X Position Register 1 REG[29h] Reserved n/a REG[2Bh] bit 7 Reserved This bit must be set to 0. REG[2Ah] bits 7-0 Cursor Y Position Bits [9:0] REG[2Bh] bits 1-0 In Cursor mode, this 10-bit register is used to program the vertical pixel position of the Cursor's top left pixel. This register must be set to 0 in Ink mode. Note: 1-98 n/a The Cursor X Position register must be set during VNDP (vertical non-display period). Check the VNDP status bit (REG[0Ah] bit 7) to determine if you are in VNDP, then update the register. EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 8: REGISTERS Cursor Y Position Register 0 REG[2Ah] Cursor Y Cursor Y Cursor Y Position Bit 7 Position Bit 6 Position Bit 5 Cursor Y Position Bit 4 Cursor Y Position Bit 3 Cursor Y Position Bit 2 Cursor Y Position Bit 1 RW Cursor Y Position Bit 0 n/a Cursor Y Position Bit 9 RW Cursor Y Position Bit 8 Cursor Y Position Register 1 REG[2Bh] Reserved n/a n/a n/a n/a REG[2Bh] bit 7 Reserved This bit must be set to 0. REG[2Ah] bits 7-0 Cursor Y Position Bits [9:0] REG[2Bh] bits 1-0 In Cursor mode, this 10-bit register is used to program the vertical pixel position of the Cursor's top left pixel. This register must be set to 0 in Ink mode. Note: The Cursor Y Position register must be set during VNDP (vertical non-display period). Check the VNDP status bit (REG[0Ah] bit 7) to determine if you are in VNDP, then update the register. Ink/Cursor Color 0 Register 0 REG[2Ch] RW Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Ink/Cursor Color 0 Register 1 REG[2Dh] RW Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 REG[2Ch] bits 7-0 Ink/Cursor Color 0 Bits [15:0] REG[2Dh] bits 7-0 These bits define the 5-6-5 RGB Ink/Cursor color 0. Ink/Cursor Color 1 Register 0 REG[2Eh] RW Cursor Color 1 Cursor Color 1 Cursor Color 1 Cursor Color 1 Cursor Color 1 Cursor Color 1 Cursor Color 1 Cursor Color 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Ink/Cursor Color 1 Register 1 REG[2Fh] RW Cursor Color 1 Cursor Color 1 Cursor Color 1 Cursor Color 1 Cursor Color 1 Cursor Color 1 Cursor Color 1 Cursor Color 1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 REG[2Eh] bits 7-0 Ink/Cursor Color 1 Bits [15:0] REG[2Fh] bits 7-0 These bits define the 5-6-5 RGB Ink/Cursor color 1. S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-99 8: REGISTERS Ink/Cursor Start Address Select Register REG[30h] Ink/Cursor Ink/Cursor Ink/Cursor Start Address Start Address Start Address Select Select Select Bit 7 Bit 6 Bit 5 Ink/Cursor Start Address Select Bit 4 Ink/Cursor Start Address Select Bit 3 Ink/Cursor Start Address Select Bit 2 Ink/Cursor Start Address Select Bit 1 RW Ink/Cursor Start Address Select Bit 0 bits 7-0 Ink/Cursor Start Address Select Bits [7:0] These bits define the start address for the Ink/Cursor buffer. The Ink/Cursor buffer must be positioned where it does not conflict with the image buffer and half-frame buffer - see Memory Mapping for details. The start address for the Ink/Cursor buffer is programmed as shown in the following table where Display Buffer Size represents the size in bytes of the attached DRAM device (see MD[7:6] in "Summary of Configuration Options"): Table 8-18 Ink/Cursor Start Address Encoding Ink/Cursor Start Address Bits [7:0] Start Address (Bytes) 0 Display Buffer Size - 1024 n = 255...1 Display Buffer Size - (n x 8192) The Ink/Cursor image is stored contiguously. The address offset from the starting word of line n to the starting word of line n+1 is calculated as follows: Ink Address Offset (words) = REG[04h] + 1 Cursor Address Offset (words) = 8 Alternate FRM Register REG[31h] RW Alternate FRM Alternate FRM Alternate FRM Alternate FRM Alternate FRM Alternate FRM Alternate FRM Alternate FRM Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 bits 7-0 Alternate Frame Rate Modulation Select Register that controls the alternate FRM scheme. When all bits are set to zero, the default FRM is selected. For single passive, or dual passive with the half frame buffer enabled, either the original or the alternate FRM scheme may be used. The alternate FRM scheme may produce more visually appealing output. The following table shows the recommended alternate FRM scheme values. Table 8-19 Recommended Alternate FRM Scheme Panel Mode Register Value Single Passive 0000 0000 or 1111 1111 Dual Passive w/Half Frame Buffer Enabled 0000 0000 or 1111 1010 Dual Passive w/Half Frame Buffer Disabled 1111 1111 1-100 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 9: DISPLAY BUFFER 9 DISPLAY BUFFER The system addresses the display buffer through the CS#, M/R#, and AB[20:0] input pins. When CS# = 0 and M/R# = 1, the display buffer is addressed by bits AB[20:0]. See the table below: Table 9-1 S1D13505 Addressing CS# M/R# 0 0 0 1 1 x Access Register access: * REG[00h] is addressed when AB[5:0] = 0 * REG[01h] is addressed when AB[5:0] = 1 * REG[n] is addressed when AB[5:0] = n Memory access: the 2M byte display buffer is addressed by AB[20:0] S1D13505 not selected The display buffer address space is always 2M bytes. However, the physical display buffer may be either 512K bytes or 2M bytes - see "Summary of Configuration Options". The display buffer can contain an image buffer, one or more Ink/Cursor buffers, and a half-frame buffer. A 512K byte display buffer is replicated in the 2M byte address space - see the figure below. 512K Byte Buffer AB[20:0] 2M Byte Buffer 000000h Image Buffer Ink/Cursor Buffer Half-Frame Buffer 07FFFFh 080000h Image Buffer Image Buffer Ink/Cursor Buffer Half-Frame Buffer Image Buffer 0FFFFFh 100000h Ink/Cursor Buffer Half-Frame Buffer Image Buffer Ink/Cursor Buffer Half-Frame Buffer 17FFFFh 180000h Ink/Cursor Buffer 1FFFFFh Half-Frame Buffer Figure 9-1 Display Buffer Addressing S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-101 9: DISPLAY BUFFER 9.1 Image Buffer The image buffer contains the formatted display mode data - see "Display Mode Data Formats". The displayed image(s) could take up only a portion of this space; the remaining area may be used for multiple images - possibly for animation or general storage. See "Display Configuration" on page 1-103 for the relationship between the image buffer and the display. 9.2 Ink/Cursor Buffers The Ink/Cursor buffers contain formatted image data for the Ink or Cursor. There may be several Ink/Cursor images stored in the display buffer but only one may be active at any given time. See "Ink/Cursor Architecture" on page 1-113 for details. 9.3 Half Frame Buffer In dual panel mode, with the half frame buffer enabled, the top of the display buffer is allocated to the half-frame buffer. The size of the half frame buffer is a function of the panel resolution and whether the panel is color or monochrome type: Half Frame Buffer Size (in bytes) = (panel width x panel length) * factor / 16 where factor = 4 for color panel = 1 for monochrome panel For example, for a 640 x 480 color panel the half frame buffer size is 75K bytes. In a 512K byte display buffer, the half-frame buffer resides from 6D400h to 7FFFFh. In a 2M byte display buffer, the half-frame buffer resides from 1ED400h to 1FFFFFh. 1-102 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 10: DISPLAY CONFIGURATION 10 DISPLAY CONFIGURATION 10.1 Display Mode Data Format The following diagrams show the display mode data formats for a little-endian system. 1-bpp: Byte 0 bit 7 A0 bit 0 A1 A2 A3 A4 A5 A6 P0P1P2P3P4P5P6P7 A7 Pn = (An) Panel Display Host Address 2-bpp: Display Memory bit 7 bit 0 Byte 0 A0 B0 A1 B1 A2 B2 A3 B3 Byte 1 A4 B4 A5 B5 A6 B6 A7 B7 P0P1P2P3P4P5P6P7 Pn = (An, Bn) Panel Display Host Address Display Memory 4-bpp: bit 7 bit 0 Byte 0 A0 B0 C0 D0 A1 B1 C1 D1 Byte 1 A2 B2 C2 D2 A3 B3 C3 D3 Byte 2 A4 B4 C4 D4 A5 B5 C5 D5 P0P1P2P3P4P5P6P7 Pn = (An, Bn, Cn, Dn) Panel Display Host Address Display Memory 8-bpp: 3-3-2 RGB bit 7 bit 0 Byte 0 A0 B0 C0 D0 E0 F0 G0 H0 Byte 1 A1 B1 C1 D1 E1 F1 G1 H1 Byte 2 A2 B2 C2 D2 E2 F2 G2 H2 P0P1P2P3P4P5P6P7 Pn = (Rn2-0, Gn2-0, Bn1-0) Panel Display Host Address Display Memory Figure 10-1 1/2/4/8 Bit-Per-Pixel Format Memory Organization S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-103 10: DISPLAY CONFIGURATION 15-bpp: P0P1P2P3P4P5P6P7 5-5-5 RGB bit 7 bit 0 Byte 0 G02 G01 G00 B04 B03 B02 B01 B00 Byte 1 R04 R03 R02 R01 R00 G04 G03 Byte 2 G12 G11 G10 B14 B13 B12 B11 B10 Byte 3 R14 R13 R12 R11 R10 G14 G13 Pn = (Rn4-0, Gn4-0, Bn4-0) Panel Display Display Memory Host Address 16-bpp: 5-6-5 RGB bit 7 P0P1P2P3P4P5P6P7 bit 0 Byte 0 G02 G01 G00 B04 B03 B02 B01 B00 Byte 1 R04 R03 R02 R01 R00 G05 G04 G03 Byte 2 G12 G11 G10 B14 B13 B12 B11 B10 Byte 3 R14 R13 R12 R11 R10 G15 G14 G13 Pn = (Rn4-0, Gn5-0, Bn4-0) Host Address Panel Display Display Memory Figure 10-2 15/16 Bit-Per-Pixel Format Memory Organization Notes: 1. The Host-to-Display mapping shown here is for a little-endian system. 2. For 15/16 bpp formats, Rn, Gn, Bn represent the red, green, and blue color components. 1-104 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 10: DISPLAY CONFIGURATION 10.2 Image Manipulation The figure below shows how Screen 1 and 2 images are stored in the image buffer and positioned on the display. Screen 1 and Screen 2 can be parts of a larger virtual image or images. * (REG[17h],REG[16h]) defines the width of the virtual image(s). * (REG[12h],REG[11h],REG[10]) defines the starting word of the Screen 1, (REG[15h],REG[14h],REG[13]) defines the starting word of the Screen 2. * REG[18h] bits [3:0] define the starting pixel within the starting word for Screen 1, REG[18h] bits [7:4] define the starting pixel within the starting word for Screen 2. * (REG[0Fh],REG[0Eh]) define the last line of Screen 1, the remainder of the display is taken up by Screen 2. Image Buffer Display (REG[12h], REG[11h], REG[10h]) REG[18h] bits [3:0] ((REG[09h], REG[08h])+1) lines Screen 1 Line 0 Line 1 Screen 1 (REG[15h], REG[14h], REG[13h]) Line (REG[0Fh], REG[0Eh]) REG[18h] bits [7:4] Screen 2 Screen 2 ((REG[04h]+1)*8) pixels (REG[17h], REG[16h]) Figure 10-3 Image Manipulation S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-105 11: LOOK-UP TABLE ARCHITECTURE 11 LOOK-UP TABLE ARCHITECTURE The following figures are intended to show the display data output path only. 11.1 Monochrome Modes The green Look-Up Table (LUT) is used for all monochrome modes. 1 Bit-Per-Pixel Monochrome Mode Green Look-Up Table 256x4 00 01 0 1 4-bit Grey Data FC FD FE FF 1 bit-per-pixel data from Image Buffer Figure 11-1 1 Bit-per-pixel Monochrome Mode Data Output Path 2 Bit-Per-Pixel Monochrome Mode Green Look-Up Table 256x4 00 01 02 03 00 01 10 11 4-bit Grey Data FC FD FE FF 2 bit-per-pixel data from Image Buffer Figure 11-2 2 Bit-per-pixel Monochrome Mode Data Output Path 1-106 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 11: LOOK-UP TABLE ARCHITECTURE 4 Bit-Per-Pixel Monochrome Mode Green Look-Up Table 256x4 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 4-bit Grey Data FC FD FE FF 4 bit-per-pixel data from Image Buffer Figure 11-3 4 Bit-per-pixel Monochrome Mode Data Output Path S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-107 11: LOOK-UP TABLE ARCHITECTURE 11.2 Color Display Modes 1 Bit-Per-Pixel Color Mode Red Look-Up Table 256x4 00 01 0 1 4-bit Red Data FC FD FE FF Green Look-Up Table 256x4 00 01 0 1 4-bit Green Data FC FD FE FF Blue Look-Up Table 256x4 00 01 0 1 4-bit Blue Data FC FD FE FF 1 bit-per-pixel data from Image Buffer Figure 11-4 1 Bit-per-pixel Color Mode Data Output Path 1-108 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 11: LOOK-UP TABLE ARCHITECTURE 2 Bit-Per-Pixel Color Mode Red Look-Up Table 256x4 00 01 02 03 00 01 10 11 4-bit Red Data FC FD FE FF Green Look-Up Table 256x4 00 01 02 03 00 01 10 11 4-bit Green Data FC FD FE FF Blue Look-Up Table 256x4 00 01 02 03 00 01 10 11 4-bit Blue Data FC FD FE FF 2 bit-per-pixel data from Image Buffer Figure 11-5 2 Bit-per-pixel Color Mode Data Output Path S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-109 11: LOOK-UP TABLE ARCHITECTURE 4 Bit-Per-Pixel Color Mode Red Look-Up Table 256x4 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 4-bit Red Data FC FD FE FF Green Look-Up Table 256x4 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 4-bit Green Data FC FD FE FF Blue Look-Up Table 256x4 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 4-bit Blue Data FC FD FE FF 4 bit-per-pixel data from Image Buffer Figure 11-6 4 Bit-per-pixel Color Mode Data Output Path 1-110 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 11: LOOK-UP TABLE ARCHITECTURE 8 Bit-Per-Pixel Color Mode Red Look-Up Table 256x4 00 01 02 03 04 05 06 07 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 4-bit Red Data 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111 F8 F9 FA FB FC FD FE FF Green Look-Up Table 256x4 00 01 02 03 04 05 06 07 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 4-bit Green Data 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111 F8 F9 FA FB FC FD FE FF Blue Look-Up Table 256x4 00 01 02 03 04 05 06 07 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 4-bit Blue Data 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111 F8 F9 FA FB FC FD FE FF 8 bit-per-pixel data from Image Buffer Figure 11-7 8 Bit-per-pixel Color Mode Data Output Path S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-111 11: LOOK-UP TABLE ARCHITECTURE 15/16 Bit-Per-Pixel Color Modes The LUT is bypassed and the color data is directly mapped for this color mode - See "Display Configuration" on page 1-103. 1-112 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 12: INK/CURSOR ARCHITECTURE 12 INK/CURSOR ARCHITECTURE 12.1 Ink/Cursor Buffers The Ink/Cursor buffers contain formatted image data for the Ink Layer or Hardware Cursor. There may be several Ink/Cursor images stored in the display buffer but only one may be active at any given time. The active Ink/Cursor buffer is selected by the Ink/Cursor Start Address register (REG[30h]). This register defines the start address for the active Ink/Cursor buffer. The Ink/Cursor buffer must be positioned where it does not conflict with the image buffer and half-frame buffer. The start address for the Ink/Cursor buffer is programmed as shown in the following table: Table 12-1 Ink/Cursor Data Format Ink/Cursor Start Address Bits [7:0] Start Address (Bytes) 0 Display Buffer Size - 1024 n = 255...1 Display Buffer Size - (n x 8192) Comments This default value is suitable for a cursor when there is no half-frame buffer. These positions can be used to: * position an Ink buffer at the top of the display buffer; * position an Ink buffer between the image and halfframe buffers; * position a Cursor buffer between the image and halfframe buffers; * select from a multiple of Cursor buffers. The Ink/Cursor image is stored contiguously. The address offset from the starting word of line n to the starting word of line n+1 is calculated as follows: Ink Address Offset (words) = REG[04h] + 1 Cursor Address Offset (words) = 8 12.2 Ink/Cursor Data Format The Ink/Cursor image is always 2 bit-per-pixel. The following diagram shows the Ink/Cursor data format for a little-endian system. 2 bpp: bit 7 bit 0 Byte 0 A0 B0 A1 B1 A2 B2 A3 B3 Byte 1 A4 B4 A5 B5 A6 B6 A7 B7 P0 P1 P2 P3 P4 P5 P6 P7 Pn = (An, Bn) Panel Display Host Address Ink/Cursor Buffer Figure 12-1 Ink/Cursor Data Format The image data for pixel n, (An, Bn), selects the color for pixel n as follows: Table 12-2 Ink/Cursor Color Select (An, Bn) 00 01 10 11 Color Color 0 Color 1 Background Inverted Background S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) Comments Ink/Cursor Color 0 Register, (REG[2Dh], REG[2Ch]) Ink/Cursor Color 1 Register, (REG[2Fh], REG[2Eh]) Ink/Cursor is transparent - show background Ink/Cursor is transparent - show inverted background EPSON 1-113 12: INK/CURSOR ARCHITECTURE 12.3 Ink/Cursor Image Manipulation Ink Image The Ink image should always start at the top left pixel, i.e. Cursor X Position and Cursor Y Position registers should always be set to zero. The width and height of the ink image are automatically calculated to completely cover the display. Cursor Image The Cursor image size is always 64x64 pixels. The Cursor X Position and Cursor Y Position registers specify the position of the top left pixel. The following diagram shows how to position a cursor. P(0;0) P(x;y) P(x+63;y) P(x;y+63) P(x+63;y+63) Figure 12-2 Cursor Positioning where x = (REG[29h] bits [1:0], REG[28h]) y = (REG[2Bh] bits [1:0], REG[2Ah]) REG[29h] bit 7 = 0 REG[2Bh] bit 7 = 0 Note: There is no means to set a negative cursor position. If a cursor must be set to a negative position, this must be dealt with through software. 1-114 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 13: SWIVELVIEWTM 13 SWIVELVIEWTM 13.1 Concept Computer displays are refreshed in landscape - from left to right and top to bottom; computer images are stored in the same manner. When a display is used in SwivelViewTM it becomes necessary to rotate the display buffer image by 90. The S1D13505 supports SwivelViewTM by rotating the image 90 clockwise as it is written to the display buffer. The rotation is done in hardware and is transparent to the programmer for all display buffer reads and writes. SwivelViewTM uses a 1024 x 1024 pixel virtual image. The following figures show how the programmer sees the image and how the image is actually stored in the display buffer. The display is refreshed in the following sense: C-A-D-B. The application image is written to the S1D13505 in the following sense: A-B-C-D. The S1D13505 rotates and stores the application image in the following sense: C-A-D-B, the same sense as display refresh. 1024 pixels B portrait window H B D W 1024 pixels display start address portrait window A C A 1024 pixels W D C H image in display buffer image seen by programmer Figure 13-1 Relationship Between the Screen Image and the Image Residing in the Display Buffer Note: The image must be written with a 1024 pixel offset between adjacent lines (e.g. 1024 bytes for 8 bpp mode or 2048 bytes for 16 bpp mode) and a display start address that is non-zero. S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-115 13: SWIVELVIEWTM 13.2 Image Manipulation in SwivelViewTM Display Start Address It can be seen from Figure 13-1 that the top left pixel of the display is not at the top left corner of the virtual image, i.e. it is non-zero. The Display Start Address register must be set accordingly: Display Start Address (words) = (1024 - W) for 16 bpp mode = (1024 - W) / 2 for 8 bpp mode Memory Address Offset The Memory Address Offset register must be set for a 1024 pixel offset: Memory Address Offset (words) = 1024 for 16 bpp mode = 512 for 8 bpp mode Horizontal Panning Horizontal panning is achieved by changing the start address. Panning of the portrait window to the right by 1 pixel is achieved by adding 1024 pixels to the Display Start Address register (or subtracting if panning to the left). * Panning to right by 1 pixel: add current start address by 1024 (16 bpp mode) or 512 (8 bpp mode). * Panning to left by 1 pixel: subtract current start address by 1024 (16 bpp mode) or 512 (8 bpp mode). How far the portrait window can be panned to the right is limited not only by 1024 pixels but also by the amount of physical memory installed. Vertical Scrolling Vertical scrolling is achieved by changing the Display Start Address register and/or changing the Pixel Panning register. * Increment/decrement Display Start Address register in 8 bpp mode: scroll down/up by 2 lines. * Increment/decrement Display Start Address register in 16 bpp mode: scroll down/up by 1 line. * Increment/decrement Pixel Panning register in 8 bpp or 16 bpp mode: scroll down/up by 1 line. 1-116 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 13: SWIVELVIEWTM 13.3 Physical Memory Requirement Because the programmer must now deal with a virtual display, the amount of image buffer required for a particular display mode has increased. The minimum amount of image buffer required is: Minimum Required Image Buffer (bytes) = (1024 x H) x 2 for 16 bpp mode = (1024 x H) for 8 bpp mode For single panel, the required display buffer size is the same as the image buffer required. For dual panel, the display buffer required is the sum of the image buffer required and the half-frame buffer memory required. The half-frame buffer memory requirement is: Half-Frame Buffer Memory (bytes) = (W x H) / 4 for color mode = (W x H) / 16 for monochrome mode The half-frame buffer memory is always located at the top of the physical memory. For simplicity the hardware cursor and ink layer memory requirement is ignored. The hardware cursor and ink layer memory must be located at 16K byte boundaries and it must not overlap the image buffer and half-frame buffer memory areas. Even though the virtual display is 1024x1024 pixels, the actual panel window is always smaller. Thus it is possible for the display buffer size to be smaller than the virtual display but large enough to fit both the required image buffer and the half-frame buffer memory. This poses a maximum "accessible" horizontal virtual size limit. Maximum Accessible Horizontal Virtual Size (pixels) = (Physical Memory - Half-Frame Buffer Memory) / 2048 for 16 bpp mode = (Physical Memory - Half-Frame Buffer Memory) / 1024 for 8 bpp mode For example, a 640x480 single panel running 8 bpp mode requires 480K byte of image buffer and 0K byte of half-frame buffer memory. The virtual display size is 1024x1024 = 1M byte. The programmer may use a 512K byte DRAM which is smaller than the 1M byte virtual display but greater than the 480K byte minimum required image buffer. The maximum accessible horizontal virtual size is = (512K byte - 0K byte) / 1024 = 512. The programmer therefore has room to pan the portrait window to the right by 512 - 480 = 32 pixels. The programmer also should not read/write to the memory beyond the maximum accessible horizontal virtual size because that memory is either reserved for the half-frame buffer or not associated with any real memory at all. The following table summarizes the DRAM size requirement for SwivelViewTM using different panel sizes and display modes. Note that DRAM size for the S1D13505 is limited to either 512K byte or 2M byte. The calculation is based on the minimum required image buffer size. The calculated minimum display buffer size is based on the image buffer and the half-frame buffer only; it does not take into account the hardware cursor/ink layer and so it may or may not be sufficient to support it - this is noted in the table. The hardware cursor requires 1K byte of memory and the 2-bit ink layer requires (W x H) / 4 bytes of memory; both must reside at 16K byte boundaries but only one is supported at a time. The table shows only one possible sprite/ink layer location - at the highest possible 16K byte boundary below the half-frame buffer which is always at the top. S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-117 13: SWIVELVIEWTM Panel Size 320 x 240 640 x 480 800 x 600 Table 13-1 Minimum DRAM Size Required for SwivleViewTM Sprite/Ink Display Display Half-Frame Minimum Ink/Cursor Layer Panel Type Layer Buffer Mode Buffer Size Buffer Size DRAM Size Location Size Single Color 8 bpp 240KB 0KB 512KB 1KB/18.75KB 496KB/480KB 16 bpp 480KB Mono 8 bpp 240KB 16 bpp 480KB Dual Color 8 bpp 240KB 18.75KB 480KB/464KB 16 bpp 480KB 480KB/-Mono 8 bpp 240KB 4.69KB 496KB/480KB 16 bpp 480KB Single Color 8 bpp 480KB 0KB 1KB/75KB 496KB/-16 bpp 960KB 2MB 2032KB/1968KB Mono 8 bpp 480KB 512KB 496KB/-16 bpp 960KB 2MB 2032K/1968K Dual Color 8 bpp 480KB 75KB 16 bpp 960KB Mono 8 bpp 480KB 18.75KB 512KB 496KB/-16 bpp 960KB 2MB 2032KB/1968KB Single Color 8 bpp 600KB 0KB 1KB/ 2032KB/1920KB 16 bpp 1.2MB 117.19KB Mono 8 bpp 600KB 16 bpp 1.2MB Dual Color 8 bpp 600KB 117.19KB 16 bpp 1.2MB Mono 8 bpp 600KB 29.30KB 16 bpp 1.2MB Where KB = K bytes and MB = 1024K bytes 13.4 Limitations The following limitations apply to SwivelViewTM: * Only 8 bpp and 16 bpp modes are supported - 1/2/4 bpp modes are not supported. * Hardware cursor and ink layer images are not rotated - software rotation must be used. SwivelViewTM must be turned off when the programmer is accessing the sprite or the ink layer. * Split screen images appear side-by-side, i.e. the portrait display is split vertically. * Pixel panning works vertically. 1-118 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 14: CLOCKING 14 CLOCKING 14.1 Maximum MCLK: PCLK Ratios Ink Table 14-1 Maximum PCLK Frequency with EDO-DRAM Maximum PCLK Allowed Display Type NRC 1 bpp 2 bpp 4 bpp 8 bpp * Single Panel. * CRT. * Dual Monochrome/Color Panel with Half Frame Buffer Disabled. * Simultaneous CRT + Single Panel. * Simultaneous CRT + Dual Monochrome/Color Panel with Half Frame Buffer Disabled. off * Dual Monochrome Panel with Half Frame Buffer Enabled. * Simultaneous CRT + Dual Monochrome Panel with Half Frame Buffer Enable. * Dual Color Panel with Half Frame Buffer Enabled. * Simultaneous CRT + Dual Color Panel with Half Frame Buffer Enable. * Single Panel. * CRT. * Dual Monochrome/Color Panel with Half Frame Buffer Disabled. * Simultaneous CRT + Single Panel. * Simultaneous CRT + Dual Monochrome/Color Panel with Half Frame Buffer Disabled. on * Dual Monochrome Panel with Half Frame Buffer Enabled. * Simultaneous CRT + Dual Monochrome Panel with Half Frame Buffer Enable. * Dual Color Panel with Half Frame Buffer Enabled. * Simultaneous CRT + Dual Color Panel with Half Frame Buffer Enable. S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 16 bpp 5, 4, 3 MCLK 5 4 MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/3 MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/3 EPSON 3 MCLK MCLK MCLK/2 MCLK/2 MCLK/2 5 4 3 5 4 MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/2 3 MCLK MCLK MCLK MCLK/3 MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/3 MCLK/3 MCLK/3 MCLK/3 MCLK/2 MCLK/2 MCLK/2 5 4 MCLK/2 MCLK/3 MCLK/3 MCLK/3 MCLK/3 MCLK/2 MCLK/2 MCLK/2 MCLK/3 MCLK/3 3 MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/3 5 4 3 MCLK/3 MCLK/3 MCLK/3 MCLK/3 MCLK/4 MCLK/2 MCLK/2 MCLK/3 MCLK/3 MCLK/3 MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/3 1-119 14: CLOCKING Table 14-2 Maximum PCLK Frequency with FPM-DRAM Maximum PCLK Allowed Display Type NRC 1 bpp 2 bpp 4 bpp 8 bpp Ink * Single Panel. * CRT. * Dual Monochrome/Color Panel with Half Frame Buffer Disabled. * Simultaneous CRT + Single Panel. * Simultaneous CRT + Dual Monochrome/Color Panel off with Half Frame Buffer Disabled. * Dual Monochrome with Half Frame Buffer Enabled. * Simultaneous CRT + Dual Monochrome Panel with Half Frame Buffer Enable. * Dual Color with Half Frame Buffer Enabled. * Simultaneous CRT + Dual Color Panel with Half Frame Buffer Enable. * Single Panel. * CRT. * Dual Monochrome/Color Panel with Half Frame Buffer Disabled. * Simultaneous CRT + Single Panel. * Simultaneous CRT + Dual Monochrome/Color Panel on with Half Frame Buffer Disabled. * Dual Monochrome with Half Frame Buffer Enabled. * Simultaneous CRT + Dual Monochrome Panel with Half Frame Buffer Enable. * Dual Color with Half Frame Buffer Enabled. * Simultaneous CRT + Dual Color Panel with Half Frame Buffer Enable. 5, 4, 3 16 bpp MCLK 5 4 3 5 4 3 5 4 MCLK/2 MCLK/2 MCLK MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK MCLK/2 MCLK/2 MCLK MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK MCLK/2 MCLK/2 MCLK MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/2 3 MCLK MCLK MCLK 5 4 3 5 4 3 MCLK/2 MCLK/2 MCLK/2 MCLK/3 MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/3 MCLK/2 MCLK/2 MCLK/3 MCLK/2 MCLK/2 MCLK/3 MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/3 MCLK/2 MCLK/2 MCLK/3 MCLK/3 MCLK/2 MCLK/3 MCLK/2 MCLK/2 MCLK/2 MCLK/3 MCLK/2 MCLK/2 MCLK/3 MCLK/3 MCLK/2 MCLK/3 MCLK/3 MCLK/3 MCLK/4 MCLK/3 MCLK/3 14.2 Frame Rate Calculation The frame rate is calculated using the following formula: PCLKmax FrameRate = ------------------------------------------------------------------------------------------( HDP + HNDP ) x ( VDP + VNDP ) Where: 1-120 VDP VNDP = Vertical Display Period = Vertical Non-Display Period HDP HNDP = Horizontal Display Period = Horizontal Non-Display Period Ts = Pixel Clock EPSON = REG[09h] bits [1:0], REG[08h] bits [7:0] + 1 = REG[0Ah] bits [5:0] + 1 = in table below = ((REG[04h] bits [6:0]) + 1) * 8Ts = ((REG[05h] bits [4:0]) + 1) * 8Ts = given in table below = PCLK S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 14: CLOCKING Table 14-3 Example Frame Rates with Ink Disabled DRAM Type1 (Speed Grade) Display * Single Panel. * CRT. * Dual Monochrome/Color Panel with Half Frame Buffer Disabled.5 50ns * Simultaneous CRT + Single Panel. EDO-DRAM * Simultaneous CRT + Dual Monochrome/Color Panel with Half MClk = 40MHz Frame Buffer Disabled.5 NRC = 4 NRP = 1.5 NRCD = 2 * Dual Color with Half Frame Buffer * * * * 60ns EDO-DRAM * * Enabled. Dual Mono with Half Frame Buffer Enabled. Single Panel. CRT. Dual Mono/Color Panel with Half Frame Buffer Disabled.5 Simultaneous CRT + Single Panel. Simultaneous CRT + Dual Mono/ Color Panel with Half Frame Buffer Disabled.5 MClk = 33MHz NRC = 4 NRP = 1.5 NRCD = 2 * Dual Color with Half Frame Buffer Enabled. * Dual Mono with Half Frame Buffer Enabled. * Single Panel. * CRT. * Dual Mono/Color Panel with Half Frame Buffer Disabled.5 * Simultaneous CRT + Single Panel. 60ns * Simultaneous CRT + Dual Mono/ Color Panel with Half Frame Buffer FPM-DRAM Disabled.5 MClk = 25MHz NRC = 4 * Dual Mono with Half Frame Buffer NRP = 1.5 Enabled. NRCD = 2 * Dual Color with Half Frame Buffer Enabled. Resolution 800x6002 640x480 640x240 480x320 320x240 800x6002,3 640x480 800x6002 640x480 640x240 480x320 320x240 800x6002,3 640x480 800x6002 640x480 640x240 480x320 320x240 800x6002 640x480 640x400 800x6002,3 640x480 Color Maximum Minimum Depth Pixel Clock Panel (bpp) (MHz) HNDP(Ts) 1/2/4/8 32 16 56 1/2/4/8 32 16 56 1/2/4/8 32 40 16 56 1/2/4/8 32 16 56 1/2/4/8 32 16 56 1/2/4/8 20 32 16 13.3 32 1/2/4/8 20 32 16 13.3 32 1/2/4/8 32 16 56 1/2/4/8 32 16 56 1/2/4/8 32 33 16 56 1/2/4/8 32 16 56 1/2/4/8 32 16 56 1/2/4/8 16.5 32 16 11 32 1/2/4/8 16.5 32 16 11 32 1/2/4/8 32 16 56 1/2/4/8 32 16 56 1/2/4/8 32 25 16 56 1/2/4/8 32 16 56 1/2/4/8 32 16 56 1/2/4/8/16 12.5 32 1/2/4/8/16 12.5 32 1/2/4/8/16 12.5 32 1/2/4/8 12.5 32 16 8.33 32 1/2/4/8 12.5 32 16 8.33 32 Maximum Frame Rate (Hz) CRT Panel4 80 60 78 60 123 85 119 85 247 242 243 232 471 441 80 53 123 82 66 55 65 55 101 78 98 78 203 200 200 196 388 380 66 43 103 68 50 48 77 60 75 60 142 136 152 145 294 280 50 77 92 50 33 77 51 - 1. Must set NRC = 4MCLK. See REG[22h], Performance Enhancement Register. 2. 800x600 @ 16 bpp requires 2M bytes of display buffer for all display types. 3. 800x600 @ 8 bpp on a dual color panel requires 2M bytes of display buffer if the half frame buffer is enabled. S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-121 14: CLOCKING 4. Optimum frame rates for panels range from 60Hz to 150Hz. If the maximum refresh rate is too high for a panel, MCLK should be reduced or PCLK should be divided down. 5. Half Frame Buffer disabled by REG[1Bh] bit 0. 6. When setting a horizontal resolution greater than 767 pixels, with a color depth of 15/16 bpp, the Memory Offset Registers (REG[16h], REG[17h]) must be set to a virtual horizontal pixel resolution of 1024. 14.3 Bandwidth Calculation When calculating the average bandwidth, there are two periods that must be calculated separately. The first period is the time when the CPU is in competition with the display refresh fetches. The CPU can only access the memory when the display refresh releases the memory controller. The CPU bandwidth during this period is called the "bandwidth during display period". The second period is the time when the CPU has full access to the memory, with no competition from the display refresh. The CPU bandwidth during this period is called the "bandwidth during non display period." To calculate the average bandwidth, calculate the percentage of time between display period and non display period. The percentage of display period is multiplied with the bandwidth during display period. The percentage of non display period is multiplied with the bandwidth during non display period. The two products are summed to provide the average bandwidth. Bandwidth during non display period Based on simulation, it requires a minimum of 12 MCLKs to service one, two byte, CPU access to memory. This includes all the internal handshaking and assumes that NRC is set to 4MCLKs and the wait state bits are set to 10b. Bandwidth during non display period = f(MCLK) / 6 Mb/s Bandwidth during display period The amount of time taken up by display refresh fetches is a function of the color depth, and the display type. Below is a table of the number of MCLKs required for various memory fetches to display 16 pixels. Assuming NRC = 4MCLKs. Table 14-4 Number of MCLKs Required for Various Memory Access Memory Access Number of MCLKs Half Frame Buffer, monochrome 7 Half Frame Buffer, color 11 Display @ 1 bpp 4 Display @ 2 bpp 5 Display @ 4 bpp 7 Display @ 8 bpp 11 Display @ 16 bpp 19 CPU 4 1-122 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 14: CLOCKING Table 14-5 Total # MCLKs Taken for Display Refresh MCLKs for Display Refresh Display 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp * * * * * Single Panel. CRT. Dual Monochrome/Color Panel with Half Frame Buffer Disabled. Simultaneous CRT + Single Panel. Simultaneous CRT + Dual Monochrome/Color Panel with Half Frame Buffer Disabled. * Dual Monochrome Panel with Half Frame Buffer Enabled. * Simultaneous CRT + Dual Monochrome Panel with Half Frame Buffer Enable. * Dual Color Panel with Half Frame Buffer Enabled. 4 5 7 11 19 11 12 14 18 26 15 16 18 22 30 Bandwidth during display period = MIN (bandwidth during non display period, B/C/D) where B = number of MCLKs left available for CPU access after every 16 pixels drawn = (f(MCLK)/f(PCLK) * 16 - Total MCLK for Display refresh), units in MCLKs 16 pixels where C = number of MCLKs required to service 1 CPU access (2 bytes of data) = 4, units in MCLKs/2 bytes where D = time to draw 16 pixels = 16 / f(PCLK), units in 16 pixels The minimum function limits the bandwidth to the bandwidth available during non display period should the display fetches constitute a small percentage of the overall memory activity. For 16 bpp single panel/CRT/dual panel with half frame buffer disable, the number of MCLKs required to fetch 16 pixels when PCLK = MCLK exceeds 16. In this case, the display fetch does not allow any CPU access during the display period. CPU access can only be achieved during non display periods. Average Bandwidth All displays have a horizontal non display period, and a vertical non display period. The formula for calculating the percentage of non display period is as follows Percentage of non display period = (HTOT * VTOT - WIDTH * HEIGHT)/(HTOT * VTOT) Percentage of non display period for CRT = (800*525 - 640*480)/(800*525) = 26.6% Percentage of non display period for single panel = (680*482 - 640*480)/680*482) = 6.2% Percentage of non display period for dual panel = (680*242 - 640*240)/680*242) = 6.6% Average Bandwidth = Percentage of non display period * Bandwidth during non display period + (1- Percentage of non display period) * Bandwidth during display period S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-123 14: CLOCKING Table 14-6 Theoretical Maximum Bandwidth M byte/sec, Cursor/Ink Disabled DRAM Type1 (Speed Grade) Max. Pixel Clock (MHz) 640x480 Display CRT. Simultaneous CRT + Single Panel. Simultaneous CRT + Dual Monochrome/Color Panel with Half Frame Buffer Disabled. Single Panel. Dual Monochrome/Color Panel with Half 50ns Frame Buffer Disabled. EDO-DRAM Dual Monochrome Panel with Half Frame MCLK = 40MHz Buffer Enabled. Simultaneous CRT + Dual Mono Panel with Half Frame Buffer Enable. Dual Color Panel with Half Frame Buffer Enabled. CRT. Simultaneous CRT + Single Panel. Simultaneous CRT + Dual Monochrome/Color Panel with Half Frame Buffer Disabled. Single Panel. Dual Monochrome/Color Panel with Half 60ns Frame Buffer Disabled. EDO-DRAM Dual Monochrome Panel with Half Frame MCLK = 33MHz Buffer Enabled. Simultaneous CRT + Dual Monochrome Panel with Half Frame Buffer Enable. Dual Color Panel with Half Frame Buffer Enabled. CRT. Simultaneous CRT + Single Panel. Simultaneous CRT + Dual Monochrome/Color Panel with Half Frame Buffer Disabled. Single Panel. Dual Monochrome/Color Panel with Half 60ns Frame Buffer Disabled. FPM-DRAM Dual Monochrome with Half Frame Buffer MCLK = 25MHz Enabled. Simultaneous CRT + Dual Monochrome Panel with Half Frame Buffer Enable. Dual Color Panel with Half Frame Buffer Enabled. 1-124 EPSON Maximum Bandwidth (M byte/sec) 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp 40 6.67 6.67 6.67 6.36 1.79 40 6.67 6.67 6.60 6.27 0.41 20 6.67 6.67 6.67 6.67 6.67 40 20 13.3 6.27 6.67 6.67 5.11 6.67 6.67 6.67 6.67 6.67 6.67 3.94 6.67 40 6.36 5.44 - - - 20 13.3 6.67 6.67 6.67 6.67 6.27 6.67 6.27 6.67 6.67 33 5.5 5.5 5.5 5.24 1.47 33 5.5 5.5 5.5 5.17 0.34 16.5 5.5 5.5 5.5 5.5 5.5 33 16.5 11 5.17 5.5 5.5 4.21 5.5 5.5 5.5 5.5 5.5 5.5 3.25 5.5 33 5.24 4.49 - - - 16.5 11 5.5 5.5 5.5 5.5 5.5 5.5 5.17 5.5 5.5 25 4.16 4.16 4.16 3.97 1.11 25 4.16 4.16 4.16 3.92 0.26 12.5 4.16 4.16 4.16 4.16 4.16 25 12.5 8.3 3.92 4.16 4.16 3.19 4.16 4.16 4.16 4.16 4.16 4.16 2.46 4.16 25 3.97 3.40 - - - 12.5 8.33 4.16 4.16 4.16 4.16 4.16 4.16 3.92 4.16 4.16 S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) 15: POWER SAVE MODES 15 POWER SAVE MODES Three power save modes are incorporated into the S1D13505 to meet the important need for power reduction in the hand-held device market. Function Display Active? Register Access Possible? Memory Access Possible? LUT Access Possible? Pins LCD outputs LCDPWR DRAM outputs CRT/DAC outputs Host Interface outputs Table 15-1 Power Save Mode Function Summary Power Save Mode (PSM) No Display Normal LCD Enable = 0 Software Suspend Hardware Suspend (Active) CRT Enable = 0 Yes No No No Yes Yes Yes No Yes Yes No No Yes Yes Yes No Table 15-2 Pin States in Power-Save Modes Pin State No Display Normal LCD Enable = 0 Software Suspend Hardware Suspend (Active) CRT Enable = 0 Active Forced Low2 Forced Low2 Forced Low2 (LCD Enable = 1) On Off Off Off (LCD Enable = 1) Active CBR Refresh only Refresh only1 Refresh only1 Active Disabled Disabled Disabled (CRT Enable = 1) Active Active Active Disabled 1. Refresh method is selectable by REG[1Ah]. Supported methods are CBR refresh, self-refresh or no refresh at all. 2. The FPFRAME and FPLINE signals are set to their inactive states during power-down. The inactive states are determined by REG[07h] bit 6 and REG[0Ch] bit 6. A problem may occur if the inactive state is high (typical TFT/D-TFD configuration) and power is removed from the LCD panel. For software suspend the problem can be solved in the following manner. At power-down, first enable software suspend, then wait ~120 VNDP, and lastly reverse the polarity bits. At power-up, first disable software suspend, then revert the polarity bits back to the configuration state. For hardware suspend an external hardware solution would be to use an AND gate on the sync signal. One input of the AND gate is connected to a sync signal, the other input would be tied to the panel's logic power supply. When the panel's logic power supply is removed, the sync signal is forced low. S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) EPSON 1-125 16: MECHANICAL DATA 16 MECHANICAL DATA 128-pin QFP15 surface mount package 16.0 0.4 14.0 0.1 96 65 97 16.0 0.4 14.0 0.1 64 Index 128 33 32 0.16 0.1 0.4 1.4 0.1 0.125 0.1 1 0~10 0.1 0.5 0.2 1.0 Figure 16-1 Mechanical Drawing QFP15 1-126 EPSON S1D13505F00A HARDWARE FUNCTIONAL SPECIFICATION (X23A-A-001-12) ll er ro t n A Co 0 0 T F R 5 0 /C 5 CD 3 1 L D AC 1 S D M A ed Em b d d e R es t No g in es m pl m ra am g o x Pr nd E a CONTENTS Contents Table of Contents 1 INTRODUCTION ............................................................................................................................ 1 2 INITIALIZATION............................................................................................................................. 2 2.1 Miscellaneous................................................................................................................................... 4 3 MEMORY MODELS ....................................................................................................................... 5 3.1 Display Buffer Location .................................................................................................................... 5 Memory Organization for One Bit-Per-Pixel (2 Colors/Gray Shades) ........................................... 5 Memory Organization for Two Bit-Per-Pixel (4 Colors/Gray Shades) ........................................... 5 Memory Organization for Four Bit-Per-Pixel (16 Colors/Gray Shades) ........................................ 6 Memory Organization for Eight Bit-Per-Pixel (256 Colors/16 Gray Shades)................................. 6 Memory Organization for Fifteen Bit-Per-Pixel (32768 Colors/16 Gray Shades).......................... 7 Memory Organization for Sixteen Bit-Per-Pixel (65536 Colors/16 Gray Shades)......................... 7 4 LOOK-UP TABLE (LUT) .............................................................................................................. 8 4.1 Look-Up Table Registers.................................................................................................................. 8 4.2 Look-Up Table Organization ............................................................................................................ 9 5 ADVANCED TECHNIQUES ............................................................................................................ 15 5.1 Virtual Display ................................................................................................................................ 15 Registers ..................................................................................................................................... 16 Examples .................................................................................................................................... 16 5.2 Panning and Scrolling .................................................................................................................... 17 Registers ..................................................................................................................................... 18 Examples .................................................................................................................................... 19 5.3 Split Screen .................................................................................................................................... 20 Registers ..................................................................................................................................... 20 Examples .................................................................................................................................... 21 6 LCD POWER SEQUENCING AND POWER SAVE MODES ................................................................. 22 6.1 Introduction to LCD Power Sequencing ......................................................................................... 22 6.2 Registers ........................................................................................................................................ 22 6.3 LCD Enable/Disable ....................................................................................................................... 23 7 HARDWARE CURSOR ................................................................................................................. 24 7.1 Introduction..................................................................................................................................... 24 7.2 Registers ........................................................................................................................................ 24 7.3 Limitations ...................................................................................................................................... 26 REG[29h] and REG[2Bh] ............................................................................................................ 26 REG[30h] .................................................................................................................................... 26 No Top/Left Clipping on Hardware Cursor .................................................................................. 26 7.4 Examples........................................................................................................................................ 26 8 HARDWARE ROTATION............................................................................................................... 27 8.1 8.2 8.3 8.4 8.5 Introduction to Hardware Rotation.................................................................................................. 27 S1D13505 Hardware Rotation ....................................................................................................... 27 Registers ........................................................................................................................................ 28 Limitations ...................................................................................................................................... 29 Examples........................................................................................................................................ 29 9 CRT CONSIDERATIONS.............................................................................................................. 31 9.1 Introduction..................................................................................................................................... 31 CRT Only .................................................................................................................................... 31 Simultaneous Display ................................................................................................................. 31 10 IDENTIFYING THE S1D13505 ..................................................................................................... 32 11 HARDWARE ABSTRACTION LAYER (HAL).................................................................................... 33 11.1 Introduction..................................................................................................................................... 33 S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-i CONTENTS 11.2 API for 13505HAL .......................................................................................................................... 33 Initialization ................................................................................................................................. 33 General HAL Support ................................................................................................................. 36 Advanced HAL Functions ........................................................................................................... 39 Register / Memory Access.......................................................................................................... 41 Color Manipulation...................................................................................................................... 43 Drawing....................................................................................................................................... 45 Hardware Cursor ........................................................................................................................ 47 Ink Layer ..................................................................................................................................... 50 Power Save ................................................................................................................................ 53 X-LIB Support ............................................................................................................................. 54 12 SAMPLE CODE ..........................................................................................................................55 12.1 Introduction .................................................................................................................................... 55 Sample Code Using the 13505HAL API ..................................................................................... 55 Sample Code Without Using the 13505HAL API........................................................................ 57 Header Files ............................................................................................................................... 63 APPENDIXSUPPORTED PANEL VALUES .............................................................................................70 2-ii EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) CONTENTS List of Figures Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5 Figure 3-6 Figure 5-1 Figure 5-2 Figure 5-3 Figure 5-4 Figure 5-5 Figure 5-6 Figure 5-7 Pixel Storage for 1 Bpp (2 Colors/Gray Shades) in One Byte of Display Buffer ..................... 5 Pixel Storage for 2 Bpp (4 Colors/Gray Shades) in One Byte of Display Buffer ..................... 5 Pixel Storage for 4 Bpp (16 Colors/Gray Shades) in One Byte of Display Buffer ................... 6 Pixel Storage for 8 Bpp (256 Colors/16 Gray Shades) in One Byte of Display Buffer ............ 6 Pixel Storage for 15 Bpp (32768 Colors/16 Gray Shades) in Two Bytes of Display Buffer..... 7 Pixel Storage for 16 Bpp (65536 Colors/16 Gray Shades) in Two Bytes of Display Buffer..... 7 Viewport Inside a Virtual Display........................................................................................... 15 Memory Address Offset Registers ........................................................................................ 16 Screen 1 Start Address Registers ......................................................................................... 18 Pixel Panning Register .......................................................................................................... 18 320x240 Single Panel for Split Screen.................................................................................. 20 Screen 1 Line Compare ........................................................................................................ 20 Screen 2 Display Start Address ............................................................................................ 21 Table 2-1 Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table 4-5 Table 4-6 Table 4-7 Table 4-8 Table 5-1 Table 5-2 Table 7-1 Table 7-2 Table A-1 Table A-2 Table A-3 S1D13505 Initialization Sequence .......................................................................................... 3 Look-Up Table Configurations................................................................................................. 9 Recommended LUT Values for 1 Bpp Color Mode ................................................................. 9 Example LUT Values for 2 Bpp Color Mode ......................................................................... 10 Suggested LUT Values to Simulate VGA Default 16 Color Palette....................................... 10 Suggested LUT Values to Simulate VGA Default 256 Color Palette..................................... 11 Recommended LUT Values for 1 Bpp Gray Shade .............................................................. 12 Suggested Values for 2 Bpp Gray Shade ............................................................................. 13 Suggested LUT Values for 4 Bpp Gray Shade...................................................................... 13 Number of Pixels Panned Using Start Address..................................................................... 18 Active Pixel Pan Bits ............................................................................................................. 18 Ink/Cursor Mode.................................................................................................................... 24 Cursor/Ink Start Address Encoding ....................................................................................... 26 Passive Single Panel with 40MHz Pixel Clock ...................................................................... 70 Passive Dual Panel with 40MHz Pixel Clock......................................................................... 71 TFT Single Panel with 25.175MHz Pixel Clock ..................................................................... 71 List of Tables S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-iii 1: INTRODUCTION 1 INTRODUCTION This guide demonstrates how to program the S1D13505 Embedded RAMDAC LCD/CDT Controller. The guide presents the basic concepts of the LCD/CRT controller and provides methods to directly program the registers. It explains some of the advanced techniques used and the special features of the S1D13505. The guide also introduces the Hardware Abstraction Layer (HAL), which is designed to make programming the S1D13505 as easy as possible. Future S1D1350x products will support the HAL allowing OEMs the ability to upgrade to future chips with relative ease. S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-1 2: INITIALIZATION 2 INITIALIZATION S1D13505 initialization can be broken into three steps. First, enable the S1D13505 controller (if necessary identify the specific controller). Next, set all the registers to their initial values. Finally, program the Look-Up Table (LUT) with color values. This section does not deal with programming the LUT, see Section 4 of this manual for LUT programming details. Note: When using an ISA evaluation board in a PC (i.e. S5U13505P00C), there are two additional steps that must be carried out before initialization. First, confirm that 16-bit mode is enabled by writing to address F80000h. Then, if hardware suspend is enabled, disable suspend mode by writing to F00000h. For further information on ISA evaluation boards refer to the S5U13505P00C Rev. 1.0 ISA Bus Evaluation Board User Manual. The following table represents the sequence and values written to the S1D13505 registers to control a configuration with these specifications: * * * * * 2-2 640x480 color dual passive format 1 LCD @ 75Hz. 8-bit data interface. 8 bit-per-pixel (bpp) - 256 colors. 31.5 MHz input clock. 50 ns EDO-DRAM, 2 CAS, 4 ms refresh, CAS before RAS. EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 2: INITIALIZATION Register [1B] [23] [01] Value 0000 0000 1000 0000 0011 0000 [22] 0100 1000 [02] [03] [04] 0001 0110 0000 0000 0100 1111 [05] [06] [07] [08] [09] 0000 0011 0000 0000 0000 0000 1110 1111 0000 0000 [0A] [0B] [0C] [0D] 0011 1000 0000 0000 0000 0000 0000 1100 [0E] [0F] [10] [11] [12] [13] [14] [15] [16] [17] 1111 1111 0000 0011 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0100 0000 0000 0001 [18] [19] 0000 0000 0000 0001 [1A] [1C] [1D] [1E] [1F] [20] [21] [24] [26] [27] [28] [29] [2A] [2B] [2C] [2D] [2E] [2F] [30] [31] [23] 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 [0D] 0000 1101 Table 2-1 S1D13505 Initialization Sequence Notes See Also Enable the host interface Disable the FIFO Memory configuration - divide ClkI by 512 to get 4 ms for 256 refresh cycles - this is 2-CAS# EDO memory Performance Enhancement 0 - refer to the hardware specification for a S1D13505 Hardware Funccomplete description of these bits tional Specification Panel type - non-EL, 8-bit data, format 1, color, dual, passive Mod rate used by older monochrome panels - set to 0 Horizontal display size = (REG[04]+1)*8 = (79+1)*8 = 640 pixels see note for REG[16h] and REG[17h] Horizontal non-display size = (REG[05]+1)*8 = (3+1)*8 = 32 pixels FPLINE start position - only required for CRT or TFT/D-TFD FPLINE polarity set to active high Vertical display size = REG[09][08] + 1 = 0000 0000 1110 1111 + 1 = 239+1 = 240 lines (total height/2 for dual panels) Vertical non-display size = REG[0A] + 1 = 57 + 1 = 58 lines FPFRAME start position - only required for CRT or TFT/D-TFD FPFRAME polarity set to active high Display mode - SwivelViewTM disabled, 8 bpp and LCD disabled, enable LCD in last step of this example. Line compare (REG[0Eh] and REG[0Fh] set to maximum allowable value. We can change this later if we want a split screen. Screen 1 Start Address (REG[10h], REG[11h], and REG[12h]) set to 0. This will start the display in the first byte of the display buffer. Screen 2 Start Address (REG[13h], REG[14h], and REG[15h]) to offset 0. Screen 2 Start Address in not used at this time. Memory Address Offset (REG[17h], REG[16h]) - 640 pixels = 640 bytes = 320 words = 140h words Note: When setting a horizontal resolution greater than 767 pixels, with a color depth of 15/16 bpp, the Memory Offset Registers (REG[16h], REG[17h]) must be set to a virtual horizontal pixel resolution of 1024. Set pixel panning for both screens to 0 Clock Configuration - set PClk to MClk/2 - the specification says that for a dual color panel the maximum PClk is MClk/2 Enable LCD Power MD Configuration Readback - we write a 0 here to keep the register configuration logic simpler General I/O Pins - set to zero. General I/O Pins Control - set to zero. The remaining register control operation of the LUT and hardware cursor/ink layer. During the chip initialization none of these registers needs to be set. It is safe to write them to zero as this is the power-up value for the registers. Enable FIFO, mask in appropriate FIFO threshold bits S1D13505 Hardware Functional Specification Display mode - SwivelViewTM disabled, 8 bpp and LCD enabled S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-3 2: INITIALIZATION 2.1 Miscellaneous This section of the notes contains recommendations which can be set at initialization time to improve display image quality. At high color depths the display FIFO introduces two conditions which must be accounted for in software. Simultaneous display while using a dual passive panel introduces another possible register change. Display FIFO Threshold At 15/16 bit-per-pixel the display FIFO threshold (bits 0-4 of REG[23h]) must be programmed to a value other than '0'. Product testing has shown that at these color depths a better quality image results when the display FIFO threshold is set to a value of 1Bh. Memory Address Offset When an 800x600 display mode is selected at 15 or 16 bpp, memory page breaks can disrupt the display buffer fetches. This disruption produces a visible flicker on the display. To avoid this set the Memory Address Offset (REG[16h] and REG[17h]) to 200h. This sets a 1024 pixel line which aligns the memory page breaks and reduces any flicker. Half Frame Buffer Disable The half frame buffer is an S1D13505 mechanism which pre-digitizes display data for dual panel displays. However, for proper simultaneous display operation the half frame buffer (HFB) must be disabled. When running simultaneous display with a dual panel the pattern used by the Frame Rate Modulator may need to be adjusted. This can be accomplished using the Alternate FRM Register Reg[31h]. In this case, the recommended value for REG[31h] of FFh, may produce more visually appealing output. For further information on the half frame buffer and the Alternate FRM Register see the "S1D13505 Hardware Functional Specification". 2-4 EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 3: MEMORY MODELS 3 MEMORY MODELS The S1D13505 is capable of several color depths. The memory model for each color depth is packed pixel. Packed pixel data changes with each color depth from one byte containing eight consecutive pixels up to two bytes being required for one pixel. 3.1 Display Buffer Location The S1D13505 requires either a 512K byte or 2M byte block of memory to be decoded by the system. System logic will determine the location of this memory block. See Section 9 of the "Hardware Functional Specification" for details. Memory Organization for One Bit-Per-Pixel (2 Colors/Gray Shades) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 Bit 1 Pixel 1 Bit 0 Pixel 2 Bit 1 Pixel 3 Bit 0 Pixel 4 Bit 1 Pixel 5 Bit 0 Pixel 6 Bit 1 Pixel 7 Bit 0 Figure 3-1 Pixel Storage for 1 Bpp (2 Colors/Gray Shades) in One Byte of Display Buffer In this memory format each byte of display buffer contains eight adjacent pixels. Setting or resetting any pixel will require reading the entire byte, masking out the appropriate bits and, if necessary, setting the bits to `1'. One bit pixels provide two gray shade/color possibilities. For monochrome panels the two gray shades are generated by indexing into the first two elements of the green component of the Look-Up Table (LUT). For color panels the two colors are derived by indexing into positions 0 and 1 of the Look-Up Table. Memory Organization for Two Bit-Per-Pixel (4 Colors/Gray Shades) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 Bit 1 Pixel 0 Bit 0 Pixel 1 Bit 1 Pixel 1 Bit 0 Pixel 2 Bit 1 Pixel 2 Bit 0 Pixel 3 Bit 1 Pixel 3 Bit 0 Figure 3-2 Pixel Storage for 2 Bpp (4 Colors/Gray Shades) in One Byte of Display Buffer In this memory format each byte of display buffer contains four adjacent pixels. Setting or resetting any pixel will require reading the entire byte, masking out the appropriate bits and, if necessary, setting the bits to `1'. Two bit pixels are capable of displaying four gray shade/color combinations. For monochrome panels the four gray shades are generated by indexing into the first four elements of the green component of the Look-Up Table. For color panels the four colors are derived by indexing into positions 0 through 3 of the Look-Up Table. S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-5 3: MEMORY MODELS Memory Organization for Four Bit-Per-Pixel (16 Colors/Gray Shades) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 Bit 3 Pixel 0 Bit 2 Pixel 0 Bit 1 Pixel 0 Bit 0 Pixel 1 Bit 3 Pixel 1 Bit 2 Pixel 1 Bit 1 Pixel 1 Bit 0 Figure 3-3 Pixel Storage for 4 Bpp (16 Colors/Gray Shades) in One Byte of Display Buffer In this memory format each byte of display buffer contains two adjacent pixels. Setting or resetting any pixel will require reading the entire byte, masking out the upper or lower nibble (4 bits) and setting the appropriate bits to `1'. Four bit pixels provide 16 gray shade/color possibilities. For monochrome panels the gray shades are generated by indexing into the first 16 elements of the green component of the Look-Up Table. For color panels the 16 colors are derived by indexing into the first 16 positions of the Look-Up Table. Memory Organization for Eight Bit-Per-Pixel (256 Colors/16 Gray Shades) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 One Pixel Figure 3-4 Pixel Storage for 8 Bpp (256 Colors/16 Gray Shades) in One Byte of Display Buffer In eight bit-per-pixel mode each byte of display buffer represents one pixel on the display. At this color depth the read-modify-write cycles of the lessor pixel depths are eliminated. Each byte indexes into one of the 256 positions of the Look-Up Table. The S1D13505 LUT supports four bits per primary color, therefore this translates into 4096 possible colors when color mode is selected. To display the fullest dynamic range of colors will require careful selection of the colors in the LUT indices and in the image to be displayed. When monochrome mode is selected, the green component of the LUT is used to determine the gray shade intensity. The green indices, with only four bits, can resolve 16 gray shades. In this situation one might as well use four bit-per-pixel mode and conserve display buffer. 2-6 EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 3: MEMORY MODELS Memory Organization for Fifteen Bit-Per-Pixel (32768 Colors/16 Gray Shades) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reserved Red Bit 4 Red Bit 3 Red Bit 2 Red Bit 1 Red Bit 0 Green Bit 4 Green Bit 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Green Bit 2 Green Bit 1 Green Bit 0 Blue Bit 4 Blue Bit 3 Blue Bit 2 Blue Bit 1 Blue Bit 0 Figure 3-5 Pixel Storage for 15 Bpp (32768 Colors/16 Gray Shades) in Two Bytes of Display Buffer In 15 bit-per-pixel mode the S1D13505 is capable of displaying 32768 colors. The 32768 color pixel is divided into four parts: one reserved bit, five bits for red, five bits for green, and five bits for blue. In this mode the Look-Up Table is bypassed and output goes directly into the Frame Rate Modulator. The full color range is only available on TFT/D-TFD or CRT displays. Passive LCD displays are limited to using the four most significant bits from each of the red, green and blue portions of each color. The result is 4096 (24 * 24 * 24) possible colors. Should monochrome mode be chosen at this color depth, the output reverts to sending the four most significant bits of the green LUT component to the modulator for a total of 16 possible gray shades. In this situation one might as well use four bit-per-pixel mode and conserve display buffer. Memory Organization for Sixteen Bit-Per-Pixel (65536 Colors/16 Gray Shades) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Red Bit 4 Red Bit 3 Red Bit 2 Red Bit 1 Red Bit 0 Green Bit 5 Green Bit 4 Green Bit 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Green Bit 2 Green Bit 1 Green Bit 0 Blue Bit 4 Blue Bit 3 Blue Bit 2 Blue Bit 1 Blue Bit 0 Figure 3-6 Pixel Storage for 16 Bpp (65536 Colors/16 Gray Shades) in Two Bytes of Display Buffer In 16 bit-per-pixel mode the S1D13505 is capable of generating 65536 colors. The 65536 color pixel is divided into three parts: five bits for red, six bits for green, and five bits for blue. In this mode the Look-Up Table is bypassed and output goes directly into the Frame Rate Modulator. The full color range is only available on TFT/D-TFD or CRT displays. Passive LCD displays are limited to using the four most significant bits from each of the red, green and blue portions of each color. The result is 4096 (24 * 24 * 24) possible colors. When monochrome mode is selected, the green component of the LUT is used to determine the gray shade intensity. The green indices, with only four bits, can resolve 16 gray shades. In this situation one might as well use four bit-per-pixel mode and conserve display buffer. S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-7 4: LOOK-UP TABLE (LUT) 4 LOOK-UP TABLE (LUT) This section is supplemental to the description of the Look-Up Table architecture found in the "S1D13505 Hardware Functional Specification". Covered here is a review of the LUT registers, recommendations for the color and gray shade LUT values, and additional programming considerations for the LUT. Refer to the "S1D13505 Hardware Functional Specification" for more detail. The S1D13505 Look-Up Table is used for both the CRT and panel interface and consists of 256 indexed red/green/blue entries. Each entry is 4 bits wide. Two registers, at offsets 0x24 and 0x26, control access to the LUT. Color depth affects how many indices will be used for image display. In color modes, pixel values are used as indices to an RGB value stored in the Look-Up Table. In monochrome modes only the green component of the LUT is used. The value in the display buffer indexes into the LUT and the amount of green at that index controls the intensity. Monochrome mode look-ups are done for the panel interface only. The CRT interface always receives the RGB values from the Look-Up Table. 4.1 Look-Up Table Registers REG[24h] Look-Up Table Address Register LUT Address LUT Address LUT Address LUT Address Bit 7 Bit 6 Bit 5 Bit 4 LUT Address Bit 3 LUT Address Bit 2 LUT Address Bit 1 Read/Write LUT Address Bit 0 LUT Address The LUT address register selects which of the 256 LUT entries will be accessed. Writing to this register will select the red bank. After three successive reads or writes to the data register this register will be incremented by one. REG[24h] Look-Up Table Address Register LUT Data LUT Data LUT Data Bit 3 Bit 2 Bit 1 LUT Data Bit 0 n/a n/a n/a Read/Write n/a LUT Data This register is where the 4-bit red/green/blue data value is written or read. With each successive read or write the internal bank select is incremented. Three reads from this register will result in reading the red, then the green, and finally the blue values associated with the index set in the LUT address register. After the third read the LUT address register is incremented and the internal index points to the red bank again. 2-8 EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 4: LOOK-UP TABLE (LUT) 4.2 Look-Up Table Organization * The Look-Up Table treats the value of a pixel as an index into an array of colors or gray shades. For example, a pixel value of zero would point to the first LUT entry; a pixel value of 7 would point to the eighth LUT entry. * The value inside each LUT entry represents the intensity of the given color or gray shade. This intensity can range in value between 0 and 0Fh. * The S1D13505 Look-Up Table is linear; increasing the LUT entry number results in a lighter color or gray shade. For example, a LUT entry of 0Fh into the red LUT entry will result in a bright red output while a LUT entry of 5 would result in a dull red. Display Mode 1 bpp gray 2 bpp gray 4 bpp gray 8 bpp gray 15 bpp gray 16 bpp gray 1 bpp color 2 bpp color 4 bpp color 8 bpp color 15 bpp color 16 bpp color RED 2 4 16 256 Table 4-1 Look-Up Table Configurations 4-Bit Wide Look-Up Table GREEN BLUE 2 4 16 16 2 4 16 256 2 4 16 256 Effective Gray Shade/Colors on an Passive Panel 2 gray shades 4 gray shades 16 gray shades 16 gray shades 16 gray shades 16 gray shades 2 colors 4 colors 16 colors 256 colors 4096 colors* 4096 colors* * On an active matrix panel the effective colors are determined by the interface width. (i.e. 9-bit=512, 12-bit=4096, 18-bit=64K colors) Passive panels are limited to 12-bits through the Frame Rate Modulator. Indicates the Look-Up Table is not used for that display mode. Color Modes In color display modes, depending on the color depth, 2 through 256 index entries are used. The selection of which entries are used is automatic. 1 bpp Color When the S1D13505 is configured for 1 bpp color mode, the LUT is limited to the first two entries. The two LUT entries can be any two RGB values but are typically set to black-and-white. Each byte in the display buffer contains 8 bits, each pertaining to adjacent pixels. A bit value of '0' results in the LUT 0 index value being displayed. A bit value of '1' results in the LUT 1 index value being displayed. The following table shows the recommended values for obtaining a black-and-white mode while in 1 bpp on a color panel. Table 4-2 Recommended LUT Values for 1 Bpp Color Mode Index Red Green Blue 00 00 00 00 01 F0 F0 F0 00 00 00 02 ... 00 00 00 00 00 00 FF Indicates unused entries in the LUT. S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-9 4: LOOK-UP TABLE (LUT) 2 bpp Color When the S1D13505 is configured for 2 bpp color mode only the first 4 entries of the LUT are used. These four entries can be set to any desired values. Each byte in the display buffer contains 4 adjacent pixels. Each pair of bits in the byte are used as an index into the LUT. The following table shows example values for 2 bpp color mode. Table 4-3 Example LUT Values for 2 Bpp Color Mode Index Red Green Blue 00 00 00 00 01 70 70 70 02 A0 A0 A0 03 F0 F0 F0 04 00 00 00 ... 00 00 00 FF 00 00 00 Indicates unused entries in the LUT. 4 bpp Color When the S1D13505 is configured for 4 bpp color mode the first 16 entries in the LUT are used. Each byte in the display buffer contains two adjacent pixels. The upper and lower nibbles of the byte are used as indices into the LUT. The following table shows LUT values that will simulate those of a VGA operating in 16 color mode. Table 4-4 Suggested LUT Values to Simulate VGA Default 16 Color Palette Index Red Green Blue 00 00 00 00 01 00 00 0A 02 00 0A 00 03 00 0A 0A 04 0A 00 00 05 0A 00 0A 06 0A 0A 00 07 0A 0A 0A 08 00 00 00 09 00 00 0F 0A 00 0F 00 0B 00 0F 0F 0C 0F 00 00 0D 0F 00 0F 0E 0F 0F 00 0F 0F 0F 0F 00 00 00 10 ... 00 00 00 FF 00 00 00 Indicates unused entries in the LUT. 2-10 EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 4: LOOK-UP TABLE (LUT) 8 bpp Color When the S1D13505 is configured for 8 bpp color mode all 256 entries in the LUT are used. Each byte in display buffer corresponds to one pixel and is used as an index value into the LUT. The S1D13505 LUT has four bits (16 intensities) of intensity control per primary color while a standard VGA RAMDAC has six bits (64 intensities). This four to one difference has to be considered when attempting to match colors between a VGA RAMDAC and the S1D13505 LUT. (i.e. VGA levels 0 - 3 map to LUT level 0, VGA levels 4 - 7 map to LUT level 1...). Additionally, the significant bits of the color tables are located at different offsets within their respective bytes. After calculating the equivalent intensity value the result must be shifted into the correct bit positions. The following table shows LUT values that will approximate the VGA default color palette. Index 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F R 00 00 00 00 A0 A0 A0 A0 50 50 50 50 F0 F0 F0 F0 00 10 20 20 30 40 50 60 70 80 90 A0 B0 C0 E0 F0 00 40 70 B0 F0 F0 F0 F0 F0 F0 F0 F0 F0 B0 70 40 G 00 00 A0 A0 00 00 50 A0 50 50 F0 F0 50 50 F0 F0 00 10 20 20 30 40 50 60 70 80 90 A0 B0 C0 E0 F0 00 00 00 00 00 00 00 00 00 40 70 B0 F0 F0 F0 F0 Table 4-5 Suggested LUT Values to Simulate VGA Default 256 Color Palette B Index R G B Index R G B Index 00 40 F0 70 70 80 30 30 70 C0 A0 41 F0 90 70 81 40 30 70 C1 00 42 F0 B0 70 82 50 30 70 C2 A0 43 F0 D0 70 83 60 30 70 C3 00 44 F0 F0 70 84 70 30 70 C4 A0 45 D0 F0 70 85 70 30 60 C5 00 46 B0 F0 70 86 70 30 50 C6 A0 47 90 F0 70 87 70 30 40 C7 50 48 70 F0 70 88 70 30 30 C8 F0 49 70 F0 90 89 70 40 30 C9 50 4A 70 F0 B0 8A 70 50 30 CA F0 4B 70 F0 D0 8B 70 60 30 CB 50 4C 70 F0 F0 8C 70 70 30 CC F0 4D 70 D0 F0 8D 60 70 30 CD 50 4E 70 B0 F0 8E 50 70 30 CE F0 4F 70 90 F0 8F 40 70 30 CF 00 50 B0 B0 F0 90 30 70 30 D0 10 51 C0 B0 F0 91 30 70 40 D1 20 52 D0 B0 F0 92 30 70 50 D2 20 53 E0 B0 F0 93 30 70 60 D3 30 54 F0 B0 F0 94 30 70 70 D4 40 55 F0 B0 E0 95 30 60 70 D5 50 56 F0 B0 D0 96 30 50 70 D6 60 57 F0 B0 C0 97 30 40 70 D7 70 58 F0 B0 B0 98 50 50 70 D8 80 59 F0 C0 B0 99 50 50 70 D9 90 5A F0 D0 B0 9A 60 50 70 DA A0 5B F0 E0 B0 9B 60 50 70 DB B0 5C F0 F0 B0 9C 70 50 70 DC C0 5D E0 F0 B0 9D 70 50 60 DD E0 5E D0 F0 B0 9E 70 50 60 DE F0 5F C0 F0 B0 9F 70 50 50 DF F0 60 B0 F0 B0 A0 70 50 50 E0 F0 61 B0 F0 C0 A1 70 50 50 E1 F0 62 B0 F0 D0 A2 70 60 50 E2 F0 63 B0 F0 E0 A3 70 60 50 E3 F0 64 B0 F0 F0 A4 70 70 50 E4 B0 65 B0 E0 F0 A5 60 70 50 E5 70 66 B0 D0 F0 A6 60 70 50 E6 40 67 B0 C0 F0 A7 50 70 50 E7 00 68 00 00 70 A8 50 70 50 E8 00 69 10 00 70 A9 50 70 50 E9 00 6A 30 00 70 AA 50 70 60 EA 00 6B 50 00 70 AB 50 70 60 EB 00 6C 70 00 70 AC 50 70 70 EC 00 6D 70 00 50 AD 50 60 70 ED 00 6E 70 00 30 AE 50 60 70 EE 00 6F 70 00 10 AF 50 50 70 EF S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON R 00 00 00 00 00 00 00 00 20 20 30 30 40 40 40 40 40 40 40 40 40 30 30 20 20 20 20 20 20 20 20 20 20 30 30 30 40 40 40 40 40 40 40 40 40 30 30 30 G 40 40 40 40 40 30 20 10 20 20 20 20 20 20 20 20 20 20 30 30 40 40 40 40 40 40 40 40 40 30 30 20 20 20 20 20 20 20 20 20 20 30 30 30 40 40 40 40 B 00 10 20 30 40 40 40 40 40 40 40 40 40 30 30 20 20 20 20 20 20 20 20 20 20 20 30 30 40 40 40 40 40 40 40 40 40 30 30 30 20 20 20 20 20 20 20 20 2-11 4: LOOK-UP TABLE (LUT) Index 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F R 00 00 00 00 00 00 00 00 70 90 B0 D0 F0 F0 F0 F0 Table 4-5 Suggested LUT Values to Simulate VGA Default 256 Color Palette (Continued) G B Index R G B Index R G B Index R F0 00 70 70 00 00 B0 00 00 40 F0 20 F0 40 71 70 10 00 B1 10 00 40 F1 20 F0 70 72 70 30 00 B2 20 00 40 F2 20 F0 B0 73 70 50 00 B3 30 00 40 F3 20 F0 F0 74 70 70 00 B4 40 00 40 F4 20 B0 F0 75 50 70 00 B5 40 00 30 F5 20 70 F0 76 30 70 00 B6 40 00 20 F6 20 40 F0 77 10 70 00 B7 40 00 10 F7 20 70 F0 78 00 70 00 B8 40 00 00 F8 00 70 F0 79 00 70 10 B9 40 10 00 F9 00 70 F0 7A 00 70 30 BA 40 20 00 FA 00 70 F0 7B 00 70 50 BB 40 30 00 FB 00 70 F0 7C 00 70 70 BC 40 40 00 FC 00 70 D0 7D 00 50 70 BD 30 40 00 FD 00 70 B0 7E 00 30 70 BE 20 40 00 FE 00 70 90 7F 00 10 70 BF 10 40 00 FF 00 G 40 40 40 40 40 30 30 30 00 00 00 00 00 00 00 00 B 20 30 30 30 40 40 40 40 00 00 00 00 00 00 00 00 15 bpp color The Look-Up Table is bypassed at this color depth, hence programming the LUT is not necessary. 16 bpp color The Look-Up Table is bypassed at this color depth, hence programming the LUT is not necessary. Gray Shade Modes This discussion of gray shade/monochrome modes only applies to the panel interface. Monochrome mode is selected when register [01] bit 2 = 0. In this mode the output value to the panel is derived solely from the green component of the LUT. The CRT image will continue to be formed from all three (RGB) Look-Up Table components. Note: In order to match the colors on a CRT with the colors on a monochrome panel it is important to ensure that the red and blue components of the Look-Up Table be set to the same intensity as the green component. 1 bpp gray shade In 1 bpp gray shade mode only the first two entries of the green LUT are used. All other LUT entries are unused. Table 4-6 Recommended LUT Values for 1 Bpp Gray Shade Address Red Green Blue 00 00 00 00 F0 F0 F0 01 02 00 00 00 ... 00 00 00 FF 00 00 00 Required to match CRT to panel Unused entries 2-12 EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 4: LOOK-UP TABLE (LUT) 2 bpp gray shade In 2 bpp gray shade mode the first four green elements are used to provide values to the panel. The remaining indices are unused. Index 0 1 2 3 4 ... FF Table 4-7 Suggested Values for 2 Bpp Gray Shade Red Green Blue 00 00 00 50 50 50 A0 A0 A0 F0 F0 F0 00 00 00 00 00 00 00 00 00 Required to match CRT to panel Unused entries 4 bpp Gray Shade The 4 bpp gray shade mode uses the first 16 LUT elements. The remaining indices of the LUT are unused. Table 4-8 Suggested LUT Values for 4 Bpp Gray Shade Index Red Green Blue 00 00 00 00 10 10 10 01 02 20 20 20 03 30 30 30 04 40 40 40 05 50 50 50 06 60 60 60 07 70 70 70 08 80 80 80 09 90 90 90 0A A0 A0 A0 0B B0 B0 B0 0C C0 C0 C0 D0 D0 D0 0D 0E E0 E0 E 0F F0 F0 F0 10 00 00 00 ... 00 00 00 FF 00 00 00 Required to match CRT to panel Unused entries S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-13 4: LOOK-UP TABLE (LUT) 8 bpp gray shade When 8 bpp gray shade mode is selected the gray shade intensity is determined by the green LUT value. The green portion of the LUT has 16 possible intensities. There is no color advantage to selecting 8 bpp mode over 4 bpp mode; however, hardware rotate can be only used in 8 and 16 bpp modes. 15 bpp gray shade The Look-Up Table is bypassed at this color depth, hence programming the LUT is not necessary. As with 8 bpp there are limitations to the colors which can be displayed. In this mode the four most significant bits of green are used to set the absolute intensity of the image. Four bits of green resolves to 16 colors. Now however, each pixel requires two bytes. 16 bpp gray The Look-Up Table is bypassed at this color depth, hence programming the LUT is not necessary. As with 8 bpp there are limitations to the colors which can be displayed. In this mode the four most significant bits of green are used to set the absolute intensity of the image. Four bits of green resolves to 16 colors. Now however, each pixel requires two bytes. 2-14 EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 5: ADVANCED TECHNIQUES 5 ADVANCED TECHNIQUES This section presents information on the following: * virtual display * panning and scrolling * split screen display 5.1 Virtual Display Virtual display refers to the situation where the image to be viewed is larger than the physical display. This can be in the horizontal, the vertical or both dimensions. To view the image, the display is used as a window (or viewport) into the display buffer. At any given time only a portion of the image is visible. Panning and scrolling are used to view the full image. The Memory Address Offset registers are used to determine the number of horizontal pixels in the virtual image. The offset registers can be set for a maximum of 211 or 2048 words. In 1 bpp display modes these 2048 words cover 16,384 pixels. At 16 bpp 2048 words cover 1024 pixels. The maximum vertical size of the virtual image is the result of a number of variables. In its simplest, the number of lines is the total display buffer divided by the number of bytes per horizontal line. The number of bytes per line is the number of words in the offset register multiplied by two. At maximum horizontal size, the greatest number of lines that can be displayed is 1024. Reducing the horizontal size makes memory available to increase the virtual vertical size. In addition to the calculated limit the virtual vertical size is limited by the size and location of the half frame buffer and the ink/cursor if present. Seldom are the maximum sizes used. Figure 5-1 "Viewport Inside a Virtual Display," depicts a more typical use of a virtual display. The display panel is 320x240 pixels, an image of 640x480 pixels can be viewed by navigating a 320x240 pixel viewport around the image using panning and scrolling. 320x240 Viewport 640x480 "Virtual" Display Figure 5-1 Viewport Inside a Virtual Display S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-15 5: ADVANCED TECHNIQUES Registers REG[16h] Memory Address Offset Register 0 Memory Memory Memory Memory Memory Memory Memory Memory Address Offset Address Offset Address Offset Address Offset Address Offset Address Offset Address Offset Address Offset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG[17h] Memory Address Offset Register 1 n/a n/a n/a n/a n/a Memory Memory Memory Address Offset Address Offset Address Offset Bit 10 Bit 9 Bit 8 Figure 5-2 Memory Address Offset Registers Registers [16h] and [17h] form an 11-bit value called the memory address offset. This offset is the number of words from the beginning of one line of the display to the beginning of the next line of the display. Note that this value does not necessarily represent the number of words to be shown on the display. The display width is set in the Horizontal Display Width register. If the offset is set to the same as the display width then there is no virtual width. To maintain a constant virtual width as color depth changes, the memory address offset must also change. At 1 bpp each word contains 16 pixels, at 16 bpp each word contains one pixel. The formula to determine the value for these registers is: offset = pixels_per_line / pixels_per_word Examples Example 1 Determine the offset value required for 800 pixels at a color depth of 8 bpp. At 8 bpp each byte contains one pixel, therefore each word contains two pixels. pixels_per_word = 16 / bpp = 16 / 8 = 2 Using the above formula. offset = pixels_per_line / pixels_per_word = 800 / 2 = 400 = 0x190 words Register [17h] would be set to 0x01 and register [16h] would be set to 0x90. Example 2 Program the Memory Address Offset Registers to support a 16 color (4 bpp) 640x480 virtual display on a 320x240 LCD panel. To create a virtual display the offset registers must be programmed to the horizontal size of the larger "virtual" image. After determining the amount of memory used by each line, do a calculation to see if there is enough memory to support the desired number of lines. 1. Initialize the S1D13505 registers for a 320x240 panel. (See "Introduction" on page 1). 2. Determine the offset register value. pixels_per_word = 16 / bpp = 16 / 4 = 4 offset = pixels_per_line / pixels_per_word = 640 / 4 = 160 words = 0x0A0 words Register [17h] will be written with 0x00 and register [16h] will be written with 0xA0. 2-16 EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 5: ADVANCED TECHNIQUES 3. Check that we have enough memory for the required virtual height. 4. Each line uses 160 words and we need 480 lines for a total of (160*480) 76,800 words. This display could be done on a system with the minimum supported memory size of 512K bytes. It is safe to continue with these values. 5.2 Panning and Scrolling The terms panning and scrolling refer to the actions used to move the viewport about a virtual display. Although the image is stored entirely in the display buffer, only a portion is actually visible at any given time. Panning describes the horizontal (side to side) motion of the viewport. When panning to the right the image in the viewport appears to slide to the left. When panning to the left the image to appears to slide to the right. Scrolling describes the vertical (up and down) motion of the viewport. Scrolling down causes the image to appear to slide up and scrolling up causes the image to appear to slide down. Both panning and scrolling are performed by modifying the start address register. The start address refers to the word offset in the display buffer where the image will start being displayed from. At color depths less than 15 bpp a second register, the pixel pan register, is required for smooth pixel level panning. Internally, the S1D13505 latches different signals at different times. Due to this internal sequence, there is an order in which the start address and pixel pan registers should be accessed during scrolling operations to provide the smoothest scrolling. Setting the registers in the wrong sequence or at the wrong time will result in a "tearing" or jitter effect on the display. The start address is latched at the beginning of each frame, therefore the start address can be set any time during the display period. The pixel pan register values are latched at the beginning of each display line and must be set during the vertical non-display period. The correct sequence for programing these registers is: 1. Wait until just after a vertical non-display period (read register [0Ah] and watch bit 7 for the nondisplay status). 2. Update the start address registers. 3. Wait until the next vertical non-display period. 4. Update the pixel paning register. S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-17 5: ADVANCED TECHNIQUES Registers REG[10h] Screen 1 Display Start Address 0 Start Address Start Address Start Address Start Address Bit 7 Bit 6 Bit 5 Bit 4 Start Address Bit 3 Start Address Bit 2 Start Address Bit 1 Start Address Bit 0 REG[11h] Screen 1 Display Start Address 1 Start Address Start Address Start Address Start Address Bit 15 Bit 14 Bit 13 Bit 12 Start Address Bit 11 Start Address Bit 10 Start Address Bit 9 Start Address Bit 8 Start Address Bit 19 Start Address Bit 18 Start Address Bit 17 Start Address Bit 16 REG[12h] Screen 1 Display Start Address 2 n/a n/a n/a n/a Figure 5-3 Screen 1 Start Address Registers These three registers form the address of the word in the display buffer where screen 1 will start displaying from. Changing these registers by one will cause a change of 0 to 16 pixels depending on the current color depth. Refer to the following table to see the minimum number of pixels affected by a change of one to these registers. Table 5-1 Number of Pixels Panned Using Start Address Color Depth (bpp) 1 2 4 8 15 16 Pixels Per Word 16 8 4 2 1 1 Number of Pixels Panned 16 8 4 2 1 1 REG[18h] Pixel Panning Register Screen 2 Pixel Screen 2 Pixel Screen 2 Pixel Screen 2 Pixel Screen 1 Pixel Screen 1 Pixel Screen 1 Pixel Screen 1 Pixel Pan Pan Pan Pan Pan Pan Pan Pan Bit 3 Bit 2 Bit 1 Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 Figure 5-4 Pixel Panning Register The pixel panning register offers finer control over pixel pans than is available with the Start Address Registers. Using this register it is possible to pan the displayed image one pixel at a time. Depending on the current color depth certain bits of the pixel pan register are not used. The following table shows this. Table 5-2 Active Pixel Pan Bits Color Depth (bpp) 1 2 4 8 15/16 2-18 Pixel Pan Bits Used bits [3:0] bits [2:0] bits [1:0] bit 0 --- EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 5: ADVANCED TECHNIQUES Examples For the examples in this section assume that the display system has been set up to view a 640x480 pixel image in a 320x240 viewport. Refer to Section 2, "Initialization" on page 2 and Section 5.1, "Virtual Display" on page 15 for assistance with these settings. Example 3 Panning - Right and Left To pan to the right, increment the pixel pan value. If the pixel pan value is equal to the current color depth then set the pixel pan value to zero and increment the start address value. To pan to the left decrement the pixel pan value. If the pixel pan value is less than zero set it to the color depth (bpp) less one and decrement the start address. Note: Scrolling operations are easier to follow if a value, call it pan_value, is used to track both the pixel pan and start address. The least significant bits of pan_value will represent the pixel pan value and the more significant bits are the start address value. The following pans to the right by one pixel in 4 bpp display mode. 1. This is a pan to the right. Increment pan_value. pan_value = pan_value + 1 2. Mask off the values from pan_value for the pixel panning and start address register portions. In this case, 4 bpp, the lower two bits are the pixel panning value and the upper bits are the start address. pixel_pan = pan_value AND 3 start_address = pan_value SHR 3(the fist two bits of the shift account for the pixel_pan the last bit of the shift converts the start_address value from bytes to words) 3. Write the pixel panning and start address values to their respective registers using the procedure outlined in the registers section. Example 4 Scrolling - Up and Down To scroll down, increase the value in the Screen 1 Display Start Address Register by the number of words in one virtual scan line. To scroll up, decrease the value in the Screen 1 Display Start Address Register by the number of words in one virtual scan line. Example 5 Scroll down one line for a 16 color 640x480 virtual image using a 320x240 single panel LCD. 1. To scroll down we need to know how many words each line takes up. At 16 colors (4 bpp) each byte contains two pixels so each word contains 4 pixels. offset_words = pixels_per_line / pixels_per_word = 640 / 4 = 160 = 0xA0 We now know how much to add to the start address to scroll down one line. 2. Increment the start address by the number of words per virtual line. start_address = start_address + words 3. Separate the start address value into three bytes. Write the LSB to register [10h] and the MSB to register [12h]. S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-19 5: ADVANCED TECHNIQUES 5.3 Split Screen Occasionally the need arises to display two distinct images on the display. For example, we may write a game where the main play area will rapidly update and we want a status display at the bottom of the screen. The Split Screen feature of the S1D13505 allows a programmer to setup a display for such an application. The figure below illustrates setting a 320x240 panel to have Image 1 displaying from scan line 0 to scan line 99 and image 2 displaying from scan line 100 to scan line 239. Although this example picks specific values, image 1 and image 2 can be shown as varying portions of the screen. Scan Line 0 ... Scan Line 99 Scan Line 100 Image 1 ... Image 2 Scan Line 239 Screen 1 Display Line Count Register = 99 lines Figure 5-5 320x240 Single Panel for Split Screen Registers The other registers required for split screen operations, [10h] through [12h] (Screen 1 Display Start Address) and [18h] (Pixel Panning Register), are described in Section 5.2 on page 2-17. REG[0E] Screen 1 Line Compare Register 0 Line Compare Line Compare Line Compare Line Compare Line Compare Line Compare Line Compare Line Compare Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG[0F] Screen 1 Line Compare Register 1 n/a n/a n/a n/a n/a n/a Line Compare Line Compare Bit 9 Bit 8 Figure 5-6 Screen 1 Line Compare These two registers form a value known as the line compare. When the line compare value is equal to or greater than the physical number of lines being displayed there is no visible effect on the display. When the line compare value is less than the number of physically displayed lines, display operation works like this: 1. From the end of vertical non-display to the number of lines indicated by line compare the display data will be from the memory pointed to by the Screen 1 Display Start Address. 2. After line compare lines have been displayed the display will begin showing data from Screen 2 Display Start Address memory. 2-20 EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 5: ADVANCED TECHNIQUES REG[13h] Screen 2 Display Start Address Register 0 Start Address Start Address Start Address Start Address Bit 7 Bit 6 Bit 5 Bit 4 Start Address Bit 3 Start Address Bit 2 Start Address Bit 1 Start Address Bit 0 REG[14h] Screen 2 Display Start Address Register 1 Start Address Start Address Start Address Start Address Bit 15 Bit 14 Bit 13 Bit 12 Start Address Bit 11 Start Address Bit 10 Start Address Bit 9 Start Address Bit 8 Start Address Bit 19 Start Address Bit 18 Start Address Bit 17 Start Address Bit 16 REG[15h] Screen 2 Display Start Address Register 2 n/a n/a n/a n/a Figure 5-7 Screen 2 Display Start Address These three registers form the twenty bit offset to the first word in display buffer that will be shown in the screen 2 portion of the display. Screen 1 memory is always the first memory displayed at the top of the screen followed by screen 2 memory. However, the start address for the screen 2 image may in fact be lower in memory than that of screen 1 (i.e. screen 2 could be coming from offset 0 in the display buffer while screen 1 was coming from an offset located several thousand bytes into display buffer). While not particularly useful, it is possible to set screen 1 and screen 2 to the same address. Examples Example 6 Display 380 scanlines of image 1 and 100 scanlines of image 2. Image 2 is located immediately after image 1 in the display buffer. Assume a 640x480 display and a color depth of 1 bpp. 1. The value for the line compare is not dependent on any other setting so we can set it immediately (380 = 0x17C). Write the line compare registers [0Fh] with 0x01 and register [0Eh] with 0x7C. 2. Screen 1 is coming from offset 0 in the display buffer. Although not necessary, ensure that the screen 1 start address is set to zero. Write 0x00 to registers [10h], [11h] and [12h]. 3. Calculate the size of the screen 1 image (so we know where the screen 2 image is located). This calculation must be performed on the virtual size (offset register). Since a virtual size was not specified assume the virtual size to be the same as the physical size. offset = pixels_per_line / pixels_per_word = 640 / 16 = 40 words per line screen1_size = offset * lines = 40 * 480 = 19,200 words = 0x4B00 words 4. Set the screen 2 start address to the value we just calculated. Write the screen 2 start address registers [15h], [14h] and [13h] with the values 0x00, 0x4B and 0x00 respectively. S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-21 6: LCD POWER SEQUENCING AND POWER SAVE MODES 6 LCD POWER SEQUENCING AND POWER SAVE MODES 6.1 Introduction to LCD Power Sequencing LCD Power Sequencing allows the LCD power supply to discharge prior to shutting down the LCD signals. Power sequencing is required to prevent long term damage to the panel and to avoid unsightly "lines" on power-down and power-up. The S1D13505 performs automatic power sequencing when the LCD is enabled or disabled through the LCD Enable bit in register [0Dh]. For most applications the internal power sequencing is the appropriate choice. There may be situations where the internal time delay is insufficient to discharge the LCD power supply before the LCD signals are shut down. This section details the sequences to manually powerup and power-down the LCD interface. Proper LCD power sequencing dictates that there must be a time delay between the time the LCD power is disabled and the time the LCD signals are shut down. During power up the LCD signals must be active prior to applying power to the LCD. This time interval varies depending on the power supply design. The power supply on the S5U13505P00C Evaluation board requires 0.5 seconds to fully discharge. Your power supply design may vary. 6.2 Registers REG[0D] Display Mode Register Simultaneous Simultaneous SwivelViewTM Display Option Display Option Enable Select Bit 1 Select Bit 0 Bit-Per-Pixel Select Bit 2 Bit-Per-Pixel Select Bit 1 Bit-Per-Pixel Select Bit 0 CRT Enable LCD Enable LCD Enable normally performs all the required power sequencing. Upon setting LCD Enable to '0' the system will begin a series of events which include turning off the LCD power supply, waiting for the power supply to discharge and finally turning off the LCD signals. REG[1A] Power Save Configuration Register Power Save Status n/a n/a n/a LCD Power Disable Suspend Suspend Refresh Select Refresh Select Bit 1 Bit 0 Software Suspend Mode Enable LCD Power Disable would be used to manually sequence the events leading to an LCD powerdown. First the program would set LCD Power Disable to '1' to begin discharging the LCD power supply. After waiting a pre-determined amount of time the software would Disable the LCD signals using the LCD Enable bit in register [0Dh]. 2-22 EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 6: LCD POWER SEQUENCING AND POWER SAVE MODES 6.3 LCD Enable/Disable Power On/Enable Sequence The following is the recommended sequence for manually powering-up an LCD panel. These steps would be used if power supply timing requirements were larger than the timings built into the S1D13505 power enable sequence. 1. Set REG[1Ah] bit 3 to 1. Ensure that LCD power is disabled. 2. Set REG[0Dh] bit 0 to 1. Turn on the LCD outputs. 3. Count 'x' Vertical Non-Display Periods. 'x' corresponds the power supply discharge time converted to the equivalent vertical non-display periods. 4. Set REG[1Ah] bit 3 to 0. This enables LCD Power. Power On Sequence The following is the recommended sequence for manually powering-down an LCD panel. These steps would be used if power supply timing requirements were larger than the timings built into the S1D13505 power disable sequence. 1. Set REG[1Ah] bit 3 to 1 - disable LCD Power. 2. Count 'x' Vertical Non-Display Periods. 'x' corresponds to the power supply discharge time converted to the equivalent vertical non-display periods. 3. Set REG[0Dh] bit 0 to 0 - turn off the LCD outputs. S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-23 7: HARDWARE CURSOR 7 HARDWARE CURSOR 7.1 Introduction The S1D13505 provides hardware support for a cursor or an ink layer. These features are mutually exclusive and therefore only one or the other may be active at any given time. A hardware cursor improves video throughput in graphical operating systems by off-loading much of the work typically assigned to software. Take the actions which must be performed when the user moves the mouse. On a system without hardware support, the operating system must restore the area under the current cursor position then save the area under the new location and finally draw the cursor shape. Contrast that with the hardware assisted system where the operating system must simply update the cursor X and cursor Y position registers. An ink layer is used to support stylus or pen input. Without an ink layer the operating system would have to save an area (possibly all) of the display buffer where pen input was to occur. After the system recognized the user entered characters, the display would have to be restored and the characters redrawn in a system font. With an ink layer the stylus path is drawn in the ink layer, where it overlays the displayed image. After character recognition takes place the display is updated with the new characters and the ink layer is simply cleared. There is no need to save and restore display data thus providing faster throughput. The S1D13505 hardware cursor/ink layer supports a 2 bpp (four color) overlay image. Two of the available colors are transparent and invert. The remaining two colors are user definable. 7.2 Registers There are a total of eleven registers dedicated to the operation of the hardware cursor/ink layer. Many of the registers need only be set once. Others, such as the positional registers, will be updated frequently. REG[27h] Ink/Cursor Control Register Ink/Cursor Ink/Cursor Mode Mode n/a Bit 1 Bit 0 n/a Cursor High Threshold Bit 3 Cursor High Threshold Bit 2 Cursor High Threshold Bit 1 Cursor High Threshold Bit 0 The Ink/Cursor mode bits determine if the hardware will function as a hardware cursor or as an ink layer. See Table 7-1 for an explanation of these bits. Table 7-1 Ink/Cursor Mode Register [27h] Bit 7 Bit 6 0 0 0 1 1 0 1 1 Operating Mode Inactive Cursor Ink Reserved When cursor mode is selected the cursor image is always 64x64 pixels. Selecting an ink layer will result in a large enough area to completely cover the display. The cursor threshold bits are used to control the Ink/Cursor FIFO depth to sustain uninterrupted display fetches. 2-24 EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 7: HARDWARE CURSOR REG[28h] Cursor X Position Register 0 Cursor X Cursor X Cursor X Position Position Position Bit 7 Bit 6 Bit 5 Cursor X Position Bit 4 Cursor X Position Bit 3 Cursor X Position Bit 2 Cursor X Position Bit 1 Cursor X Position Bit 0 n/a n/a n/a Cursor X Position Bit 9 Cursor X Position Bit 8 REG[29h] Cursor X Position Register 1 Reserved n/a n/a Registers [28h] and [29h] control the horizontal position of the hardware cursor. The value in this register specifies the location of the left edge of the cursor. When ink mode is selected these registers should be set to zero. Cursor X Position bits 9-0 determine the horizontal location of the cursor. With 10 bits of resolution the horizontal cursor range is 1024 pixels. REG[2Ah] Cursor Y Position Register 0 Cursor Cursor Cursor Y Position Y Position Y Position Bit 7 Bit 6 Bit 5 Cursor Y Position Bit 4 Cursor Y Position Bit 3 Cursor Y Position Bit 2 Cursor Y Position Bit 1 Cursor Y Position Bit 0 n/a n/a n/a Cursor Y Position Bit 9 Cursor Y Position Bit 8 REG[2Bh] Cursor Y Position Register 1 Reserved n/a n/a Registers [2Ah] and [2Bh] control the vertical position of the hardware cursor. The value in this register specifies the location of the left edge of the cursor. When ink mode is selected these registers should be set to zero. Cursor Y Position bits 9-0 determine the location of the cursor. With ten bits of resolution the vertical cursor range is 1024 pixels. REG[2Ch] Ink/Cursor Color 0 Register 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG[2Dh] Ink/Cursor Color 0 Register 1 Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 REG[2Eh] Ink/Cursor Color 1 Register 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG[2Fh] Ink/Cursor Color 1 Register 1 Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Cursor Color 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Acting in pairs, Registers [2Ch], [2Dh] and registers [2Eh], [2Fh] are used to form the 16 bpp (5-65) RGB values for the two user defined colors. S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-25 7: HARDWARE CURSOR REG[30h] Ink/Cursor Start Address Select Register Ink/Cursor Ink/Cursor Ink/Cursor Ink/Cursor Start Address Start Address Start Address Start Address Bit 7 Bit 6 Bit 5 Bit 4 Ink/Cursor Start Address Bit 3 Ink/Cursor Start Address Bit 2 Ink/Cursor Start Address Bit 1 Ink/Cursor Start Address Bit 0 Register [30h] determines the location in the display buffer where the cursor/ink layer will be located. Table 7-2 can be used to determine this location. Note: Bit 7 is write only, when reading back the register this bit reads a '0'. Table 7-2 Cursor/Ink Start Address Encoding Ink/Cursor Start Address Bits [7:0] Start Address (Bytes) 0 Display Buffer Size - 1024 1 - 0xFF Display Buffer Size - (n * 8192) 7.3 Limitations There are limitations for using the hardware cursor/ink layer which should be noted. REG[29h] and REG[2Bh] Bit seven of registers [29h] and [2Bh] are write only, and must always be set to zero as setting these bits to one, will cause undefined cursor behavior. REG[30h] Bit 7 of register [30h] is write only, therefore programs cannot determine the current cursor/ink layer start address by reading register [30h]. It is suggested that values written to this register be stored elsewhere and used when the current state of this register is required. No Top/Left Clipping on Hardware Cursor The S1D13505 does not clip the hardware cursor on the top or left edges of the display. For cursor shapes where the hot spot is not the upper left corner of the image (the hourglass for instance), the cursor image will have to be modified to clip the cursor shape. 7.4 Examples See Section 12, "Sample Code" for hardware cursor programming examples. 2-26 EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 8: HARDWARE ROTATION 8 HARDWARE ROTATION 8.1 Introduction to Hardware Rotation Most computer displays operate in landscape mode. In landscape mode the display is wider than it is high. For instance, a standard display size is 640x480 where the width is 640 pixels and the height is 480 pixels. Portrait mode rotates the display image clockwise ninety degrees, resulting in a display that is taller than it is wide. Placing the 640x480 display in portrait mode will yield a display that is now 480 pixels wide and 640 pixels high. 8.2 S1D13505 Hardware Rotation The S1D13505 provides hardware support for portrait mode output in 16 and 8 bpp modes. The switch to portrait mode carries several conditions: * The (virtual) display offset must be set to 1024 pixels. * The display start address is calculated differently in portrait mode. * Calculations that would result in panning in portrait mode result in scrolling in portrait mode and vice-versa. S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-27 8: HARDWARE ROTATION 8.3 Registers This section will detail each of the registers used to setup portrait mode operations on the S1D13505. The functionality of most of these registers has been covered in previous sections but is included here to make this section complete. The first step toward setting up portrait mode operation is to set the SwivelViewTM Enable bit to 1 (bit 7 of register [0Dh]). REG[0Dh] Display Mode Register Simultaneous Simultaneous SwivelViewTM Display Option Display Option Enable Select Bit 1 Select Bit 0 Bit-Per-Pixel Select Bit 2 Bit-Per-Pixel Select Bit 1 Bit-Per-Pixel Select Bit 0 CRT Enable LCD Enable Step two involves setting the screen 1 start address registers. Set to 1024 - width for 16 bpp modes and to (1024 - width) / 2 for 8 bpp modes. REG[10h] Screen 1 Display Start Address Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 11 Bit 10 Bit 9 Bit 8 Bit 19 Bit 18 Bit 17 Bit 16 REG[11h] Screen 1 Display Start Address Register 1 Bit 15 Bit 14 Bit 13 Bit 12 REG[12h] Screen 1 Display Start Address Register 2 n/a n/a n/a n/a Finally set the memory address offset registers to 1024 pixels. In 16 bpp mode load registers [17h:16h] with 1024 and in 8 bpp mode load the registers with 512. REG[16h] Memory Address Offset Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 n/a n/a Bit 10 Bit 9 Bit 8 REG[17h] Memory Address Offset Register 1 n/a 2-28 n/a n/a EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 8: HARDWARE ROTATION 8.4 Limitations The following limitations apply to SwivelViewTM: * Only 8 bpp and 16 bpp modes are supported - 1/2/4 bpp modes are not supported. * Cursor and ink images are not rotated - software rotation must be used. SwivelViewTM must be turned off when the programmer is accessing the Cursor or the ink layer. * Split screen images appear side-by-side, i.e. the portrait display is split vertically. * Pixel panning works vertically. Note: Drawing into the hardware cursor/ink layer with rotation enabled does not work without some form of address manipulation. The easiest way to ensure correct cursor/ink images is to disable SwivelViewTM, draw in the cursor/ink memory, then re-enable SwivelViewTM. While writing the cursor/ink memory each pixel must be transformed to its rotated position. 8.5 Examples Example 7 Enable portrait mode for a 640x480 display at 8 bpp. Before switching to portrait mode, display memory should be cleared to make the transition smoother. Currently displayed images can not be simply rotated by hardware. 1. The first step toward enabling portrait mode is to set the line offset to 1024 pixels. The Line Offset register is the offset in words. Write 0x200 to registers [17h]:[16h]. That is write 0x02 to register [17h] and 0x00 to register [16h]. 2. The second step to enabling portrait mode is to set the Display 1 Start Address. The Display Start Address registers form a pointer to a word, therefore the value to set the start. Write 0xC0 (192 or (1024 - 480)/2) to registers [10h], [11h] and [12h]. That is write 0xC) to register [10h], 0x00 to register [11h] and 0x00 to register [12h]. 3. Enable display rotation by setting bit 7 of register [0Dh]. 4. The display is now configured for portrait mode use. Offset zero into display memory will correspond to the upper left corner of the display. The only difference seen by the programmer will be in acknowledging that the display offset is now 1024 pixels regardless of the physical dimensions of the display surface. S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-29 8: HARDWARE ROTATION Example 8 Pan the above portrait mode image to the right by 3 pixels then scroll it up by 4 pixels. Pan the above portrait mode image to the right by 3 pixels then scroll it up by 4 pixels. 1. With portrait mode enabled, the x and y control is rotated as well. Simply swap the x and y co-ordinates and calculate as if the display were not rotated. 2. Calculate the new start address and pixel pan values. BytesPerScanline = 1024 PixelPan = newX & 0x01; StartAddr = (newY * BytesPerScanline / 2) + (newX & 0xFFFE) >> 1; 3. Write the start address during the display enabled portion of the frame. a) loop waiting for vertical non-display (b7 of register [0Ah] high). do register = ReadRegister(0x0A) while (0x80 != (register & 0x80)); b) Loop waiting for the end of vertical non-display. do register = ReadRegister(0x0A) while (0x80 == (register & 0x80)); c) Write the new start address. SetRegister(REG_SCRN1_DISP_START_ADDR0, (BYTE) (dwAddr & 0xFF)); SetRegister(REG_SCRN1_DISP_START_ADDR1, (BYTE)((dwAddr >> 8) & 0xFF)); SetRegister(REG_SCRN1_DISP_START_ADDR2, (BYTE)((dwAddr >> 16) & 0x0F)); do register = ReadRegister(0x0A) while (0x80 == (register & 0x80)); 4. Write the pixel pan value during the vertical non-display portion of the frame. a) Coming from the above code wait for beginning of the non-display period. do register = ReadRegister(0x0A) while (0x80 != (register & 0x80)); b) Write the new pixel panning value. register = ReadRegister(0x18); register &= 0xF0; register |= (PixelPan & 0x0F); WriteRegister(0x18, register); 2-30 EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 9: CRT CONSIDERATIONS 9 CRT CONSIDERATIONS 9.1 Introduction The S1D13505 is capable of driving either an LCD panel, or a CRT display, or both simultaneously. As display devices, panels tend to be lax in their horizontal and vertical timing requirements. CRT displays often cannot vary by more than a very small percentage in their timing requirements before the image is degraded. Central to the following sections are VESA timings. Rather than fill this section of the guide with pages full of register values it is recommended. For more information on VESA timings contact the Video Electronics Standards association. CRT Only All CRT output should meet VESA timing specifications. The VESA specification details all the parameters of the display and non-display times as well as the input clock required to meet the times. Simultaneous Display As mentioned in the previous section, CRT timings should always comply to the VESA specification. This requirement implies that during simultaneous operation the timing must still be VESA compliant. For most panels, being run at CRT frequencies is not a problem. One side effect of running with these usually slower timings will be a flicker on the panel. One limitation of simultaneous display is that should a dual panel be the second display device the half frame buffer must be disabled for correct operation. S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-31 10: IDENTIFYING THE S1D13505 10 IDENTIFYING THE S1D13505 Identification of the S1D13505 can only occur after the host interface has been enabled. From reset the steps to identifying the S1D13505 are as follows: 1. If hardware suspend has been enabled then disable the suspend. On the S1D13505 ISA evaluation board this is accomplished by performing a read operation to address 0xF00000. 2. Write a 00h to register [1B] to enable the host interface. 3. Read register [00h] 4. The production version of the S1D13505 is 0x0C. 2-32 EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 11: HARDWARE ABSTRACTION LAYER (HAL) 11 HARDWARE ABSTRACTION LAYER (HAL) 11.1 Introduction The HAL is a processor independent programming library provided by Seiko Epson. The HAL was developed to aid the implementation of internal test programs. The HAL provides an easy, consistent method of programming the S1D13505 on different processor platforms. The HAL also allows for easier porting of programs between S1D1350x products. The HAL keeps sample code simpler, although end programmers may find the HAL functions to be limited in their scope, and may wish to ignore the HAL. 11.2 API for 13505HAL The following is a description of the HAL library. Updates and revisions to the HAL may include new functions not included in the following documentation Initialization The following section describes the HAL functions dealing with initialization of the S1D13505. Typically a programmer has only to concern themselves with calls to seRegisterDevice() and seSetInit(). int seRegisterDevice(const LPHAL_STRUC lpHalInfo, int * pDevice) Description: Register the S1D13505 device parameters with the HAL library. The device parameters have been configured with address range, register values, desired frame rate, etc., and have been saved in the HAL_STRUCT structure pointed to by lpHalInfo. Additionally this routine allocates, from system memory, address space for accessing registers and the display buffer. Parameters: lpHalInfo pDevice - pointer to HAL_STRUCT information structure - pointer to the integer to receive the device ID Return Value: ERR_OK - operation completed with no problems Note: No S1D13505 registers are changed by calling seRegisterDevice(). S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-33 11: HARDWARE ABSTRACTION LAYER (HAL) int seSetInit(int DevID) Description: Configures the system for operation using the specified default settings. Everything required for operation is set in this call. Parameters: DevID Return Value: ERR_OK - operation completed with no problems ERR_FAILED - unable to complete operation. Occurs as a result of requesting parameters that exceed timing specifications. - registered device ID Notes: * This function and seSetDisplayMode() are nearly identical. The largest difference is that seSetInit() always uses the configuration designated to be the default by 13505CFG.EXE and seSetDisplayMode() allows the programmer to select which configuration. * This routine does not configure the Look-Up Tables. int seSetDisplayMode(int DevID, int DisplayMode, int flags) Description: This routine sets the S1D13505 registers according to the values contained in the HAL_STRUCT register section referred to by DisplayMode. Setting all the registers means that timing, display surface dimensions,... all aspects of chip operation are set with this call. 2-34 Parameters: DevID - a valid registered device ID DisplayMode - the HAL_STRUCT register set to use: DISP_MODE_LCD, DISP_MODE_CRT, or DISP_MODE_SIMULTANEOUS flags - can be set to one or more flags. Each flag added by using the logical OR command. Do not add mutually exclusive flags. Flags can be set to 0 to use defaults. DONT_CLEAR_MEM (default) - do not clear memory CLEAR_MEM - clear display buffer memory DISP_FIFO_OFF - turn off display FIFO (blank screen except for cursor or ink layer) DISP_FIFO_ON (default) - turn on display FIFO Return Value: ERR_OK - no problems encountered ERR_FAILED - unable to complete operation. Occurs as a result of requesting parameters that exceed timing specifications. Example: seSetDisplayMode(DevID, DISP_MODE_LCD, CLEAR_MEM | DISP_FIFO_OFF); The above will initialize for the LCD, and then clear display buffer memory and blank the screen. The advantage to this approach is that afterwards the application can write to the display without showing the image until memory is completely updated; the application would then call seDisplayFIFO(DevID, ON). EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 11: HARDWARE ABSTRACTION LAYER (HAL) int seInitHal(void) Description: This function initializes variable used by the HAL library. This function must be called once when the application starts. Normally programmers do not have to concern themselves with seInitHal(). On PC platforms, seRegisterDevice() automatically calls seInitHal(). Consecutive calls to seRegisterDevice() will not call seInitHal() again. On non-PC platforms the start-up code, supplied by Seiko, will call seInitHal(). If however support code for a new operating platform is written the programmer must ensure that seInitHAL is called prior to calling other HAL functions. Parameters: None Return Value: ERR_OK S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) - operation completed with no problems EPSON 2-35 11: HARDWARE ABSTRACTION LAYER (HAL) General HAL Support General HAL support covers the miscellaneous functions. There is usually no more than one or two functions devoted to any particular aspect of S1D13505 operation. int seGetId(int DevID, int * pId) Description: Reads the S1D13505 revision code register to determine the chip product and revisions. The interpreted value is returned in pID. Parameters: Device pId - registered device ID - pointer to the byte to receive the controller ID. For the S1D13505 the return values are currently: ID_S1D13505 ID_S1D13505F00A ID_UNKNOWN Other HAL libraries will return their respective controller IDs upon detection of their controller. Return Value: ERR_OK - operation completed with no problems ERR_UNKNOWN_DEVICE - returned when pID returns ID_UNKNOWN. The HAL was unable to identify the display controller. Note: seGetId() will disable hardware suspend Intel platforms, and will enable the host interface (register [1Bh]) on all platforms. void seGetHalVersion(const char ** pVersion, const char ** pStatus, const char **pStatusRevision) Description: Retrieves the HAL library version. The return values are all ASCII strings. A typical return would be: "1.01" (HAL version 1.01), "B" (The 'B' is the beta designator), "5" (This example would be Beta5, if pStatus is NULL the so should pStatusRevision). Parameters: pVersion - must point to an allocated string of size VER_SIZE pStatus - must point to an allocated string of size STATUS_SIZE pStatusRevision - must point to an allocated string of size STAT_REV_SIZE Return Value: None int seGetMemSize(int DevID, DWORD * pSize) 2-36 Description: This routine returns the amount of installed video memory. The memory size is determined by reading the status of MD6 and MD7. *pSize will be set to either 0x80000 (512 KB) or 0x200000 (2 MB). Parameters: DevID pSize - registered device ID - pointer to a DWORD to receive the size Return Value: ERR_OK - the operation completed successfully EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 11: HARDWARE ABSTRACTION LAYER (HAL) int seGetLastUsableByte(int DevID, DWORD * pLastByte) Description: Calculates the offset of the last byte in the display buffer which can be used by applications. Locations following LastByte are reserved for system use. Items such as the half frame buffer, hardware cursor and ink layer will be located in memory from GetLastUsableByte() + 1 to the end of memory. It is assumed that the registers will have been initialized before calling seGetLastUsableByte(). Factors such as the half frame buffer and hardware cursor / ink layer being enabled dynamically alter the amount of display buffer available to an application. Call seGetLastUsableByte() any time the true end of usable memory is required. Parameters: DevID - registered device ID pLastByte - pointer to a DWORD to receive the offset to the last usable byte of display buffer Return Value: ERR_OK - operation completed with no problems int seGetBytesPerScanline(int DevID, UINT * pBytes) Description: Determines the number of bytes per scan line of current display mode. It is assumed that the registers have already been correctly initialized before seGetBytesPerScanline() is called. The number of bytes per scanline calculation includes the value in the offset register. For rotated modes the return value will be either 1024 or 2048 to reflect the 1024 x 1024 virtual area of the rotated memory. Parameters: DevID pBytes - registered device ID - pointer to an integer which indicates the number of bytes per scan line Return Value: ERR_OK - operation completed with no problems ERR_FAILED - returned when this function is called for rotated display modes other than 8 or 16 bpp. int seGetScreenSize(int DevID, UINT * Width, UINT * Height) Description: Gets the width and height in pixels of the display surface. The width and height are derived by reading the horizontal and vertical timing registers and calculating the dimensions. When the display is in portrait mode the dimensions will be swapped. (i.e. a 640x480 display in portrait mode will return a width and height of 480 and 640, respectively. Parameters: DevID Width Height - registered device ID - unsigned integer to receive the display width - unsigned integer to receive the display height Return value: ERR_OK - the operation completed successfully S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-37 11: HARDWARE ABSTRACTION LAYER (HAL) int seSelectBusWidth(int DevID, int Width) Description: Call this function to select the interface bus width on the ISA evaluation card. Selectable widths are 8 bit and 16 bit. Parameters: DevID Width - registered device ID - desired bus width. Must be 8 or 16. Return Value: ERR_OK ERR_FAILED - the operation completed successfully - the function was called on a non-ISA platform or width was not set to 8 or 16. Note: This call applies to the S1D13505 ISA evaluation cards only. int seGetHostBusWidth(int DevID, int * Width) Description: This function retrieves the default (as set by 13505CFG.EXE) value for the host bus interface width and returns it in Width. Parameters: DevID Width - registered device ID - integer to hold the returned value of the host bus width Return Value: ERR_OK - the function completed successfully int seDisplayEnable(int DevID, BYTE State) Description: This routine turns the display on or off by enabling or disabling the ENABLE bit of the display device (PANEL, CRT, or SIMULTANEOUS). The configuration defined in 13505CFG determines which device(s) will be affected. Parameters: DevID State - registered device ID - set to ON or OFF to respectively enable or disable the display Return Value: ERR_OK - the function completed successfully int seDisplayFifo(int DevID, BYTE State) Description: This routine turns the display on or off by enabling or disabling the display FIFO (the hardware cursor and ink layer are not affected). Enabling and disabling the display FIFO has a much faster and cleaner appearing effect when the display is to be blanked and it allows full CPU bandwidth to the display buffer. Parameters: DevID State - registered device ID - set to ON or OFF to respectively enable or disable the display FIFO Return Value: ERR_OK - the function completed successfully Note: Disabling the display FIFO will force all display data outputs to zero but horizontal and vertical sync pulses and panel power supply are still active. 2-38 EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 11: HARDWARE ABSTRACTION LAYER (HAL) int seDelay(int DevID, DWORD Seconds) Description: This function will delay for the number of seconds given in Seconds before returning to the caller. This function was originally intended for non-PC platforms. Information on how to access the timers was not always immediately available however we do know frame rate and can use that for timing calculations. The S1D13505 registers must be initialized for this function to work correctly. PC platform function calls the C timing functions and is therefore independent of the register settings. Parameters: DevID Seconds - registered device ID - time to delay in seconds Return Value: ERR_OK - operation completed with no problems ERR_FAILED - returned only on non-PC platforms when the S1D13505 registers have not bee initialized Advanced HAL Functions Advanced HAL functions include the functions to support split and virtual screen operation and are the same features that were described in the section on advanced programming techniques. int seSplitInit(int DevID, DWORD Scrn1Addr, DWORD Scrn2Addr) Description: This function prepares the system for split screen operation. In order for split screen to function the starting address in display buffer for the upper portion screen 1, and the lower portion - screen 2 must be specified. Screen 1 is always displayed above screen 2 on the display regardless of the location of their respective starting addresses. Parameters: DevID Scrn1Addr Scrn2Addr - registered device ID - offset in display buffer, in bytes, to the start of screen 1 - offset in display buffer, in bytes, to the start of screen 2 Return Value: ERR_OK - operation completed with no problems Note: It is assumed that the system has been properly initialized prior to calling seSplitInit(). int seSplitScreen(int DevID, int WhichScreen, long VisibleScanlines) Description: Changes the relevant registers to adjust the split screen according to the number of visible lines requested. WhichScreen determines which screen, screen 1 or screen 2, to change. The smallest screen 1 can be set to is one line. This is due to the way the register values are used internally on the S1D13505. Setting the line compare register to zero results in one line of screen 1 being displayed before starting on screen 2. Parameters: DevID WhichScreen Return Value: ERR_OK - operation completed with no problems ERR_HAL_BAD_ARG - argument VisibleScanlines is negative or is greater than vertical panel size or WhichScreen is not SCREEN1 or SCREEN2. - registered device ID - must be set to 1 or 2, or use the constants SCREEN1 or SCREEN2, to identify which screen to base calculations on VisibleScanlines - number of lines to show for the selected screen Note: seSplitInit() must be called before calling seSplitScreen(). S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-39 11: HARDWARE ABSTRACTION LAYER (HAL) int seVirtInit(int DevID, DWORD VirtX, DWORD * VirtY) Description: This function prepares the system for virtual screen operation. The programmer passes the desired virtual width, in pixels, as VirtX. When the routine returns VirtY will contain the maximum number of line that can be displayed at the requested virtual width. Parameter: DevID VirtX VirtY Return Value: - registered device ID - horizontal size of virtual display in pixels. (Must be greater or equal to physical size of display) - a return placeholder for the maximum number of lines available at the requested and returns value in yVirt. ERR_OK - operation completed with no problems ERR_HAL_BAD_ARG - returned in three situations 1) the virtual width (VirtX) is greater than the largest attainable width (The maximum allowable xVirt is 0x3FF * (16 / bpp)) 2) the virtual width is less than the physical width or 3) the maximum number of lines is less than the physical number of lines Note: The system must have been properly initialized prior to calling seVirtInit(). int seVirtMove(int DevID, int WhichScreen, DWORD x, DWORD y) Description: This routine pans and scrolls the display. In the case where split screen operation is being used the WhichScreen argument specifies which screen to move. The x and y parameters specify, in pixels, the starting location in the virtual image for the top left corner of the applicable display. Parameter: DevID - registered device ID WhichScreen - must be set to 1 or 2, or use the constants SCREEN1 or SCREEN2, to identify which screen to base calculations on x - new starting X position in pixels y - new starting Y position in pixels Return Value: ERR_OK- operation completed with no problems ERR_HAL_BAD_ARG- there are several reasons for this return value: 1) WhichScreen is not SCREEN1 or SCREEN2. 2) the y argument is greater than the last available line less the screen height. Note: seVirtInit() must be been called before calling seVirtMove(). 2-40 EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 11: HARDWARE ABSTRACTION LAYER (HAL) Register / Memory Access The Register/Memory Access functions provide access to the S1D13505 registers and display buffer through the HAL. int seSetReg(int DevID, int Index, BYTE Value) Description: Writes Value to the register specified by Index. Parameters: DevID Index Value - registered device ID - register index to set - value to write to the register Return Value: ERR_OK - operation completed with no problems int seGetReg(int DevID, int Index, BYTE * pValue) Description: Reads the value in the register specified by index. Parameters: Device Index pValue - registered device ID - register index to read - return value of the register Return Value: ERR_OK - operation completed with no problems int seWriteDisplayBytes(int DevID, DWORD Offset, BYTE Value, DWORD Count) Description: This routine writes one or more bytes to display buffer at the offset specified by Addr. If a count greater than one is specified all bytes will have the same value. Parameters: DevID Offset Value Count Return Value: ERR_OK - operation completed with no problems ERR_HAL_BAD_ARG - if the value for Addr is greater than the amount of installed memory or if Addr plus Count is greater than the installed memory. - registered device ID - offset from start of the display buffer - BYTE value to write - number of bytes to write int seWriteDisplayWords(int DevID, DWORD Offset, WORD Value, DWORD Count) Description: Writes one or more words to the display buffer. Parameters: DevID Offset Value Count Return Value: ERR_OK - operation completed with no problems ERR_HAL_BAD_ARG - if the value for Addr is greater than the amount of installed memory or if Addr plus Count is greater than the installed memory. S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) - registered device ID - offset from start of the display buffer - WORD value to write - number of words to write EPSON 2-41 11: HARDWARE ABSTRACTION LAYER (HAL) int seWriteDisplayDwords(int DevID, DWORD Offset, DWORD Value, DWORD Count) Description: Writes one or more dwords to the display buffer. Parameters: DevID Offset Value Count Return Value: ERR_OK - operation completed with no problems ERR_HAL_BAD_ARG - if the value for Addr is greater than the amount of installed memory or if Addr plus Count is greater than the installed memory. - registered device ID - offset from start of the display buffer - DWORD value to write - number of dwords to write int seReadDisplayByte(int DevID, DWORD Offset, BYTE *pByte) Description: Reads a byte from the display buffer at the specified offset and returns the value in pByte. Parameters: DevID Offset pByte Return Value: ERR_OK - operation completed with no problems ERR_HAL_BAD_ARG - if the value for Addr is greater than the amount of installed memory. - registered device ID - offset, in bytes, from start of the display buffer - return value of the display buffer location. int seReadDisplayWord(int DevID, DWORD Offset, WORD *pWord) Description: Reads a word from the display buffer at the specified offset and returns the value in pWord. Parameters: DevID Offset pWord Return Value: ERR_OK - operation completed with no problems ERR_HAL_BAD_ARG - if the value for Addr is greater than the amount of installed memory. - registered device ID - offset, in bytes, from start of the display buffer - return value of the display buffer location int seReadDisplayDword(int DevID, DWORD Offset, DWORD *pDword) 2-42 Description: Reads a dword from the display buffer at the specified offset and returns the value in pDword. Parameters: DevID Offset pDword Return Value: ERR_OK - operation completed with no problems ERR_HAL_BAD_ARG - if the value for Addr is greater than the amount of installed memory. - registered device ID - offset from start of the display buffer - return value of the display buffer location EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 11: HARDWARE ABSTRACTION LAYER (HAL) Color Manipulation The functions in the Color Manipulation section deal with altering the color values in the Look-Up Table directly through the accessor functions and indirectly through the color depth setting functions. int seSetLut(int DevID, BYTE *pLut, int Count) Description: This routine can write one or more LUT entries. The writes always start with LookUp Table index 0 and continue for Count entries. A Look-Up Table entry consists of three bytes, one each for Red, Green, and Blue. The color information is stored in the four most significant bits of each byte. Parameters: DevID - registered device ID pLut - pointer to an array of BYTE lut[16][3] lut[x][0] == RED component lut[x][1] == GREEN component lut[x][2] == BLUE component Count - the number of LUT entries to write. Return Value: ERR_OK - operation completed with no problems int seGetLut(int DevID, BYTE *pLUT, int Count) Description: This routine reads one or more LUT entries and puts the result in the byte array pointed to by pLUT. A Look-Up Table entry consists of three bytes, one each for Red, Green, and Blue. The color information is stored in the four most significant bits of each byte. Parameters: Return Value: DevID pLUT Count - registered device ID - pointer to an array of BYTE lut[16][3] pLUT must point to enough memory to hold Count x 3 bytes of data. - the number of LUT elements to read. ERR_OK - operation completed with no problems int seSetLutEntry(int DevID, int Index, BYTE *pEntry) Description: This routine writes one LUT entry. Unlike seSetLut, the LUT entry indicated by Index can be any value from 0 to 255. A Look-Up Table entry consists of three bytes, one each for Red, Green, and Blue. The color information is stored in the four most significant bits of each byte. Parameters: DevID Index pLUT - registered device ID - index to LUT entry (0 to 15) - pointer to an array of three bytes. Return Value: ERR_OK - operation completed with no problems S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-43 11: HARDWARE ABSTRACTION LAYER (HAL) int seGetLutEntry(int DevID, int index, BYTE *pEntry) Description: This routine reads one LUT entry from any index. Parameters: DevID Index pEntry - registered device ID - index to LUT entry (0 to 15) - pointer to an array of three bytes Return Value: ERR_OK - operation completed with no problems int seSetBitsPerPixel(int DevID, UINT BitsPerPixel) Description: This routine sets the system color depth. Valid arguments for BitsPerPixel is are: 1, 2, 4, 8, 15, and 16. After performing validity checks for the requested color depth the appropriate registers are changed and the Look-Up Table is set its default value. This call is similar to a mode set call on a standard VGA. Parameter: DevID BitsPerPixel - registered device ID - desired color depth in bits per pixel Return Value: ERR_OK - operation completed with no problems ERR_FAILED - possible causes for this error message include: 1) attempted to set 15/16 bpp at 800x600 resolution (not supported on the S1D13505) 2) attempted to set other than 8 or 15/16 bpp in portrait mode (portrait mode only supports 8 and 15/16 bpp) 3) factors such as input clock and memory speed will affect the ability to set some color depths. If the requested color depth cannot be set this call will fail int seGetBitsPerPixel(int DevID, UINT * pBitsPerPixel) Description: This function reads the S1D13505 registers to determine the current color depth and returns the result in pBitsPerPixel. Determines the color depth of current display mode. 2-44 Parameters: DevID - registered device ID pBitsPerPixel - return value is the current color depth Return Value: ERR_OK - operation completed with no problems EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 11: HARDWARE ABSTRACTION LAYER (HAL) Drawing The Drawing section covers HAL functions that deal with displaying pixels, lines and shapes. int seSetPixel(int DevID, long x, long y, DWORD Color) Description: Draws a pixel at coordinates x,y in the requested color. This routine can be used for any color depth. Parameters: DevID x y Color Return Value: ERR_OK - operation completed with no problems - registered device ID - horizontal coordinate of the pixel (starting from 0) - vertical coordinate of the pixel (starting from 0) - at 1, 2, 4, and 8 bpp Color is an index into the LUT. At 15 and 16 bpp Color defines the color directly (i.e. rrrrrggggggbbbbb) int seGetPixel(int DevID, long x, long y, DWORD *pColor) Description: Reads the pixel color at coordinates x,y. This routine can be used for any color depth. Parameters: DevID x y pColor Return Value: ERR_OK - operation completed with no problems - registered device ID - horizontal coordinate of the pixel (starting from 0) - vertical coordinate of the pixel (starting from 0) - at 1, 2, 4, and 8 bpp pColor points to an index into the LUT. At 15 and 16 bpp pColor points to the color directly (i.e. rrrrrggggggbbbbb) int seDrawLine(int DevID, long x1, long y1, long x2, long y2, DWORD Color) Description: This routine draws a line one the display from the endpoints defined by x1,y1 to x2,y2 in the requested Color. Currently seDrawLine() only draws horizontal and vertical lines. Parameters: Device (x1, y1) (x2, y2) Color - registered device ID - top left corner of line - bottom right corner of line (see note below) - color of line - for 1, 2, 4, and 8 bpp, 'Color' refers to the pixel value which points to the respective LUT/DAC entry. - for 15 and 16 bpp, 'Color' refers to the pixel value which stores the red, green, and blue intensities within a WORD. Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid. S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-45 11: HARDWARE ABSTRACTION LAYER (HAL) int seDrawRect(int DevID, long x1, long y1, long x2, long y2, DWORD Color, BOOL SolidFill) Description: This routine draws and optionally fills a rectangular area of display buffer. The upper right corner of the rectangle is defined by x1,y1 and the lower right corner is defined by x2,y2. The color, defined by Color, applies to the border and to the optional fill. Parameters: DevID x1, y1 x2, y2 Color Return Value: ERR_OK - operation completed with no problems - registered device ID - top left corner of the rectangle (in pixels) - bottom right corner of the rectangle (in pixels) - the color to draw the rectangle outline and fill with - at 1, 2, 4, and 8 bpp Color is an index into the Look-Up Table. - at 15/16 bpp Color defines the color directly (i.e. rrrrrggggggbbbbb) SolidFill - flag whether to fill the rectangle or simply draw the border. - set to 0 for no fill, set to non-0 to fill the inside of the rectangle int seDrawEllipse(int DevID, long xc, long yc, long xr, long yr, DWORD Color, BOOL SolidFill) Description: This routine draws an ellipse with the center located at xc,yc. The xr and yr parameters specify the x any y radii, in pixels, respectively. The ellipse will be drawn in the color specified in 'Color'. Parameters: DevID xc, yc xr yr Color Return Value: ERR_OK - operation completed with no problems - registered device ID - the center location of the ellipse (in pixels) - horizontal radius of the ellipse (in pixels) - vertical radius of the ellipse (in pixels) - the color to draw the ellipse - at 1, 2, 4, and 8 bpp Color is an index into the Look-Up Table. - at 15/16 bpp Color defines the color directly (i.e. rrrrrggggggbbbbb) SolidFill - unused Note: The 'SolidFill' argument is currently unused and is included for future considerations. int seDrawCircle(int DevID, long xc, long yc, long Radius, DWORD Color, BOOL SolidFill) Description: This routine draws an circle with the center located at xc,yc and a radius of Radius. The circle will be drawn in the color specified in Color. Parameters: DevID xc, yc Radius Color Return Value: ERR_OK - operation completed with no problems - registered device ID - the center of the circle (in pixels) - the circles radius (in pixels) - the color to draw the ellipse - at 1, 2, 4, and 8 bpp Color is an index into the Look-Up Table. - at 15/16 bpp Color defines the color directly (i.e. rrrrrggggggbbbbb) SolidFill - unused Note: The SolidFill argument is currently unused and is included for future considerations. 2-46 EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 11: HARDWARE ABSTRACTION LAYER (HAL) Hardware Cursor The routines in this section support hardware cursor functionality. Several of the calls look similar to normal drawing calls (i.e. seDrawCursorLine()) however these calls remove the programmer from having to know the particulars of the cursor memory location, layout and whether portrait mode is enabled. int seInitCursor(int DevID) Description: Prepares the hardware cursor for use. This consists of determining a location in display buffer for the cursor, setting cursor memory to the transparent color and enabling the cursor. When this call returns the cursor is enabled, the cursor image is transparent and ready to be drawn. Parameters: DevID - a registered device ID Return Value: ERR_OK - operation completed with no problems int seCursorOn(int DevID) Description: This function enables the cursor after it has been disabled through a call to seCursorOff(). After enabling the cursor will have the same shape and position as it did prior to being disabled. The exception to the size and position occurs if the ink layer was used while the cursor was disabled. Parameters: DevID - a registered device ID Return Value: ERR_OK - operation completed with no problems int seCursorOff(int DevID) Description: This routine disables the cursor. While disabled the cursor is invisible. Parameters: DevID - a registered device ID Return Value: ERR_OK - operation completed with no problems int seGetCursorStartAddr(int DevID, DWORD * Offset) Description: This function retrieves the offset to the first byte of hardware cursor memory. Parameters: DevID Offset - a registered device ID - a DWORD to hold the return value. Return Value: ERR_OK - operation completed with no problems int seMoveCursor(int DevID, long x, long y) Description: Moves the upper left corner of the hardware cursor to the pixel position x,y. Parameters: DevID x, y - a registered device ID - the x,y position (in pixels) to move the cursor to Return Value: ERR_OK - operation completed with no problems S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-47 11: HARDWARE ABSTRACTION LAYER (HAL) int seSetCursorColor(int DevID, int Index, DWORD Color) Description: Sets the color of the specified cursor index to 'Color'. The user definable hardware cursor colors are 16-bit 5-6-5 RGB colors. The hardware cursor image is always 2 bpp or four colors. Two of the colors are defined to be transparent and inverse. This leaves two colors which are user definable. Parameters: DevID Index Color - a registered device ID - the cursor index to set. Valid values are 0 and 1 - a DWORD value which hold the requested color Return Value: ERR_OK - operation completed with no problems ERR_FAILED - returned if Index if other than 0 or 1 int seSetCursorPixel(int DevID, long x, long y, DWORD Color) Description: Draws a single pixel into the hardware cursor. The pixel will be of color 'Color' located at x,y pixels relative to the top left of the hardware cursor. The value of 'Color' must be 0 to 3. Values 0 and 1 refer to the two user definable colors. If 'Color' is 2 then the pixel will be transparent and if the value is 3 the pixel will be an inversion of the underlying screen color. Parameters: DevID x, y Color - a registered device ID - draw coordinates, in pixels, relative to the top left corner of the cursor - a value of 0 to 3 to draw the pixel with Return Value: ERR_OK - operation completed with no problems int seDrawCursorLine(int DevID, long x1, long y1, long x2, long y2, DWORD Color) Description: Draws a line between the two endpoints, x1,y1 and x2,y2, in the hardware cursor display buffer using color 'Color'. The value of 'Color' must be 0 to 3. Values 0 and 1 refer to the two user definable colors. If 'Color' is 2 then the pixel will be transparent and if the value is 3 the pixel will be an inversion of the underlying screen color. 2-48 Parameters: DevID x1,y1 x2,y2 Color - a registered device ID - first line endpoint (in pixels) - second line endpoint (in pixels) - a value of 0 to 3 to draw the pixel with Return Value: ERR_OK - operation completed with no problems EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 11: HARDWARE ABSTRACTION LAYER (HAL) int seDrawCursorRect(int DevID, long x1, long y1, long x2, long y2, DWORD Color, BOOL SolidFill) Description: This routine will draw a rectangle in hardware cursor memory. The upper left corner of the rectangle is defined by the point x1,y1 and the lower right is the point x2,y2. Both points are relative to the upper left corner of the cursor. The value of 'Color' must be 0 to 3. Values 0 and 1 refer to the two user definable colors. If 'Color' is 2 then the pixel will be transparent and if the value is 3 the pixel result will be an inversion of the underlying screen color. If 'SolidFill' is specified the interior of the rectangle will be filled with 'Color', otherwise the rectangle is only outlined in 'Color'. Parameters: DevID x1,y1 x2,y2 Color SolidFill - a registered device ID - upper left corner of the rectangle (in pixels) - lower right corner of the rectangle (in pixels) - a 0 to 3 value to draw the rectangle with - flag for filling the rectangle interior - if equal to 0 then outline the rectangle if not equal to 0 then fill the rectangle Return Value: ERR_OK - operation completed with no problems int seDrawCursorEllipse(int DevID, long xc, long yc, long xr, long yr, DWORD Color, BOOL SolidFill) Description: This routine draws an ellipse within the hardware cursor display buffer. The ellipse will be centered on the point xc,yc and will have a horizontal radius of xr and a vertical radius of yr. The value of 'Color' must be 0 to 3. Values 0 and 1 refer to the two user definable colors. If 'Color' is 2 then the pixel will be transparent and if the value is 3 the pixel will be an inversion of the underlying screen color. Currently seDrawCursorEllipse() does not support solid fill of the ellipse. Parameters: DevID xc, yc xr yr Color SolidFill - a registered device ID - center of the ellipse (in pixels) - horizontal radius (in pixels) - vertical radius (in pixels) - 0 to 3 value to draw the pixels with - flag to solid fill the ellipse (not currently used) Return Value: ERR_OK - operation completed with no problems S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-49 11: HARDWARE ABSTRACTION LAYER (HAL) int seDrawCursorCircle(int DevID, long x, long y, long Radius, DWORD Color, BOOL SolidFill) Description: This routine draws a circle in hardware cursor display buffer. The center of the circle will be at x,y and the circle will have a radius of 'Radius' pixels. The value of 'Color' must be 0 to 3. Values 0 and 1 refer to the two user definable colors. If 'Color' is 2 then the pixel will be transparent and if the value is 3 the pixel will be an inversion of the underlying screen color. Currently seDrawCursorCircle() does not support the solid fill option. Parameters: DevID x,y Radius Color SolidFill - a registered device ID - center of the circle (in pixels) - radius of the circle (in pixels) - 0 to 3 value to draw the circle with - flag to solid fill the circle (currently not used) Return Value: ERR_OK - operation completed with no problems Ink Layer The functions in this section support the hardware ink layer. Overall these functions are nearly identical to the hardware cursor routines. In fact the same S1D13505 hardware is used for both features which means that only the cursor or the ink layer can be active at any given time.The difference between the hardware cursor and the ink layer is that in cursor mode the image is a maximum of 64x64 pixels and can be moved around the display while in ink layer mode the image is as large as the display and is in a fixed position. In both cases the number of colors and the way the colors are handled are identical. int seInitInk(int DevID) Description: This routine prepares the ink layer for use. This consists of determining the start address for the ink layer, setting the ink layer to the transparent color and enabling the ink layer. When this function returns the ink layer is enable, transparent and ready to be drawn on. Parameters: DevID - a registered device ID Return Value: ERR_OK - operation completed with no problems ERR_FAILED - if the ink layer cannot be enabled do to timing constraints this value will be returned. int seInkOn(int DevID) 2-50 Description: Enables the ink layer after a call to seInkOff(). If the hardware cursor has not been used between the time seInkOff() was called and this call then the contents of the ink layer should be exactly as it was prior to the call to seInkOff(). Parameters: DevID - a registered device ID Return Value: ERR_OK - operation completed with no problems EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 11: HARDWARE ABSTRACTION LAYER (HAL) int seInkOff(int DevID) Description: Disables the ink layer. When disabled the ink layer is not visible. Parameters: DevID - a registered device ID Return Value: ERR_OK - operation completed with no problems int seGetInkStartAddr(int DevID, DWORD * Offset) Description: This function retrieves the offset to the first byte of hardware ink layer memory. Parameters: DevID Offset - a registered device ID - a DWORD to hold the return value. Return Value: ERR_OK - operation completed with no problems int seSetInkColor(int DevID, int Index, DWORD Color) Description: Sets the color of the specified cursor index to 'Color'. The user definable hardware cursor colors are sixteen bit 5-6-5 RGB colors. The hardware cursor image is always 2 bpp or four colors. Two of the colors are defined to be transparent and inverse. This leaves two colors which are user definable. Parameters: DevID Index Color - a registered device ID - the index, 0 or 1, to write the color to - a sixteen bit RRRRRGGGGGGBBBBB color to write to 'Index' Return Value: ERR_OK - operation completed with no problems ERR_FAILED - an index other than 0 or 1 was specified. int seSetInkPixel(int DevID, long x, long y, DWORD Color) Description: Sets one pixel located at x,y to the value 'Color'. The point x,y is relative to the upper left corner of the display. The value of 'Color' must be 0 to 3. Values 0 and 1 refer to the two user definable colors. If 'Color' is 2 then the pixel will be transparent and if the value is 3 the pixel will be an inversion of the underlying screen color. Parameters: DevID x,y Color - a registered device ID - coordinates of the pixel to draw - a 0 to 3 value to draw the pixel with Return Value: ERR_OK - operation completed with no problems S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-51 11: HARDWARE ABSTRACTION LAYER (HAL) int seDrawInkLine(int DevID, long x1, long y1, long x2, long y2, DWORD Color) Description: This routine draws a line in 'Color' between the endpoints x1,y1 and x2,y2. The value of 'Color' must be 0 to 3. Values 0 and 1 refer to the two user definable colors. If 'Color' is 2 then the pixel will be transparent and if the value is 3 the pixel will be an inversion of the underlying screen color. Parameters: DevID x1,y1 x1,y2 Color - a registered device ID - first endpoint of the line (in pixels) - second endpoint of the line (in pixels) - a value from0 to 3 to draw the line with Return Value: ERR_OK - operation completed with no problems int seDrawInkRect(int DevID, long x1, long y1, long x2, long y2, DWORD Color, BOOL SolidFill) Description: Draws a rectangle of color 'Color' and optionally fills it. The upper left corner of the rectangle is the point x1,y1 and the lower right corner of the rectangle is the point x2,y2. The value of 'Color' must be 0 to 3. Values 0 and 1 refer to the two user definable colors. If 'Color' is 2 then the pixel will be transparent and if the value is 3 the pixel will be an inversion of the underlying screen color. Parameters: DevID x1,y1 x2.Y2 Color SolidFill - a registered device ID - upper left corner of the rectangle (in pixels) - lower right corner of the rectangle (in pixels) - a two bit value (0 to 3) to draw the rectangle with - a flag to indicate the interior should be filled Return Value: ERR_OK - operation completed with no problems int seDrawInkEllipse(int DevID, long xc, long yc, long xr, long yr, DWORD Color, BOOL SolidFill) Description: This routine draws an ellipse with the center located at xc,yc. The xr and yr parameters specify the x any y radii, in pixels, respectively. The ellipse will be drawn in the color specified by 'Color'. The value of 'Color' must be 0 to 3. Values 0 and 1 refer to the two user definable colors. If 'Color' is 2 then the pixel will be transparent and if the value is 3 the pixel will be an inversion of the underlying screen color. This solid fill option is not yet available for this function. 2-52 Parameters: DevID xc,yc xr yr Color SolidFill - a registered device ID - center point for the ellipse (in pixels) - horizontal radius of the ellipse (in pixels) - vertical radius of the ellipse (in pixels) - a two bit value (0 to 3) to draw the rectangle with - flag to enable filling the interior of the ellipse (not used) Return Value: ERR_OK - operation completed with no problems EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 11: HARDWARE ABSTRACTION LAYER (HAL) int seDrawInkCircle(int DevID, long x, long y, long Radius, DWORD Color, BOOL SolidFill) Description: This routine draws a circle in the ink layer display buffer. The center of the circle will be at x,y and the circle will have a radius of 'Radius' pixels. The value of 'Color' must be 0 to 3. Values 0 and 1 refer to the two user definable colors. If 'Color' is 2 then the pixel will be transparent and if the value is 3 the pixel will be an inversion of the underlying screen color. Currently seDrawCursorCircle() does not support the solid fill option. Parameters: DevID x,y Radius Color SolidFill - a registered device ID - center of the circle (in pixels) - circle radius (in pixels) - a two bit (0 to 3) value to draw the circle with - flag to fill the interior of the circle (not used) Return Value: ERR_OK - operation completed with no problems Power Save This section covers the HAL functions dealing with the Power Save features of the S1D13505. int seSWSuspend(int DevID, BOOL Suspend) Description: Causes the S1D13505 to enter software suspend mode. When software suspend mode is engaged the display is disabled and display buffer is inaccessible. In this mode the registers and the LUT are accessible. Parameters: DevID Suspend - a registered device ID - boolean flag to indicate which state to engage. - enter suspend mode when non-zero and return to normal power when equal to zero. Return Value: ERR_OK - operation completed with no problems int seHWSuspend(int DevID, BOOL Suspend) Description: Causes the S1D13505 to enter/leave hardware suspend mode. This option in only supported on S5U13505P00C ISA evaluation boards. When hardware suspend mode is engaged the display is disabled and display buffer is inaccessible and the registers and LUT are inaccessible. Parameters: DevID Suspend - a registered device ID - boolean flag to indicate which state to engage. - enter suspend mode when non-zero and return to normal power when equal to zero. Return Value: ERR_OK - operation completed with no problems S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-53 11: HARDWARE ABSTRACTION LAYER (HAL) X-LIB Support int seGetLinearDispAddr(int device, DWORD * pDispLogicalAddr) 2-54 Description: Determines the logical address of the start of the display buffer. This address may be used in programs for direct control over the display buffer. Parameter: device - registered device ID pDispLogicalAddr - logical address is returned in this variable Return Value: ERR_OK - operation completed with no problems EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 12: SAMPLE CODE 12 SAMPLE CODE 12.1 Introduction There are two included examples of programming the S1D13505 color graphics controller. First is a demonstration using the HAL library and the second without. These code samples are for example purposes only. Lastly, are three header files that may make some of the structures used clearer. Sample Code Using the 13505HAL API */ // Sample code using 1355HAL API */ */ **------------------------------------------------------------------------** ** Created 1998, Epson Research & Development ** Vancouver Design Centre ** Copyright (c) Seiko Epson Corp. 1998. All rights reserved. ** ** The HAL API code is configured for the following: ** ** 25.175 MHz ClkI ** 640x480 8 bit dual color STN panel @60Hz ** 50 ns EDO, 32 ms (self) refresh time ** Initial color depth - 8 bpp ** **------------------------------------------------------------------------*/ #include <stdio.h> #include <stdlib.h> #include <string.h> #include "hal.h" * Structures, constants and prototypes. */ #include "appcfg.h" * HAL configuration information. */ / / /*--------------------------------------------------------------------------*/ void main(void) { int ChipId; int Device; /* ** Initialize the HAL. ** This step sets up the HAL for use but does not access the 1355. */ switch (seRegisterDevice(&HalInfo, &Device)) { case ERR_OK: break; case HAL_DEVICE_ERR: printf("\nERROR: Too many devices registered."); exit(1); default: printf("\nERROR: Could not register SED1355 device."); exit(1); } /* ** Identify that this is indeed an SED1355. */ seGetId( Device, &ChipId); if (ID_S1D13505F00A != ChipId) { printf("\nERROR: Did not detect SED1355."); exit(1); } /* ** Initialize the SED1355. S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-55 12: SAMPLE CODE ** This step will actually program the registers with values taken from ** the default register table in appcfg.h. */ if (ERR_OK != seSetInit(Device)) { printf("\nERROR: Could not initialize device."); exit(1); } /* ** The default initialization clears the display. ** Draw a 100x100 red rectangle in the upper left corner (0,0) ** of the display. */ seDrawRect(Device, 0, 0, 100, 100, 1, TRUE); /* ** Init the HW cursor. The HAL performs several calculations to ** determine the best location to place the cursor image and ** will use that location from here on. ** The background must be set to transparent. */ seInitCursor(Device); seDrawCursorRect(Device, 0, 0, 63, 63, 2, TRUE); /* ** Set the first user definable color to black and ** the second user definable color to white. */ seSetCursorColor(Device, 0, 0); seSetCursorColor(Device, 1, 0xFFFFFFFF); /* ** Draw a hollow rectangle around the cursor and move ** the cursor to 101,101. */ seDrawCursorRect(Device, 0, 0, 63, 63, 1, FALSE); seMoveCursor(Device, 101, 101); exit(0); 2-56 EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 12: SAMPLE CODE Sample Code Without Using the 13505HAL API /* **=========================================================================== ** INIT13505.C - sample code demonstrating the initialization of the SED1355. ** Beta release 2.0 98-10-29 ** ** The code in this example will perform initialization to the following ** specification: ** ** - 640 x 480 dual 16-bit color passive panel. ** - 75 Hz frame rate. ** - 8 BPP (256 colors). ** - 33 MHz input clock. ** - 2 MB of 60 ns EDO memory. ** ** *** This is sample code only! *** ** This means: ** 1) Generic C is used. I assume that pointers can access the ** relevent memory addresses (this is not always the case). ** i.e. using the 1355B0B card on an Intel 16 bit platform will require ** changes to use a DOS extender to access memory and registers. ** 2) Register setup is done with discrete writes rather than being ** table driven. This allows for clearer commenting. A real program ** would probably store the register settings in an array and loop ** through the array writing each element to a control register. ** 3) The pointer assignment for the register offset does not work on ** Intel 16 bit platforms. ** **--------------------------------------------------------------------------** Copyright (c) 1998 Epson Research and Development, Inc. ** All Rights Reserved. **=========================================================================== */ /* ** Note that only the upper four bits of the LUT are actually used. */ unsigned char LUT8[256*3] = { /* Primary and secondary colors */ 0x00, 0x00, 0x00, 0x00, 0x00, 0xA0, 0x00, 0xA0, 0x00, 0x00, 0xA0, 0xA0, 0xA0, 0x00, 0x00, 0xA0, 0x00, 0xA0, 0xA0, 0xA0, 0x00, 0xA0, 0xA0, 0xA0, 0x50, 0x50, 0x50, 0x00, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0x00, 0xF0, 0xF0, 0xF0, 0x00, 0x00, 0xF0, 0x00, 0xF0, 0xF0, 0xF0, 0x00, 0xF0, 0xF0, 0xF0, /* Gray shades */ 0x00, 0x00, 0x00, 0x10, 0x10, 0x10, 0x20, 0x20, 0x20, 0x30, 0x30, 0x30, 0x40, 0x40, 0x40, 0x50, 0x50, 0x50, 0x60, 0x60, 0x60, 0x70, 0x70, 0x70, 0x80, 0x80, 0x80, 0x90, 0x90, 0x90, 0xA0, 0xA0, 0xA0, 0xB0, 0xB0, 0xB0, 0xC0, 0xC0, 0xC0, 0xD0, 0xD0, 0xD0, 0xE0, 0xE0, 0xE0, 0xF0, 0xF0, 0xF0, /* Black to red */ 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x20, 0x00, 0x00, 0x30, 0x00, 0x00, 0x40, 0x00, 0x00, 0x50, 0x00, 0x00, 0x60, 0x00, 0x00, 0x70, 0x00, 0x00, 0x80, 0x00, 0x00, 0x90, 0x00, 0x00, 0xA0, 0x00, 0x00, 0xB0, 0x00, 0x00, 0xC0, 0x00, 0x00, 0xD0, 0x00, 0x00, 0xE0, 0x00, 0x00, 0xF0, 0x00, 0x00, /* Black to green */ 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x20, 0x00, 0x00, 0x30, 0x00, 0x00, 0x40, 0x00, 0x00, 0x50, 0x00, 0x00, 0x60, 0x00, 0x00, 0x70, 0x00, 0x00, 0x80, 0x00, 0x00, 0x90, 0x00, 0x00, 0xA0, 0x00, 0x00, 0xB0, 0x00, 0x00, 0xC0, 0x00, 0x00, 0xD0, 0x00, 0x00, 0xE0, 0x00, 0x00, 0xF0, 0x00, /* Black to blue */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x20, 0x00, 0x00, 0x30, 0x00, 0x00, 0x40, 0x00, 0x00, 0x50, 0x00, 0x00, 0x60, 0x00, 0x00, 0x70, 0x00, 0x00, 0x80, 0x00, 0x00, 0x90, 0x00, 0x00, 0xA0, 0x00, 0x00, 0xB0, 0x00, 0x00, 0xC0, 0x00, 0x00, 0xD0, 0x00, 0x00, 0xE0, 0x00, 0x00, 0xF0, /* Blue to cyan (blue and green) */ 0x00, 0x00, 0xF0, 0x00, 0x10, 0xF0, 0x00, 0x20, 0xF0, 0x00, 0x30, 0xF0, 0x00, 0x40, 0xF0, 0x00, 0x50, 0xF0, 0x00, 0x60, 0xF0, 0x00, 0x70, 0xF0, 0x00, 0x80, 0xF0, 0x00, 0x90, 0xF0, 0x00, 0xA0, 0xF0, 0x00, 0xB0, 0xF0, 0x00, 0xC0, 0xF0, 0x00, 0xD0, 0xF0, 0x00, 0xE0, 0xF0, 0x00, 0xF0, 0xF0, /* Cyan (blue and green) to green */ 0x00, 0xF0, 0xF0, 0x00, 0xF0, 0xE0, 0x00, 0xF0, 0xD0, 0x00, 0xF0, 0xC0, 0x00, 0xF0, 0xB0, 0x00, 0xF0, 0xA0, 0x00, 0xF0, 0x90, 0x00, 0xF0, 0x80, 0x00, 0xF0, 0x70, 0x00, 0xF0, 0x60, 0x00, 0xF0, 0x50, 0x00, 0xF0, 0x40, 0x00, 0xF0, 0x30, 0x00, 0xF0, 0x20, 0x00, 0xF0, 0x10, 0x00, 0xF0, 0x00, /* Green to yellow (red and green) */ 0x00, 0xF0, 0x00, 0x10, 0xF0, 0x00, 0x20, 0xF0, 0x00, 0x30, 0xF0, 0x00, 0x40, 0xF0, 0x00, 0x50, 0xF0, 0x00, 0x60, 0xF0, 0x00, 0x70, 0xF0, 0x00, 0x80, 0xF0, 0x00, 0x90, 0xF0, 0x00, 0xA0, 0xF0, 0x00, 0xB0, 0xF0, 0x00, S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-57 12: SAMPLE CODE 0xC0, 0xF0, 0x00, 0xD0, 0xF0, 0x00, /* Yellow (red and green) to red */ 0xF0, 0xF0, 0x00, 0xF0, 0xE0, 0x00, 0xF0, 0xB0, 0x00, 0xF0, 0xA0, 0x00, 0xF0, 0x70, 0x00, 0xF0, 0x60, 0x00, 0xF0, 0x30, 0x00, 0xF0, 0x20, 0x00, /* Red to magenta (blue and red) */ 0xF0, 0x00, 0x00, 0xF0, 0x00, 0x10, 0xF0, 0x00, 0x40, 0xF0, 0x00, 0x50, 0xF0, 0x00, 0x80, 0xF0, 0x00, 0x90, 0xF0, 0x00, 0xC0, 0xF0, 0x00, 0xD0, /* Magenta (blue and red) to blue */ 0xF0, 0x00, 0xF0, 0xE0, 0x00, 0xF0, 0xB0, 0x00, 0xF0, 0xA0, 0x00, 0xF0, 0x70, 0x00, 0xF0, 0x60, 0x00, 0xF0, 0x30, 0x00, 0xF0, 0x20, 0x00, 0xF0, /* Black to magenta (blue and red) */ 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x40, 0x00, 0x40, 0x50, 0x00, 0x50, 0x80, 0x00, 0x80, 0x90, 0x00, 0x90, 0xC0, 0x00, 0xC0, 0xD0, 0x00, 0xD0, /* Black to cyan (blue and green) */ 0x00, 0x00, 0x00, 0x00, 0x10, 0x10, 0x00, 0x40, 0x40, 0x00, 0x50, 0x50, 0x00, 0x80, 0x80, 0x00, 0x90, 0x90, 0x00, 0xC0, 0xC0, 0x00, 0xD0, 0xD0, /* Red to white */ 0xF0, 0x00, 0x00, 0xF0, 0x10, 0x10, 0xF0, 0x40, 0x40, 0xF0, 0x50, 0x50, 0xF0, 0x80, 0x80, 0xF0, 0x90, 0x90, 0xF0, 0xC0, 0xC0, 0xF0, 0xD0, 0xD0, /* Green to white */ 0x00, 0xF0, 0x00, 0x10, 0xF0, 0x10, 0x40, 0xF0, 0x40, 0x50, 0xF0, 0x50, 0x80, 0xF0, 0x80, 0x90, 0xF0, 0x90, 0xC0, 0xF0, 0xC0, 0xD0, 0xF0, 0xD0, /* Blue to white */ 0x00, 0x00, 0xF0, 0x10, 0x10, 0xF0, 0x40, 0x40, 0xF0, 0x50, 0x50, 0xF0, 0x80, 0x80, 0xF0, 0x90, 0x90, 0xF0, 0xC0, 0xC0, 0xF0, 0xD0, 0xD0, 0xF0, }; 0xE0, 0xF0, 0x00, 0xF0, 0xF0, 0x00, 0xF0, 0xF0, 0xF0, 0xF0, 0xD0, 0x90, 0x50, 0x10, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xF0, 0xF0, 0xF0, 0xC0, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xF0, 0xF0, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x20, 0x60, 0xA0, 0xE0, 0xF0, 0xF0, 0xF0, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x30, 0x70, 0xB0, 0xF0, 0xD0, 0x90, 0x50, 0x10, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xF0, 0xF0, 0xF0, 0xC0, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xF0, 0xF0, 0xF0, 0x20, 0x60, 0xA0, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x20, 0x60, 0xA0, 0xE0, 0x30, 0x70, 0xB0, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x30, 0x70, 0xB0, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x20, 0x60, 0xA0, 0xE0, 0x20, 0x60, 0xA0, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x30, 0x70, 0xB0, 0xF0, 0x30, 0x70, 0xB0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0x20, 0x60, 0xA0, 0xE0, 0x20, 0x60, 0xA0, 0xE0, 0xF0, 0xF0, 0xF0, 0xF0, 0x30, 0x70, 0xB0, 0xF0, 0x30, 0x70, 0xB0, 0xF0, 0x20, 0x60, 0xA0, 0xE0, 0xF0, 0xF0, 0xF0, 0xF0, 0x20, 0x60, 0xA0, 0xE0, 0x30, 0x70, 0xB0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0x30, 0x70, 0xB0, 0xF0, 0x20, 0x60, 0xA0, 0xE0, 0x20, 0x60, 0xA0, 0xE0, 0xF0, 0xF0, 0xF0, 0xF0, 0x30, 0x70, 0xB0, 0xF0, 0x30, 0x70, 0xB0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0 /* ** REGISTER_OFFSET points to the starting address of the SED1355 registers */ #define REGISTER_OFFSET ((unsigned char *) 0x14000000) /* ** DISP_MEM_OFFSET points to the starting address of the display buffer memory */ #define DISP_MEM_OFFSET ((unsigned char *) 0x4000000) /* ** DISP_MEMORY_SIZE is the size of display buffer memory */ #define DISP_MEMORY_SIZE 0x200000 /* ** Calculate the value to put in Ink/Cursor Start Address Select Register ** Offset = (DISP_MEM_SIZE - (X * 8192) ** We want the offset to be just past the end of display memory so: ** (640 * 480) = DISP_MEMORY_SIZE - (X * 8192) ** ** CURSOR_START = (DISP_MEMORY_SIZE - (640 * 480)) / 8192 */ #define CURSOR_START 218 void main(void) { unsigned char * pRegs = REGISTER_OFFSET; unsigned char * pMem; unsigned char * pLUT; unsigned char * pTmp; unsigned char * pCursor; long lpCnt; int idx; int rgb; long x, y; /* ** Initialize the chip. */ /* ** Step 1: Enable the host interface. 2-58 EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 12: SAMPLE CODE ** ** Register 1B: Miscellaneous Disable - host interface enabled, half frame ** buffer enabled. */ *(pRegs + 0x1B) = 0x00; /* 0000 0000 */ /* ** Step 2: Disable the FIFO */ *(pRegs + 0x23) = 0x80; /* 1000 0000 */ /* ** Step 3: Set Memory Configuration ** ** Register 1: Memory Configuration - 4 ms refresh, EDO */ *(pRegs + 0x01) = 0x30; /* 0011 0000 */ /* ** Step 4: Set Performance Enhancement 0 register */ *(pRegs + 0x22) = 0x24; /* 0010 0100 */ /* ** Step 5: Set the rest of the registers in order. */ /* ** Register 2: Panel Type - 16-bit, format 1, color, dual, passive. */ *(pRegs + 0x02) = 0x26; /* 0010 0110 */ /* ** Register 3: Mod Rate */ *(pRegs + 0x03) = 0x00; /* 0000 0000 */ /* ** Register 4: Horizontal Display Width (HDP) - 640 pixels ** (640 / 8) - 1 = 79t = 4Fh */ *(pRegs + 0x04) = 0x4f; /* 0100 1111 */ /* ** Register 5: Horizontal Non-Display Period (HNDP) ** PCLK ** Frame Rate = ----------------------------** (HDP + HNDP) * (VDP + VNDP) ** ** 16,500,000 ** = ----------------------------** (640 + HNDP) * (480 + VNDP) ** ** HNDP and VNDP must be calculated such that the desired frame rate ** is achieved. */ *(pRegs + 0x05) = 0x1F; /* 0001 1111 */ /* ** Register 6: HRTC/FPLINE Start Position - applicable to CRT/TFT only. */ *(pRegs + 0x06) = 0x00; /* 0000 0000 */ /* ** Register 7: HRTC/FPLINE Pulse Width - applicable to CRT/TFT only. */ *(pRegs + 0x07) = 0x00; /* 0000 0000 */ /* ** Registers 8-9: Vertical Display Height (VDP) - 480 lines. ** 480/2 - 1 = 239t = 0xEF */ *(pRegs + 0x08) = 0xEF; /* 1110 1111 */ *(pRegs + 0x09) = 0x00; /* 0000 0000 */ /* ** Register A: Vertical Non-Display Period (VNDP) ** This register must be programed with register 5 (HNDP) ** to arrive at the frame rate closest to the desired ** frame rate. */ *(pRegs + 0x0A) = 0x01; /* 0000 0001 */ /* ** Register B: VRTC/FPFRAME Start Position - applicable to CRT/TFT only. */ *(pRegs + 0x0B) = 0x00; /* 0000 0000 */ /* ** Register C: VRTC/FPFRAME Pulse Width - applicable to CRT/TFT only. */ *(pRegs + 0x0C) = 0x00; /* 0000 0000 */ /* ** Register D: Display Mode - 8 BPP, LCD disabled. S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-59 12: SAMPLE CODE */ *(pRegs + 0x0D) = 0x0C; /* 0000 1100 */ /* ** Registers E-F: Screen 1 Line Compare - unless setting up for ** split screen operation use 0x3FF. */ *(pRegs + 0x0E) = 0xFF; /* 1111 1111 */ *(pRegs + 0x0F) = 0x03; /* 0000 0011 */ /* ** Registers 10-12: Screen 1 Display Start Address - start at the ** first byte in display memory. */ *(pRegs + 0x10) = 0x00; /* 0000 0000 */ *(pRegs + 0x11) = 0x00; /* 0000 0000 */ *(pRegs + 0x12) = 0x00; /* 0000 0000 */ /* ** Register 13-15: Screen 2 Display Start Address - not applicable ** unless setting up for split screen operation. */ *(pRegs + 0x13) = 0x00; /* 0000 0000 */ *(pRegs + 0x14) = 0x00; /* 0000 0000 */ *(pRegs + 0x15) = 0x00; /* 0000 0000 */ /* ** Register 16-17: Memory Address Offset - this address represents the ** starting WORD. At 8BPP our 640 pixel width is 320 ** WORDS */ *(pRegs + 0x16) = 0x40; /* 0100 0000 */ *(pRegs + 0x17) = 0x01; /* 0000 0001 */ /* ** Register 18: Pixel Panning */ *(pRegs + 0x18) = 0x00; /* 0000 0000 */ /* ** Register 19: Clock Configuration - In this case we must divide ** PCLK by 2 to arrive at the best frequency to set ** our desired panel frame rate. */ *(pRegs + 0x19) = 0x01; /* 0000 0001 */ /* ** Register 1A: Power Save Configuration - enable LCD power, CBR refresh, ** not suspended. */ *(pRegs + 0x1A) = 0x00; /* 0000 0000 */ /* ** Register 1C-1D: MD Configuration Readback - these registers are ** read only, but it's OK to write a 0 to keep ** the register configuration logic simpler. */ *(pRegs + 0x1C) = 0x00; /* 0000 0000 */ *(pRegs + 0x1D) = 0x00; /* 0000 0000 */ /* ** Register 1E-1F: General I/O Pins Configuration */ *(pRegs + 0x1E) = 0x00; /* 0000 0000 */ *(pRegs + 0x1F) = 0x00; /* 0000 0000 */ /* ** Register 20-21: General I/O Pins Control */ *(pRegs + 0x20) = 0x00; /* 0000 0000 */ *(pRegs + 0x21) = 0x00; /* 0000 0000 */ /* ** Registers 24-26: LUT control. ** For this example do a typical 8 BPP LUT setup. ** ** Setup the pointer to the LUT data and reset the LUT index register. ** Then, loop writing each of the RGB LUT data elements. */ pLUT = LUT8; *(pRegs + 0x24) = 0; for (idx = 0; idx < 256; idx++) { for (rgb = 0; rgb < 3; rgb++) { *(pRegs + 0x26) = *pLUT; pLUT++; } } /* ** Register 27: Ink/Cursor Control - disable ink/cursor 2-60 EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 12: SAMPLE CODE */ *(pRegs + 0x27) = 0x00; /* 0000 0000 */ /* ** Registers 28-29: Cursor X Position */ *(pRegs + 0x28) = 0x00; /* 0000 0000 */ *(pRegs + 0x29) = 0x00; /* 0000 0000 */ /* ** Registers 2A-2B: Cursor Y Position */ *(pRegs + 0x2A) = 0x00; /* 0000 0000 */ *(pRegs + 0x2B) = 0x00; /* 0000 0000 */ /* ** Registers 2C-2D: Ink/Cursor Color 0 - blue */ *(pRegs + 0x2C) = 0x1F; /* 0001 1111 */ *(pRegs + 0x2D) = 0x00; /* 0000 0000 */ /* ** Registers 2E-2F: Ink/Cursor Color 1 - green */ *(pRegs + 0x2E) = 0xE0; /* 1110 0000 */ *(pRegs + 0x2F) = 0x07; /* 0000 0111 */ /* ** Register 30: Ink/Cursor Start Address Select */ *(pRegs + 0x30) = 0x00; /* 0000 0000 */ /* ** Register 31: Alternate FRM Register */ *(pRegs + 0x31) = 0x00; /* ** Register 23: Performance Enhancement - display FIFO enabled, optimum ** performance. The FIFO threshold is set to 0x00; for ** 15/16 bpp modes, set the FIFO threshold ** to a higher value, such as 0x1B. */ *(pRegs + 0x23) = 0x00; /* 0000 0000 */ /* ** Register D: Display Mode - 8 BPP, LCD enable. */ *(pRegs + 0x0D) = 0x0D; /* 0000 1101 */ /* ** Clear memory by filling 2 MB with 0 */ pMem = DISP_MEM_OFFSET; for (lpCnt = 0; lpCnt < DISP_MEMORY_SIZE; lpCnt++) { *pMem = 0; pMem++; } /* ** Draw a 100x100 red rectangle in the upper left corner (0, 0) ** of the display. */ pMem = DISP_MEM_OFFSET; for (y = 0; y < 100; y++) { pTmp = pMem + y * 640L; for (x = 0; x < 100; x++) { *pTmp = 0x0c; pTmp++; } } /* ** Init the HW cursor. In this example the cursor memory will be located ** immediately after display memory. Why here? Because it's an easy ** location to calculate and will not interfere with the half frame buffer. ** Additionally, the HW cursor can be turned into an ink layer quite ** easily from this location. */ *(pRegs + 0x30) = CURSOR_START; pTmp = pCursor = pMem + (DISP_MEMORY_SIZE - (CURSOR_START * 8192L)); /* ** Set the contents of the cursor memory such that the cursor ** is transparent. To do so, write a 10101010b pattern in each byte. ** The cursor is 2 bpp so a 64x64 cursor requires ** 64/4 * 64 = 1024 bytes of memory. */ for (lpCnt = 0; lpCnt < 1024; lpCnt++) S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-61 12: SAMPLE CODE { *pTmp = 0xAA; pTmp++; } /* ** Set the first user definable cursor color to black and ** the second user definable cursor color to white. */ *(pRegs + 0x2C) = 0; *(pRegs + 0x2D) = 0; *(pRegs + 0x2E) = 0xFF; *(pRegs + 0x2F) = 0xFF; /* ** Draw a hollow rectangle around the cursor. */ pTmp = pCursor; for (lpCnt = 0; lpCnt < 16; lpCnt++) { *pTmp = 0x55; pTmp++; } for (lpCnt = 0; lpCnt < 14; lpCnt++) { *pTmp = 0x6A; pTmp += 15; *pTmp = 0xA9; pTmp++; } for (lpCnt = 0; lpCnt < 16; lpCnt++) { *pTmp = 0x55; pTmp++; } /* ** Move the cursor to 100, 100. */ /* ** First we wait for the next vertical non-display ** period before updating the position registers. */ while (*(pRegs + 0x0A) & 0x80); /* wait while in VNDP */ while (!(*(pRegs + 0x0A) & 0x80)); /* wait while in VDP */ /* ** Now update the position registers. */ *(pRegs + 0x28) = 100; /* Set Cursor X = 100 */ *(pRegs + 0x29) = 0x00; *(pRegs + 0x2A) = 100; /* Set Cursor Y = 100 */ *(pRegs + 0x2B) = 0x00; /* ** Enable the hardware cursor. */ *(pRegs + 0x27) = 0x40; } } 2-62 EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 12: SAMPLE CODE Header Files The following header files are included as they help to explain some of the structures used when programming the S1D13505. The following header file defines the structure used to store the configuration information contained in all utilities using the S1D13505HAL API. /**************************************************************/ /* 1355 HAL INF (do not remove) */ /* HAL_STRUCT Information generated by 1355CFG.EXE */ /* Copyright (c) 1998 Seiko Epson Corp. All rights reserved. */ /* */ /* Include this file ONCE in your primary source file */ /**************************************************************/ HAL_STRUCT HalInfo = { "1355 HAL EXE", 0x1234, sizeof(HAL_STRUCT), 0, /* /* /* /* ID string */ Detect Endian */ Size */ Default Mode */ { { 0x00, 0xEF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 0x00, 0xDF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 0xFF, 0xDF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00 /* LCD */ 0x16, 0x00, 0x34, 0x00, 0x00, 0x00, 0x02, 0x00, 0x48, 0x00, 0x00, 0x00, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x40, 0x00, 0x00, 0x00, 0x00, 0x03, 0x01, 0x00, 0x00, 0x00, /* CRT */ 0x16, 0x00, 0x2B, 0x09, 0x00, 0x00, 0x02, 0x01, 0x48, 0x00, 0x00, 0x00, 0x4F, 0x01, 0x00, 0x00, 0x00, 0x00, 0x13, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x01, 0xFF, 0x40, 0x00, 0x00, 0x00, 0x0B, 0x03, 0x01, 0x00, 0x00, 0x00, /* SIMUL */ 0x16, 0x00, 0x2B, 0x09, 0x00, 0x00, 0x02, 0x01, 0x48, 0x00, 0x00, 0x00, 0x4F, 0x01, 0x00, 0x00, 0x00, 0x00, 0x13, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x01, 0xFF, 0x40, 0x00, 0x00, 0x00, 0x0B, 0x03, 0x01, 0x00, 0x00, 0x00, }, { }, { }, }, 25175, 8000, 0xE00000, 0xC00000, 60, 60, 50, 84, 30, 50, 16 /* ClkI (kHz) */ /* BusClk (kHz) */ /* Register Address */ /* Display Address */ /* Panel Frame Rate (Hz) */ /* CRT Frame Rate (Hz) */ /* Memory speed in ns */ /* Ras to Cas Delay in ns */ /* Ras Access Charge time in ns */ /* RAS Access Charge time in ns */ /* Host CPU bus width in bits */ }; /* S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-63 12: SAMPLE CODE The following header file defines the S1D13505HAL registers. /*=========================================================================== ** HAL_REGS.H **--------------------------------------------------------------------------** Created 1998, Epson Research & Development ** Vancouver Design Center. ** Copyright(c) Seiko Epson Corp. 1997, 1998. All rights reserved. **--------------------------------------------------------------------------** ** $Header: $ ** ** $Revision: $ ** ** $Log: $ ** ===========================================================================*/ #ifndef __HAL_REGS_H__ #define __HAL_REGS_H__ /* ** 1355 register names */ #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define REG_REVISION_CODE REG_MEMORY_CONFIG REG_PANEL_TYPE REG_MOD_RATE REG_HORZ_DISP_WIDTH REG_HORZ_NONDISP_PERIOD REG_HRTC_START_POSITION REG_HRTC_PULSE_WIDTH REG_VERT_DISP_HEIGHT0 REG_VERT_DISP_HEIGHT1 REG_VERT_NONDISP_PERIOD REG_VRTC_START_POSITION REG_VRTC_PULSE_WIDTH REG_DISPLAY_MODE REG_SCRN1_LINE_COMPARE0 REG_SCRN1_LINE_COMPARE1 REG_SCRN1_DISP_START_ADDR0 REG_SCRN1_DISP_START_ADDR1 REG_SCRN1_DISP_START_ADDR2 REG_SCRN2_DISP_START_ADDR0 REG_SCRN2_DISP_START_ADDR1 REG_SCRN2_DISP_START_ADDR2 REG_MEM_ADDR_OFFSET0 REG_MEM_ADDR_OFFSET1 REG_PIXEL_PANNING REG_CLOCK_CONFIG REG_POWER_SAVE_CONFIG REG_MISC REG_MD_CONFIG_READBACK0 REG_MD_CONFIG_READBACK1 REG_GPIO_CONFIG0 REG_GPIO_CONFIG1 REG_GPIO_CONTROL0 REG_GPIO_CONTROL1 REG_PERF_ENHANCEMENT0 REG_PERF_ENHANCEMENT1 REG_LUT_ADDR REG_RESERVED_1 REG_LUT_DATA REG_INK_CURSOR_CONTROL REG_CURSOR_X_POSITION0 REG_CURSOR_X_POSITION1 REG_CURSOR_Y_POSITION0 REG_CURSOR_Y_POSITION1 REG_INK_CURSOR_COLOR0_0 REG_INK_CURSOR_COLOR0_1 REG_INK_CURSOR_COLOR1_0 REG_INK_CURSOR_COLOR1_1 REG_INK_CURSOR_START_ADDR REG_ALTERNATE_FRM 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 /* ** WARNING!!! MAX_REG must be the last available register!!! 2-64 EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 12: SAMPLE CODE */ #define MAX_REG #endif 0x31 /* __HAL_REGS_H__ */ The following header file defines the structures used in the S1D13505HAL API. **=========================================================================== ** HAL.H **--------------------------------------------------------------------------** Created 1998, Epson Research & Development ** Vancouver Design Center. ** Copyright(c) Seiko Epson Corp. 1997, 1998. All rights reserved. **=========================================================================== */ #ifndef _HAL_H_ #define _HAL_H_ #pragma warning(disable:4001) // Disable the 'single line comment' warning. #include "hal_regs.h" /*-------------------------------------------------------------------------*/ typedef typedef typedef typedef typedef unsigned unsigned unsigned unsigned char short long int int BYTE; WORD; DWORD; UINT; BOOL; #ifdef INTEL typedef BYTE far *LPBYTE; typedef WORD far *LPWORD; typedef DWORD far *LPDWORD; #else typedef BYTE *LPBYTE; typedef WORD *LPWORD; typedef DWORD *LPDWORD; #endif #ifndef LOBYTE #define LOBYTE(w) #endif ((BYTE)(w)) #ifndef HIBYTE #define HIBYTE(w) #endif ((BYTE)(((UINT)(w) >> 8) & 0xFF)) #ifndef LOWORD #define LOWORD(l) #endif ((WORD)(DWORD)(l)) #ifndef HIWORD #define HIWORD(l) #endif ((WORD)((((DWORD)(l)) >> 16) & 0xFFFF)) #ifndef MAKEWORD #define MAKEWORD(lo, hi) ((WORD)(((WORD)(lo)) | (((WORD)(hi)) << 8)) ) #endif #ifndef MAKELONG #define MAKELONG(lo, hi) ((long)(((WORD)(lo)) | (((DWORD)((WORD)(hi))) << 16))) #endif #ifndef TRUE #define TRUE #endif 1 #ifndef FALSE #define FALSE #endif 0 #define OFF 0 #define ON 1 S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-65 12: SAMPLE CODE #ifndef NULL #ifdef __cplusplus #define NULL 0 #else #define NULL ((void *)0) #endif #endif /*-------------------------------------------------------------------------*/ /* ** SIZE_VERSION is the ** SIZE_STATUS is the ** SIZE_REVISION is the */ #define SIZE_VERSION #define SIZE_STATUS #define SIZE_REVISION #ifdef ENABLE_DPF #define #define #define #define size of the version string (eg. "1.00") size of the status string (eg. "b" for beta) size of the status revision string (eg. "00") 5 2 3 /* Debug_printf() */ DPF(exp) printf(#exp "\n") DPF1(exp) printf(#exp " = %d\n", exp) DPF2(exp1, exp2) printf(#exp1 "=%d " #exp2 "=%d\n", exp1, exp2) DPFL(exp) printf(#exp " = %x\n", exp) #else #define DPF(exp) ((void)0) #define DPF1(exp) ((void)0) #define DPFL(exp) ((void)0) #endif /*-------------------------------------------------------------------------*/ enum { ERR_OK = 0, ERR_FAILED, /* No error, call was successful. */ /* General purpose failure. */ ERR_UNKNOWN_DEVICE, ERR_INVALID_PARAMETER, ERR_HAL_BAD_ARG, ERR_TOOMANY_DEVS, /* */ /* Function was called with invalid parameter. */ ERR_INVALID_STD_DEVICE }; /******************************************* * Definitions for seGetId() *******************************************/ enum { ID_UNKNOWN, ID_SED1355, ID_SED1355F0A }; #define MAX_DEVICE 10 /* ** SE_RESERVED is for reserved device */ #define SE_RESERVED 0 /* ** DetectEndian is used to determine whether the most significant ** and least significant bytes are reversed by the given compiler. */ #define ENDIAN 0x1234 #define REV_ENDIAN 0x3412 /******************************************* * Definitions for Internal calculations. *******************************************/ 2-66 EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 12: SAMPLE CODE #define MIN_NON_DISP_X #define MAX_NON_DISP_X 32 256 #define MIN_NON_DISP_Y #define MAX_NON_DISP_Y 2 64 /******************************************* * Definitions for seSetFont *******************************************/ enum { HAL_STDOUT, HAL_STDIN, HAL_DEVICE_ERR }; #define FONT_NORMAL #define FONT_DOUBLE_WIDTH #define FONT_DOUBLE_HEIGHT 0x00 0x01 0x02 enum { RED, GREEN, BLUE }; /******************************************* * Definitions for seSplitScreen() *******************************************/ enum { SCREEN1 = 1, SCREEN2 }; /******************************************* * Definitions for sePowerSaveMode() *******************************************/ #define PWR_CBR_REFRESH #define PWR_SELF_REFRESH #define PWR_NO_REFRESH 0x00 0x01 0x02 /*************************************************************************/ enum { DISP_MODE_LCD = 0, DISP_MODE_CRT, DISP_MODE_SIMULTANEOUS, MAX_DISP_MODE }; typedef struct tagHalStruct { char szIdString[16]; WORD wDetectEndian; WORD wSize; WORD wDefaultMode; BYTE Regs[MAX_DISP_MODE][MAX_REG + 1]; DWORD DWORD DWORD DWORD WORD dwClkI; dwBusClk; dwRegAddr; dwDispMem; wPanelFrameRate; /* /* /* /* /* WORD WORD WORD wCrtFrameRate; wMemSpeed; wTrc; /* Desired CRT rate */ /* Memory speed in ns */ /* Ras to Cas Delay in ns */ S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) Input Clock Frequency (in kHz) */ Bus Clock Frequency (in kHz) */ Starting address of registers */ Starting address of display buffer memory */ Desired panel frame rate */ EPSON 2-67 12: SAMPLE CODE WORD WORD WORD wTrp; wTrac; wHostBusWidth; /* Ras Precharge time in ns */ /* Ras Access Charge time in ns */ /* Host CPU bus width in bits */ } HAL_STRUCT; typedef HAL_STRUCT * PHAL_STRUCT; #ifdef INTEL typedef HAL_STRUCT far * LPHAL_STRUCT; #else typedef HAL_STRUCT * LPHAL_STRUCT; #endif /*=========================================================================*/ /* FUNCTION PROTO-TYPES */ /*=========================================================================*/ /*---------------------------- HAL Support --------------------------------*/ int int int int seInitHal( void ); seGetDetectedBusWidth(int *bits); seRegisterDevice( const LPHAL_STRUCT lpHalInfo, int *Device ); seGetMemSize( int seReserved1, DWORD *val ); #define CLEAR_MEM TRUE #define DONT_CLEAR_MEM FALSE int seSetDisplayMode(int device, int DisplayMode, int ClearMem); int seSetInit(int device); int seGetId( int seReserved1, int *pId ); void seGetHalVersion( const char **pVersion, const char **pStatus, const char **pStatusRevision ); /*---------------------------- Chip Access --------------------------------*/ int seGetReg( int seReserved1, int index, BYTE *pValue ); int seSetReg( int seReserved1, int index, BYTE value ); /*------------------------------- Misc ------------------------------------*/ int seSetBitsPerPixel( int seReserved1, UINT nBitsPerPixel ); int seGetBitsPerPixel( int seReserved1, UINT *pBitsPerPixel ); int int int int seGetBytesPerScanline( int seReserved1, UINT *pBytes ); seGetScreenSize( int seReserved1, UINT *width, UINT *height ); seHWSuspend(int seReserved1, BOOL val); seSelectBusWidth(int seReserved1, int width); int seDelay( int seReserved1, DWORD Seconds ); int seGetLastUsableByte( int seReserved1, DWORD *LastByte ); int seDisplayEnable(int seReserved1, BYTE NewState); int int int int seSplitInit( int seReserved1, DWORD wScrn1Addr, DWORD wScrn2Addr ); seSplitScreen( int nReserved1, int WhichScreen, long VisibleScanlines ); seVirtInit( int seReserved1, DWORD xVirt, DWORD *yVirt ); seVirtMove( int seReserved1, int nWhichScreen, DWORD x, DWORD y ); /*-------------------------- Power Save -----------------------------------*/ int seSetPowerSaveMode( int seReserved1, int PowerSaveMode ); /*------------------------- Memory Access ---------------------------------*/ int seReadDisplayByte( int seReserved1, DWORD offset, BYTE *pByte ); int seReadDisplayWord( int seReserved1, DWORD offset, WORD *pWord ); int seReadDisplayDword( int seReserved1, DWORD offset, DWORD *pDword ); int seWriteDisplayBytes( int seReserved1, DWORD addr, BYTE val, DWORD count ); int seWriteDisplayWords( int seReserved1, DWORD addr, WORD val, DWORD count ); int seWriteDisplayDwords( int seReserved1, DWORD addr, DWORD val, DWORD count ); /*------------------------------- Drawing ---------------------------------*/ int seGetInkStartAddr(int seReserved1, DWORD *addr); int seGetPixel( int seReserved1, long x, long y, DWORD *pVal ); 2-68 EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) 12: SAMPLE CODE int seSetPixel( int seReserved1, long x, long y, DWORD color ); int seDrawLine( int seReserved1, long x1, long y1, long x2, long y2, DWORD color ); int seDrawRect( int seReserved1, long x1, long y1, long x2, long y2, DWORD color, BOOL SolidFill ); int seDrawEllipse(int seReserved1, long xc, long yc, long xr, long yr, DWORD color, BOOL SolidFill); int seDrawCircle( int seReserved1, long xCenter, long yCenter, long radius, DWORD color, BOOL SolidFill ); /*------------------------------- Hardware Cursor ---------------------------------*/ int seInitCursor(int seReserved1); int seCursorOff(int seReserved1); int seGetCursorStartAddr(int seReserved1, DWORD *addr); int seMoveCursor(int seReserved1, long x, long y); int seSetCursorColor(int seReserved1, int index, DWORD color); int seSetCursorPixel( int seReserved1, long x, long y, DWORD color ); int seDrawCursorLine( int seReserved1, long x1, long y1, long x2, long y2, DWORD color ); int seDrawCursorRect( int seReserved1, long x1, long y1, long x2, long y2, DWORD color, BOOL SolidFill ); int seDrawCursorEllipse(int seReserved1, long xc, long yc, long xr, long yr, DWORD color, BOOL SolidFill); int seDrawCursorCircle( int seReserved1, long xCenter, long yCenter, long radius, DWORD color, BOOL SolidFill ); /*------------------------------- Hardware Ink Layer ---------------------------------*/ int seInitInk(int seReserved1); int seInkOff(int seReserved1); int seGetInkStartAddr(int seReserved1, DWORD *addr); int seSetInkColor(int seReserved1, int index, DWORD color); int seSetInkPixel( int seReserved1, long x, long y, DWORD color ); int seDrawInkLine( int seReserved1, long x1, long y1, long x2, long y2, DWORD color ); int seDrawInkRect( int seReserved1, long x1, long y1, long x2, long y2, DWORD color, BOOL SolidFill ); int seDrawInkEllipse(int seReserved1, long xc, long yc, long xr, long yr, DWORD color, BOOL SolidFill); int seDrawInkCircle( int seReserved1, long xCenter, long yCenter, long radius, DWORD color, BOOL SolidFill ); /*------------------------------ Color ------------------------------------*/ int int int int seSetLut( int seReserved1, BYTE seGetLut( int seReserved1, BYTE seSetLutEntry( int seReserved1, seGetLutEntry( int seReserved1, *pLut, int *pLut, int int index, int index, count ); count ); BYTE *pEntry ); BYTE *pEntry ); /*--------------------------- C Like Support ------------------------------*/ int seDrawText( int seReserved1, char *fmt, ... ); int sePutChar( int seReserved1, int ch ); int seGetChar( void ); /*--------------------------- XLIB Support --------------------------------*/ int seGetLinearDispAddr(int seReserved1, DWORD *pDispLogicalAddr); int InitLinear(int seReserved1); #endif /* _HAL_H_ */ S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) EPSON 2-69 APPENDIX: SUPPORTED PANEL VALUES APPENDIX SUPPORTED PANEL VALUES The following tables show related register data for different panels. All the examples are based on 8 bpp and 2M bytes of 50 ns EDO-DRAM. Register REG[02h] REG[03h] REG[04h] REG[05h] REG[08h] REG[09h] REG[0Ah] REG[0Dh] REG[19h] REG[1Bh] REG[24h] REG[26h] Register REG[02h] REG[03h] REG[04h] REG[05h] REG[08h] REG[09h] REG[0Ah] REG[0Dh] REG[19h] REG[1Bh] REG[24h] REG[26h] Table A-1 Passive Single Panel with 40MHz Pixel Clock Mono 4-Bit Color 8-Bit Color 8-Bit EL Format 2 Mono 4-Bit 320X240@60Hz 320X240@60Hz 0000 0000 0000 0000 0010 0111 0001 0111 1110 1111 0000 0000 0011 1110 0000 1101 0000 0011 0000 0001 0000 0000 load LUT 320X240@60Hz 1000 0000 0000 0000 0010 0111 0001 0111 1110 1111 0000 0000 0011 1110 0000 1101 0000 0011 0000 0001 0000 0000 load LUT Notes 320X240@60Hz 0001 0100 0000 0000 0010 0111 0001 0111 1110 1111 0000 0000 0011 1110 0000 1101 0000 0011 0000 0001 0000 0000 load LUT 0001 1100 0000 0000 0010 0111 0001 0111 1110 1111 0000 0000 0011 1110 0000 1101 0000 0011 0000 0001 0000 0000 load LUT Mono 8-Bit Color 8-Bit Color 16-Bit 640X480@60Hz 640X480@60Hz 640X480@60Hz 0001 0000 0000 0000 0100 1111 0000 0011 1101 1111 0000 0001 0000 0010 0000 1101 0000 0001 0000 0001 0000 0000 load LUT 0001 0100 0000 0000 0100 1111 0000 0011 1101 1111 0000 0001 0000 0010 0000 1101 0000 0001 0000 0001 0000 0000 load LUT 0010 0100 0000 0000 0100 1111 0000 0011 1101 1111 0000 0001 0000 0010 0000 1101 0000 0001 0000 0001 0000 0000 load LUT set panel type set MOD rate set horizontal display width set horizontal non-display period set vertical display height bits 7-0 set vertical display height bits 9-8 set vertical non-display period set 8 bpp and LCD enable set MCLK and PCLK divide disable half frame buffer set Look-Up Table address to 0 load Look-Up Table Notes set panel type set MOD rate set horizontal display width set horizontal non-display period set vertical display height bits 7-0 set vertical display height bits 9-8 set vertical non-display period set 8 bpp and LCD enable set MCLK and PCLK divide disable half frame buffer set Look-Up Table address to 0 load Look-Up Table Note: The following settings may not reflect the ideal settings for your system configuration. Power, speed and cost reguirements may dictate different starting parameters for your system (e.g. 320 x 240 @ 78 Hz using 12 MHz clock). 2-70 EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) APPENDIX: SUPPORTED PANEL VALUES Register Table A-2 Passive Dual Panel with 40MHz Pixel Clock Mono 8-Bit Color 8-Bit Color 16-Bit Mono 4-Bit EL 640X480@60Hz REG[02h] REG[03h] REG[04h] REG[05h] REG[08h] REG[09h] REG[0Ah] REG[0Dh] REG[19h] REG[1Bh] REG[24h] REG[26h] Register REG[02h] REG[03h] REG[04h] REG[05h] REG[06h] REG[07h] REG[08h] REG[09h] REG[0Ah] REG[0Bh] REG[0Ch] REG[0Dh] REG[19h] REG[1Bh] REG[24h] REG[26h] 640X480@60Hz 640X480@60Hz 640X480@60Hz 1000 0010 0000 0000 0100 1111 0000 0101 1110 1111 0000 0000 0011 1110 0000 1101 0000 0010 0000 0000 0000 0000 load LUT 0001 0010 0000 0000 0100 1111 0000 0101 1110 1111 0000 0000 0011 1110 0000 1101 0000 0010 0000 0000 0000 0000 load LUT 0001 0110 0000 0000 0100 1111 0000 0101 1110 1111 0000 0000 0011 1110 0000 1101 0000 0010 0000 0000 0000 0000 load LUT 0010 0110 0000 0000 0100 1111 0000 0101 1110 1111 0000 0000 0011 1110 0000 1101 0000 0010 0000 0000 0000 0000 load LUT Notes set panel type set MOD rate set horizontal display width set horizontal non-display period set vertical display height bits 7-0 set vertical display height bits 9-8 set vertical non-display period set 8 bpp and LCD enable set MCLK and PCLK divide enable half frame buffer set Look-Up Table address to 0 load Look-Up Table Table A-3 TFT Single Panel with 25.175MHz Pixel Clock Color 16-Bit Notes 640X480@60Hz 0010 0101 0000 0000 0100 1111 0001 0011 0000 0001 0000 1011 1101 1111 0000 0001 0010 1011 0000 1001 0000 0001 0000 1101 0000 0000 0000 0001 0000 0000 load LUT S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) set panel type set MOD rate set horizontal display width set horizontal non-display period set HSYNC start position set HSYNC polarity and pulse width set vertical display height bits 7-0 set vertical display height bits 9-8 set vertical non-display period set VSYNC start position set VSYNC polarity and pulse width set 8 bpp and LCD enable set MCLK and PCLK divide disable half frame buffer set Look-Up Table address to 0 load Look-Up Table EPSON 2-71 APPENDIX: SUPPORTED PANEL VALUES THIS PAGE IS BLANK. 2-72 EPSON S1D13505 PROGRAMMING NOTES AND EXAMPLES (X23A-G-003-05) ll er ro t n A Co 0 0 T F R 5 0 /C 5 CD 3 1 L D AC 1 S D M A ed Em b d d e R s Ut ie ilit CONTENTS Contents Table of Contents 1 13505CFG CONFIGURATION PROGRAM ...................................................................................3-1 1.1 13505CFG .....................................................................................................................................3-1 S1D13505 Supported Evaluation Platforms ..............................................................................3-1 Installation ..................................................................................................................................3-1 Usage.........................................................................................................................................3-1 1.2 13505CFG Configuration Pages ...................................................................................................3-2 General Page .............................................................................................................................3-3 Memory Page.............................................................................................................................3-4 Panel Page ................................................................................................................................3-5 CRT Page ..................................................................................................................................3-6 Default Page ..............................................................................................................................3-7 Open Dialog Box ........................................................................................................................3-8 Save As Dialog Box ...................................................................................................................3-9 Example ...................................................................................................................................3-10 Comments................................................................................................................................3-11 Sample Program Messages.....................................................................................................3-12 2 13505SHOW DEMONSTRATION PROGRAM ..............................................................................3-13 2.1 13505SHOW ...............................................................................................................................3-13 S1D13505 Supported Evaluation Platforms ............................................................................3-13 Installation ................................................................................................................................3-13 Usage.......................................................................................................................................3-14 13505SHOW Examples ...........................................................................................................3-14 Comments................................................................................................................................3-15 Program Messages ..................................................................................................................3-16 3 13505SPLT DISPLAY UTILITY ................................................................................................3-17 3.1 13505SPLT .................................................................................................................................3-17 S1D13505 Supported Evaluation Platforms ............................................................................3-17 Installation ................................................................................................................................3-17 Usage.......................................................................................................................................3-18 13505SPLT Example ...............................................................................................................3-18 Comments................................................................................................................................3-18 Program Messages ..................................................................................................................3-19 4 13505VIRT DISPLAY UTILITY .................................................................................................3-20 4.1 13505VIRT ..................................................................................................................................3-20 S1D13505 Supported Evaluation Platforms ............................................................................3-20 Installation ................................................................................................................................3-20 Usage.......................................................................................................................................3-21 13505VIRT Example ................................................................................................................3-21 Comments................................................................................................................................3-21 Program Messages ..................................................................................................................3-22 5 13505PLAY DIAGNOSTIC UTILITY ..........................................................................................3-23 5.1 13505PLAY .................................................................................................................................3-23 S1D13505 Supported Evaluation Platforms ............................................................................3-23 Installation ................................................................................................................................3-23 Usage.......................................................................................................................................3-24 13505PLAY Example ...............................................................................................................3-25 Scripting ...................................................................................................................................3-26 Comments................................................................................................................................3-26 Program Messages ..................................................................................................................3-27 6 13505BMP DEMONSTRATION PROGRAM .................................................................................3-28 6.1 13505BMP...................................................................................................................................3-28 S1D13505 Supported Evaluation Platforms ............................................................................3-28 UTILITIES (X23A-B-001-02) EPSON 3-i CONTENTS Installation................................................................................................................................ 3-28 Usage ...................................................................................................................................... 3-28 13505BMP Examples .............................................................................................................. 3-28 Comments ............................................................................................................................... 3-29 Program Messages.................................................................................................................. 3-29 7 13505PWR SOFTWARE SUSPEND POWER SEQUENCING UTILITY ...............................................3-30 7.1 13505PWR.................................................................................................................................. 3-30 S1D13505 Supported Evaluation Platforms ............................................................................ 3-30 Installation................................................................................................................................ 3-30 Usage ...................................................................................................................................... 3-31 13505PWR Examples.............................................................................................................. 3-31 Comments ............................................................................................................................... 3-31 Program Messages.................................................................................................................. 3-32 3-ii EPSON UTILITIES (X23A-B-001-02) CONTENTS List of Figures Figure 1-1 Figure 1-2 Figure 1-3 Figure 1-4 Figure 1-5 General Page .......................................................................................................................3-3 Memory Page .......................................................................................................................3-4 Panel Page...........................................................................................................................3-5 CRT Page.............................................................................................................................3-6 Default Page.........................................................................................................................3-7 UTILITIES (X23A-B-001-02) EPSON 3-iii 1: 13505CFG CONFIGURATION PROGRAM 1 13505CFG CONFIGURATION PROGRAM 1.1 13505CFG 13505CFG is an interactive Windows(R) `9x program that calculates the S1D13505 register values for a user-defined LCD panel/CRT configuration. The S1D13505 utilities can have their configurations opened, changed, and saved, all from within 13505CFG. 13505CFG is designed to work with the S1D13505 utilities, or any program designed by a software/ hardware developer using the Hardware Abstraction Layer (HAL) library. The configuration information can be saved directly into the utility or into a text header file for use by the software/hardware developer. Note: Seiko Epson does not assume liability for any damage done to the display device as a result of software configuration errors. S1D13505 Supported Evaluation Platforms 13505CFG only runs on a PC system running Windows `9x. 13505CFG can edit the executable files for the following S1D13505 evaluation platforms: * PC system with an Intel 80x86 processor. * M68332BCC (Business Card Computer) board, revision B, with a Motorola MC68332 processor. * M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. * SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. Installation Copy the file 13505CFG.EXE to a directory on your hard drive that is in the DOS path. Usage In Windows 95, double-click the following icon: UTILITIES (X23A-B-001-02) EPSON 3-1 1: 13505CFG CONFIGURATION PROGRAM 1.2 13505CFG Configuration Pages 13505CFG provides a series of pages which can be selected by a tab at the top of the main window. The pages are "General", "Memory", "Panel", "CRT", and "Default". At the bottom of the window are three buttons: Open, Save As, and Exit. The basic procedure for using 13505CFG is as follows: OPEN the configuration values from a current utility (this step is optional). Change the configuration values as required (see each page description for configuration details). SAVE the configuration values into the desired utilities, or into an ASCII header file. Each utility must be configured seperately. Note: 13505CFG is designed to work with utilities programmed using a given version of the HAL. If the configuration structure is of a different version, an error message is displayed. 3-2 EPSON UTILITIES (X23A-B-001-02) 1: 13505CFG CONFIGURATION PROGRAM General Page Figure 1-1 General Page The General Page allows the user to select the following general platform settings: Register Address Memory Address CPU Bus Width ClkI Bus Clk General Page Starting address of the registers (in hexadecimal). Starting address of the display buffer (in hexadecimal). Host CPU bus width (applicable only to PC). Clock frequency. Host bus clock frequency. Also displayed is the memory clock frequency and the pixel clock frequencies for the following modes: LCD, CRT , and simultaneous display. These clock values will change based on settings on both the General Page and other configuration pages. These clock frequencies are useful in determining why a particular display mode cannot be set. See the "S1D13505 Hardware Functional Specification" for more details. UTILITIES (X23A-B-001-02) EPSON 3-3 1: 13505CFG CONFIGURATION PROGRAM Memory Page Figure 1-2 Memory Page The Memory Page allows the user to select the following settings: Timing (ns) Memory Type WE# Control Refresh time (ms) Trc Trp Trac Suspend Mode Refresh 3-4 Memory Page Access time for memory. EDO or FPM. 2CAS# or 2WE#. DRAM Refresh Rate (time for 256 refresh cycles). Use the values in the DRAM specification. For the S5U13505P00C Evaluation Board, use the values shown in the "Default" column. The values in the "Default" column will change based on the Memory Timing. Type of DRAM refresh used in suspend mode. EPSON UTILITIES (X23A-B-001-02) 1: 13505CFG CONFIGURATION PROGRAM Panel Page Figure 1-3 Panel Page The Panel Page allows the user to select the following settings: Single/Dual Disable half frame buffer Mono/Color Format 2 STN/TFT EL Panel Interface FPline Polarity FPframe Polarity Dimensions Frame Rate UTILITIES (X23A-B-001-02) Panel Page Select between a single and dual panel. If no panel exists, select single. The half frame buffer is used only for dual panels. Disabling the half frame buffer is not recommended as this will reduce the display quality. Select between a monochrome and color panel. If no panel exists, select color. Select color passive LCD panel format 2. See the "S1D13505 Hardware Functional Specification" for format 1/format 2 description. Select between a passive LCD and TFT/D-TFD panel. Enable EL panel support. Select panel interface width in bits. The bit width values will change when selecting between STN and TFT/D-TFD panels. Select the polarity of the FPLINE pulse. Select the polarity of the FPFRAME pulse. Select the width and height of the panel in pixels. Select the desired frame rate. EPSON 3-5 1: 13505CFG CONFIGURATION PROGRAM CRT Page Figure 1-4 CRT Page The CRT Page allows the user to select the following settings: CRT Dimensions CRT Frame Rate Simultaneous Display Options 3-6 CRT Page Select the desired resolution. See "Comments" on page 11 if the desired CRT dimensions are grayed out. Select the desired frame rate. See "Comments" on page 11 to determine valid CRT frame rates. For simultaneous display only. Will be grayed out if simultaneous display is not supported based on the other configuration settings. For summary of Simultaneous Display options see the Hardware Functional Specification. EPSON UTILITIES (X23A-B-001-02) 1: 13505CFG CONFIGURATION PROGRAM Default Page Figure 1-5 Default Page The Default Page allows the user to select the following settings: Display Color Depth UTILITIES (X23A-B-001-02) Default Page Select the default display device. Three display modes (LCD, CRT, and Simultaneous) are saved, but the S1D13505 software initializes the registers based on the default mode. Select the default color depth. EPSON 3-7 1: 13505CFG CONFIGURATION PROGRAM Open Dialog Box When the "OPEN" button is pressed on the main window, the Open Dialog Box is shown. 13505CFG will read the configuration values from a specific EXE file for Intel platforms, and from a specific S9 file for non-Intel platforms. The file must have been compiled using a valid version of the 13505HAL library. 3-8 EPSON UTILITIES (X23A-B-001-02) 1: 13505CFG CONFIGURATION PROGRAM Save As Dialog Box When the "Save As" button is pressed on the main window, 13505CFG checks for any invalid configuration values and shows any appropriate warning or error messages. If it is possible to save the values, the Save As Dialog Box is shown. The configuration values can be saved to a specific EXE file for Intel platforms, and to a specific S9 file for non-Intel platforms. The file must have been compiled using a valid version of the 13505HAL library. The configuration values can also be saved to an ASCII header file (ie. 13505reg.h) for use by the software/hardware developer. UTILITIES (X23A-B-001-02) EPSON 3-9 1: 13505CFG CONFIGURATION PROGRAM Example Configure for an 8-bit color single passive 640x480 LCD panel and the S5U13505P00C Evaluation Board on a PC: General Page Register Address Memory Address CPU Bus Width ClkI Bus Clk Timing (ns) Memory Type WE# Control Refresh time (ms) Trc Trp Trac Suspend Mode Refresh Single/Dual Disable half frame buffer Mono/Color Format 2 STN/TFT EL Panel Interface FPline Polarity FPframe Polarity Dimensions Frame Rate CRT Dimensions CRT Frame Rate Simultaneous Display Options 0xE00000 0xC00000 16 bit 25175 kHz 8000 kHz Memory Page 60 ns EDO 2-CAS# 32 ms 104 ns 40 ns 60 ns CAS before RAS Panel Page Single (unchecked) Color (unchecked) STN (unchecked) 8 bit Hi Hi 640 x 480 60 CRT Page 640 x 480 60 Normal Default Page Display Color Depth Panel 16 bpp Note: The above configuration also supports simultaneous display and CRT only modes. 3-10 EPSON UTILITIES (X23A-B-001-02) 1: 13505CFG CONFIGURATION PROGRAM Comments * It is assumed that the 13505CFG user is familiar with S1D13505 hardware and software. Refer to the "S1D13505 Functional Hardware Specification" and the "S1D13505 Programming Notes and Examples" for more details. * 13505CFG verifies that the given configuration meets the limitations in the hardware specification. Part of this verification process is as follows: 1. The divide ratio for the source clock/MClk is determined based on Table 14-3: Example Frame Rates with Ink Disabled from the Functional Hardware Specification. According to this table, MClk cannot exceed 40 MHz for 50ns EDO-DRAM, MClk cannot exceed 33 MHz for 60ns EDO-DRAM, and MClk cannot exceed 25 MHz for 60ns FPM-DRAM. If MClk exceeds the maximum value, the MCLK value is set to the source clock divided by two (MClk = source clock / 2). Otherwise the MCLK value is set to the source clock (MClk = source clock). 13505CFG shows the MClk value on the General Page. 2. The divide ratio for MClk/PClk is determined based on Table 14-1: Maximum PCLK Frequency with EDO-DRAM and Table 14-2: Maximum PCLK Frequency with FPM-DRAM. Once this ratio is determined, PClk = MClk / ratio. Note that there are two PClk divide ratios based on the three display modes: panel, CRT, and simultaneous display (CRT and simultaneous display use the same ratio). 13505CFG shows the PClk values for these three modes on the General Page. 3. The HNDP and VNDP values are calculated based on the desired frame rate for each of the three modes (panel, CRT, simultaneous), the display's HDP (X resolution), VDP (Y resolution), and maximum PCLK as calculated in step 3. PCLK FrameRate = ---------------------------------------------------------------------------------------( HDP + HNDP ) x ( VDP + VNDP ) 4. If it is not possible to reach the desired frame rate within 5%, an error message is shown when saving the configuration. * When configuring either the CRT or TFT/D-TFD panel, the PClk must be the same as the required VESA frequency for the given VESA mode. The following VESA modes are supported: Resolution 640x480 800x600 Frame Rate (Hz) PCLK (MHz) 60 25.175 72 75 85 56 60 31.500 31.500 36.000 36.000 40.000 Supported DRAM Types 50ns EDO, 60ns EDO, 70ns EDO, 60ns FPM 50ns EDO, 60ns EDO 50ns EDO, 60ns EDO 50ns EDO 50ns EDO 50ns EDO * 13505CFG does not support 50ns FPM-DRAM. * 13505CFG programs TFT/D-TFD panels with the same VESA timings as a CRT, so the CRT restrictions shown in the hardware specification also apply to TFT/D-TFD panels. Consequently for TFT/D-TFD panels, use the CRT frame rate and CRT PCLK as described above. * For simultaneous display, select a CRT VESA mode, and use the CRT's frame rate for the panel's frame rate. UTILITIES (X23A-B-001-02) EPSON 3-11 1: 13505CFG CONFIGURATION PROGRAM Sample Program Messages ERROR: Panel frame rate must be greater than zero Select an appropriate panel frame rate as recommended in the panel specifications. ERROR: Unable to save current settings Could not save configuration values. The reason why is generally given before this message is shown. ERROR: Invalid clock frequency selected The ClkI frequency is either too low or too high. ERROR: Max. clock for 50ns FPM is unspecified 13505CFG does not support 50ns FPM-DRAM. WARNING: Cannot set panel display mode This message is shown if the configuration settings do not meet the hardware specifications, or if the desired frame rate cannot be reached within 5%. See "Comments" on page 11 for more information. WARNING: Cannot set simul display mode This message is shown if the configuration settings do not meet the hardware specifications, or if the desired frame rate cannot be reached within 5%. See "Comments" on page 11 for more information. WARNING: Cannot set CRT display mode This message is shown if the configuration settings do not meet the hardware specifications, or if the desired frame rate cannot be reached within 5%. See "Comments" on page 11 for more information. -PClk too slow to support 640 x 480 This message is shown after the "Cannot set ??? display mode" message. See "Comments" on page 11 to adjust the PClk. -PClk too slow to support 800 x 600 This message is shown after the "Cannot set ??? display mode" message. See "Comments" on page 11 to adjust PClk. Notice: Invalid clock selected for VESA frequencies. The monitor may not sync! This message is shown in the CRT Page when the PClk is not set to a standard VESA frequency. See "Comments" on page 11 to adjust the PClk. ERROR: Unknown HAL version. When reading from or writing to a S1D13505 utility, 13505CFG could not find the start of a valid configuration table. ERROR: Unable to open <filename> Possible cause - no HAL information 13505CFG could not find the HAL configuration table. ERROR: encountered while reading .S9 file. The S9 file is corrupted. ERROR: while attempting to write .S9 file. The S9 file is corrupted. 3-12 EPSON UTILITIES (X23A-B-001-02) 2: 13505SHOW DEMONSTRATION PROGRAM 2 13505SHOW DEMONSTRATION PROGRAM 2.1 13505SHOW 13505SHOW is designed to demonstrate and test some of the S1D13505 display capabilities. The program can cycle through all the color depths and display a pattern showing all available colors, or the user can specify a color depth and display configuration. The 13505SHOW demonstration program must be configured and/or compiled to work with your hardware platform. The program 13505CFG.EXE can be used to configure 13505SHOW. Consult the "13505CFG Configuration Program (X23A-B-001-02)" for more information on configuring S1D13505 utilities. This software is designed to work in both embedded and personal computer (PC) environments. For the embedded environment, it is assumed that the system has a means of downloading software from the PC to the target platform. Typically this is done by serial communications, where the PC uses a terminal program to send control commands and information to the target processor. Alternatively, the PC can program an EPROM, which is then placed in the target platform. Some target platforms can also communicate with the PC via a parallel port connection, or an Ethernet connection. S1D13505 Supported Evaluation Platforms 13505SHOW supports the following S1D13505 evaluation platforms: * PC system with an Intel 80x86 processor. * M68332BCC (Business Card Computer) board, revision B, with a Motorola MC68332 processor. * M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. * SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. Installation * PC platform: copy the file 13505SHOW.EXE to a directory that is in the DOS path on your hard drive. * Embedded platform: download the program 13505SHOW to the system. UTILITIES (X23A-B-001-02) EPSON 3-13 2: 13505SHOW DEMONSTRATION PROGRAM Usage PC platform: at the prompt, type 13505show [b=??] [/a] [/crt] [/g] [/lcd] [/noinit] [/p] [/read] [/ s] [/?]. Embedded platform: execute 13505show and at the prompt, type the command line argument. Where: b=?? starts 13505SHOW at a user specified bit-per-pixel (bpp) level, where ?? can be: 1, 2, 4, 8, 15, or 16 /a automatically cycles through all video modes /crt displays the image on the CRT /g shows grid on the image /lcd displays the image on the LCD panel /noinit bypasses register initialization /p draws the image in portrait mode /read after drawing the image, continually read from the screen (for testing purposes) /s displays vertical stripe pattern /? displays the help screen Note: Pressing the ESC key will exit the program. 13505SHOW Examples The 13505SHOW demonstration program is designed to both demonstrate and test some of the features of the S1D13505. Some examples follow showing how to use the program in both instances. Using 13505SHOW For Demonstration 1. To show color patterns which must be manually stepped through all bit-per-pixel modes, type the following: 13505SHOW The program will display 16 bit-per-pixel mode. Press any key to go to the next screen. The program will display 15 bit-per-pixel mode. Once all screens are shown the program exits. To exit the program immediately press ESC. 2. To show color patterns which automatically step through all bit-per-pixel modes, type the following: 13505SHOW /a The program will display 16 bit-per-pixel mode. Each screen is shown for approximately 1 second, then the next screen is automatically shown. The program exits after the last screen is shown. To exit the program immediately press CTRL+BREAK. 3. To show a color pattern for a specific bit-per-pixel mode, type the following: 13505SHOW b=[mode] where mode = 1, 2, 4, 8, 15, or 16. The program will display the requested screen and then exit. 3-14 EPSON UTILITIES (X23A-B-001-02) 2: 13505SHOW DEMONSTRATION PROGRAM 4. To show the color patterns in portrait mode, type the following: 13505SHOW /p The program will display 16 bit-per-pixel mode. Press any key to go to the next screen. The program will next display 15 bit-per-pixel mode and then 8 bit-per-pixel mode. Since portrait mode is limited to 8, 15, and 16 bit-per-pixel mode the program exits. To exit the program immediately press ESC. The "/p" switch can be used in combination with other command line switches. 5. To show solid vertical stripes, type the following: 13505SHOW /s The program will display 16 bit-per-pixel mode. Press any key to go to the next screen. The program will display 15 bit-per-pixel mode. Once all screens are shown the program exits. To exit the program immediately press ESC. The "/s" switch can be used in combination with other command line switches. Using 13505SHOW For Testing 1. To show a test grid other the color pattern, type the following: 13505SHOW b=8 /g The program will display the 8 bit-per-pixel color pattern overlayed with a white grid pattern and then exit. Note the grid is not aligned with the color pattern, therefore the color boxes will not match the grid boxes. The "/g" switch can be used in combination with other command line switches. 2. To test background memory reads, type the following: 13505SHOW b=16 /read The program will test screen reads. If there is a problem with memory access, the displayed pattern will appear different than when the "/read" switch is not used. If there is a problem, check the configuration parameters of 13505SHOW using the utility 13505CFG. See the 13505CFG Configuration Program (X23A-B-001-02) for more information. The "/read" switch should be used in combination with the "b=" setting, otherwise the test will always start with the 16 bit-per-pixel screen. To exit the program after using "/read", press ESC and wait for a couple of seconds (the keystroke is checked after reading a full screen). Comments * 13505SHOW cannot show a greater color depth than the display allows. * Portrait mode is available only for 8, 15, and 16 bit-per-pixel. * When using a PC with the S5U13505P00C evaluation board, the PC must not have more than 12M bytes of system memory. * 13505SHOW uses the panel color setup to determine whether to display a mono or color image on both the panel and the CRT. When editing in 13505CFG with CRT enabled and panel disabled, select "Color" from the "Panel" dialog box if you want the CRT to show color. * For simultaneous display, select both "/lcd" and "/crt". * If the "b=" option is not used, 13505SHOW will cycle through all available bit-per-pixel modes. UTILITIES (X23A-B-001-02) EPSON 3-15 2: 13505SHOW DEMONSTRATION PROGRAM Program Messages ERROR: Could not initialize device. These messages generally mean that the given hardware/software setup violates the timing limitations described in the S1D13505 Hardware Functional Specification. ERROR: Too many devices registered. There are too many display devices attached to the HAL. The HAL currently supports only one device. ERROR: Could not register S1D13505F00A device. A S1D13505 device was not found at the configured addresses. Check the configuration address using the "13505CFG configuration program". ERROR: Did not find a 13505 device. The HAL was unable to read the revision code register on the S1D13505. Ensure that the S1D13505 hardware is installed and that the hardware platform has been set up correctly. ERROR: Continual screen read will not work with the /a switch. The continual screen read function reads one screen indefinitely, so it is not possible to automatically cycle through the video modes. WARNING: b= option used with /noinit, so bit-per-pixel and display memory will NOT be changed. The b= option requests that registers be changed for a given bit-per-pixel mode, while the /noinit option requests the opposite. To resolve this contradiction 13505SHOW will not change either the registers or the display memory. Consequently "13505SHOW b=?? /noinit" is only useful for continually reading the display memory. UNSUPPORTED MODE: Cannot show ?? bpp in portrait mode. Only 8, 15, 16 bit-per-pixel modes are supported in portrait mode. 3-16 EPSON UTILITIES (X23A-B-001-02) 3: 13505SPLT DISPLAY UTILITY 3 13505SPLT DISPLAY UTILITY 3.1 13505SPLT 13505SPLT demonstrates S1D13505 split screen capability by showing two different areas of display memory on the screen simultaneously. Screen 1 shows horizontal bars and Screen 2 shows vertical bars. Screen 1 memory is located at the start of the display buffer. Screen 2 memory is located immediately after Screen 1 in the display buffer. On user input, or elapsed time, the line compare register value is changed to adjust the amount of area displayed on either screen. The result is a movement up or down of screen 2 on the display. The 13505SPLT display utility must be configured and/or compiled to work with your hardware platform. The program 13505CFG.EXE can be used to configure 13505SPLT. Consult the "13505CFG Configuration Program (X23A-B-001-02)" for more information on configuring S1D13505 utilities. This software is designed to work in both embedded and personal computer (PC) environments. For the embedded environment, it is assumed that the system has a means of downloading software from the PC to the target platform. Typically, this is done by serial communications. The PC uses a terminal program to send control commands and information to the target processor. Alternatively, the PC can program an EPROM, which is then placed in the target platform. Some target platforms can also communicate with the PC via a parallel port connection, or an Ethernet connection. S1D13505 Supported Evaluation Platforms 13505SPLT supports the following S1D13505 evaluation platforms: * PC system with an Intel 80x86 processor. * M68332BCC (Business Card Computer) board, revision B, with a Motorola MC68332 processor. * M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. * SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. Installation PC platform: copy the file 13505SPLT.EXE to a directory that is in the DOS path on your hard drive. Embedded platform: download the program 13505SPLT to the system. UTILITIES (X23A-B-001-02) EPSON 3-17 3: 13505SPLT DISPLAY UTILITY Usage PC platform: at the prompt, type 13505splt [/a] [/?]. Embedded platform: execute 13505splt and at the prompt, type the command line argument. Where: no argument enables manual split screen operation /a enables automatic split screen operation /? displays the help screen The following keyboard commands are for navigation within the program. Manual mode: moves Screen 2 up one line moves Screen 2 down one line CTRL- moves Screen 2 up several lines CTRL- moves Screen 2 down several lines HOME Screen 2 moved up as high as possible END Screen 2 moved down as low as possible Automatic and Manual modes: b changes the color depth (bit-per-pixel) ESC exits 13505SPLT 13505SPLT Example 1. Type "13505splt /a" to automatically move the split screen. 2. Press "b" to change the bit-per-pixel value from 16 to 15 bit-per-pixel. 3. Repeat step 2 for the remaining bit-per-pixel color depths: 8, 4, 2, and 1. 4. Press <ESC> to exit the program. Comments * When using a PC with the S5U13505P00C evaluation board, the PC must not have more than 12M bytes of system memory. 3-18 EPSON UTILITIES (X23A-B-001-02) 3: 13505SPLT DISPLAY UTILITY Program Messages ERROR: Did not find a 13505 device. The HAL was unable to read the revision code register on the S1D13505. Ensure that the S1D13505 hardware is installed and that the hardware platform has been set up correctly. ERROR: Too many devices registered. There are too many display devices attached to the HAL. The HAL currently supports only one device. ERROR: Could not register S1D13505F00A device. A S1D13505 device was not found at the configured addresses. Check the configuration address using the 13505CFG configuration program. ERROR: Could not set ?? bit-per-pixel display mode. This message generally means that the given hardware/software setup violates the timing limitations described in the "S1D13505 Hardware Functional Specification". UTILITIES (X23A-B-001-02) EPSON 3-19 4: 13505VIRT DISPLAY UTILITY 4 13505VIRT DISPLAY UTILITY 4.1 13505VIRT 13505VIRT demonstrates the virtual display capability of the S1D13505. A virtual display is where the image to be displayed is larger than the physical display device (CRT or LCD). 13505VIRT uses panning and scrolling to allow the display device to show a "window" into the entire image. The 13505VIRT display utility must be configured and/or compiled to work with your hardware platform. The program 13505CFG.EXE can be used to configure 13505VIRT. Consult the "13505CFG Configuration Program (X23A-B-001-02)" for more information on configuring S1D13505 utilities. This software is designed to work in both embedded and personal computer (PC) environments. For the embedded environment, it is assumed that the system has a means of downloading software from the PC to the target platform. Typically this is done by serial communications, where the PC uses a terminal program to send control commands and information to the target processor. Alternatively, the PC can program an EPROM, which is then placed in the target platform. Some target platforms can also communicate with the PC via a parallel port connection, or an Ethernet connection. S1D13505 Supported Evaluation Platforms 13505VIRT has been tested with the following S1D13505 supported evaluation platforms: * PC system with an Intel 80x86 processor. * M68332BCC (Business Card Computer) board, revision B, with a Motorola MC68332 processor. * M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. * SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. Installation PC platform: copy the file 13505VIRT.EXE to a directory that is in the DOS path on your hard drive. Embedded platform: download the program 13505VIRT to the system. 3-20 EPSON UTILITIES (X23A-B-001-02) 4: 13505VIRT DISPLAY UTILITY Usage PC platform: at the prompt, type 13505virt [w=??] [/a] [/?]. Embedded platform: execute 13505virt and at the prompt, type the command line argument. Where: no argument panning and scrolling is performed manually w=?? for manual mode, specifies the width of the virtual display which must be a multiple of 8 and less than 2048 (the default width is double the physical panel width); the maximum height is based on the display memory /a panning and scrolling is performed automatically /? displays the help screen The following keyboard commands are for navigation within the program. Manual mode: scrolls up scrolls down pans to the left pans to the right CTRL- scrolls up several lines CTRL- scrolls down several lines CTRL- pans to the left several lines CTRL- pans to the right several lines HOME moves the display screen so that the upper right corner of the virtual screen shows in the display END moves the display screen so that the lower left corner of the virtual screen shows in the display Automatic and Manual modes: b changes the color depth (bit-per-pixel) ESC exits 13505VIRT 13505VIRT Example 1. Type "13505virt /a" to automatically pan and scroll. 2. Press "b" to change the bit-per-pixel value from 16 to 15 bit-per-pixel. 3. Repeat step 2 for the following bit-per-pixel values: 16, 15, 8, 4, 2, and 1. 4. Press <ESC> to exit the program. Comments * When using a PC with the S5U13505P00C evaluation board, the PC must not have more than 12M bytes of system memory. UTILITIES (X23A-B-001-02) EPSON 3-21 4: 13505VIRT DISPLAY UTILITY Program Messages ERROR: Did not find a 13505 device. The HAL was unable to read the revision code register on the S1D13505. Ensure that the S1D13505 hardware is installed and that the hardware platform has been set up correctly. ERROR: Too many devices registered. There are too many display devices attached to the HAL. The HAL currently supports only one device. ERROR: Could not register S1D13505F00A device. A S1D13505 device was not found at the configured addresses. Check the configuration address using the 13505CFG configuration program. ERROR: Not enough display buffer memmory for ?? bpp. There was not enough memory for a virtual screen. 3-22 EPSON UTILITIES (X23A-B-001-02) 5: 13505PLAY DIAGNOSTIC UTILITY 5 13505PLAY DIAGNOSTIC UTILITY 5.1 13505PLAY 13505PLAY is a diagnostic utility which allows the user to read/write to all the S1D13505 Registers, Look-Up Tables and Display Buffer. 13505PLAY is similar to the DOS DEBUG program; commands are received from the standard input device, and output is sent to the standard output device (console for Intel, terminal for embedded platforms). This utility requires the target platform to support standard IO (stdio). 13505PLAY commands can be entered interactively by a user, or be executed from a script file. Scripting is a powerful feature which allows command sequences to be used repeatedly without re-entry. The 13505PLAY diagnostic utility must be configured and/or compiled to work with your hardware platform. The program 13505CFG.EXE can be used to configure 13505PLAY. "Consult the 13505CFG Configuration Program (X23A-B-001-02)" for more information on configuring S1D13505 utilities. This software is designed to work in both embedded and personal computer (PC) environments. For the embedded environment, it is assumed that the system has a means of downloading software from the PC to the target platform. Typically this is done by serial communications, where the PC uses a terminal program to send control commands and information to the target processor. Alternatively, the PC can program an EPROM, which is then placed in the target platform. Some target platforms can also communicate with the PC via a parallel port connection, or an Ethernet connection. S1D13505 Supported Evaluation Platforms 13505PLAY supports the following S1D13505 evaluation platforms: * PC system with an Intel 80x86 processor. * M68332BCC (Business Card Computer) board, revision B, with a Motorola MC68332 processor. * M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. * SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. Installation PC platform: copy the file 13505PLAY.EXE to a directory that is in the DOS path on your hard drive. Embedded platform: download the program 13505PLAY to the system. UTILITIES (X23A-B-001-02) EPSON 3-23 5: 13505PLAY DIAGNOSTIC UTILITY Usage PC platform: at the prompt, type 13505play [/?]. Embedded platform: execute 13505play and at the prompt, type the command line argument. Where: /? displays program version information. The following commands are valid within the 13505PLAY program. b 8|16 - Sets the ISA bus to 8 or 16 bits. - Only sets up the PAL on the S5U13505P00C evaluation board. There is no readback capability. - Only supported on a S5U13505P00C evaluation board for the PC platform. Switch 1-1 on the ealuation board must be set to the same bus width as used with this command. f[w] addr1 addr2 data . . . - Fills bytes or words [w] from address 1 to address 2 with the data specified. - Data can be multiple values (e.g. F 0 20 1 2 3 4 fills 0 to 0x20 with a repeating pattern of 1 2 3 4). h [lines] - Halts after lines of display. This feature halts the display during long read operations to prevent data from scrolling off the display. Similar to the DOS MORE command. - Set to 0 to disable this feature. i [LCD] [CRT] - Initializes the chip with the specified configuration. The configuration is embedded in the 13505PLAY utility and can be changed using the 13505CFG util ity. See the "13505CFG Configuration Program (X23AB-001-02)", for instructions on changing the configuration. - If the output device is specified, the user can select LCD, CRT, or both devices. l index [red green blue] - Reads/writes Look-Up Table (LUT) values. - Writes data to the LUT[index] when data is speci fied. - Reads the LUT[index] when the data is not speci fied. la - Reads all LUT values. m [bpp] - Reads current mode information. - Sets the color depth (bpp) if "bpp" is specified. 3-24 EPSON UTILITIES (X23A-B-001-02) 5: 13505PLAY DIAGNOSTIC UTILITY - Set power mode (hardware suspend). 1 = set hardware suspend. 0 = reset hardware suspend. p 1|0 - This command is only supported on a S5U13505P00C evaluation board for the PC platform. q - Quits the 13505PLAY utility. r[w] addr [count] - Reads number of bytes or words [w] from the address specified by "addr". If "count" is not specified, then 16 bytes/words are read. v - Calculates the frame rate from VNDP count (PC platform only). w[w] addr data . . . - Writes bytes or words [w] of data to the address specified by "addr". - Data can be multiple values (e.g. W 0 1 2 3 4 writes the byte values 1 2 3 4 starting at address 0). x index [data] - Reads/writes the registers. - - Writes data to REG[index] when "data" is specified. Reads data from REG[index] when "data" is not specified. xa - Reads all registers. ? - Displays Help information. 13505PLAY Example 1. Type "13505PLAY" to start the program. 2. Type "?" for help. 3. Type "i" to initialize the registers. 4. Type "xa" to display the contents of the registers. 5. Type "x 5" to read register 5. 6. Type "x 3 10" to write 10h to register 3. 7. Type "f 0 ffff aa" to fill the first FFFFh bytes of the display buffer with AAh. 8. Type "f 0 1fffff aa" to fill 2M bytes of the display buffer with AAh. 9. Type "r 0 100" to read the first 100h bytes of the display buffer. 10. Type "q" to exit the program. UTILITIES (X23A-B-001-02) EPSON 3-25 5: 13505PLAY DIAGNOSTIC UTILITY Scripting 13505PLAY can be driven by a script file. This is useful when: * there is no display output and a current register status is required. * various registers must be quickly changed to view results. A script file is an ASCII text file with one 13505PLAY command per line. All scripts must end with a "q" (quit) command. On a PC platform, a typical script command line might be: "13505PLAY < dumpregs.scr > results." This causes the file "dumpregs.scr" to be interpreted as commands by 13505PLAY and the results to be sent to the file "results." Example: Create an ASCII text file that contains the commands i, xa, and q. ; This file initializes the S1D13505 and reads the registers. ; Note: after a semicolon (;), all characters on a line are ignored. ; Note: all script files must end with the "q" command. i xa q Comments * All numeric values are considered to be hexadecimal unless identified otherwise. For example, 10 = 10h = 16 decimal; 10t = 10 decimal; 010b = 2 decimal. * Redirecting commands from a script file (PC platform) allows those commands to be executed as though they were typed. * When using a PC with the S5U13505P00C evaluation board, the PC must not have more than 12M bytes of system memory. 3-26 EPSON UTILITIES (X23A-B-001-02) 5: 13505PLAY DIAGNOSTIC UTILITY Program Messages WARNING: Did not find a 13505 device. The HAL was unable to read the revision code register on the S1D13505. Ensure that the S1D13505 hardware is installed and that the hardware platform has been set up correctly. ERROR: Failed to change to ?? mode. Could not change to CRT, LCD, or SIMUL mode. This message generally means that the given hardware/software setup violates the timing limitations described in the S1D13505 Hardware Functional Specification. ERROR: Could not change to ?? bit-per-pixel. This message generally means that the given hardware/software setup violates the timing limitations described in the S1D13505 Hardware Functional Specification. ERROR: Too many devices registered. There are too many display devices attached to the HAL. The HAL currently supports only one device. ERROR: Could not register S1D13505F00A device. A S1D13505 device was not found at the configured addresses. Check the configuration address using the 13505CFG configuration program. ERROR: Insufficient memory for ?? bit-per-pixel. The given display resolution requires a larger display buffer than is available to store the image. Either increase the amount of display buffer or select a lower color depth (bpp). WARNING: Clocks are too fast for given mode. This message is only shown if the "m" command was entered and the MCLK/PCLK frequencies violated the timings in the "S1D13505 Hardware Functional Specification". UTILITIES (X23A-B-001-02) EPSON 3-27 6: 13505BMP DEMONSTRATION PROGRAM 6 13505BMP DEMONSTRATION PROGRAM 6.1 13505BMP 13505BMP is a demonstration utility used to show the S1D13505 display capabilities by rendering bitmap images on the display. The program will display any bitmap in Windows BMP file format and then exit. A 24-bit true color bitmap will be truncated to 16 bit-per-pixel mode. 13505BMP is designed to operate on a personal computer (PC) in the DOS environment. Other embedded platforms are not supported due to the lack of memory and structured file systems. The 13505BMP demonstration utility must be configured and/or compiled to work with your hardware configuration. The program 13505CFG.EXE can be used to configure 13505BMP. "Consult the 13505CFG Configuration Program (X23A-B-001-02)" for more information on configuring S1D13505 utilities. S1D13505 Supported Evaluation Platforms 13505BMP supports the following S1D13505 evaluation platforms: * PC system with an Intel 80x86 processor. Note: The 13505BMP source code may be modified by the OEM to support other evaluation platforms. Installation Copy the file 13505BMP.EXE to a directory that is in the DOS path on your hard drive. Usage At the prompt, type 13505bmp bmpfile [/a] [/crt] [/lcd] [/p] [/?]. Where: bmpfile filename of a windows format bmp image /a adds a 2 second delay before automatically exiting /crt displays the image on a CRT /lcd displays the image on a LCD /p portrait mode /? displays the Help screen Note: 13505BMP will automatically finish execution and return to the prompt. 13505BMP Examples To display a bmp image on a CRT, type the following: 13505BMP bmpfile.bmp /crt To display a bmp image on a LCD, type the following: 13505BMP bmpfile.bmp /lcd To display a bmp image on a LCD in portrait mode, type the following: 13505BMP bmpfile.bmp /lcd /p To display a bmp image on a CRT and delay 2 seconds before exiting, type the following: 13505BMP bmpfile.bmp /crt /a 3-28 EPSON UTILITIES (X23A-B-001-02) 6: 13505BMP DEMONSTRATION PROGRAM Comments * 13505BMP displays only Windows BMP format images. * The PC must not have more than 12M bytes of memory when used with the S5U13505P00C evaluation board. * Only the green component of the image will be seen on a monochrome display. Program Messages ERROR: Could not initialize device. These messages generally mean that the given hardware/software setup violates the timing limitations described in the "S1D13505 Hardware Functional Specification". ERROR: Did not find a 13505 device. The HAL was unable to read the revision code register on the S1D13505. Ensure that the S1D13505 hardware is installed and that the hardware platform has been set up correctly. ERROR: Too many devices registered. There are too many display devices attached to the HAL. The HAL currently supports only one device. ERROR: Could not register S1D13505F00A device. A S1D13505 device was not found at the configured addresses. Check the configuration address using the 13505CFG configuration program. ERROR: Did not detect S1D13505. The HAL was unable to read the revision code register on the S1D13505. Ensure that the S1D13505 hardware is installed and that the hardware platform has been set up correctly. ERROR: Insufficient memory for ?? bit-per-pixel. The given display resolution requires more memory than is available to store one complete image. Either increase the amount of display memory or select an image with a lower bit-per-pixel value. UTILITIES (X23A-B-001-02) EPSON 3-29 7: 13505PWR SOFTWARE SUSPEND POWER SEQUENCING UTILITY 7 13505PWR SOFTWARE SUSPEND POWER SEQUENCING UTILITY 7.1 13505PWR 13505PWR is a diagnostic utility used to test some of the power save capabilities of the S1D13505. 13505PWR enables or disables the software suspend mode, hardware suspend mode, and the LCD, allowing testing of the power sequencing in each mode. To measure the timing for power sequencing, GPIO pin 1 is used to trigger an oscilloscope at the point the requested power sequencing function is activated/deactivated. For further information on LCD Power Sequencing and Power Save Modes, refer to the "S1D13505 Programming Notes and Examples" and the "S1D13505 Functional Hardware Specification". The 13505PWR software suspend power sequencing utility must be configured and/or compiled to work with your hardware platform. The program 13505CFG.EXE can be used to configure 13505PWR. Consult the "13505CFG Configuration Program (X23A-B-001-02)" for more information on configuring S1D13505 utilities. This software is designed to work in both embedded and personal computer (PC) environments. For the embedded environment, it is assumed that the system has a means of downloading software from the PC to the target platform. Typically this is done by serial communications, where the PC uses a terminal program to send control commands and information to the target processor. Alternatively, the PC can program an EPROM, which is then placed in the target platform. Some target platforms can also communicate with the PC via a parallel port connection, or an Ethernet connection. S1D13505 Supported Evaluation Platforms 13505PWR supports the following S1D13505 evaluation platforms: * PC system with an Intel 80x86 processor. * M68332BCC (Business Card Computer) board, revision B, with a Motorola MC68332 processor. * M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. * SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. Installation PC platform: copy the file 13505PWR.EXE to a directory that is in the DOS path on your hard drive. Embedded platform: download the program 13505PWR to the system. 3-30 EPSON UTILITIES (X23A-B-001-02) 7: 13505PWR SOFTWARE SUSPEND POWER SEQUENCING UTILITY Usage PC platform: at the prompt, type 13505pwr [/software /hardware | /lcd] [/enable /disable] [/i] [/0 | /1] [/?]. Embedded platform: execute 13505pwr and at the prompt, type the command line argument. Where: /software selects software suspend /hardware selects hardware suspend (PC only) /lcd selects the LCD /enable activates software suspend, hardware suspend, or the LCD /disable deactivates software suspend, hardware suspend, or the LCD /i initializes registers /0 GPIO1 triggers on falling edge (1->0) /1 GPIO1 triggers on rising edge (0->1) /? displays this usage message Note: 13505PWR will automatically finish execution and return to the prompt. 13505PWR Examples To enable software suspend mode, type the following: 13505PWR /software /enable To disable software suspend mode, type the following: 13505PWR /software /disable To enable hardware suspend mode, type the following: 13505PWR /hardware /enable To disable hardware suspend mode, type the following: 13505PWR /hardware /disable To enable the LCD, type the following: 13505PWR /lcd /enable To disable the LCD, type the following: 13505PWR /lcd /disable Comments * The /i argument is to be used when the registers have not been previously initialized. * When using a PC with the S5U13505P00C evaluation board, the PC must not have more than 12M bytes of system memory. * GPIO1 is used to signal when the software suspend mode, hardware suspend mode, or LCD has been enabled or disabled. * Hardware suspend is changed by reading or writing to a memory address decoded by the PAL on the S5U13505P00C evaluation board. This PAL is currently only used for PC platforms, so the S5U13505P00C evaluation board does not support hardware suspend on embedded platforms. UTILITIES (X23A-B-001-02) EPSON 3-31 7: 13505PWR SOFTWARE SUSPEND POWER SEQUENCING UTILITY Program Messages ERROR: Did not detect S1D13505. The HAL was unable to read the revision code register on the S1D13505. Ensure that the S1D13505 hardware is installed and that the hardware platform has been set up correctly. ERROR: Unknown command line argument. An invalid command line argument was entered. Enter a valid command line argument. ERROR: Already selected SOFTWARE. Command line argument /software was selected more than once. Select /software only once. ERROR: Already selected HARDWARE. Command line argument /hardware was selected more than once. Select /hardware only once. ERROR: Already selected LCD. Command line argument /lcd was selected more than once. Select /lcd only once. ERROR: Already selected ENABLE. Command line argument /enable was selected more than once. Select /enable only once. ERROR: Already selected DISABLE. Command line argument /disable was selected more than once. Select /disable only once. ERROR: Select /software, /hardware or /lcd. Did not select one of the following command line arguments: /software, /hardware or /lcd. Select /software, /hardware or /lcd. ERROR: Select /enable or /disable. Neither command line argument /enable or /disable was selected. Select /enable or /disable. ERROR: Too many devices registered. There are too many display devices attached to the HAL. The HAL currently supports only one device. ERROR: Could not register S1D13505F00A device. A S1D13505 device was not found at the configured addresses. Check the configuration address using the 13505CFG configuration program. 3-32 EPSON UTILITIES (X23A-B-001-02) ll er ro t n A Co 0 0 T F R 5 0 /C 5 CD 3 1 L D AC 1 S D M A ed Em b d d e R C 0 P0 rd 5 a 0 35 s n Boal 1 U u o u S5 A B uati an IS val 's M E ser U CONTENTS Contents Table of Contents 1 INTRODUCTION .........................................................................................................................4-1 1.1 Features ........................................................................................................................................4-1 2 INSTALLATION AND CONFIGURATION ...........................................................................................4-2 3 LCD INTERFACE PIN MAPPING .................................................................................................4-3 4 CPU/BUS INTERFACE CONNECTOR PINOUTS ..............................................................................4-4 5 HOST BUS INTERFACE PIN MAPPING .........................................................................................4-6 6 TECHNICAL DESCRIPTION ..........................................................................................................4-7 6.1 ISA Bus Support ............................................................................................................................4-7 6.2 Non-ISA Bus Support ....................................................................................................................4-7 6.3 DRAM Support ..............................................................................................................................4-7 6.4 Decode Logic ................................................................................................................................4-7 6.5 Clock Input Support .......................................................................................................................4-7 6.6 Monochrome LCD Panel Support .................................................................................................4-8 6.7 Color Passive LCD Panel Support ................................................................................................4-8 6.8 Color TFT/D-TFD LCD Panel Support...........................................................................................4-8 6.9 CRT Support .................................................................................................................................4-8 6.10 Power Save Modes .......................................................................................................................4-8 6.11 Adjustable LCD Panel Negative Power Supply .............................................................................4-8 6.12 Adjustable LCD Panel Positive Power Supply ..............................................................................4-8 6.13 CPU/Bus Interface Header Strips..................................................................................................4-9 6.14 Schematic Notes ...........................................................................................................................4-9 7 PARTS LIST ...........................................................................................................................4-10 8 SCHEMATIC DIAGRAMS ...........................................................................................................4-11 S5U13505P00C REV. 1.0 ISA BUS EVALUATION BOARD USER'S MANUAL (X23A-G-004-04) EPSON 4-i CONTENTS List of Figures Figure 8-1 Figure 8-2 Figure 8-3 Figure 8-4 S5U13505P00C Schematic Diagram (1 of 4) .................................................................... 4-11 S5U13505P00C Schematic Diagram (2 of 4) .................................................................... 4-12 S5U13505P00C Schematic Diagram (3 of 4) .................................................................... 4-13 S5U13505P00C Schematic Diagram (4 of 4) .................................................................... 4-14 Table 2-1 Table 2-2 Table 2-3 Table 3-1 Table 4-1 Table 4-2 Table 5-1 Configuration DIP Switch Settings ....................................................................................... 4-2 Host Bus Selection............................................................................................................... 4-2 Jumper Settings ................................................................................................................... 4-2 LCD Signal Connector (J6) .................................................................................................. 4-3 CPU/BUS Connector (H1) Pinout ........................................................................................ 4-4 CPU/BUS Connector (H2) Pinout ........................................................................................ 4-5 CPU Interface Pin Mapping ................................................................................................. 4-6 List of Tables 4-ii EPSON S5U13505P00C REV. 1.0 ISA BUS EVALUATION BOARD USER'S MANUAL (X23A-G-004-04) 1: INTRODUCTION 1 INTRODUCTION This manual describes the setup and operation of the S5U13505P00C Rev. 1.0 Evaluation Board. Implemented using the S1D13505 Embedded RAMDAC LCD/CRT Controller, the S5U13505P00C is designed for the ISA bus environment. It also provides CPU/Bus interface connectors for non-ISA bus support. For more information regarding the S1D13505, refer to the "S1D13505 Hardware Functional Specification". 1.1 Features * 128-pin QFP15 surface mount package. * SMT technology for all appropriate devices. * 4/8-bit monochrome passive LCD panel support. * 4/8/16-bit color passive LCD panel support. * 9/12/18-bit LCD TFT/D-TFD panel support. * Embedded RAMDAC for CRT support. * 16-bit ISA bus support. * Oscillator support for CLKI (up to 40.0MHz). * 5.0V 1M x 16 EDO-DRAM (2M byte). * Support for software and hardware suspend modes. * On-board adjustable LCD bias power supply (+24..38V or -24..14V). * CPU/Bus interface header strips for non-ISA bus support. S5U13505P00C REV. 1.0 ISA BUS EVALUATION BOARD USER'S MANUAL (X23A-G-004-04) EPSON 4-1 2: INSTALLATION AND CONFIGURATION 2 INSTALLATION AND CONFIGURATION The S1D13505 has 16 configuration inputs MD[15:0] which are read on the rising edge of RESET#. Inputs MD[5:1] are fully configurable on this evaluation board for different host bus selections; one eight-position DIP switch is provided for this purpose. All remaining configuration inputs are hardwired. See the "S1D13505 Hardware Functional Specification" for more information. The following settings are recommended when using the S5U13505P00C with the ISA bus. Switch SW1-1 SW1-2 SW1-3 SW1-4 SW1-5 SW1-6 SW1-7 SW1-8 Signal MD1 MD2 MD3 MD4 MD5 MD13 MD14 MD15 MD3 / SW1-3 open (0) open (0) open (0) open (0) closed (1) closed (1) closed (1) closed (1) Table 2-1 Configuration DIP Switch Settings Closed (1) Open (0) See "Host Bus Selection" table below See "Host Bus Selection" table below Little Endian Wait# signal is active high Reserved MD2 / SW1-2 open (0) open (0) closed (1) closed (1) open (0) open (0) closed (1) closed (1) Big Endian Wait# signal is active low Table 2-2 Host Bus Selection MD1 / SW1-1 Host Bus Interface open (0) SH-3/SH-4 bus interface closed (1) MC68K bus 1 interface (e.g. MC68000) open (0) MC68K bus 2 interface (e.g. MC68030) closed (1) Generic bus interface open (0) Reserved closed (1) MIPS/ISA open (0) PowerPC closed (1) PC Card (PCMCIA) = recommended settings (configured for ISA bus support) JP1 JP2 Description DRDY (pin 76, S1D13505) LCD VDD selection Table 2-3 Jumper Settings 1-2 Pin 76 connected to J6 pin 38 5.0V LCD driver VDD 2-3 Pin 76 connected to J6 pin 35 3.3V LCD driver VDD Note: JP1 is for internal use only, default setting is 1-2. 4-2 EPSON S5U13505P00C REV. 1.0 ISA BUS EVALUATION BOARD USER'S MANUAL (X23A-G-004-04) 3: LCD INTERFACE PIN MAPPING 3 LCD INTERFACE PIN MAPPING Table 3-1 LCD Signal Connector (J6) Color TFT/D-TFD Color Passive Mono Passive S1D13505 Pin Names Connector Pin No. FPDAT0 1 R2 R3 R5 LD0 LD0 LD0 FPDAT1 3 R1 R2 R4 LD1 LD1 LD1 FPDAT2 5 R0 R1 R3 LD2 LD2 LD2 FPDAT3 7 G2 G3 G5 LD3 LD3 LD3 FPDAT4 9 G1 G2 G4 UD0 UD0 UD0 UD0 UD0 FPDAT5 11 G0 G1 G3 UD1 UD1 UD1 UD1 UD1 FPDAT6 13 B2 B3 B5 UD2 UD2 UD2 UD2 UD2 FPDAT7 15 B1 B2 B4 UD3 UD3 UD3 UD3 UD3 FPDAT8 17 B0 B1 B3 LD4 FPDAT9 19 R0 R2 LD5 FPDAT10 21 FPDAT11 23 FPDAT12 25 FPDAT13 27 FPDAT14 29 FPDAT15 31 FPSHIFT 33 DRDY 35 FPLINE 37 FPLINE FPFRAME 39 FPFRAME GND GND 2-26 (Even Pins) N/C 28 VEEH 30 Adjustable -24..-14V negative LCD bias LCDVCC 32 Jumper selectable +3.3V/+5V +12V 34 +12V VDDH 36 Adjustable +15..+38V positive LCD bias DRDY 38 DRDY LCDPWR# 40 LCDPWR# 9-bit 12-bit G0 B0 18-bit 4-bit 8-bit 16-bit R1 LD6 G2 LD7 G1 UD4 G0 UD5 B2 UD6 B1 UD7 4-bit 8-bit FPSHIFT FPSHIFT2 S5U13505P00C REV. 1.0 ISA BUS EVALUATION BOARD USER'S MANUAL (X23A-G-004-04) MOD EPSON FPSHIFT2 MOD 4-3 4: CPU/BUS INTERFACE CONNECTOR PINOUTS 4 CPU/BUS INTERFACE CONNECTOR PINOUTS Table 4-1 CPU/BUS Connector (H1) Pinout Connector Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 4-4 Comments Connected to DB0 of the S1D13505 Connected to DB1 of the S1D13505 Connected to DB2 of the S1D13505 Connected to DB3 of the S1D13505 Ground Ground Connected to DB4 of the S1D13505 Connected to DB5 of the S1D13505 Connected to DB6 of the S1D13505 Connected to DB7 of the S1D13505 Ground Ground Connected to DB8 of the S1D13505 Connected to DB9 of the S1D13505 Connected to DB10 of the S1D13505 Connected to DB11 of the S1D13505 Ground Ground Connected to DB12 of the S1D13505 Connected to DB13 of the S1D13505 Connected to DB14 of the S1D13505 Connected to DB15 of the S1D13505 Connected to RESET# of the S1D13505 Ground Ground Ground +12 volt supply +12 volt supply Connected to WE0# of the S1D13505 Connected to WAIT# of the S1D13505 Connected to CS# of the S1D13505 Connected to MR# of the S1D13505 Connected to WE1# of the S1D13505 Not connected EPSON S5U13505P00C REV. 1.0 ISA BUS EVALUATION BOARD USER'S MANUAL (X23A-G-004-04) 4: CPU/BUS INTERFACE CONNECTOR PINOUTS Table 4-2 CPU/BUS Connector (H2) Pinout Connector Pin No. Comments 1 Connected to AB0 of the S1D13505 2 Connected to AB1 of the S1D13505 3 Connected to AB2 of the S1D13505 4 Connected to AB3 of the S1D13505 5 Connected to AB4 of the S1D13505 6 Connected to AB5 of the S1D13505 7 Connected to AB6 of the S1D13505 8 Connected to AB7 of the S1D13505 9 Ground 10 Ground 11 Connected to AB8 of the S1D13505 12 Connected to AB9 of the S1D13505 13 Connected to AB10 of the S1D13505 14 Connected to AB11 of the S1D13505 15 Connected to AB12 of the S1D13505 16 Connected to AB13 of the S1D13505 17 Ground 18 Ground 19 Connected to AB14 of the S1D13505 20 Connected to AB15 of the S1D13505 21 Connected to AB16 of the S1D13505 22 Connected to AB17 of the S1D13505 23 Connected to AB18 of the S1D13505 24 Connected to AB19 of the S1D13505 25 Ground 26 Ground 27 +5 volt supply 28 +5 volt supply 29 Connected to RD/WR# of the S1D13505 30 Connected to BS# of the S1D13505 31 Connected to BUSCLK of the S1D13505 32 Connected to RD# of the S1D13505 33 Connected to AB20 of the S1D13505 34 Not connected S5U13505P00C REV. 1.0 ISA BUS EVALUATION BOARD USER'S MANUAL (X23A-G-004-04) EPSON 4-5 5: HOST BUS INTERFACE PIN MAPPING 5 HOST BUS INTERFACE PIN MAPPING Table 5-1 CPU Interface Pin Mapping S1D13505 Pin Names SH-3 SH-4 MC68K Bus MC68K Bus 1 2 Generic MIPS/ISA PowerPC PCMCIA AB20 A20 A20 A20 A20 A20 LatchA20 A11 A20 AB[16:13] A[19:13] A[19:13] A[19:13] A[19:13] A[19:13] SA[19:13] A[12:18] A[19:13] AB[12:1] A[12:1] A[12:1] A[12:1] A[12:1] A[12:1] SA[12:1] A[19:30] A[12:1] AB0 A0 A0 LDS# A0 A0 SA0 A31 A0 DB[15:0] D[15:0] D[15:0] D[15:0] D[31:16] D[15:0] SD[15:0] D[0:15] D[15:0] WE1# WE1# WE1# UDS# DS# WE1# SBHE# BI# -CE2 CLKI M/R# External Decode CS# External Decode BUSCLK CKIO CKIO CLK CLK BCLK CLK CLKOUT BS# BS# BS# AS# AS# VDD VDD TS# VDD RD/WR# RD/WR# RD/WR# R/W# R/W# RD1# VDD RD/WR# -CE1 RD# RD# RD# VDD SIZ1 RD0# MEMR# TSIZ0 -OE WE0# WE0# WE0# VDD SIZ0 WE0# MEMW# TSIZ1 -WE WAIT# WAIT# RDY DTACK# DSACK1# WAIT# IOCHRDY TA# -WAIT RESET# RESET# RESET# RESET# RESET# RESET# inverted RESET RESET# inverted RESET 4-6 EPSON S5U13505P00C REV. 1.0 ISA BUS EVALUATION BOARD USER'S MANUAL (X23A-G-004-04) 6: TECHNICAL DESCRIPTION 6 TECHNICAL DESCRIPTION 6.1 ISA Bus Support The S5U13505P00C directly supports the 16-bit ISA bus environment. All the configuration options [MD15:0] are either hard-wired or selectable through the eight-position DIP Switch S1. Refer to Table 2-1, "Configuration DIP Switch Settings," on page 4-2 for detail. Notes: 1. The S5U13505P00C evaluation board supports a 16-bit ISA bus only. 2. The S1D13505 is a memory-mapped device with 2M bytes of linear addressed display buffer and a separate 47 byte register space. On the S5U13505P00C, the S1D13505 2M byte display buffer has been mapped to a start address of C00000h and the registers have been mapped to a start address of E00000h. 3. When using this board in a PC environment, system memory must be limited to 12M bytes, to prevent the system addresses will conflict with the S1D13505 display buffer/register addresses. 6.2 Non-ISA Bus Support This evaluation board is specifically designed to support the standard 16-bit ISA bus. However, the S1D13505 directly supports many other host bus interfaces. Header strips H1 and H2 have been provided and contain all the necessary I/O pins to interface to these buses. See, Section 4, "CPU/Bus Interface Connector Pinouts" , Table 2-1, "Configuration DIP Switch Settings," and Table 2-3, "Jumper Settings," for details. When using the header strips to provide the bus interface observe the following: * All I/O signals on the ISA bus card edge must be isolated from the ISA bus (do not plug the card into a computer). Voltage lines are provided on the header strips. * For the ISA bus, a 22V10 PAL (U4, socketed) is currently used to provide the S1D13505 CS# (pin 4), M/R# (pin 5) and other decode logic signals. This functionality must now be provided externally. Remove the PAL from its socket to eliminate conflicts resulting from two different outputs driving the same input. Refer to Table 2-2, "Host Bus Selection," for connection details. 6.3 DRAM Support The S1D13505 supports 256K x 16 as well as 1M x 16 FPM/EDO-DRAM in symmetrical and asymmetrical formats. The S5U13505P00C board supports a 5.0V 1M x 16 symmetrical EDO-DRAM (42-pin SOJ package). This provides a 2M byte display buffer. 6.4 Decode Logic This board utilizes the MIPS/ISA Interface of the S1D13505 (see the "S1D13505 Hardware Functional Specification"). All required decode logic is provided through a 22V10 PAL (U4, socketed). 6.5 Clock Input Support The S1D13505 supports up to a 40.0MHz input clock frequency. A 40.0MHz oscillator (U2, socketed) is provided on the S5U13505P00C board as the clock (CLKI) source. S5U13505P00C REV. 1.0 ISA BUS EVALUATION BOARD USER'S MANUAL (X23A-G-004-04) EPSON 4-7 6: TECHNICAL DESCRIPTION 6.6 Monochrome LCD Panel Support The S1D13505 supports 4 and 8-bit, dual and single, monochrome passive LCD panels. All necessary signals are provided on the 40-pin ribbon cable header J6. The interface signals on the cable are alternated with grounds to reduce crosstalk and noise. Refer to Table 3-1, "LCD Signal Connector (J6)," for connection information. 6.7 Color Passive LCD Panel Support The S1D13505 directly supports 4, 8 and 16-bit, dual and single, color passive LCD panels. All the necessary signals are provided on the 40-pin ribbon cable header J6. The interface signals on the cable are alternated with grounds to reduce crosstalk and noise. Refer to Table 3-1, "LCD Signal Connector (J6)," for connection information. 6.8 Color TFT/D-TFD LCD Panel Support The S1D13505 supports 9, 12 and 18-bit active matrix color TFT/D-TFD panels. All the necessary signals can also be found on the 40-pin LCD connector J6. The interface signals on the cable are alternated with grounds to reduce crosstalk and noise. When supporting an 18-bit TFT/D-TFD panel, the S1D13505 can display 64K of a possible 256K colors. A maximum 16 of the possible 18 bits of LCD data are available from the S1D13505. Refer to the "S1D13505 Hardware Functional Specification" for details. Refer to Table 3-1, "LCD Signal Connector (J6)," for connection information. 6.9 CRT Support This evaluation board provides CRT support through the S1D13505's embedded RAMDAC. Refer to the "S1D13505 Hardware Functional Specification" for details. 6.10 Power Save Modes The S1D13505 supports one hardware suspend and one software suspend Power Save Mode. 6.11 Adjustable LCD Panel Negative Power Supply Most monochrome passive LCD panels require a negative power supply to provide between -18V and -23V (Iout=45mA). For ease of implementation, such a power supply has been provided as an integral part of this design. The signal VLCD can be adjusted by R29 to supply an output voltage from -14V to -23V and is enabled/disabled by the S1D13505 control signal LCDPWR#. Determine the panel's specific power requirements and set the potentiometer accordingly before connecting the panel. 6.12 Adjustable LCD Panel Positive Power Supply Most passive LCD passive color panels and most single monochrome 640x480 passive LCD panels require a positive power supply to provide between +23V and +40V (Iout=45mA). For ease of implementation, such a power supply has been provided as an integral part of this design. The signal VDDH can be adjusted by R23 to provide an output voltage from +23V to +40V and is enabled/disabled by the S1D13505 control signal LCDPWR#. Determine the panel's specific power requirements and set the potentiometer accordingly before connecting the panel. 4-8 EPSON S5U13505P00C REV. 1.0 ISA BUS EVALUATION BOARD USER'S MANUAL (X23A-G-004-04) 6: TECHNICAL DESCRIPTION 6.13 CPU/Bus Interface Header Strips All of the CPU/Bus interface pins of the S1D13505 are connected to the header strips H1 and H2 for easy interface to a CPU, or bus other than ISA. Refer to Table 4-1, "CPU/BUS Connector (H1) Pinout," and Table 4-2, "CPU/BUS Connector (H2) Pinout," for specific settings. Note: These headers only provide the CPU/Bus interface signals from the S1D13505. When another host bus interface is selected through [MD3:1] configuration, appropriate external decode logic MUST be used to access the S1D13505. See the section "Host Bus Interface Pin Mapping" of the S1D13505 Hardware Functional Specification. 6.14 Schematic Notes The following schematics are for reference only and may not reflect actual implementation. Please request updated information before starting any hardware design. S5U13505P00C REV. 1.0 ISA BUS EVALUATION BOARD USER'S MANUAL (X23A-G-004-04) EPSON 4-9 7: PARTS LIST 7 PARTS LIST Item No. Qty/Board Designation 1 16 C1,C2,C3,C4,C5,C6,C7,C10,C11, C12,C13,C18,C25,C27,C28,C29 2 1 C8 3 2 C9,C30 4 2 C14,C19 5 3 C15,C16,C17 6 1 C20 7 4 C21,C22,C23,C24 9 3 D1,D2,D3 10 2 H1,H2 11 2 JP1,JP2 12 1 J1 13 1 J2 14 1 J3 15 1 J4 16 1 J5 17 1 J6 18 6 L1,L2,L3,L4,L5,L7 19 1 L6 20 2 Q1,Q3 21 1 Q2 22 10 R1,R2,R21,R26,R30,R31,R32,R33, R34,R35 23 2 R3,R4 24 3 R5,R6,R7 25 1 R8 26 1 R9 27 1 R10 28 10 R11,R12,R13,R14,R15,R16,R17, R18,R19,R20 29 1 R22 30 1 R23 31 1 R24 32 1 R25 33 2 R28,R27 34 1 R29 35 1 S1 36 1 U1 37 1 U2 38 1 U3 39 1 U4 40 1 U5 41 1 U6 42 3 U7,U8,U9 43 1 U10 4-10 Part Value 0.1uF Description 0805 ceramic capacitor 0.01uF 1uF 6V 47uF 6V 4.7uF 50V 56uF 35V 4.7uF 16V BAV99 HEADER 17X2 HEADER 3 VGA connector AT CON-A AT CON-B AT CON-C AT CON-D CON40A Ferrite bead Inductor 1H MMBT2222A MMBT2907A 10K 0805 ceramic capacitor Tantalum capacitor size A Tantalum capacitor size D Tantalum capacitor size D Low-ESR electrolytic Tantalum capacitor size B Signal diode 39 Ohms 150 1% 2.8K 1% 1K 1% 140 1% 15K 0805 resistor 0805 resistor 0805 resistor 0805 resistor 0805 resistor 0805 resistor 470K 200K Pot. 14K 4.7K 100K 100K Pot. SW DIP-8 S1D13505F00A 40MHz oscillator MT4C1M16E5DJS-5 PAL22V10-15 RD-0412 EPN001 74AHC244 LT1117CM-3.3 0805 resistor EPSON Philips BDS3/3/8.9-4S2 0805 resistor 0805 resistor 0805 resistor 0805 resistor 50ns self-refresh EDO DRAM Xentek RD-0412 Xentek EPN001 "5V to 3.3V regulator, 800mA" S5U13505P00C REV. 1.0 ISA BUS EVALUATION BOARD USER'S MANUAL (X23A-G-004-04) D C B VCC VCC 1 0.1uF C1 C2 0.1uF FERRITE BEAD L5 C10 0.1uF FERRITE BEAD L4 VCC 4 8 + VCC 40 MHz GND VCC U2 C9 1uF 6V AVCC C3 0.1uF OUT NC 2 VCC 5 1 2 C4 0.1uF AVCC VCC C7 0.1uF C5 0.1uF BUSCLK WAIT# CS# M/R# RESET# RD/WR# WE1# WE0# RD# BS# D[0..15] AVCC VCC C8 0.01uF C6 0.1uF VCC D[0..15] A[0..19] 3 R1 10K 3 R2 10K AVCC VCC VCC A20 A20 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 70 98 106 14 32 50 68 78 87 96 110 99 102 104 12 33 55 72 97 109 69 13 15 4 5 11 10 9 8 7 6 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 3 2 1 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 4 4 S1D13505F00A TESTE N DAC_VSS1 DAC_VSS2 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 DAC_VDD1 DAC_VDD2 DAC_VDD3 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 CLKI BUSCLK WAIT# CS# M/R# RESET# RD/WR# WE1# WE0# RD# BS# DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 AB0 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 U1 AVCC 101 108 107 105 103 100 79 80 81 82 83 84 85 86 88 89 90 91 92 93 94 95 73 74 77 76 71 75 54 51 52 53 35 37 39 41 43 45 47 49 48 46 44 42 40 38 36 34 61 63 65 67 66 64 62 60 58 56 59 57 5 2.8K 1% R8 IREF VRTC HRTC BLUE GREEN RED FPDAT0 FPDAT1 FPDAT2 FPDAT3 FPDAT4 FPDAT5 FPDAT6 FPDAT7 FPDAT8 FPDAT9 FPDAT10 FPDAT11 FPDAT12 FPDAT13 FPDAT14 FPDAT15 FPFRAME FPLINE FPSHIFT DRDY SUSPEND# LCDPWR RAS# LCAS# UCAS# WE# MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9/GPIO3 MA10/GPIO1 MA11/GPIO2 5 R9 1K 1% FPDAT0 FPDAT1 FPDAT2 FPDAT3 FPDAT4 FPDAT5 FPDAT6 FPDAT7 FPDAT8 FPDAT9 FPDAT10 FPDAT11 FPDAT12 FPDAT13 FPDAT14 FPDAT15 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD1 0 MD1 1 MD1 2 MD1 3 MD1 4 MD1 5 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 R10 140 1% Q1 MMBT2222 A L1 MD[0..15] MA[0..9] 6 R5 150 1% FERRITE BEAD 6 R6 150 1% L3 3 D2 BAV9 9 AVCC 39 2 Date: Size B Tuesday, March 24, 1998 7 Document Number S5U13505P00C ISA Bus Evaluation Board Epson Research & Development, Inc. R4 FERRITE BEAD R3 39 3 D1 BAV9 9 R7 150 1% FERRITE BEAD L2 FPDAT[0..15] FPFRAME FPLINE FPSHIFT FPSHIFT2 SUSPEND# LCDPWR# RAS# LCAS# UCAS# WE# MD[0..15] MA[0..9] 7 2 A[0..19] 2 1 EPSON 1 S5U13505P00C REV. 1.0 ISA BUS EVALUATION BOARD USER'S MANUAL (X23A-G-004-04) 1 A 1 3 D3 BAV9 9 Sheet 1 6 1 11 7 2 12 8 3 13 9 4 14 10 5 15 8 of 4 Rev 1.0 PS/2 CONNECTOR J1 8 D C B A 8: SCHEMATIC DIAGRAMS 8 SCHEMATIC DIAGRAMS Figure 8-1 S5U13505P00C Schematic Diagram (1 of 4) 4-11 D C B A LCDPWR# WE# RAS# UCAS# LCAS# 1 VCC PSVCC + C18 0.1uF FERRITE BEAD L7 C14 47uF 6V U5 RD-0412 DC_IN 2 REMOTE 3 PSVCC 2 NC PSVCC 9 GND GND GND GND GND GND GND 4 5 6 7 8 10 11 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 2 29 11 12 32 13 14 30 31 17 18 19 20 23 24 25 26 27 28 16 15 VOUT_ADJ 1 MA[0..9] DC_OUT 12 3 + 1 MA[0..9] C19 47uF 6V R24 14K R23 200K Pot. R22 470 K + C15 4.7uF 50V VSS VSS VSS VCC VCC VCC DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 2 U6 EPN001 MT4C1M16E5D JS-5 /OE NC NC NC /W /RAS /UCAS /LCAS A0 A1 A2 A3 A4 A5 A6 A7 A8R/A8 A9R/A9 A10/NC A11/NC U3 3 100K Pot. R29 22 37 42 1 6 21 2 3 4 5 7 8 9 10 33 34 35 36 38 39 40 41 + 2 L6 VCC 1uH C16 4.7uF 50V MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD1 0 MD1 1 MD1 2 MD1 3 MD1 4 MD1 5 VOUT_ADJ 6 3 GND GND 5 4 2 5 VCC + C11 0.1uF 4 4 C20 56uF 35V DC_OUT MD[0..15] DC_IN DC_IN 11 10 NC NC NC NC 9 8 7 3 1 3 1 DC_OUT 2 EPSON 1 4-12 + MD[0..15] C12 0.1uF 100 K R27 4.7K R25 C17 4.7uF 50V VCC MD[0..15] VDDH MMBT2222A Q3 R26 10K Q2 MMBT2907 A PSVCC 5 R28 100 K 1 2 3 4 5 6 7 8 SW DIP-8 S1 VEEH LA[17..23] MD6 MD1 0 MD1 MD2 MD3 MD4 MD5 MD13 MD14 MD15 RFSH# BALE RD# WE0# RESET PSVCC LA[17..23] 5 16 15 14 13 12 11 10 9 LA19 LA20 LA21 LA22 LA23 6 6 R11 15 K 1 2 3 4 5 6 7 8 9 10 11 13 R13 15 K O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 23 22 21 20 19 18 17 16 15 14 R14 15 K R15 15 K 7 VCC Document Number Friday, March 27, 1998 7 Date: S5U13505P00C ISA Bus Evaluation Board Size B R17 15 K C13 0.1uF RESET# CS# M/R# SUSPEND# A20 R16 15 K Epson Research & Development, Inc. 22V 10 I1/CLK I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 U4 R12 15 K VCC Sheet VCC R18 15 K 10 K R21 2 R19 15 K 8 8 of 4 MCS1 6# R20 15 K Rev 1.0 D C B A 8: SCHEMATIC DIAGRAMS Figure 8-2 S5U13505P00C Schematic Diagram (2 of 4) S5U13505P00C REV. 1.0 ISA BUS EVALUATION BOARD USER'S MANUAL (X23A-G-004-04) S5U13505P00C REV. 1.0 ISA BUS EVALUATION BOARD USER'S MANUAL (X23A-G-004-04) EPSON D C B A 1 RD# WE0# WE1# LA[17..23] A[0..19] WAIT# D[0..15] 1 + VCC VCC C21 4.7uF 16V D[0..15] R34 10K + VCC VCC VCC 2 C22 4.7uF 16V R35 10K R31 10K 2 + C23 4.7uF 16V VCC VCC LA[17..23] A[0..19] 10 K R33 + 3 C24 4.7uF 16V +12 V 3 D7 D6 D5 D4 D3 D2 D1 D0 D8 D9 D10 D11 D12 D13 D14 D15 LA23 LA22 LA21 LA20 LA19 LA18 LA17 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 4 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 AT CON-C /SBHE LA23 LA22 LA21 LA20 LA19 LA18 LA17 /MEMR /MEMW SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 J4 AT CON-A /IOCHCK SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 IOCHRDY AEN SA1 9 SA1 8 SA1 7 SA1 6 SA1 5 SA1 4 SA1 3 SA1 2 SA1 1 SA1 0 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 J2 GND RESET +5V IRQ9 -5V DRQ2 -12V OWS +12V GND /SMEMW /SMEMR /IOW /IOR /DACK3 DRQ3 /DACK1 DRQ1 /REFRESH CLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 /DACK2 T/C BALE +5V OSC GND 5 /MEMCS16 /IOCS16 IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 /DACK0 DRQ0 /DACK5 DRQ5 /DACK6 DRQ6 /DACK7 DRQ7 +5V MASTER GND AT CON-D J5 AT CON-B J3 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VCC VCC +1 2V 6 VCC 6 10 K R32 VCC R30 10K Date: Si ze B Tuesday, March 24, 1998 7 Document Number S5U13505P00C ISA Bus Evaluation Board Epson Research & Development, Inc. 7 Sheet 3 MCS1 6# BALE RFSH# BUSCLK RESET 8 8 of 4 Rev 1.0 D C B A 8: SCHEMATIC DIAGRAMS Figure 8-3 S5U13505P00C Schematic Diagram (3 of 4) 4-13 EPSON D C B D[0..15] VCC 1 C29 0.1uF VIN D[0..15] 3 U10 LT1117CM- 3.3 ADJ 2 D12 D14 D8 D10 D4 D6 D0 D2 2 +1 2V WE0# CS# WE1# RESET# VOUT FPDAT[0..15] + 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 HEADER 17X2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 H1 C30 1uF 6V 3.3V FPDAT[0..15] 3 2 1 2 FPSHIFT FPSHIFT2 FPLINE FPFRAME LCDPWR# 3 FPDAT8 FPDAT9 FPDAT10 FPDAT11 FPDAT12 FPDAT13 FPDAT14 FPDAT15 FPDAT0 FPDAT1 FPDAT2 FPDAT3 FPDAT4 FPDAT5 FPDAT6 FPDAT7 LCDVCC +1 2V WAIT# M/R# D13 D15 D9 D11 D5 D7 D1 D3 VCC JP2 HEADER 3 3 A[0..19] 1 19 2 4 6 8 11 13 15 17 1 19 2 4 6 8 11 13 15 17 1 19 2 4 6 8 11 13 15 17 4 VCC GND 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 VCC GND 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 VCC GND 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 A[0..19] 74AHC244 1G 2G 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 U9 74AHC244 1G 2G 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 U8 74AHC244 1G 2G 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 U7 4 20 10 18 16 14 12 9 7 5 3 20 10 18 16 14 12 9 7 5 3 20 10 18 16 14 12 9 7 5 3 VCC BUSCLK A20 RD/WR# A14 A16 A18 A8 A10 A12 A0 A2 A4 A6 5 C28 0.1uF C27 0.1uF C25 0.1uF 5 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 HEADER 17X2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 H2 FPL FPF FPD0 FPD1 FPD2 FPD3 FPD4 FPD5 FPD6 FPD7 FPD8 FPD9 FPD10 FPD11 FPD12 FPD13 FPD14 FPD15 FPS 6 6 VCC A15 A17 A19 A9 A11 A13 A1 A3 A5 A7 BS# RD# 1 2 3 4-14 1 A 1 JP1 HEADER 3 FPS2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 LCDP# +1 2V Document Number Tuesday, March 24, 1998 7 Size B Date: S5U13505P00C ISA Bus Evaluation Board Epson Research & Development, Inc. CON40A 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 J6 COLOR/MONO LCD CONNECTOR 7 Sheet VDDH VEEH 4 8 8 of 4 Rev 1.0 D C B A 8: SCHEMATIC DIAGRAMS Figure 8-4 S5U13505P00C Schematic Diagram (4 of 4) S5U13505P00C REV. 1.0 ISA BUS EVALUATION BOARD USER'S MANUAL (X23A-G-004-04) ll er ro t n A Co 0 0 T F R 5 0 /C 5 CD 3 1 L 1D AC S D M d e d Em d e b RA i on p Ap l t ica s N e ot CONTENTS Contents Table of Contents 1 INTERFACING THE S1D13505 TO THE PC CARD BUS .............................................................. 5-1 1.1 Introduction.................................................................................................................................5-1 General Description ................................................................................................................5-1 Register/Memory Mapping ......................................................................................................5-2 1.2 S1D13505 Configuration ............................................................................................................5-3 Hardware Configuration ..........................................................................................................5-3 Performance ...........................................................................................................................5-3 2 INTERFACING TO THE NEC VR4102TM /VR4111TM MICROPROCESSOR ..................................... 5-4 2.1 Introduction.................................................................................................................................5-4 General Description ................................................................................................................5-4 2.2 S1D13505 Configuration ............................................................................................................5-5 Hardware Description .............................................................................................................5-5 NEC VR4102TM/VR4111TM Configuration................................................................................5-5 3 INTERFACING TO THE NEC VR4121TM MICROPROCESSOR ....................................................... 5-6 3.1 Introduction.................................................................................................................................5-6 3.2 Configuration ..............................................................................................................................5-7 Hardware Description .............................................................................................................5-7 NEC VR4121TM Configuration.................................................................................................5-8 Memory Mapping and Aliasing................................................................................................5-8 S1D13505 Pin Mapping ..........................................................................................................5-9 S1D13505 Configuration.........................................................................................................5-9 4 INTERFACING TO THE PHILIPS MIPS PR31500/PR31700 PROCESSOR ................................... 5-10 4.1 Introduction................................................................................................................................5-10 4.2 Interfacing to the PR31500/PR31700........................................................................................5-10 4.3 S1D13505 Host Bus Interface ...................................................................................................5-11 PR31500/PR31700 Host Bus Interface Pin Mapping ............................................................5-11 PR31500/PR31700 Host Bus Interface Signals.....................................................................5-11 4.4 Direct Connection to the Philips PR31500/PR31700 ................................................................5-12 Hardware Description ............................................................................................................5-12 S1D13505 Configuration........................................................................................................5-14 Memory Mapping and Aliasing...............................................................................................5-14 4.5 System Design Using the IT8368E PC Card Buffer ..................................................................5-15 Hardware Description ............................................................................................................5-15 IT8368E Configuration ...........................................................................................................5-15 S1D13505 Configuration........................................................................................................5-15 4.6 Software ....................................................................................................................................5-16 5 INTERFACING TO THE TOSHIBA MIPS TX3912 PROCESSOR .................................................... 5-17 5.1 Introduction................................................................................................................................5-17 5.2 Interfacing to the TX3912 ..........................................................................................................5-17 5.3 S1D13505 Host Bus Interface ...................................................................................................5-18 TX3912 Host Bus Interface Pin Mapping ...............................................................................5-18 TX3912 Host Bus Interface Signals .......................................................................................5-19 5.4 Direct Connection to the Toshiba TX3912 ................................................................................5-19 Hardware Description ............................................................................................................5-19 S1D13505 Configuration........................................................................................................5-21 Memory Mapping and Aliasing...............................................................................................5-21 5.5 System Design Using the IT8368E PC Card Buffer ..................................................................5-22 Hardware Description ............................................................................................................5-22 IT8368E Configuration ...........................................................................................................5-22 S1D13505 Configuration........................................................................................................5-22 5.6 Software ....................................................................................................................................5-23 APPLICATION NOTES (X23A-G-005-05) EPSON 5-i CONTENTS 6 INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR ................................................ 5-24 6.1 Introduction ............................................................................................................................... 5-24 General Description ............................................................................................................... 5-24 6.2 Hardware Connections.............................................................................................................. 5-25 6.3 Hardware Configuration ............................................................................................................ 5-27 S1D13505 Configuration ....................................................................................................... 5-27 MPC821 Chip Select Configuration ....................................................................................... 5-28 6.4 Test Software ............................................................................................................................ 5-29 Test Software Source Code................................................................................................... 5-29 7 DAC APPLICATION NOTES ................................................................................................... 5-30 7.1 DAC Application Notes.............................................................................................................. 5-30 Introduction ............................................................................................................................ 5-30 Notes When Operating the S1D13505 Built-in DAC.............................................................. 5-30 DAC Isolated Power Source .................................................................................................. 5-31 Peripheral Circuit of DAC Pins............................................................................................... 5-32 RED/GREEN/BLUE Pins ................................................................................................. 5-33 IREF Pin........................................................................................................................... 5-34 HRTC and VRTC Pins ..................................................................................................... 5-34 Notes When the DAC is Not Used......................................................................................... 5-35 Isolated DAC Power Pin ........................................................................................................ 5-35 Isolated DAC Signal Pins....................................................................................................... 5-36 8 POWER CONSUMPTION ......................................................................................................... 5-37 8.1 S1D13505 Power Consumption................................................................................................ 5-37 Conditions.............................................................................................................................. 5-38 8.2 Summary................................................................................................................................... 5-38 5-ii EPSON APPLICATION NOTES (X23A-G-005-05) CONTENTS List of Figures Figure 1-1 Figure 2-1 Figure 3-1 Figure 4-1 Figure 4-2 Figure 5-1 Figure 5-2 Figure 6-1 Schematic for S1D13505 in PC Card Bus............................................................................5-2 NEC VR4102TM to S1D13505 Configuration Schematic ......................................................5-4 NEC VR4121TM to S1D13505 Configuration Schematic ......................................................5-7 Typical Implementation of Direct Connection.....................................................................5-13 IT8368E Implementation Block Diagram............................................................................5-15 Typical Implementation of Direct Connection.....................................................................5-20 IT8368E Implementation Block Diagram............................................................................5-22 Schematic for MPC821/S1D13505 Interface .....................................................................5-25 Table 1-1 Table 1-2 Table 2-1 Table 3-1 Table 3-2 Table 4-1 Table 4-2 Table 4-3 Table 5-1 Table 5-2 Table 5-3 Table 6-1 Table 6-2 Table 6-3 Table 6-4 Table 7-1 Table 7-2 Table 8-1 Register/Memory Mapping Typical Implementation .............................................................5-2 Summary of Power On/Reset Options .................................................................................5-3 Summary of Power-On/Reset Options .................................................................................5-5 S1D13505 to NEC VR4121TM Pin Mapping..........................................................................5-9 S1D13505 Configuration for NEC VR4121TM ................................................................................................ 5-9 PR31500/PR31700 Host Bus Interface Pin Mapping.........................................................5-11 S1D13505 Configuration for Direct Connection .................................................................5-14 PR31500/PR31700 to PC Card Slots Address Remapping for Direct Connection ............5-14 TX3912 Host Bus Interface Pin Mapping ...........................................................................5-18 S1D13505 Configuration for Direct Connection .................................................................5-21 TX3912 to PC Card Slots Address Remapping for Direct Connection...............................5-21 List of Connections from MPC821ADS to S1D13505 ........................................................5-26 S1D13505 Configuration Settings ......................................................................................5-27 Host Bus Selection .............................................................................................................5-27 Memory Configuration ........................................................................................................5-27 S1D13505 Power Supply Pin Description ..........................................................................5-31 S1D13505 DAC Pin Description.........................................................................................5-32 S1D13505 Total Power Consumption ................................................................................5-38 List of Tables APPLICATION NOTES (X23A-G-005-05) EPSON 5-iii 1: INTERFACING THE S1D13505 TO THE PC CARD BUS 1 INTERFACING THE S1D13505 TO THE PC CARD BUS 1.1 Introduction This application note describes the hardware necessary to provide an interface between the S1D13505 Embedded RAMDAC LCD/CRT Controller and the PC Card (PCMCIA) bus. For further information on the S1D13505 please refer to its "Hardware Functional Specification". For information on the PC Card standard contact the Personal Computer Memory Card International Association (PCMCIA). General Description The S1D13505 was designed to directly support a variety of CPU's, providing an interface to their unique `local bus'. However, in order to provide support for processors not having an appropriate local bus, the S1D13505 also supports both a Generic (ISA-Bus like interface) and a specific PC Card (PCMCIA) interface. The S1D13505 provides a direct `glueless' interface to the 16-bit PC Card bus, with the following exceptions; 1. The RESET# signal on the S1D13505 is active low and therefore must be inverted to support the active high RESET provided by the PC Card interface 2. Although the S1D13505 supports an asynchronous bus interface, a clock source is required on the BCLK input pin. Note: The BCLK frequency is not critical and does not have to be synchronized to the bus signals. APPLICATION NOTES (X23A-G-005-05) EPSON 5-1 1: INTERFACING THE S1D13505 TO THE PC CARD BUS The following diagram demonstrates a typical implementation of the interface. PC Card socket S1D13505 OE# WE# RD# WE0# CE1# CE2# RD/WR# WE1# RESET VDD RESET# BS# CS# A21 M/R# A[20:0] A[25:0] D[15:0] AB[20:0] DB[15:0] 15K WAIT# WAIT# BUSCLK Oscillator CLKI Figure 1-1 Schematic for S1D13505 in PC Card Bus Register/Memory Mapping The PC Card socket provides 64M byte of address space. The S1D13505 is a memory mapped device; 2M byte Display Buffer, and 47 byte Internal Register Set. Table 1-1 shows a typical implementation having the Chip Select pin (CS#) connected to ground (always enabled) and the Memory/Register Select pin (M/R#) connected to Address bit A21. This provides the following decoding: Table 1-1 Register/Memory Mapping Typical Implementation CS# 0 0 M/R# (A21) 0 1 Address Range Function 0 - 1FFFFFh 200000h - 3FFFFFh Internal Register Set decoded 1 Display Buffer decode Note: The internal register set only requires 47 bytes. Therefore, without further resolution on the decode select logic (M/R# connected to A21), the entire register set is aliased for every 64 byte boundary within the specified address range above. Since address bits A25 to A22 are ignored, the S1D13505 registers and display memory are aliased sixteen times. If aliasing is not desirable, the upper addresses must be fully decoded. 5-2 EPSON APPLICATION NOTES (X23A-G-005-05) 1: INTERFACING THE S1D13505 TO THE PC CARD BUS 1.2 S1D13505 Configuration Hardware Configuration The S1D13505 is configured on power-up by latching the power-on state of the DRAM data pins, MD[15:0]. Refer to the "S1D13505 Hardware Functional Specification" for details. The "partial" table below shows those configuration settings important in interfacing to the PC Card bus as shaded. Table 1-2 Summary of Power On/Reset Options S1D13505 Pin Name MD0 MD[3:1] MD4 MD5 MD11 MD12 value on this pin at rising edge of RESET# is used to configure:(1/0) 1 0 8-bit host bus interface 16-bit host bus interface 111 = PC Card bus interface Little Endian Big Endian WAIT# is active high (1 = insert wait state) WAIT# is active low (0 = insert wait state) Alternate host bus interface selected Primary host bus interface selected BUSCLK input divided by two BUSCLK input not divided by two Performance The S1D13505 PC Card Interface is specified to support a BCLK of up to 50MHz, and therefore can provide a high performance display solution. APPLICATION NOTES (X23A-G-005-05) EPSON 5-3 2: INTERFACING TO THE NEC VR4102TM /VR4111TM MICROPROCESSOR 2 INTERFACING TO THE NEC VR4102TM /VR4111TM MICROPROCESSOR 2.1 Introduction This application note describes the hardware and software environment necessary to provide an interface between the S1D13505 Embedded RAMDAC LCD/CRT Controller and the NEC VR4102TM (PD30102) or V R4111TM (PD30111) Microprocessor. For further information on either device refer to their respective technical specifications. General Description The NEC VR4102TM Microprocessor is specifically designed to support an external LCD controller. It provides the necessary internal address decoding and control signals. The S1D13505 can make use of the interface to easier support the NEC VR4102TM. The diagram below shows a typical implementation. NEC VR4102 S1D13505 WR# WE0# SHB# WE1# RD# RD# LCDCS# CS# Pull-up LCDRDY WAIT# A21 M/R# RSTOUT RESET# ADD[25:0] AB[20:0] DAT[15:0] DB[15:0] BUSCLK BUSCLK VDD BS# RD/WR# Figure 2-1 NEC VR4102TM to S1D13505 Configuration Schematic 5-4 EPSON APPLICATION NOTES (X23A-G-005-05) 2: INTERFACING TO THE NEC VR4102TM /VR4111TM MICROPROCESSOR 2.2 S1D13505 Configuration Hardware Description The S1D13505 is configured on power-up by latching the power-on state of the DRAM data pins, MD[15:0]. Refer to the "S1D13505 Hardware Specification" for details. The "partial" table below shows those configuration settings important to the NEC VR4102TM/ VR4111TM CPU interface. Table 2-1 Summary of Power-On/Reset Options Value on this pin at rising edge of RESET# is used to configure: (1/0) S1D13505 Pin Name 1 MD0 8-bit host bus interface MD[3:1] 101 = MIPS/ISA bus interface 0 16-bit host bus interface MD4 Little Endian Big Endian MD5 WAIT# is active high (1 = insert wait state) WAIT# is active low (0 = insert wait state) MD11 Alternate host bus interface selected Primary host bus interface selected NEC VR4102TM/VR4111TM Configuration The NEC VR4102TM/VR4111TM provides the internal address decoding necessary to map to an external LCD controller. Physical address 0x0A000000h to 0x0AFFFFFFh (16M bytes) is reserved for an external LCD controller. The S1D13505 supports up to 2M bytes of display buffer. The NEC VR4102TM/VR4111TM address line A21 is used to select between the S1D13505 display buffer and internal registers. APPLICATION NOTES (X23A-G-005-05) EPSON 5-5 3: INTERFACING TO THE NEC VR4121TM MICROPROCESSOR 3 INTERFACING TO THE NEC VR4121TM MICROPROCESSOR 3.1 Introduction This application note describes the hardware and software environment necessary to provide an interface between the S1D13505 Embedded RAMDAC LCD/CRT Controller and the NEC VR4121TM (PD30121) microprocessor. For further information on the S1D13505, refer to the "S1D13505 Hardware Functional Specification". 5-6 EPSON APPLICATION NOTES (X23A-G-005-05) 3: INTERFACING TO THE NEC VR4121TM MICROPROCESSOR 3.2 Configuration Hardware Description The NEC VR4121TM microprocessor is specifically designed to support an external LCD controller. It provides all the necessary internal address decoding and control signals required by the S1D13505. The diagram below shows a typical implementation utilizing the S1D13505. NEC VR4121 S1D13505 WR# WE0# SHB# WE1# RD# RD# LCDCS# CS# Pull-up LCDRDY WAIT# System RESET RESET# M/R# ADD21 ADD[25:0] AB[20:0] DAT[15:0] DB[15:0] BUSCLK BUSCLK VDD(+3.3V) BS# VDD3 VDD2 +3.3V RD/WR# +2.5V VDD Figure 3-1 NEC VR4121TM to S1D13505 Configuration Schematic APPLICATION NOTES (X23A-G-005-05) EPSON 5-7 3: INTERFACING TO THE NEC VR4121TM MICROPROCESSOR NEC VR4121TM Configuration The NEC VR4121TM register BCUCNTREG1 bit ISAM/LCD must be set to "0". A "0" indicates that the reserved address space is for the LCD controller, and not for the high-speed ISA memory. The register BCUCNTREG2 bit GMODE must be set to "1" to indicate that a non-inverting data bus is used for LCD controller accesses. The LCD interface must be set to operate using a 16-bit data bus. This is accomplished by setting the NEC VR4121TM register BCUCNTREG3 bit LCD32/ISA32 to "0". Note: Setting the register BCUCNTREG3 bit LCD32/ISA32 to "0" affects both the LCD controller and highspeed ISA memory access. The frequency of the BUSCLK output can be programmed from the state of pins TxD/CLKSEL2, RTS#/CLKSEL1 and DTR#/CLKSEL0 during reset, and from the PMU (Power Management Unit) configuration registers of the NEC VR4121TM. The S1D13505 works at any of the frequencies provided by the NEC VR4121TM. Memory Mapping and Aliasing The NEC VR4121TM provides the internal address decoding required by an external LCD controller. The physical address range from 0A000000h to 0AFFFFFFh (16M bytes) is reserved for use by an external LCD controller (e.g. S1D13505). The S1D13505 supports up to 2M bytes of display buffer. The NEC VR4121TM address line ADD21 (connected to M/R#) is used to select between the S1D13505 display buffer (ADD21=1) and the S1D13505 internal registers (ADD21=0). NEC VR4121TM address lines ADD[23:22] are ignored, thus the S1D13505 is aliased four times at 4M byte intervals over the LCD controller address range. Address lines ADD[25:24] are set at 10b and never change while the LCD controller is being addressed. 5-8 EPSON APPLICATION NOTES (X23A-G-005-05) 3: INTERFACING TO THE NEC VR4121TM MICROPROCESSOR S1D13505 Pin Mapping Table 3-1 S1D13505 to NEC VR4121TM Pin Mapping S1D13505 Pin Name NEC VR4121 Pin Name WE1# SHB# RD# RD# WE0# WR# WAIT# LCDRDY CS# LCDCS# DB[15:0] DAT[15:0] AB[20:0] ADD[20:0] M/R# ADD21 RESET# RESET BUSCLK BUSCLK BS#, RD/WR# are connected to VDD (+3.3V) S1D13505 Configuration The S1D13505 latches MD0 through MD15 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. The partial table below shows those configuration settings relevant to the MIPS/ISA host bus interface used by the NEC VR4121TM microprocessor. Table 3-2 S1D13505 Configuration for NEC VR4121TM Value on this pin at rising edge of RESET# is used to configure: (1/0) S1D13505 Pin Name 1 MD0 8-bit host bus interface MD[3:1] 101 = MIPS/ISA host bus interface 0 16-bit host bus interface MD4 Little Endian Big Endian MD5 WAIT# is active high (1 = insert wait state) WAIT# is active low (0 = insert wait state) MD11 Alternate host bus interface selected Primary host bus interface selected = configuration for NEC VR4121TM microprocessor APPLICATION NOTES (X23A-G-005-05) EPSON 5-9 4: INTERFACING TO THE PHILIPS MIPS PR31500/PR31700 PROCESSOR 4 INTERFACING TO THE PHILIPS MIPS PR31500/PR31700 PROCESSOR 4.1 Introduction This application note describes the hardware and software environment necessary to provide an interface between the S1D13505 Embedded RAMDAC LCD/CRT Controller and the Philips MIPS PR31500/PR31700 Processor. 4.2 Interfacing to the PR31500/PR31700 The Philips MIPS PR31500/PR31700 processor supports up to two PC Card (PCMCIA) slots. It is through this host bus interface that the S1D13505 connects to the PR31500/PR31700 processor. The S1D13505 can be successfully interfaced using one of the following configurations: * Direct connection to the PR31500/PR31700. * System design using the ITE IT8368E PC Card/GPIO buffer chip. 5-10 EPSON APPLICATION NOTES (X23A-G-005-05) 4: INTERFACING TO THE PHILIPS MIPS PR31500/PR31700 PROCESSOR 4.3 S1D13505 Host Bus Interface The S1D13505 implements a 16-bit host bus interface specifically for interfacing to the PR31500/ PR31700 microprocessor. The PR31500/PR31700 host bus interface is selected by the S1D13505 on the rising edge of RESET#. After releasing reset, the bus interface signals assume their selected configuration. For details on S1D13505 configuration, see "S1D13505 Configuration" on page 14. Note: At reset, the Host Interface Disable bit in the Miscellaneous Disable Register (REG[1Bh] bit 7) is set to 1. This means that only REG[1Ah] (read-only) and REG[1Bh] are accessible until a write to REG[1Bh] sets bit 7 to 0 making all registers accessible. When debugging a new hardware design, this can sometimes give the appearance that the interface is not working, so it is important to remember to clear this bit before proceeding with debugging. PR31500/PR31700 Host Bus Interface Pin Mapping The following table shows the function of each host bus interface signal. Table 4-1 PR31500/PR31700 Host Bus Interface Pin Mapping S1D13505 Pin Name AB20 AB19 AB18 AB17 AB[16:13] AB[12:0] DB[15:8] DB[7:0] Philips PR31500/PR31700 ALE /CARDREG /CARDIORD /CARDIOWR VDD A[12:0] D[23:16] D[31:24] WE1# M/R# CS# BUSCLK BS# RD/WR# RD# WE0# WAIT# RESET# /CARDxCSH VDD VDD DCLKOUT VDD /CARDxCSL /RD /WE /CARDxWAIT RESET# PR31500/PR31700 Host Bus Interface Signals When the S1D13505 is configured to operate with the PR31500/PR31700, the host interface requires the following signals: * BUSCLK is a clock input required by the S1D13505 host bus interface. It is separate from the input clock (CLKI) and should be driven by the PR31500/PR31700 bus clock output DCLKOUT. * Address input AB20 corresponds to the PR31500/PR31700 signal ALE (address latch enable) whose falling edge indicates that the most significant bits of the address are present on the multiplexed address bus (AB[12:0]). * Address input AB19 should be connected to the PR31500/PR31700 signal /CARDREG. This signal is active when either IO or configuration space of the PR31500/PR31700 PC Card slot is being accessed. * Address input AB18 should be connected to the PR31500/PR31700 signal /CARDIORD. Either AB18 or the RD# input must be asserted for a read operation to take place. APPLICATION NOTES (X23A-G-005-05) EPSON 5-11 4: INTERFACING TO THE PHILIPS MIPS PR31500/PR31700 PROCESSOR * Address input AB17 should be connected to the PR31500/PR31700 signal /CARDIOWR. Either AB17 or the WE0# input must be asserted for a write operation to take place. * Address inputs AB[16:13] and control inputs M/R#, CS# and BS# must be tied to VDD as they are not used in this interface mode. * Address inputs AB[12:0], and the data bus DB[15:0], connect directly to the PR31500/PR31700 address and data bus, respectively. MD4 must be set to select the proper endian mode on reset (see "S1D13505 Configuration" on page 14). Because of the PR31500/PR31700 data bus naming convention and endian mode, S1D13505 DB[15:8] must be connected to PR31500/PR31700 D[23:16], and S1D13505 DB[7:0] must be connected to PR31500/PR31700 D[31:24]. * Control inputs WE1# and RD/WR# should be connected to the PR31500/PR31700 signals / CARDxCSH and /CARDxCSL respectively for byte steering. * Input RD# should be connected to the PR31500/PR31700 signal /RD. Either RD# or the AB18 input (/CARDIORD) must be asserted for a read operation to take place. * Input WE0# should be connected to the PR31500/PR31700 signal /WR. Either WE0# or the AB17 input (/CARDIOWR) must be asserted for a write operation to take place. * WAIT# is a signal output from the S1D13505 that indicates the host CPU must wait until data is ready (read cycle) or accepted (write cycle) on the host bus. Since the host CPU accesses to the S1D13505 may occur asynchronously to the display update, it is possible that contention may occur in accessing the S1D13505 internal registers and/or display buffer. The WAIT# line resolves these contentions by forcing the host to wait until the resource arbitration is complete. 4.4 Direct Connection to the Philips PR31500/PR31700 The S1D13505 was specifically designed to support the Philips MIPS PR31500/PR31700 processor. When configured, the S1D13505 will utilize one of the PC Card slots supported by the processor. Hardware Description In this example implementation, the S1D13505 occupies one PC Card slot and resides in the Attribute and IO address range. The processor provides address bits A[12:0], with A[23:13] being multiplexed and available on the falling edge of ALE. Peripherals requiring more than 8K bytes of address space would require an external latch for these multiplexed bits. However, the S1D13505 has an internal latch specifically designed for this processor making additional logic unnecessary. To further reduce the need for external components, the S1D13505 has an optional BUSCLK divideby-2 feature, allowing the high speed DCLKOUT from the processor to be directly connected to the BUSCLK input of the S1D13505. An optional external oscillator may be used for BUSCLK since the S1D13505 will accept host bus control signals asynchronously with respect to BUSCLK. The following diagram shows a typical implementation of the interface. 5-12 EPSON APPLICATION NOTES (X23A-G-005-05) 4: INTERFACING TO THE PHILIPS MIPS PR31500/PR31700 PROCESSOR VDD (+3.3V) PR31500/PR31700 S1D13505 M/R# CS# BS# AB[16:13] AB[12:0] DB[15:8] DB[7:0] A[12:0] D[23:16] D[31:24] ALE /CARDREG AB20 /CARDIORD AB18 /CARDIOWR AB17 AB19 /CARDxCSH /CARDxCSL /RD /WE /CARDxWAIT VDD pull-up System RESET WE1# RD/WR# RD# WE0# WAIT# RESET# ENDIAN DCLKOUT ...or... Oscillator See text BUSCLK CLKI Note: When connecting the S1D13505 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13505 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states). Figure 4-1 Typical Implementation of Direct Connection The host interface control signals of the S1D13505 are asynchronous with respect to the S1D13505 bus clock. This gives the system designer full flexibility to choose theb appropriate source (or sources) for CLKI and BUSCLK. The choice of whether both clocks should be the same, whether to use DCLKOUT as clock source, and whether an external or internal clock divider is needed, should be based on the desired: * pixel and frame rates. * power budget. * part count. * maximum S1D13505 clock frequencies. The S1D13505 also has internal CLKI dividers providing additional flexibility. APPLICATION NOTES (X23A-G-005-05) EPSON 5-13 4: INTERFACING TO THE PHILIPS MIPS PR31500/PR31700 PROCESSOR S1D13505 Configuration The S1D13505 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the "S1D13505 Hardware Functional Specification". The table below shows those configuration settings relevant to the Philips PR31500/PR31700 host bus interface. Table 4-2 S1D13505 Configuration for Direct Connection S1D13505 Pin Name Value on this pin at rising edge of RESET# is used to configure: 1 (VDD) 0 (VSS) MD0 8-bit host bus interface MD[3:1] 111 = Philips PR31500/PR31700 host bus interface if Alternate host bus interface is selected 16-bit host bus interface MD4 Little Endian Big Endian MD5 WAIT# is active high (1 = insert wait state) WAIT# is active low (0 = insert wait state) MD11 Alternate host bus interface selected Primary host bus interface selected MD12 BUSCLK input divided by two: use with DCLKOUT BUSCLK input not divided: use with external oscillator = configuration for Philips PR31500/PR31700 host bus interface Memory Mapping and Aliasing The PR31500/PR31700 uses a portion of the PC Card Attribute and IO space to access the S1D13505. The S1D13505 responds to both PC Card Attribute and IO bus accesses, thus freeing the programmer from having to set the PR31500/PR31700 Memory Configuration Register 3 bit CARD1IOEN (or CARD2IOEN if slot 2 is used). As a result, the PR31500/PR31700 sees the S1D13505 on its PC Card slot as described in the table below. Table 4-3 PR31500/PR31700 to PC Card Slots Address Remapping for Direct Connection S1D13505 Uses PC Card Slot # 1 2 5-14 Philips Address Size Function 0800 0000h 16M byte Card 1 IO or Attribute 0900 0000h 8M byte S1D13505 registers, aliased 4 times at 2M byte intervals 0980 0000h 8M byte S1D13505 display buffer, aliased 4 times at 2M byte intervals 0A00 0000h 32M byte Card 1 IO or Attribute 6400 0000h 64M byte Card 1 Memory 0C00 0000h 16M byte Card 2 IO or Attribute 0D00 0000h 8M byte S1D13505 registers, aliased 4 times at 2M byte intervals 0D80 0000h 8M byte S1D13505 display buffer, aliased 4 times at 2M byte intervals 0E00 0000h 32M byte Card 2 IO or Attribute 6800 0000h 64M byte Card 2 Memory EPSON APPLICATION NOTES (X23A-G-005-05) 4: INTERFACING TO THE PHILIPS MIPS PR31500/PR31700 PROCESSOR 4.5 System Design Using the IT8368E PC Card Buffer In a system design using one or two ITE IT8368E PC Card and multiple-function IO buffers, the S1D13505 can be interfaced so as to share one of the PC Card slots. Hardware Description The IT8368E can be programmed to allocate the same portion of the PC Card Attribute and IO space to the S1D13505 as in the direct connection implementation described in Section 4.4, "Direct Connection to the Philips PR31500/PR31700" on page 12. Following is a block diagram showing an implementation using the IT8368E PC Card buffer. PR31500/ PR31700 S1D13505 IT8368E PC Card Device IT8368E PC Card Device Figure 4-2 IT8368E Implementation Block Diagram IT8368E Configuration The ITE IT8368E has been specifically designed to support EPSON LCD/CRT controllers. Older EPSON Controllers not supporting a direct interface to the Philips processor can utilize the IT8368E MFIO pins to provide the necessary control signals, however when using the S1D13505 this is not necessary as the Direct Connection described in Section 4.4, "Direct Connection to the Philips PR31500/PR31700" on page 12 can be used. The IT8368E must have both "Fix Attribute/IO" and "VGA" modes enabled. When both these modes are enabled a 16M byte portion of the system PC Card attribute and IO space is allocated to address the S1D13505. When the IT8368E senses that the S1D13505 is being accessed, it does not propagate the PC Card signals to its PC Card device. This makes S1D13505 accesses transparent to any PC Card device connected to the same slot. For mapping details, refer to "Memory Mapping and Aliasing" on page 14. For further information on configuring the IT8368E, refer to the "IT8368E PC Card/GPIO Buffer Chip Specification". S1D13505 Configuration For details on S1D13505 configuration, see "S1D13505 Configuration" on page 14. APPLICATION NOTES (X23A-G-005-05) EPSON 5-15 4: INTERFACING TO THE PHILIPS MIPS PR31500/PR31700 PROCESSOR 4.6 Software Test utilities and Windows(R) CE v2.0 display drivers are available for the S1D13505. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13505CFG, or by directly modifying the source. The Windows(R) CE v2.0 display drivers can be customized by the OEM for different panel types, resolutions and color depths only by modifying the source. 5-16 EPSON APPLICATION NOTES (X23A-G-005-05) 5: INTERFACING TO THE TOSHIBA MIPS TX3912 PROCESSOR 5 INTERFACING TO THE TOSHIBA MIPS TX3912 PROCESSOR 5.1 Introduction This application note describes the hardware and software environment necessary to provide an interface between the S1D13505 Embedded RAMDAC LCD/CRT Controller and the Toshiba MIPS TX3912 Processor. 5.2 Interfacing to the TX3912 The Toshiba MIPS TX3912 processor supports up to two PC Card (PCMCIA) slots. It is through this host bus interface that the S1D13505 connects to the TX3912 processor. The S1D13505 can be successfully interfaced using one of the following configurations: * Direct connection to the TX3912 * System design using the ITE IT8368E PC Card/GPIO buffer chip APPLICATION NOTES (X23A-G-005-05) EPSON 5-17 5: INTERFACING TO THE TOSHIBA MIPS TX3912 PROCESSOR 5.3 S1D13505 Host Bus Interface The S1D13505 implements a 16-bit host bus interface specifically for interfacing to the TX3912 microprocessor. The TX3912 host bus interface is selected by the S1D13505 on the rising edge of RESET#. After releasing reset, the bus interface signals assume their selected configuration. For S1D13505 configuration, refer to "S1D13505 Configuration" on page 14. Note: At reset, the Host Interface Disable bit in the Miscellaneous Disable Register (REG[1Bh] bit 7) is set to 1. This means that only REG[1Ah] (read-only) and REG[1Bh] are accessible until a write to REG[1Bh] sets bit 7 to 0 making all registers accessible. When debugging a new hardware design, this can sometimes give the appearance that the interface is not working, so it is important to remember to clear this bit before proceeding with debugging. TX3912 Host Bus Interface Pin Mapping The following table shows the function of each host bus interface signal. Table 5-1 TX3912 Host Bus Interface Pin Mapping 5-18 S1D13505 Pin Name AB20 AB19 AB18 AB17 AB[16:13] AB[12:0] DB[15:8] DB[7:0] ALE CARDREG* CARDIORD* CARDIOWR* VDD A[12:0] D[23:16] D[31:24] WE1# M/R# CS# BUSCLK BS# RD/WR# RD# WE0# WAIT# RESET# CARDxCSH* VDD VDD DCLKOUT VDD CARDxCSL* RD* WE* CARDxWAIT* PON* Toshiba TX3912 EPSON APPLICATION NOTES (X23A-G-005-05) 5: INTERFACING TO THE TOSHIBA MIPS TX3912 PROCESSOR TX3912 Host Bus Interface Signals When the S1D13505 is configured to operate with the TX3912, the host interface requires the following signals: * BUSCLK is a clock input required by the S1D13505 host bus interface. It is separate from the input clock (CLKI) and should be driven by the TX3912 bus clock output DCLKOUT. * Address input AB20 corresponds to the TX3912 signal ALE (address latch enable) whose falling edge indicates that the most significant bits of the address are present on the multiplexed address bus (AB[12:0]). * Address input AB19 should be connected to the TX3912 signal CARDREG*. This signal is active when either IO or configuration space of the TX3912 PC Card slot is being accessed. * Address input AB18 should be connected to the TX3912 signal CARDIORD*. Either AB18 or the RD# input must be asserted for a read operation to take place. * Address input AB17 should be connected to the TX3912 signal CARDIOWR*. Either AB17 or the WE0# input must be asserted for a write operation to take place. * Address inputs AB[16:13] and control inputs M/R#, CS# and BS# must be tied to VDD as they are not used in this interface mode. * Address inputs AB[12:0], and the data bus DB[15:0], connect directly to the TX3912 address and data bus, respectively. MD4 must be set to select the proper endian mode on reset (see "S1D13505 Configuration" on page 14). Because of the TX3912 data bus naming convention and endian mode, S1D13505 DB[15:8] must be connected to TX3912 D[23:16], and S1D13505 DB[7:0] must be connected to TX3912 D[31:24]. * Control inputs WE1# and RD/WR# should be connected to the TX3912 signals CARDxCSH* and CARDxCSL* respectively for byte steering. * Input RD# should be connected to the TX3912 signal RD*. Either RD# or the AB18 input (CARDIORD*) must be asserted for a read operation to take place. * Input WE0# should be connected to the TX3912 signal WR*. Either WE0# or the AB17 input (CARDIOWR*) must be asserted for a write operation to take place. * WAIT# is a signal output from the S1D13505 that indicates the TX3912 must wait until data is ready (read cycle) or accepted (write cycle) on the host bus. Since the TX3912 accesses to the S1D13505 may occur asynchronously to the display update, it is possible that contention may occur in accessing the S1D13505 internal registers and/or display buffer. The WAIT# line resolves these contentions by forcing the host to wait until the resource arbitration is complete. 5.4 Direct Connection to the Toshiba TX3912 The S1D13505 was specifically designed to support the Toshiba MIPS TX3912 processor. When configured, the S1D13505 will utilize one of the PC Card slots supported by the processor. Hardware Description In this example implementation, the S1D13505 occupies one PC Card slot and resides in the Attribute and IO address range. The processor provides address bits A[12:0], with A[23:13] being multiplexed and available on the falling edge of ALE. Peripherals requiring more than 8K bytes of address space would require an external latch for these multiplexed bits. However, the S1D13505 has an internal latch specifically designed for this processor making additional logic unnecessary. To further reduce the need for external components, the S1D13505 has an optional BUSCLK divideby-2 feature, allowing the high speed DCLKOUT from the processor to be directly connected to the BUSCLK input of the S1D13505. An optional external oscillator may be used for BUSCLK since the S1D13505 will accept host bus control signals asynchronously with respect to BUSCLK. APPLICATION NOTES (X23A-G-005-05) EPSON 5-19 5: INTERFACING TO THE TOSHIBA MIPS TX3912 PROCESSOR The following diagram shows a typical implementation of the interface. VDD (+3.3V) TX3912 S1D13505 M/R# CS# BS# AB[16:13] AB[12:0] DB[15:8] DB[7:0] A[12:0] D[23:16] D[31:24] ALE CARDREG* AB20 CARDIORD* AB18 CARDIOWR* AB17 CARDxCSH* WE1# RD/WR# RD# WE0# WAIT# CARDxCSL* RD* WE* CARDxWAIT* AB19 VDD pull-up System RESET RESET# ENDIAN DCLKOUT ...or... Oscillator See text BUSCLK CLKI Note: When connecting the S1D13505 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13505 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states). Figure 5-1 Typical Implementation of Direct Connection The host interface control signals of the S1D13505 are asynchronous with respect to the S1D13505 bus clock. This gives the system designer full flexibility to choose the appropriate source (or sources) for CLKI and BUSCLK. The choice of whether both clocks should be the same, whether to use DCLKOUT as clock source, and whether an external or internal clock divider is needed, should be based on the desired: * pixel and frame rates. * power budget. * part count. * maximum S1D13505 clock frequencies. The S1D13505 also has internal CLKI dividers providing additional flexibility. 5-20 EPSON APPLICATION NOTES (X23A-G-005-05) 5: INTERFACING TO THE TOSHIBA MIPS TX3912 PROCESSOR S1D13505 Configuration The S1D13505 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the "S1D13505 Hardware Functional Specification". The table below shows those configuration settings relevant to the Toshiba TX3912 host bus interface. Table 5-2 S1D13505 Configuration for Direct Connection Value on this pin at rising edge of RESET# is used to configure: S1D13505 Pin Name 1 (VDD) 0 (VSS) MD0 8-bit host bus interface MD[3:1] 111 = Toshiba TX3912 host bus interface if Alternate host bus interface is selected 16-bit host bus interface MD4 Little Endian Big Endian MD5 WAIT# is active high (1 = insert wait state) WAIT# is active low (0 = insert wait state) MD11 Alternate host bus interface selected Primary host bus interface selected MD12 BUSCLK input divided by two: use with DCLKOUT BUSCLK input not divided: use with external oscillator = configuration for Toshiba TX3912 host bus interface Memory Mapping and Aliasing The TX3912 uses a portion of the PC Card Attribute and IO space to access the S1D13505. The S1D13505 responds to both PC Card Attribute and IO bus accesses, thus freeing the programmer from having to set the TX3912 Memory Configuration Register 3 bit CARD1IOEN (or CARD2IOEN if slot 2 is used). As a result, the TX3912 sees the S1D13505 on its PC Card slot as described in the table below. Table 5-3 TX3912 to PC Card Slots Address Remapping for Direct Connection S1D13505 Uses PC Card Slot # 1 2 Toshiba Address Size Function 0800 0000h 16M byte Card 1 IO or Attribute 0900 0000h 8M byte S1D13505 registers, aliased 4 times at 2M byte intervals 0980 0000h 8M byte S1D13505 display buffer, aliased 4 times at 2M byte intervals 0A00 0000h 32M byte Card 1 IO or Attribute 6400 0000h 64M byte Card 1 Memory 0C00 0000h 16M byte Card 2 IO or Attribute 0D00 0000h 8M byte S1D13505 registers, aliased 4 times at 2M byte intervals 0D80 0000h 8M byte S1D13505 display buffer, aliased 4 times at 2M byte intervals 0E00 0000h 32M byte Card 2 IO or Attribute 6800 0000h 64M byte Card 2 Memory APPLICATION NOTES (X23A-G-005-05) EPSON 5-21 5: INTERFACING TO THE TOSHIBA MIPS TX3912 PROCESSOR 5.5 System Design Using the IT8368E PC Card Buffer In a system design using one or two ITE IT8368E PC Card and multiple-function IO buffers, the S1D13505 can be interfaced so as to share one of the PC Card slots. Hardware Description The IT8368E can be programmed to allocate the same portion of the PC Card Attribute and IO space to the S1D13505 as in the direct connection implementation described in Section 4.4, "Direct Connection to the Philips PR31500/PR31700" on page 12. Following is a block diagram showing an implementation using the IT8368E PC Card buffer. TX3912 S1D13505 IT8368E PC Card Device IT8368E PC Card Device Figure 5-2 IT8368E Implementation Block Diagram IT8368E Configuration The ITE IT8368E has been specifically designed to support EPSON LCD/CRT controllers. Older EPSON Controllers not supporting a direct interface to the Toshiba processor can utilize the IT8368E MFIO pins to provide the necessary control signals, however when using the S1D13505 this is not necessary as the Direct Connection described in Section 4.4, "Direct Connection to the Philips PR31500/PR31700" on page 12 can be used. The IT8368E must have both "Fix Attribute/IO" and "VGA" modes enabled. When both these modes are enabled a 16M byte portion of the system PC Card attribute and IO space is allocated to address the S1D13505. When the IT8368E senses that the S1D13505 is being accessed, it does not propagate the PC Card signals to its PC Card device. This makes S1D13505 accesses transparent to any PC Card device connected to the same slot. For mapping details, refer to "Memory Mapping and Aliasing" on page 14. For further information on configuring the IT8368E, refer to the "IT8368E PC Card/GPIO Buffer Chip Specification". S1D13505 Configuration For S1D13505 configuration, refer to "S1D13505 Configuration" on page 14. 5-22 EPSON APPLICATION NOTES (X23A-G-005-05) 5: INTERFACING TO THE TOSHIBA MIPS TX3912 PROCESSOR 5.6 Software Test utilities and Windows(R) CE v2.0 display drivers are available for the S1D13505. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13505CFG, or by directly modifying the source. The Windows(R) CE v2.0 display drivers can be customized by the OEM for different panel types, resolutions and color depths only by modifying the source. APPLICATION NOTES (X23A-G-005-05) EPSON 5-23 6: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR 6 INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR 6.1 Introduction This application note describes the hardware and software necessary to provide an interface between the S1D13505 Embedded RAMDAC LCD/CRT Controller and the Motorola MPC821 Processor. For further information on the "S1D13505 refer to its Hardware Functional Specification". For information on the Motorola MPC821 Processor contact the Motorola Design Line or your local Motorola sales office. General Description The S1D13505 provides native Power PC bus support making it very simple to interface the two devices. This application note describes, both the environment necessary to connect the S1D13505 to the MPC821 native system bus, and the connection between the S5U13505P00C Evaluation Board and the Motorola MPC821 Application Development System (ADS). Additionally, by implementing a dedicated display buffer, the S1D13505 can reduce system power consumption, improve image quality, and increase system performance as compared to the MPC821's on-chip LCD controller. 5-24 EPSON APPLICATION NOTES (X23A-G-005-05) 6: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR 6.2 Hardware Connections The S1D13505 implements a native MPC8xx bus interface mode and through the use of the MPC821 chip selects, can share the system bus with all other MPC821 peripherals. Figure 6-1 demonstrates a typical implementation of the interface. MPC821 S1D13505 M/R# A10 A[11-31] AB[20-0] D[0-15] DB[15-0] CS4 CS# TS BS# TA WAIT# RD/WR# R/W TSIZ0 RD# TSIZ1 WE0# BI WE1# SYSCLK BUSCLK RESET RESET# Figure 6-1 Schematic for MPC821/S1D13505 Interface Table 6-1 shows the connections between the pins and signals of the MPC821 and the S1D13505. Note: The interface was designed using a Motorola MPC821 Application Development System (ADS). The ADS board has 5 volt logic connected to the data bus, so the interface included two 74F245 octal buffers on the D[0:15] between the ADS and the S1D13505. In a true 3 volt system, no buffering is necessary. APPLICATION NOTES (X23A-G-005-05) EPSON 5-25 6: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR Table 6-1 List of Connections from MPC821ADS to S1D13505 MPC821 Signal Name#1 Vcc A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 SRESET SYSCLK CS4 SRESET SYSCLK CS4 TS TA R/W TSIZ0 TSIZ1 BI Gnd #1: 5-26 MPC821ADS Connector and Pin Name P6-A1, P6-B1 P6-C23 P6-A22 P6-B22 P6-C21 P6-C20 P6-D20 P6-B24 P6-C24 P6-D23 P6-D22 P6-D19 P6-A19 P6-D28 P6-A28 P6-C27 P6-A26 P6-C26 P6-A25 P6-D26 P6-B25 P6-B19 P6-D17 P12-A9 P12-C9 P12-D9 P12-A8 P12-B8 P12-D8 P12-B7 P12-C7 P12-A15 P12-C15 P12-D15 P12-A14 P12-B14 P12-D14 P12-B13 P12-C13 P9-D15 P9-C2 P6-D13 P9-D15 P9-C2 P6-D13 P6-B7 P6-B6 P6-D8 P6-B18 P6-C18 P6-B9 P12-A1, P12-B1, P12-A2, P12-B2, P12-A3, P12-B3, P12-A4, P12-B4, P12-A5, P12-B5, P12-A6, P12-B6, P12-A7 S1D13505 Signal Name Vcc M/R# AB20 AB19 AB18 AB17 AB16 AB15 AB14 AB13 AB12 AB11 AB10 AB9 AB8 AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RESET# BUSCLK CS# RESET# BUSCLK CS# BS# WAIT# RD/WR# RD# WE0# WE1# Vss Note that the bit numbering of the PowerPC bus signals is reversed. e.g. the most significant address bit is A0, the next is A1, A2, etc. EPSON APPLICATION NOTES (X23A-G-005-05) 6: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR 6.3 Hardware Configuration S1D13505 Configuration The S1D13505 uses MD0 through MD15 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. Table 6-2 shows the settings used for the S1D13505 in this interface. Signal MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 Table 6-2 S1D13505 Configuration Settings 1 0 8-bit host bus interface 16-bit host bus interface See "Host Bus Selection" table below See "Host Bus Selection" table below Little Endian Wait# signal is active high See "Memory Configuration" table below Big Endian Wait# signal is active low See "Memory Configuration" table below Configure DACRD#, BLANK#, DACP0, DACWR#, DACRS0, DACRS1, HRTC, VRTC as GPIO4-11 Reserved Active low (On) LCDPWR / GPO polarity Alternate host bus interface Reserved Reserved Reserved Reserved Configure DACRD#, BLANK#, DACP0, DACWR#, DACRS0, DACRS1, HRTC, VRTC as DAC / CRT outputs Configure SUSPEND# pin as Hardware Suspend Enable Active high (On) LCDPWR / GPO polarity Primary host bus interface Reserved Reserved Reserved Reserved = required settings for MPC821 support. MD11 0 0 0 0 0 0 0 0 1 MD3 0 0 0 0 1 1 1 1 x 0 0 1 1 0 0 1 1 x MD7 0 0 1 1 0 1 0 1 0 1 0 1 x Table 6-3 Host Bus Selection Option Host Bus Interface 1 SH-3/SH-4 bus interface 2 MC68K Bus 1 3 MC68K Bus 2 4 Generic 5 Reserved 6 MIPS/ISA 7 Power PC 8 PC Card (PCMCIA) 9+ Reserved 1 2 3 4 Table 6-4 Memory Configuration Option Memory Selection Symmetrical 256K x 16 DRAM Symmetrical 1M x 16 DRAM Asymmetrical 256K x 16 DRAM Asymmetrical 1M x 16 DRAM MD2 MD1 MD6 0 1 0 1 APPLICATION NOTES (X23A-G-005-05) EPSON 5-27 6: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR MPC821 Chip Select Configuration The DRAM on the MPC821 ADS board extends from address 0 through 0x3fffff, so the S1D13505 was addressed starting at 0x400000. A total of 4M bytes of address space is used, where the lower 2M bytes is reserved for the S1D13505 on-chip registers and the upper 2M bytes is used to access the S1D13505 display buffer. Chip select 4 was used to control the S1D13505. The following options were selected in the base address register (BR4): * * * * * * BA (0:16) = 0000 0000 0100 0000 0 AT (0:2) = 0 PS (0:1) = 1:0 PARE = 0 WP = 0 MS (0:1) = 0:0 - set starting address of S1D13505 to 0x40 0000 - ignore address type bits - memory port size is 16 bits - disable parity checking - disable write protect - select General Purpose Chip Select module to control this chip select - set valid bit to enable chip select * V=1 The following options were selected in the option register (OR4): * AM (0:16) = 1111 1111 1100 0000 0 - mask all but upper 10 address bits; S1D13505 consumes 4M byte of address space * ATM (0:2) = 0 - ignore address type bits * CSNT = 0 - normal CS/WE negation * ACS (0:1) = 1:1 - delay CS assertion by clock cycle from address lines * BI = 0 - do not assert Burst Inhibit * SCY (0:3) = 0 - wait state selection; this field is ignored since external transfer acknowledge is used; see SETA below * SETA = 1 - the S1D13505 generates an external transfer acknowledge using the WAIT# line * TRLX = 0 - normal timing * EHTR = 0 - normal timing 5-28 EPSON APPLICATION NOTES (X23A-G-005-05) 6: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR 6.4 Test Software The test software is very simple. It configures chip select 4 (CS4) on the MPC821 to map the S1D13505 to an unused 4M byte block of address space. Next, it loads the appropriate values into the option register for CS4 and writes the value 0 to the S1D13505 register REG[1Bh] to enable the S1D13505 host interface. Lastly, the software runs a tight loop that reads the S1D13505 Revision Code Register REG[00h]. This allows monitoring of the bus timing on a logic analyzer. Test Software Source Code The following source code was entered into the memory of the MPC821ADS using the line-by-line assembler in MPC8BUG, the debugger provided with the ADS board.1 Once the program was executed on the ADS, a logic analyzer was used to verify operation of the interface hardware. It is important to note that when the MPC821 comes out of reset, it's on-chip caches and MMU are disabled. If the data cache is enabled, then the MMU must be set up so that the S1D13505 memory block is tagged as non-cacheable. This ensures the MPC821 does not attempt to cache any data read from, or written to, the S1D13505 or its display refresh buffer. BR4 equ $120 ; CS4 base register OR4 equ $124 ; CS4 option register MemStart equ $40 ; upper word of S1D13505 start address DisableReg equ $1b ; address of S1D13505 Disable Register RevCodeReg equ 0 ; address of Revision Code Register Start mfspr r1,IMMR ; get base address of internal registers andis. r1,r1,$ffff ; clear lower 16 bits to 0 andis. r2,r0,0 ; clear r2 oris r2,r2,MemStart ; write base address ori r2,r2,$0801 ; port size 16 bits; select GPCM; enable stw r2,BR4(r1) ; write value to base register andis. r2,r0,0 ; clear r2 oris r2,r2,$ffc0 ; address mask - use upper 10 bits ori r2,r2,$0608 ; normal CS negation; delay CS clock; ; no burst inhibit (13505 does this) Loop stw r2,OR4(r1) ; write to option register andis. r1,r0,0 ; clear r1 oris r1,r1,MemStart ; point r1 to start of S1D13505 mem space stb r1,DisableReg(r1) ; write 0 to disable register lbz b r0,RevCodeReg(r1) ; read revision code into r1 Loop ; branch forever end 1. MPC8BUG does not support comments or symbolic equates; these have been added for clarity. APPLICATION NOTES (X23A-G-005-05) EPSON 5-29 7: DAC APPLICATION NOTES 7 DAC APPLICATION NOTES 7.1 DAC Application Notes Introduction A video-DAC for CRT display is built-in the S1D13505. It operates with something like analog data, which is very different from other logic parts operated digitally. When operating the DAC normally, some checks are needed. Furthermore, even though the DAC does not need to operate when displaying on a LCD panel and not on a CRT display, some checks are needed when operating the S1D13505. This document describes DAC. Please check these notes for normal S1D13505 operation. Notes When Operating the S1D13505 Built-in DAC Please check these notes when operating the S1D13505 built-in DAC, as described in the following sections: 5-30 EPSON APPLICATION NOTES (X23A-G-005-05) 7: DAC APPLICATION NOTES DAC Isolated Power Source Table 7-1 shows power source required to operate the S1D13505. Table 7-1 S1D13505 Power Supply Pin Description Power Source Pin Name VDD VSS DACVDD DAVVSS Power Source Specification Uses for digital system power source of internal logic and I/O cells. Uses for digital system ground of internal logic and I/O cells. Built -in DAC isolated power source Built-in DAC isolated ground The power source and ground of digital and analog systems are separated in the S1D13505, because if they are used commonly at the S1D13505, a digital power source system noise occurs and the analog characteristics of the DAC can not be maintained. Therefore, the external part of the S1D13505 on the board between digital and analog systems must be separated. To achieve the separation, we recommend that digital and analog systems be physically enclosed by wiring on the board or noise should be stopped by using ferrite beads, a choke coil or a noise filter. VDD S1D13505 Digital VDD Analog VDD Digital Circuit DAC Analog Circuit VSS VSS VSS APPLICATION NOTES (X23A-G-005-05) EPSON 5-31 7: DAC APPLICATION NOTES Ferrite Beads Isolated Analog Power / Ground 106 98 S1D13505 Digital Power / Ground All analog parts should be located in the area of the analog power system, separate from the digital power system. Peripheral Circuit of DAC Pins There are pins for the DAC in the S1D13505, as shown in Table 7-2. Each pin should be used where it is necessary to construct a circuit. Table 7-2 S1D13505 DAC Pin Description Pin Name RED GREEN BLUE IREF HRTC VRTC 5-32 Functions Analog red (red) signal output pin Analog green (green) signal output pin Analog blue (blue) signal output pin Standard current source connecting pin Retrace signal output pin in the horizontal direction Retrace signal output pin in the vertical direction EPSON Necessary Circuit Load resistance Load resistance Load resistance Constant-current source circuit - - APPLICATION NOTES (X23A-G-005-05) 7: DAC APPLICATION NOTES RED/GREEN/BLUE Pins These pins are used for RGB analog signals to output a CRT display. As shown in the following figures, when the combined resistance of 50 is the total load of the external resistance of 150 and the internal resistance of 75 of the CRT display connected to the S1D13505, the peak level of 0.7 V is outputted. Therefore, the load resistance of 150 should be connected to the RGB output pins of DAC in the S1D13505 and the output level is adjusted correctly. S1D13505 CRT RED GREEN DAC BLUE External Load Resistance RL=150x3 CRT Internal Input Resistasnce RI=75x3 Do not insert a part to change the resistance to maintain the analog characteristics of these RGB analog signal outputs. Except for the application device's built-in CRT display, a general type of CRT display may be used as an external device connecting to another device. In this case, the RGB analog pins of the DAC become external pins and the outputs of the DAC interface directly to the external device. Therefore, when composing an application device, the RGB pins may require some countermeasures to prevent EMI and static electricity noise. The RGB output pins should be enclosed to prevent noise in an application device or an external device. However, do not use a part that changes its resistance. When the RGB output pins need to be enclosed, use ferrite beads, a choke coil or a noise filter. The DAC of the S1D13505 can be protected from general levels of static electricity. However, the protection level of the DAC is set in an IC (Integrated Circuit) and it is not set in the device level. Therefore, when the RGB pins of the DAC are external pins, special countermeasures to static electricity are necessary to prevent malfunctions or breakdowns caused by static electricity. One effective countermeasures to insert a diode for the static electricity into each RGB pin. Counterneasure for Noise -ferrite beads and so on S1D13505 RED Connecter to CRT GREEN DAC BLUE Countermeasure for static electricity -diode and so on APPLICATION NOTES (X23A-G-005-05) EPSON 5-33 7: DAC APPLICATION NOTES IREF Pin As the IREF pin is used to adjust the standard operation current of the DAC, the normal constantcurrent should flow from the IREF pin to ground. To output 0.7 V from the RGB pins at the peak level, 4.6mA of normal constant-current is needed. Therefore, the constant-current circuit through which the current flows to ground must be connected to the IREF pin. The following circuit diagram shows an example of a 4.6 mA constant current circuit. The most important thing is the 4.6 mA constant-current circuit. If other parts and their constant values need to be changed, they can be composed at the circuit. DACVDD=3.3V OR DACVDD=2.7V to 5.5V 1.5k 4.6mA 1% 4.6mA 1F 4.6mA IREF 2N2222 140 1% LM334 1k 1% 290 1% 29 1% DACVSS 1N457 DACVSS The current value of the IREF pin is in proportion to the RGB analog output level. Therefore, when the current is more than 4.6 mA, the output level of 0.7 V goes up and the luminance of the CRT display also goes up. This means that the luminance displayed on the CRT can be adjusted by the current at the IREF pin. If the constant-current value is changed from 4.6 mA to adjust the luminance, take care with the input level of the RGB pin of the CRT display. HRTC and VRTC Pins The FRTC and VRTC signals do not need a peripheral circuit. Connect them directly to the input signal of the CRT. However, if the CRT display is used for the external device, the countermeasure may be needed to noise of EMI or static electricity, because both the FRCT and VRTC signals are used directly for the external pins in the same way as the RGB pins. As non-analog characteristics of both pins-FRTC and VRTC are the same as the RGB pins, a resistance should be inserted to the pins according to need for the countermeasure. 5-34 EPSON APPLICATION NOTES (X23A-G-005-05) 7: DAC APPLICATION NOTES Notes When the DAC is Not Used Even when the DAC is not used, the S1D13505 may malfunction if the power system and pins of the DAC are correctly set. When the DAC is not used, note the points described in the following sections. Isolated DAC Power Pin The DACVDD and DACVSS of the analog power system must be connected to the VDD and VSS, respectively, of the digital power system. Never set the power system to be floating even when the DAC is not used, because the internal circuit of the S1D13505 is not stable and it may malfunction. When the DAC is connected to the power of the digital system, the noise-proof facility described in "DAC Isolated Power Source", -for example, the DAC enclosed by wiring on the board or using the noise filter, is not needed. Even if the DAC is connected directly to the digital power system, there is no problem because it is most important that the electric potential in the internal circuit is stable. Usually, the DAC built-into the S1D13505 is set to disable automatically by the internal signal, except when using the DAC when the CRT mode is enabled. Futhermore, the internal circuit is set to be disabled and static. This is why no current flows even if the power system of the DAC is connected to the power of the digital system when the DAC is not used. APPLICATION NOTES (X23A-G-005-05) EPSON 5-35 7: DAC APPLICATION NOTES Isolated DAC Signal Pins When the DAC built-in S1D13505 is not used, the isolated DAC signal pins should be set as shown in the following table. Pin Name RED GREEN BLUE IREF HRTC VRTC How to Set Open, NC Open, NC Open, NC Open, NC Open, NC Open, NC As these analog RGB outputs, HRTC and VRTC signals are used for the isolated output pins, even if they are set open and connected to nothing, no trouble will happen. However, care must be taken when opening the IREF, because the IREF pin is used to conduct the IREF current to ground. When the DAC is not used, if the IREF pin is grounded, more current than the normal capacity flows from the DACVDD through the IREF pin to the DACVSS. In this case, the wiring in the internal circuit may be damaged by over current. Futhermore, when the CRT display is disabled, the IREF circuit of the DAC is disabled by the internal signal. Therefore, if the S1D13505 is normally controlled, no over-capacity current must be generated. However, the IREF pin must be open, because if the setting is mistaken, it is very dangerous. Futhermore, although the IREF pin may be connected to the DACVDD, never connect it to the DACVSS. VDD VDD VDD DACVDD DACVDD DACVDD open IREF DACVSS OK 5-36 IREF DACVSS OK EPSON IREF DACVSS NG APPLICATION NOTES (X23A-G-005-05) 8: POWER CONSUMPTION 8 POWER CONSUMPTION 8.1 S1D13505 Power Consumption S1D13505 power consumption is affected by many system design variables. * Input clock frequency (CLKI): The CLKI frequency determines the LCD frame-rate, CPU performance to memory, and other functions - the higher the input clock frequency, the higher the frame-rate, performance and power consumption. * CPU interface: The S1D13505 current consumption depends on the BUSCLK frequency, data width, number of toggling pins, and other factors - the higher the BUSCLK, the higher the CPU performance and power consumption. * VDD voltage level: The voltage level affects power consumption - the higher the voltage, the higher the consumption. * Display mode: The resolution and color depth affect power consumption - the higher the resolution/color depth, the higher the consumption. * Internal CLK divide: Internal registers allow the input clock to be divided before going to the internal logic blocks - the higher the divide, the lower the power consumption. There are two power save modes in the S1D13505: Software and Hardware SUSPEND. The power consumption of these modes is affected by various system design variables. * DRAM refresh mode (CBR or self-refresh): Self-refresh capable DRAM allows the S1D13505 to disable the internal memory clock thereby saving power. * CPU bus state during SUSPEND: The state of the CPU bus signals during SUSPEND has a substantial effect on power consumption. An inactive bus (e.g. BUSCLK = low, Addr = low etc.) reduces overall system power consumption. * CLKI state during SUSPEND: Disabling the CLKI during SUSPEND has substantial power savings. APPLICATION NOTES (X23A-G-005-05) EPSON 5-37 8: POWER CONSUMPTION Conditions Table 8-1 below gives an example of a specific environment and its effects on power consumption. Table 8-1 S1D13505 Total Power Consumption Test Condition Total Power Consumption Gray Shades / VDD = 3.3V Power Save Mode Colors Active ISA Bus (8MHz) Software Hardware Input Clock = 6MHz Black-and-White 18.6mW 1 LCD Panel = 320x240 4-bit Single Monochrome 4 Gray Shades 20.3mW 4.29mW*1 0.33W*2 16 Gray Shades 22.8mW Input Clock = 6MHz 4 Colors 22.3mW 2 LCD Panel = 320x240 8-bit Single Color 16 Colors 25.3mW 4.32mW*1 0.33W*2 256 Colors 29.0mW Input Clock = 25MHz Black-and-White 58.5mW 3 LCD Panel = 640x480 8-bit Dual Monochrome 5.71mW*1 0.33W*2 16 Gray Shades 71.7mW Input Clock = 25MHz 4 LCD Panel = 640x480 16-bit Dual Color 5 Input Clock = 33.333MHz CRT = 640x480 Color 16 Colors 256 Colors 64K Colors 16 Colors 256 Colors 64K Colors 93.4mW 98.1mW 101.3mW 221.1mW 234.0mW 237.3mW 5.74mW*1 0.33W*2 6.34mW*1 0.33W*2 Notes: *1. Conditions for Software SUSPEND: * CPU interface active (signals toggling) * CLKI active * Self-Refresh DRAM *2. Conditions for Hardware SUSPEND: * CPU interface inactive (high impedance) * CLKI stopped * Self-Refresh DRAM 8.2 Summary The system design variables in Section 8.1, "S1D13505 Power Consumption" and in Table 8-1 show that S1D13505 power consumption depends on the specific implementation. Active Mode power consumption depends on the desired CPU performance and LCD frame-rate, whereas Power Save Mode consumption depends on the CPU Interface and Input Clock state. In a typical design environment, the S1D13505 can be configured to be an extremely power-efficient LCD Controller with high performance and flexibility. 5-38 EPSON APPLICATION NOTES (X23A-G-005-05) ll er ro t n A Co 0 0 T F R 5 0 /C 5 CD 3 1 L D AC 1 S D M A ed Em b d d e R CEers s riv w do ay D n i W ispl D (R) CONTENTS Contents Table of Contents 1 WINDOWS(R) CE DISPLAY DRIVERS.............................................................................................6-1 1.1 Program Requirements .................................................................................................................6-1 1.2 Example Driver Builds ...................................................................................................................6-1 Build for the Hitachi D9000 and ETMA ODO Evaluation Systems ............................................6-1 Build for CEPC (X86) .................................................................................................................6-3 1.3 Example Installation ......................................................................................................................6-5 Installation for Hitachi D9000 and ETMA ODO ..........................................................................6-5 Installation for CEPC Environment ............................................................................................6-5 1.4 Comments .....................................................................................................................................6-6 WINDOWS(R) CE DISPLAY DRIVERS (X23A-E-001-04) EPSON 6-i 1: WINDOWS(R) CE DISPLAY DRIVERS 1 WINDOWS(R) CE DISPLAY DRIVERS The Windows(R) CE display drivers are designed to support the S1D13505 Embedded RAMDAC LCD/CRT Controller running under the Microsoft Windows(R) CE operating system. Available drivers include: 4, 8 and 16 bit-per-pixel landscape modes, and 8 and 16 bit-per-pixel portrait modes. For updated source code, visit Epson R&D on the World Wide Web at www.erd.epson.com, or contact your Seiko Epson or Epson Electronics America sales representative. 1.1 Program Requirements Video Controller : S1D13505 Display Type : LCD or CRT Windows Version : CE Version 2.0 1.2 Example Driver Builds Build for the Hitachi D9000 and ETMA ODO Evaluation Systems To build a Windows(R) CE v2.0 display driver for the Hitachi D9000 or ETMA ODO platform, follow the instructions below. The instructions assume the S5U13505P00C-D9000 evaluation board is plugged into slots 6 and 7 on the D9000/ODO platform, and the SEIKO EPSON common interface FPGA (ODO.RBF) is used to interface with the S1D13505. 1. Install Microsoft Windows NT v4.0. 2. Install Microsoft Visual C/C++ v5.0. 3. Install the Microsoft Windows(R) CE Embedded Toolkit (ETK) by running SETUP.EXE from the ETK compact disc #1. 4. Create a new project by following the procedure documented in "Creating a New Project Directory" from the Windows(R) CE ETK V2.0. Alternately, use the current "DEMO7" project included with the ETK v2.0. Follow the steps below to create a "SH3 DEMO7" shortcut on the Windows NT v4.0 desktop which uses the current "DEMO7" project: a. Right click on the "Start" menu on the taskbar. b. Click on the item "Open All Users" and the "Start Menu" window will come up. c. Click on the icon "Programs". d. Click on the icon "Windows(R) CE Embedded Development Kit". e. Drag the icon "SH3 DEMO1" onto the desktop using the right mouse button. f. Click on "Copy Here". g. Rename the icon "SH3 DEMO1" on the desktop to "SH3 DEMO7" by right clicking on the icon and choosing "rename". h. Right click on the icon "SH3 DEMO7" and click on "Properties" to bring up the "SH3 DEMO7 Properties" window. i. Replace the string "DEMO1" under the entry "Target" with "DEMO7". 5. Create a sub-directory named S1D13505 under \wince\platform\odo\drivers\display. 6. Copy the source code to the S1D13505 subdirectory. 7. Add an entry for the S1D13505 in the file \wince\platform\odo\drivers\display\dirs. WINDOWS(R) CE DISPLAY DRIVERS (X23A-E-001-04) EPSON 6-1 1: WINDOWS(R) CE DISPLAY DRIVERS 8. Modify the file PLATFORM.BIB (using any text editor such as NOTEPAD) to set the default display driver to the file S1D13505.DLL. S1D13505.DLL will be created during the build in step 12. Note that PLATFORM.BIB is located in X:\wince\platform\odo\files (where X: is the drive letter). You may replace the following lines in PLATFORM.BIB: IF ODO_NODISPLAY ! IF ODO_DISPLAY_CITIZEN_8BPP ddi.dll $(_FLATRELEASEDIR)\citizen.dll NK SH ENDIF IF ODO_DISPLAY_CITIZEN_2BPP ddi.dll $(_FLATRELEASEDIR)\citizen.dll NK SH ENDIF IF ODO_DISPLAY_CITIZEN_8BPP ! IF ODO_DISPLAY_CITIZEN_2BPP ! ddi.dll $(_FLATRELEASEDIR)\odo2bpp.dll NK SH $(_FLATRELEASEDIR)\SED1355.dll NK ENDIF ENDIF ENDIF with this line: ddi.dll SH 9. Edit the file MODE.H (located in X:\wince\platform\odo\drivers\display\SED1355) to set the desired screen resolution, color depth (bpp) and panel type. The sample code defaults to a 640x480 color dual passive 16-bit LCD panel. To support one of the other listed panels, change the #define statement. 10. Edit the file PLATFORM.REG to set the same screen resolution and color depth (bpp) as in MODE.H. PLATFORM.REG is located in X:\wince\platform\odo\files. The display driver section of PLATFORM.REG should be: ; Default for EPSON Display Driver ; 640x480 at 8bits/pixel ; Useful Hex Values ; 1024=0x400, 768=0x300 640=0x280 480=0x1E0 320=140 240=0xF0 [HKEY_LOCAL_MACHINE\Drivers\Display\SED1355] "CxScreen"=dword:280 "CyScreen"=dword:1E0 "Bpp"=dword:8 11. Generate the proper building environment by double-clicking on the sample project icon (i.e., SH3 DEMO7). 12. Type BLDDEMO <ENTER> at the DOS prompt of the SH3 DEMO7 window to generate a Windows(R) CE image file (NK.BIN). 6-2 EPSON WINDOWS(R) CE DISPLAY DRIVERS (X23A-E-001-04) 1: WINDOWS(R) CE DISPLAY DRIVERS Build for CEPC (X86) To build a Windows(R) CE v2.0 display driver for the CEPC (X86) platform using a S5U13505P00C evaluation board, follow the instructions below: 1. Install Microsoft Windows NT v4.0. 2. Install Microsoft Visual C/C++ v5.0. 3. Install the Microsoft Windows(R) CE Embedded Toolkit (ETK) by running SETUP.EXE from the ETK compact disc #1. 4. Create a new project by following the procedure documented in "Creating a New Project Directory" from the Windows(R) CE ETK V2.0. Alternately, use the current "DEMO7" project included with the ETK v2.0. Follow the steps below to create a "X86 DEMO7" shortcut on the Windows NT v4.0 desktop which uses the current "DEMO7" project: a. Right click on the "Start" menu on the taskbar. b. Click on the item "Open All Users" and the "Start Menu" window will come up. c. Click on the icon "Programs". d. Click on the icon "Windows(R) CE Embedded Development Kit". e. Drag the icon "X86 DEMO1" onto the desktop using the right mouse button. f. Click on "Copy Here". g. Rename the icon "X86 DEMO1" on the desktop to "X86 DEMO7" by right clicking on the icon and choosing "rename". h. Right click on the icon "X86 DEMO7" and click on "Properties" to bring up the "X86 DEMO7 Properties" window. i. Replace the string "DEMO1" under the entry "Target" with "DEMO7". j. Click on "OK" to finish. 5. Create a sub-directory named S1D13505 under \wince\platform\cepc\drivers\display. 6. Copy the source code to the S1D13505 subdirectory. 7. Add an entry for the S1D13505 in the file \wince\platform\cepc\drivers\display\dirs. 8. Modify the file CONFIG.BIB (using any text editor such as NOTEPAD) to set the system RAM size, the S1D13505 IO port and display buffer address mapping. Note that CONFIG.BIB is located in X:\wince\platform\cepc\files (where X: is the drive letter). Since the S5U13505P00C maps the IO port to 0xE00000 and memory to 0xC00000, the CEPC machine should use the CMOS setup to create a 4M byte hole from address 0xC00000 to 0xFFFFFF. The following lines should be in CONFIG.BIB: NK 80200000 00500000 RAMIMGE RAM 80700000 00500000 RAM Note: S1D13505.H should include the following: #define PhysicalVmemSize 0x00200000L #define PhysicalPortAddr 0x00E00000L #define PhysicalVmemAddr 0x00C00000L 9. Edit the file PLATFORM.BIB (located in X:\wince\platform\cepc\files) to set the default display driver to the file S1D13505.DLL. S1D13505.DLL will be created during the build in step 13. WINDOWS(R) CE DISPLAY DRIVERS (X23A-E-001-04) EPSON 6-3 1: WINDOWS(R) CE DISPLAY DRIVERS You may replace the following lines in PLATFORM.BIB: IF CEPC_DDI_VGA2BPP ddi.dll $(_FLATRELEASEDIR)\ddi_vga2.dll NK SH ENDIF IF CEPC_DDI_VGA8BPP ddi.dll $(_FLATRELEASEDIR)\ddi_vga8.dll NK SH ENDIF IF CEPC_DDI_VGA2BPP ! IF CEPC_DDI_VGA8BPP ! ddi.dll $(_FLATRELEASEDIR)\ddi_s364.dll NK SH ENDIF ENDIF with this line: ddi.dll$(_FLATRELEASEDIR)\SED1355.dllNK SH 10. Edit the file MODE.H (located in X:\wince\platform\odo\drivers\display\SED1355) to set the desired screen resolution, color depth (bpp) and panel type. The sample code defaults to a 640x480 color dual passive 16-bit LCD panel. To support one of the other listed panels, change the #define statement. 11. Edit the file PLATFORM.REG to set the same screen resolution and color depth (bpp) as in MODE.H. PLATFORM.REG is located in X:\wince\platform\cepc\files. The display driver section of PLATFORM.REG should be: ; Default for EPSON Display Driver ; 640x480 at 8bits/pixel ; Useful Hex Values ; 1024=0x400, 768=0x300 640=0x280 480=0x1E0 320=140 240=0xF0 [HKEY_LOCAL_MACHINE\Drivers\Display\SED1355] "CxScreen"=dword:280 "CyScreen"=dword:1E0 "Bpp"=dword:8 12. Generate the proper building environment by double-clicking on the sample project icon (i.e. X86 DEMO7). 13. Type BLDDEMO <ENTER> at the DOS prompt of the X86 DEMO7 window to generate a Windows(R) CE image file (NK.BIN). 6-4 EPSON WINDOWS(R) CE DISPLAY DRIVERS (X23A-E-001-04) 1: WINDOWS(R) CE DISPLAY DRIVERS 1.3 Example Installation Installation for Hitachi D9000 and ETMA ODO Follow the procedures from your Hitachi D9000 (or ETMA ODO) manual and download the following to the D9000 platform: 1. Download SEIKO EPSON's common interface FPGA code (ODO.RBF) to the EEPROM of the D9000 system. 2. Download the Windows(R) CE binary ROM image (NK.BIN) to the FLASH memory of the D9000 system. Installation for CEPC Environment Windows(R) CE v2.0 can be loaded on a PC using a floppy drive or a hard drive. The two methods are described below: 1. To load CEPC from a floppy drive: a. Create a DOS bootable floppy disk. b. Edit CONFIG.SYS on the floppy disk to contain the following line only. device=a:\himem.sys c. Edit AUTOEXEC.BAT on the floppy disk to contain the following lines. mode com1:9600,n,8,1 loadcepc /B:9600 /C:1 /D:2 c:\wince\release\nk.bin d. Copy LOADCEPC.EXE from c:\wince\public\common\oak\bin to the bootable floppy disk. e. Confirm that NK.BIN is located in c:\wince\release. f. Reboot the system from the bootable floppy disk. 2. To load CEPC from a hard drive: a. Copy LOADCEPC.EXE to the root directory of the hard drive. b. Edit CONFIG.SYS on the hard drive to contain the following line only. device=c:\himem.sys c. Edit AUTOEXEC.BAT on the hard drive to contain the following lines. mode com1:9600,n,8,1 loadcepc /B:9600 /C:1 /D:2 c:\wince\release\nk.bin d. Confirm that NK.BIN is located in c:\wince\release. e. Reboot the system from the hard drive. WINDOWS(R) CE DISPLAY DRIVERS (X23A-E-001-04) EPSON 6-5 1: WINDOWS(R) CE DISPLAY DRIVERS 1.4 Comments * Some of the D9000 systems may not be able to provide enough current for your LCD panel to operate properly. If this is the case, an external power supply should be connected to the panel. * The Seiko Epson Common Interface FPGA code assumes the display buffer starts at 0x12200000 and IO starts at 0x12000000. If the display buffer or IO location is modified, the corresponding entries in the file S1D13505.H have to be changed. S1D13505.H is located in X:\wince\platform\odo\drivers\display\S1D13505 (where X: is the drive letter). * The driver is CPU independent but will require another ODO.RBF file to support other CPUs when running on the Hitachi D9000 or ETMA ODO platform. Please check with Seiko Epson for the latest supported CPU ODO files. * As the time of this printing, the drivers have been tested on the SH-3 and x86 CPUs and have only been run with version 2.0 of the ETK. We are constantly updating the drivers so please check our website at www.erd.epson.com, or contact your Seiko Epson or Epson Electronics America sales representative. 6-6 EPSON WINDOWS(R) CE DISPLAY DRIVERS (X23A-E-001-04) International Sales Operations AMERICA ASIA EPSON ELECTRONICS AMERICA, INC. EPSON (CHINA) CO., LTD. - HEADQUARTERS - 28F, Beijing Silver Tower 2# North RD DongSanHuan ChaoYang District, Beijing, CHINA Phone: 64106655 Fax: 64107319 150 River Oaks Parkway San Jose, CA 95134, U.S.A. Phone: +1-408-922-0200 Fax: +1-408-922-0238 SHANGHAI BRANCH 4F, Bldg., 27, No. 69, Gui Jing Road Caohejing, Shanghai, CHINA Phone: 21-6485-5552 Fax: 21-6485-0775 - SALES OFFICES West 1960 E. Grand Avenue EI Segundo, CA 90245, U.S.A. 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EPSON EUROPE ELECTRONICS GmbH No. 1 Temasek Avenue, #36-00 Millenia Tower, SINGAPORE 039192 Phone: +65-337-7911 Fax: +65-334-2716 13F-3, No. 295, Kuang-Fu Road, Sec. 2 HsinChu 300 Phone: 03-573-9900 Fax: 03-573-9169 - HEADQUARTERS Riesstrasse 15 80992 Munich, GERMANY Phone: +49-(0)89-14005-0 Fax: +49-(0)89-14005-110 SALES OFFICE Altstadtstrasse 176 51379 Leverkusen, GERMANY Phone: +49-(0)2171-5045-0 Fax: +49-(0)2171-5045-10 UK BRANCH OFFICE Unit 2.4, Doncastle House, Doncastle Road Bracknell, Berkshire RG12 8PE, ENGLAND Phone: +44-(0)1344-381700 Fax: +44-(0)1344-381701 FRENCH BRANCH OFFICE 1 Avenue de l' Atlantique, LP 915 Les Conquerants Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE Phone: +33-(0)1-64862350 Fax: +33-(0)1-64862355 BARCELONA BRANCH OFFICE Barcelona Design Center Edificio Prima Sant Cugat Avda. Alcalde Barrils num. 64-68 E-08190 Sant Cugat del Valles, SPAIN Phone:+34-93-544-2490 Fax:+34-93-544-2491 SEIKO EPSON CORPORATION KOREA OFFICE 50F, KLI 63 Bldg., 60 Yoido-dong Youngdeungpo-Ku, Seoul, 150-763, KOREA Phone: 02-784-6027 Fax: 02-767-3677 SEIKO EPSON CORPORATION ELECTRONIC DEVICES MARKETING DIVISION Electronic Device Marketing Department IC Marketing & Engineering Group 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5816 Fax: +81-(0)42-587-5624 ED International Marketing Department Europe & U.S.A. 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5812 Fax: +81-(0)42-587-5564 ED International Marketing Department Asia 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5814 Fax: +81-(0)42-587-5110 In pursuit of "Saving" Technology, Epson electronic devices. Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers' dreams. Epson IS energy savings. MF1151-05 S1D13505F00A Technicl Manual Embedded RAMDAC LCD/CRT Controller S1D13505F00A Technical Manual S1D13505F00A Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ This manual was made with recycle papaer, and printed using soy-based inks. First issue February,1999 M Printed April, 2001 in Japan C B