Fairchild Semiconductors Semiconductors Integrated Circuits - Digital CMOS 34000 Series CMOS GENERAL DESCRIPTION Fairchild CMOS logic combines the popular 4000 series functions with the advanced isoplanar C process. The result is a logic family with a superior combination of noise immunity and standardised drive characteristics. At static conditions, these devices dissipate very low power, typically 10nW per gate. The low power combined with the wide (3 to 15V) supply voltage requirement greatly minimises power supply costs. The CMOS family is designed with standardised output drive characteristics which, combined with relative insensitivity to output capacitance loading, simplify system design. FEATURES Low power -~ typically 10nW per gate static. Wide supply voltage range - 3 to 15V. High noise immunity. Buffered outputs standardise output drive and reduce variation of propagation delay with output capacitance. Wide operating temperature range. Commercial 40C to +85C. High DC fan out - greater than 50. ISOPLANAR C The Fairchild CMOS logic family uses Isoplanar C for high performance. This technology combines local oxidation isotation techniques with silicon gate technology to achieve an approximate 35% savings in area as shown in Figure 1a. Operating speeds are increased due to the self-alignment of the silicon gate and reduced sidewall capacitance. Conventional CMOS circuits are fabricated on an N-type substrate as shown in Figure 16. The P-type substrate required for complementary N-channel MOS is obtained by diffusing a lightly doped P-region into the N-type substrate. Conventional CMOS fabrication requires more chip area and has slower circuit speeds than Isoplanar C CMOS. This is a result of the N+ or p-+ guard ring which surrounds the P- or N-channels respectively in CMOS. Silicon gate CMOS (Figure 1c') has a negligible reduction in area, though transient. performance is improved. Fig 1a. Isoplanar CMOS structure reduces area 35%. Fig 1b. Conventional metal gate CMOS structure Fig 1c. Conventional silicon gate CMOS structure reduces area 8%. sss ee PLEASE QUOTE STOCK NO. AND MANUFACTURER'S CODE WHEN ORDERING 799Fairchild Semiconductors Semiconductors Integrated Circuits ~ Digital CMOS 34000 Series CMOS Fully Buffered Configuration Description Fairchild CMOS logic is designed with the system user in mind. Output buffering is used on all devices to achieve high performance, standardised output drive, highest noise immunity and decreased AC sensitivity to output loading. Figure 2 illustrates a conventional unbuffered 2-Input NOR gate. Either N-channel transistor connected to Vss (ground) conducts when either input is HIGH, causing the output to go LOW through the ON resistance of the device. If both inputs are HIGH, both N-channel devices are on; effectively halving the ON resistance, thereby making the output impedance (and hence fall time) a function of input variables. Similarly the P-channel devices are switched on by LOW signals; i.e. when both inputs are LOW, conduction from Vopo to the output will occur. Since the P-channel devices are in series, their ON resistance must be decreased (larger chip area) to hold output HIGH impedance within specification. As the number of gate inputs increases, even targer P-channel devices are required, and the output impedance to Vs; becomes even more pattern sensitive. A conventional unbuffered CMOS 2-Input NAND gate interchanges the paralie! and seriai transistor gating to achieve the dual logic function (Figure 3). The changes in output resistance then move to the P-channel transistors connected to Vop, while the N-channel devices must be increased in size due to their serial connection. Fairchild CMOS uses small geometry logic tran- sistors to generate the required function which drive standard low impedance output buffers (Figures 4 and 5). This technique reduces chip size, since only two large output transistors are required and rise and fall times are independent of input pattern. Buffered outputs also increase system speeds and make propagation delay less sensitive to output capacitance. Figure 6 illustrates typical propagation delay vs. output capacitance for conventional and buffered CMOS gates. Another advantage of the Fairchild approach is improved noise immunity. Because of the increased voltage gain, nearly ideal transfer characteristics are realized as shown in Figure 7. The high gain (greater than 10,000) also provides significant pulse shaping; the waveforms of Figures 8 and 9 compare the output waveforms of conventional and buffered CMOS gates. For input transition times of 100ns or less, the outputs of both gate types are similar. FIG 2 CONVENTIONAL NON-BUFFERED 2INPUT NOR GATE FIG 4 FAIRCHILD 34001 FULLY BUFFERED NOR GATE AE Te FIG 3 CONVENTIONAL NON~ BUFFERED 2 INPUT NAND GATE Dm a FIG 5 FAIRCHILD FULLY BUFFERED NAND GATE MANUFACTURER'S CURRENT LIST PRICES ARE ALWAYS CHARGEDFairchild Semiconductors Semiconductors Integrated Circuits Digital. CMOS 34000 Series CMOS Description (continued) When the input transitions are stretched to one microsecond, the conventional gate exhibits increased transition times while the buffered gate has unchanged output transition times. This feature eliminates progressive deterioration of pulse characteristics in a system. The combination of Isoplanar C and buffered outputs results in new standards of CMOS logic performance. Recommended Operating Conditions Fairchild CMOS will operate over Vop power supply ranges of 3 to 15V, as referenced to Vss (usually ground). Parametric limits are guaranteed for Voo equat to 5 and 10V where low power dissipation is required, the lowest power supply voltage, consistent with required speed, should be used. For larger noise immunity, higher power supply voltages should be specified. Because of its wide operating range, power supply regulation and filtering are fess critical than with other types of logic. The lower limit of supply regulation is 3V, or as determined by required system speed and/or noise immunity or interface to other fogic. The upper limit is 15V or as - determined by power dissipation constraints or interface to other logic. Unused inputs must be connected to Vpp, Vss or another input. Care should be used in handling CMOS devices; large static charges may damage the device. Operating temperature range is 40C to +85C for commercial. ABSOLUTE MAXIMUM RATINGS Supply voltage Voo 0.5 to +15V Voltage on any input 0.5 to Von +0.5V Input current +10mMA Maximum power dissipation 400m W Storage temperature 65C to 150C Lead temperature 300C (soldering, 10 seconds) Fig. 6 COMPARISON OF PROPAGATION DELAY V8 LOAD CAPACITANCE FOR CONVENTIONAL AND FULLY BUFFERED NAND GATES 270 5 2 g < i t ao] 0 100 180 200 C, - LOAD CAPACITANCE - pF Fig B POSITIVE-GOING INPUT RAMPS OF 0.1 us AND 1.0 us APPLIED TO CONVENTIONAL AND FULLY BUFFERED GATES 2 & LOGIC LEVELS - VOLTS 2. TOME = 9 Fig. 7 TYPICAL VOLTAGE TRANSFER CHARACTERISTICS FOR CONVENTIONAL AND FULLY BUFFERED DEVICES tT?" Your ~ OUTPUT VOLTAGE ~ VOLTS @ so 10 . Vy ~ INPUT VOLTAGE VOLTS mo Fig. 9 NEGATIVE-GOING INPUT RAMPS OF 0.1 us AND 1.0 us APPLIED TO CONVENTIONAL AND FULLY BUFFERED GATES Logic LEVELS - VOLTS. Tome | a ee ee EEEEoEIyE>EEyeyeEE PLEASE QUOTE STOCK NO: AND MANUFACTURER'S CODE WHEN ORDERING 801Fairchild Semiconductors Semiconductors Integrated Circuits - Digital CMOS: 34000 Series CMOSPlastic Dual In Line Package REFERENCE TABLE *Check with sales desk for availability Connection Stock Diagram Code . Function No. No. F34001PC Quad 2-input NOR gate 35969G E1 F34002PC Dual 4-input NOR gate 35970X E2 F340t1PC Quad 2-input NAND gate 35971H 6 F34012PC Dual 4-input NAND gate 35972F E7 F34013PC Dual D flip flop 359730 8 *F34014PC 8-stage parailel-to-serial shift register 35974R E9 F34015PC Dual 4-stage shift register 35975X E27 *F34016PC/34066PC Quad bilateral switch 35976R E10 *F34017PC Decade sequencer 35977G E11 F34019PC Quad 2-input multiplexer 35978E E12 F34020PC 14-stage timer 35979C E17 *F34021PC 8-stage serial-to-parallel shift register 35980F E13 F34023PC Triple 3-input NAND gate 35981D E14 *F34024PC T-stage binary counter 35982B E15 F34025PC Triple 3-input NOR gate 35983X E19 F34027PC Dual JK flip flop 35984R E20 F34028PC 1-of-10 decoder 35985G E30 *F34029PC 4-bit binary/BCD, up/down counter 35986E 31 F34030PC/34070PC Quad exclusive OR 35987C E21 *F34035PC 4-bit parallel injout shift register 35988A E16 F34040PC 12-stage timer 35989X E37 Fa4042PC Quad D latch 359908 E39 F34049PC Hex inverting buffer 35991X 22 Fa4050PC Hex non-inverting buffer 35992R E23 F34081PC - 8-Input analog multiplexer 359936 E43 F34052PC Differential 4-input multiplexer 35994E E44 *F34068PC 8-input NAND gate 35995C - F34069PC Hex inverter 35096A - F34071PC Quad 2-input AND gate 35997X _ F34077PC/34811PC Quad exclusive NOR gate 35998H - F34081PC Quad 2-input OR gate 35900F _ F3a40s5sPC Duai 2-wide, 2-input AO1 36000F _ F34086PC Expandable 4-wide, 2-input A01 36001D _ *F34099PC 8-bit addressable latch 36002B - *F34104PC TTL-to-high-level CMOS converter 36003X _- F34512PC 8-input multiplexer 36004R _ *F34518PC Dual 4-bit decade counter 36005G - *F34527PC BCD rate multiplier 36006E -_ *F3455SPC Dual 1-of-4 decoder 36007C _ *F340085SPC 4-bit magnitude comparator 36008A _ *F340089PC 16 x4 bit RAM 36000KK - F340097PC Hex 3-state non-inverting buffer 360108 _ F340088P.C Hex 3-state inverting buffer 36011X - F340160PC 4-bit decade asynchronous reset counter 36012R _ F340161PC 4-bit binary asynchronous reset counter 36013G _ F340162PC 4-bit decade synchronous reset counter 36014E F340163PC 4-bit binary synchronous reset counter 36015C _ *F340174PC Hex-D flip flop 36016A - *F340175PC Quad D flip flop 36017X - *F340192PC 4-bit up/down, synchronous decade counter 36018Hi *F340193PC 4-bit up/down, synchronous binary counter 36019F _ F340194PC 4-bit right/left shift register 36020R _ F340195PC 4-bit shift register 360216 _- MANUFACTURER'S CURRENT LIST PRICES ARE ALWAYS CHARGED