PE4302-52 - Peregrine Semiconductor Corp.

Page 1 of 11

The PE4302 is a high linearity, 6-bit RF Digital Step Attenuator

(DSA) covering a 31.5 dB attenuation range in 0.5 dB steps.

This 50-ohm RF DSA provides both parallel and serial CMOS

control interface operates on a single 3-volt supply and

maintains high attenuation accuracy over frequency and

temperature. It also has a unique control interface that allows

the user to select an initial attenuation state at power-up. The

PE4302 exhibits very low insertion loss and low power

consumption. This functionality is delivered in a 4x4 mm QFN

footprint.

The PE4302 is manufactured on Peregrine’s UltraCMOS™

process, a patented variation of silicon-on-insulator (SOI)

technology on a sapphire substrate, offering the performance

of GaAs with the economy and integration of conventional

CMOS.

Product Specification

50 Ω RF Digital Attenuator

6-bit, 31.5 dB, DC – 4.0 GHz

Product Description

Figure 1. Functional Schematic Diagram

PE4302

Features

• Attenuation: 0.5 dB steps to 31.5 dB

• Flexible parallel and serial programming

interfaces

• Unique power-up state selection

• Positive CMOS control logic

• High attenuation accuracy and linearity

over temperature and frequency

• Very low power consumption

• Single-supply operation

• 50  impedance

• Packaged in a 20 lead 4x4mm QFN

Control Logic Interface

Parallel Control

Power-Up Control

Serial Control

RF Input RF Output

Switched Attenuator Array

Table 1. Electrical Specifications @ +25°C, VDD = 3.0 V

Parameter Test Conditions Frequency Minimum Typical Maximum Units

Operation Frequency DC 4000 MHz

Insertion Loss2 DC - 2.2 GHz - 1.5 1.75 dB

Attenuation Accuracy Any Bit or Bit

Combination DC  1.0 GHz

1.0 < 2.2 GHz - -

±(0.10 + 3% of atten setting)

±(0.15 + 5% of atten setting) dB

1 dB Compression3 1 MHz - 2.2 GHz 30 34 - dBm

Input IP31,2 Two-tone inputs

+18 dBm 1 MHz - 2.2 GHz - 52 - dBm

Return Loss DC - 2.2 GHz 15 20 - dB

Switching Speed 50% control to 0.5 dB

of final value - - 1 µs

Notes: 1. Device Linearity will begin to degrade below 1 Mhz

2. See Max input rating in Table 3 & Figures on Pages 2 to 4 for data across frequency.

3. Note Absolute Maximum in Table 3.

Figure 2. Package Type

4x4 mm 20-Lead QFN

Product Specification

PE4302

Page 2 of 11

-50

-40

-30

-20

-10

0 500 1000 1500 2000 2500 3000 3500 4000

S22 (dB)

RF Frequency (MHz)

31.5dB

-50

-40

-30

-20

-10

0 500 1000 1500 2000 2500 3000 3500 4000

S11 (dB)

RF Frequency (MHz)

16dB

31.5dB

0 500 1000 1500 2000 2500 3000 3500 4000

Attenuation (dB)

Normalized to Insertion Loss

RF Frequency (MHz)

31.5dB

4dB

8dB

16dB

0.5dB

1dB

2dB

-6

-5

-4

-3

-2

-1

0 500 1000 1500 2000 2500 3000 3500 4000

Insertion Loss (dB)

RF Frequency (MHz)

25C

-40C

85C

Typical Performance Data @ 25°C, VDD = 3.0 V

Figure 4. Attenuation at Major steps

Figure 6. Output Return Loss at Major

Attenuation Steps

Figure 5. Input Return Loss at Major

Attenuation Steps

Figure 3. Insertion Loss

Product Specification

PE4302

Page 3 of 11

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0 5 10 15 20 25 30 35 40

Attenuation Error (dB)

Attenuation Setting (dB)

1000Mhz, -40C

1000Mhz, 85C

1000Mhz, 25C

1500Mhz, -40C

1490Mhz, 25C

1490Mhz, 85C

-1.5

-1

-0.5

0.5

0 5 10 15 20 25 30 35 40

Attenuation Error (dB)

Attenuation Setting (dB)

10Mhz

500Mhz

1000Mhz

1500Mhz

2000Mhz

2200Mhz

-10

-8

-6

-4

-2

0 500 1000 1500 2000 2500 3000 3500 4000

Attenuation Error (dB)

RF Frequency (MHz)

31.5 (dB)

-0.6

-0.4

-0.2

0.2

0.4

0.6

0 5 10 15 20 25 30 35 40

Attenuation Error (dB)

Attenuation Setting (dB)

10Mhz, -40C

500Mhz, -40C

10Mhz, 25C

500Mhz, 25C

10Mhz, 85C

500Mhz, 85C

Figure 8. Attenuation Error Vs. Attenuation

Setting

Figure 10. Attenuation Error Vs. Attenuation

Setting

Figure 9. Attenuation Error Vs. Attenuation

Setting

Figure 7. Attenuation Error Vs. Frequency

Typical Performance Data @ 25°C, VDD = 3.0 V

Note: Positive attenuation error indicates higher attenuation than target value

Product Specification

PE4302

Page 4 of 11

0 500 1000 1500 2000 2500 3000

0dB

0.5dB

1dB

2dB

4dB

8dB

16dB

31.5dB

RF Frequency (MHz)

1dB Compression (dBm)

0 500 1000 1500 2000 2500 3000

0dB

.5dB

1dB

2dB

4dB

8dB

16dB

31.5dB

Input IP3 (dBm)

RF Frequency (MHz)

-1.5

-1

-0.5

0.5

0 5 10 15 20 25 30 35 40

Attenuation Error (dB)

Attenuation Setting (dB)

2000Mhz, -40C

2200Mhz, -40C

2200Mhz, 25C

2000Mhz, 25C

2000Mhz, 85C

2200Mhz, 85C

Figure 12. Input IP3 Vs. Frequency

Figure 13. Input 1 dB Compression

Figure 11. Attenuation Error Vs. Frequency

Typical Performance Data @ 25°C, VDD = 3.0 V

Note: Positive attenuation error indicates higher attenuation than target value

Product Specification

PE4302

Page 5 of 11

Table 2. Pin Descriptions

Electrostatic Discharge (ESD) Precau tions

When handling this UltraCMOS™ de vice, observe the

same precautions that you would use with other ESD-

sensitive devices. Although this device contains

circuitry to protect it from damage due to ESD,

precautions should be taken to avoid exceeding the

rate specified in Table 3.

Exposed Solder Pad Connection

The exposed solder pad on the bottom of the package

must be grounded for proper device operation.

Note 1: Both RF ports must be held at 0 VDC or DC blocked with an

external series capacitor.

2: Latch Enable (LE) has an internal 100 k resistor to VDD.

3: Connect pin 12 to GND to enable internal negative voltage

generator. Connect pin 12 to VSS (-VDD) to bypass and

disable internal negative voltage generator.

4. Place a 10 k resistor in series, as close to pin as possible to

avoid frequency resonance.

Figure 14. Pin Configuration (Top View)

PUP1

PUP2

GND

C16

RF1

Data

Clock

LE GND

Vss/GND

P/S

RF2

GND

C0.5

20-lead QFN

4x4mm

Exposed Solder Pad

No. Pin

Name Description

1 C16 Attenuation control bit, 16dB (Note 4).

2 RF1 RF port (Note 1).

3 Data Serial interface data input (Note 4).

4 Clock Serial interface clock input.

5 LE Latch Enable input (Note 2).

6 VDD Power supply pin.

7 PUP1 Power-up selection bit, MSB.

8 PUP2 Power-up selection bit, LSB.

9 VDD Power supply pin.

10 GND Ground connection.

11 GND Ground connection.

12 Vss/GND Negative supply voltage or GND

connection(Note 3)

13 P/S Parallel/Serial mode select.

14 RF2 RF port (Note 1).

15 C8 Attenuation control bit, 8 dB.

16 C4 Attenuation control bit, 4 dB.

17 C2 Attenuation control bit, 2 dB.

18 GND Ground connection.

19 C1 Attenuation control bit, 1 dB.

20 C0.5 Attenuation control bit, 0.5 dB.

Paddle GND Ground for proper operation

Latch-Up Avoidance

Unlike conventional CMOS devices, UltraCMOS™ de-

vices are immune to latch-up.

Switching Frequency

The PE4302 has a maximum 25 kHz switching rate.

Resistor on Pin 1 & 3

A 10 k resistor on the inputs to Pin 1 & 3 (see Figure

16) will eliminate package resonance between the RF

input pin and the two digital inputs. Specified

attenuation error versus frequency performance is

dependent upon this condition.

Table 3. Absolute Maximum Ratings

Table 4. Operating Ranges

Symbol Parameter/Conditions Min Max Units

VDD Power supply voltage -0.3 4.0 V

VI Voltage on any DC input -0.3 VDD+

0.3 V

TST Storage temperature range -65 150 °C

PIN Input power (50) +30 dBm

VESD ESD voltage (Human Body

Model) 500 V

Parameter Min Typ Max Units

VDD Power Supply

Voltage 2.7 3.0 3.3 V

IDD Power Supply

Current 100 µA

Digital Input High 0.7xVDD V

Digital Input Low 0.3xVDD V

Digital Input Leakage 1 µA

Input Power +24 dBm

Temperature range -40 85 °C

Exceeding absolut e maximum ratings may cause per-

manent damage. Operation should be restricted to th e

limits in the Operating Ranges table. Operation be-

tween operating range maximum and ab solute ma xi-

mum for extended periods may reduce reliability.

Product Specification

PE4302

Page 6 of 11

Programming Options

Parallel/Serial Selection

Either a parallel or serial interface can be used to

control the PE4302. The P/S bit provides this

selection, with P/S=LOW selecting the parallel

interface and P/S=HIGH selecting the serial

interface.

Parallel Mode Interface

The parallel interface consists of five CMOS-

compatible control lines that select the desired

attenuation state, as shown in Table 5.

The parallel interface timing requirements are

defined by Figure 18 (Parallel Interface Timing

Diagram), Table 9 (Parallel Interface AC

Characteristics), and switching speed (Table 1).

For latched parallel programming the Latch Enable

(LE) should be held LOW while changing attenuation

state control values, then pulse LE HIGH to LOW

(per Figure 18) to latch new attenuation state into

device.

For direct parallel programming, the Latch Enable

(LE) line should be pulled HIGH. Changing

attenuation state control values will change device

state to new attenuation. Direct Mode is ideal for

manual control of the device (using hardwire,

switches, or jumpers).

P/S C16 C8 C4 C2 C1 C0.5

Attenuation

State

0 0 0 0 0 0 0 Reference Loss

0 0 0 0 0 0 1 0.5 dB

0 0 0 0 0 1 0 1 dB

0 0 0 0 1 0 0 2 dB

0 0 0 1 0 0 0 4 dB

0 0 1 0 0 0 0 8 dB

0 1 0 0 0 0 0 16 dB

0 1 1 1 1 1 1 31.5 dB

Table 5. Truth Table

Note: Not all 64 possible combinations of C0.5-C16 are shown in table

Serial Interface

The serial interface is a 6-bit serial-in, parallel-out

shift register buffered by a transparent latch. It is

controlled by three CMOS-compatible signals : Data,

Clock, and Latch Enable (LE). The Data and Clock

inputs allow data to be serially entered into the shift

the LE input.

The LE input controls the latch. When LE is HIGH,

the latch is transparent and the contents of the serial

shift register control the attenuator. When LE is

brought LOW, data in the shift register is latched.

The shift register should be loaded while LE is held

LOW to prevent the attenuator value from changing

as data is entered. The LE input should then be

toggled HIGH and brought LOW again, latching the

new data. The timing for this operation is defined by

Figure 17 (Serial Interface Timing Diagram) and

Table 8 (Serial Interface AC Characteristics).

Power-up Control Settings

The PE4302 always assumes a specifiable

attenuation setting on power-up. This feature exists

for both the Serial and Parallel modes of operation,

and allows a known attenuation state to be

established before an initial serial or parallel control

word is provided.

When the attenuator powers up in Serial mode (P/

S=1), the six control bits are set to whatever data is

present on the six parallel data inputs (C0.5 to C16).

This allows any one of the 64 attenuation settings to

be specified as the power-up state.

When the attenuator powers up in Parallel mode (P/

S=0) with LE=0, the control bits are automatically set

to one of four possible values. These four values

are selected by the two power-up control bits, PUP1

and PUP2, as shown in Table 6 (Power-Up Truth

Table, Parallel Mode).

P/S LE PUP2 PUP1 Attenuation State

0 0 0 0 Reference Loss

0 0 1 0 8 dB

0 0 0 1 16 dB

0 0 1 1 31 dB

0 1 X X Defined by C0.5-C16

Table 6. Parallel PUP Truth Table

Note: Power up with LE=1 provide s normal parallel operation with

C0.5-C16, and PUP1 and PUP2 are not active.

Product Specification

PE4302

Page 7 of 11

Evaluation Kit

The Digital Attenuator Evaluation Kit board was

designed to ease customer evaluation of the

PE4302 Digital Step Attenuator.

J9 is used in conjunction with the supplied DC

cable to supply VDD, GND, and –VDD. If use of

the internal negative voltage generator is desired,

then connect –VDD (Black banana plug) to

ground. If an external –VDD is desired, then apply

-3V.

J1 should be connected to the parallel port of a

PC with the supplied ribbon cable. The evaluation

software is written to operate the DSA in serial

mode, so Switch 7 (P/S) on the DIP switch SW1

should be ON with all other switches off. Using the

software, enable or disable each attenuation

setting to the desired combined attenuation. The

software automatically programs the DSA each

time an attenuation state is enabled or disabled.

To evaluate the Power Up options, first disconnect

the parallel ribbon cable from the evaluation

board. The parallel cable must be removed to

prevent the PC parallel port from biasing the

control pins.

During power up with P/S=1 high and LE=0 or P/

S=0 low and LE=1, the default power-up signal

attenuation is set to the value present on the six

control bits on the six parallel data inputs (C0.5 to

C16). This allows any one of the 64 attenuation

settings to be specified as the power-up state.

During power up with P/S=0 high and LE=0, the

control bits are automatically set to one of four

possible values presented through the PUP

interface. These four values are selected by the

two power-up control bits, PUP1 and PUP2, as

shown in the Table 6.

Resistor on Pin 1 & 3

A 10 k resistor on the inputs to Pin 1 & 3 (Figure

16) will eliminate package resonance between the

RF input pin and the two digital inputs. Specified

attenuation error versus frequency performance is

dependent upon this condition.

Figure 15. Evaluation Board Layout

Figure 16. Evaluation Board Schematic

Z=50 Ohm

PUP2

SMA

C16

CLK

100 pF

DATA

C4C0.5

10k

Z=50 Ohm

PUP1

VDD

MLPQ4X4

C16

RFin

DATA

CLK

VDD

PUP1

PUP2

VDD_D

GND

Vss/GND

RFout

GND

SMA

Note: Resistors on pins 1 and 3 are required to avoid package

resonance and meet error specifications over frequency.

Peregrine Specification 101/0112

Peregrine Specification 102/0144

Product Specification

PE4302

Page 8 of 11

Table 7. 6-Bit Attenuator Serial Programming

Table 9. Parallel Interface AC Characteristics

Figure 18. Parallel Interface Timing Diagram

Table 8. Serial Interface AC Characteristics

Figure 17. Serial Interface Timing Diagram

Clock

Data MSB LSB

LESUP

SDSUP

SDHLD

LEPW

B5 B4 B3 B2 B1 B0

C16C8C4C2C1C0.5

↑↑

LSB (last in)MSB (first in)

PDSUP

PDHLD

Parallel Data

C16:C0.5

LEPW

Symbol Parameter Min Max Unit

fClk Serial data clock

frequency (Note 1) 10 MHz

tClkH Serial clock HIGH time 30 ns

tClkL Serial clock LOW time 30 ns

tLESUP LE set-up time after last

clock falling edge 10 ns

tLEPW LE minimum pulse width 30 ns

tSDSUP Serial data set-up time

before clock rising edge 10 ns

tSDHLD Serial data hold time

after clock falling edge 10 ns

Note: fClk is verified during the functional pattern test. Serial

programming sections of the functional pattern are clocked at

10 MHz to verify fclk specification.

Symbol Parameter Min Max Unit

tLEPW LE minimum pulse width 10 ns

tPDSUP Data set-up time before

rising edge of LE 10 ns

tPDHLD Data hold time after

falling edge of LE 10 ns

VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified

Product Specification

PE4302

Page 9 of 11

Figure 19. Package Drawing

1.00

2.00

0.23

0.10 C A B

EXPOSED PAD

4.00

DETAIL A

115

0.50

TYP

2.00

TYP

0.55

DETAIL A

0.18

0.435

SEATING

PLANE

0.08 C

0.10 C

0.020

0.20 REF

EXPOSED PAD &

TERMINAL PADS

0.80

- C -

2.00 X 2.00

2.00

4.00

- B -

- A -

INDEX AREA

0.25 C

1. Dimension applies to metallized terminal and is measured

between 0.25 and 0.30 from terminal tip.

2. Coplanarity applies to the exposed heat sink slug as well as

the terminals.

3. Dimensions are in millimeters.

Product Specification

PE4302

Page 10 of 11

Figure 20. Marking Specifications

Figure 21. Tape and Reel Drawing

4302

YYWW

ZZZZZ

YYWW = Date Code

ZZZZZ = Last five digits of PSC Lot Number

Table 10. Ordering Information

Order Code Part Marking Description Package Shipping Method

4302-00 PE4302-EK PE4302-20MLP 4x4mm-EK Evaluation Kit 1 / Box

4302-51 4302 PE4302G-20MLP 4x4mm-75A Green 20-lead 4x4mm QFN 75 units / Tube

4302-52 4302 PE4302G-20MLP 4x4mm-3000C Green 20-lead 4x4mm QFN 3000 units / T&R

Product Specification

PE4302

Page 11 of 11

Sales Offices

The Americas

Peregrine Semiconductor Corporation

9380 Carroll Park Drive

San Diego, CA 92121

Tel: 858-731-9400

Fax: 858-731-9499

Europe

Peregrine Semiconductor Europe

Bâtiment Maine

13-15 rue des Quatre Vents

F-92380 Garches, France

Tel: +33-1-4741-9173

Fax : +33-1-4741-9173

For a list of representatives in your area, please refer to our Web site at: www.psemi.com

Data Sheet Identification

Advance Information

The product is in a formative or design stage. The data

sheet contains design target specifications for product

development. Specifications and features may change in

any manner without notice.

Preliminary Specification

The data sheet contains preli m inary data. Additional data

may be added at a later date. Peregrine reserves the right

to change specifications at any time without notice in order

to supply the best possible product.

Product Specification

The data sheet contains final data. In the event Peregrine

decides to change the specifications, Peregrine will notify

customers of the intended changes by issuing a DCN

(Document Change Notice).

The information in this data sheet is beli eved to be reliable.

However, Peregrine assumes no li ability for the use of this

information. Use shall be entirely at the user ’s own risk.

No patent rights or licenses to any circuits describe d in this

data sheet are implied or gran ted to any third party.

Peregrine’s products are not designed or intended for use in

devices or systems intended for surgical implant, or in other

applications intended to supp ort or sustain life, or in any

application in which the failure of the Peregrine product could

create a situation in which personal injury or death might occur.

Peregrine assumes no li ability for damages, including

consequential or incidental da mages, arising out of the use of

its products in such applications.

The Peregrine name, logo, and UTSi are registered trademarks

and UltraCMOS, HaRP and MultiSwitch are trademarks of

Peregrine Semiconductor Cor p.

Space and Defense Products

Americas:

Tel: 858-731-9453

Europe, Asia Pacific:

180 Rue Jean de Guiram and

13852 Aix-En-Provence Cedex 3, France

Tel: +33-4-4239-3361

Fax: +33-4-4239-7227

Peregrine Semiconductor, Asia Pacific (APAC)

Shanghai, 200040, P.R. China

Tel: +86-21-5836-8276

Fax: +86-21-5836-7652

Peregrine Semiconductor, Korea

#B-2607, Kolon Tripolis, 210

Geumgok-dong, Bundang- gu, Seongnam-si

Gyeonggi-do, 463-943 South Korea

Tel: +82-31-728-3939

Fax: +82-31-728-3940

Peregrine Semiconductor K.K., Japan

Teikoku Hotel Tower 10B-6

1-1-1 Uchisaiwai-cho, Chiyoda-ku

Tokyo 100-0011 Japan

Tel: +81-3-3502-5211

Fax: +81-3-3502-5213