ANALOG Monolithic DEVICES 12-Bit Quad DAC AD664 1.1 Scope. This specification covers the detail requirement for a 12-bit multiplying, quad, voltage output, digital-to- analog converter with readback and selectable modes. 1.2 Part Number. The complete part number per Table 1 of this specification is as follows: Device Part Number! -1 AD664SD-UNI/883B -2 AD664SD-BIP/883B -3 AD664TD-UNI/883B -4 AD664TD-BIP/883B -5 AD664TE/883B -6 AD664TJ/883B NOTE 'See paragraph 1.2.3 for package identifier. 1.2.3 Case Outline. See Appendix 1 of General Specification ADI-M-1000: package outline: Type Package Description D D-28 28-Pin Ceramic DIP E E-44A 44-Pin LCC J J-44 44-Pin JLCC 1.3 Absolute Maximum Ratings. (T,=+25C unless otherwise noted) Vip toDGND 2.0 ete ene tee eens Oto +7V Voc tO DGND 11 cee tee teen cence eens 0t0 +18 V Veg tODGND 2... ccc ec tee nett teen nee -18Vt0c0V Soldering 6.0.2.6. eee teen ene eee nena +300C, 10 sec Power Dissipation ......6.. 00. ee eee een nee ens 1000 mW AGND to DGND ... 00... eee nent een neee -1Vto+lV Reference Input .... 0.0.0... ce eee eee Vepp=l0 V and Vegr=(Vcc2 Vs Vezt2 V) Voc tO VER cic cc ee ene eee en ene ne eee ete eee 0 to +36 V Digital Inputs 0... eee etree nent ene nee -0.3 Vto +7 V Analog Outputs ..... 0.0.00. Indefinite Shorts to Vcc, Vit, Vez and GND 1.5 Thermal Characteristics. Thermal Resistance 6;< = 25C/W for D-28 814 = 60C/W for D-28 Oic = 42C/W for E-44A Oya = 125C/W for E-44A Qjc = 3.6C/W for J-44 lt REV. C DIGITAL-TO-ANALOG CONVERTERS 8-39 DIGITAL-TO-ANALOG CONVERTERS aAD664 SPECIFICATIONS Table 1. Design Sub [Sub | Sub Limit Group | Group | Group Test Symbol | Device @ +25C 1 2,3 4 Test Condition! Units Resolution RES 1, 2, 3,4, 5,6] 12 12 12 Bits Relative Accuracy RA -1,2 3/4 3/4 1 +LSB max 3,4 1/2 3/4 1 1/2 5,6 V2 1/2 3/4 Differential Nonlinearity | DNL -1,2 3/4 3/4 1 Major Carry Errors +LSB max -3,4 1/2 3/4 1 1/2 ~5,6 1/2 1/2 1 Gain Error Ag -1,2 7 7 All Bits On +LSB max | 3,4 5 7 5 | 3,6 5 5 Gain Tempco TCA, |-1,2 12 12 All Bits On tppm/C max | =3,4,5,6 10 10 . Unipolar Offset Error Vos -1 2 2 All Bits Off +LSB max 3 1 2 1 5,6 1 1 Unipolar Offset Tempco | TCVog | -1 3 3 All Bits Off +ppm/C max . -3,5,6 2 2 Bipolar Zero Error? Boze -2 3 3 MSB On, All Others Off | +LSB max 4 2 3 2 -5,6 2 2 Bipolar Zero Tempco TCpze | -2 12 12 MSB On, All Others Off | ppm/C max -4,5,6 10 10 Reference Input Rw -1, 2, 3, 4,5, 6)1.3 kO min Resistance 26 kD max Ref Voltage Range Vrer | 1, 2:3, 4,5, 6] Veg +2, Voc ~2 Volts Voltage Output, UNI? | Vou ~1, 3, 5,6 0, Vee -2 Volts Voltage Output, BIP* =| Vog -2, 4, 5, 6 Voc 2; Ver +2 Volts Output Current lour -1, 2, 3, 4,5, 6/5 mA min I Short Circuit Isc ~1, 2, 3, 4, 5, 6/40 mA max Ourput Voltage Settling Time toy ~1, 2, 3, 4, 5, 6} 10 ws max Power Supply Current | Ip, 1, 2, 3, 4, 5, 6/6 6 Vin = +2, Viz = 0.8 mA max 1 1 Vie = Vit Vir = 9 lee 1, 2, 3, 4, 5, 6/15 15 Ic: All Bits On lee -1, 2, 3, 4,5, 6} 19 19 Igc: All Bits Off Gain Matching Error? |[mAg | -1, 2 6 6 +LSB max 3,4 4 6 4 -5,6 14 4 Offset Matching Error? [mVos [-1 2 2 +LSB max -3 1 2 1 5,6 1 1 Bipolar Zero Matching |mBpz_ | 2 3 3 +LSB max Error 4 2 3 3 5,6 2 2 8-40 DIGITAL-TO-ANALOG CONVERTERS REV. CAD664 Design Sub [Sub | Sub Limit Group | Group | Group Test Symbol | Device @ +25C 1 2,3 4 Test Condition! Units Digital In High Voltage | Viz 1, 2, 3, 4, 5, 6] 2.0 2.0 2.0 Volts min Digital In Low Voltage | Vir. 1, 2, 3, 4,5, 6/0.8 0.8 0.8 Volts max Digital In High Current | Ip, -1, 2, 3, 4, 5,6 Vin = Vi: 10 10 10 Data Inputs +yA max 10 10 10 CS/DSO/DS/RST/RDILS | + 2A max 10 10 10 MS/TR +pA min 10 10 10 QS0/QS1/QS28 +pA max Digital In Low Current | Ij, 1, 2, 3, 4, 5,6 Vin = DGND: 10 10 10 Data Inputs tpA max 10 10 10 CS/DS0/DSI/RST/RD/LS | + pA max 10 10 10 MS/TR ~pA max 10 10 10 QS0/QS1/QS28 +pA max Digital Out Low Voltage Voi 1, 2, 3, 4, 5,6] 0.4 0.4 0.4 + Volts max Digital Out High Voltage Vor -1, 2,3, 4,5, 6}2.4 2.4 2.4 + Volts min Power Supply Gain PSGS -1, 2, 3, 4, 5,6 5 11.4 V<Vec=16.5 V +ppm/% Sensitivity 5 16.5 VeVpp=-1l4 V 5 4.5 VsV,155.5 V NOTES Veco = +15 V, Veg = -15 V, 50 9 resistor Pin 6 to Pin 7, AO, Al, A2, A3, CS = Logic 0, Vi = 2.0 V, Vy, = 0.8 V, unipolar configuration. *Bipolar zero error is the difference from the ideal output (0 volts) and the actual output voltage with code 100 000 000 000 applied to the inputs. 3For Voc<12 V and V__>~-12 V. Voltage not to exceed 10 V maximum. *A minimum power supply of + 12.0 V is required for 0 to +10 V and +10 V operation. A minimum power supply of +11.4 V is required for -5 V to +5 V operation. 5Gain error matching is the largest difference in gain error between any two DACs in one package. Offset error matching is the largest difference in offset error between any two DACs in one package. "Bipolar zero matching is the largest difference in bipolar zero error between any two DACs in one package. 44-pin versions only. 3.2.1 Functional Block Diagrams and Terminal Assignments. Veo Vee +32Vi4 BV ~12V~ 1V ANALOG GROUND 3 I g tT tT {Tf tf Ost O50 aat 28-Pin Block Diagram REV.C +8 0 ONGITAL Vu GRQUND Year Vee Ven ANALOG S12Ni4 VV -12V'-15Y GROUND a egee a i gga ii y TO BW OFF A-0 bP OFF A j RB & eae [ws Lae =F" ent _ hd ar > TO Ves &-O nae A roo s : V 4 1 Tue Ort No ce Xz SWITCHES aDtes ah Bw OFF C " ab Ver Ry x2 fe Re per ee one ro LatouEs ae a" a oes > Vv om | i an aa Vy Dez f us my = ay > aes] v Y 66.1.2 mot comes (= 6 i TR ME os: peo ST sv BGT, 44-Pin Block Diagram DIGITAL-TO-ANALOG CONVERTERS 8-41 DIGITAL-TO-ANALOG CONVERTERS aAD664 D Package (DIP) J Package (JLCC) and WwW E Package (LCC) Vacew [9 | e 28] Vos ss v, (2] 27] v, : : 5 5 5 5 " " se EF PE. Ge Voo [3 | [26] Vee(~12v/15v) 25 3 zz & Zz: ~~ = QO eo 2 OO = as [4 | 25 | Vee(+12V/+ 151 23 g Seaeseee8 oso (5 | 24] AGNO fe) (5) (2113) f+) fo3} faz] [a9] feo} osi[ | 23 | is fre DY 33] DB10 vi bes ocno [7 | AD664 [22] Ab on 18 Be _ TOP VIEW Voe [9] pes mst [es] (Notto Sealey [21] viitesv) Ree [36] OB7 0B0 use(s | 20] 0811 (MSB} Vace wu [1] ADse4 3] oes 0B1| 10 19 | 0810 Rec ware tle) [34] NO CONNECT oe2|11 18 | DBS Voc [13] 33] OBS DB3 | 12 17 | Das Voo [14] 2] 084 A DB3 ea [13 16 | oa7 ro Ls} a NO CONNECT [r6] 30] DBZ 15 | 086 DBs [14 1s} 08 NO CONNECT 29] DB1 9} [29] [21] i) ao Fr a |e ha oe i Bge2bRB BERS a a w 2 3.2.4 Microcircuit Technology Group. This microcircuit is covered by technology group (56). 4.2.1 Life TestBurn-In Circuit. Steady state life test is per MIL-STD-883 Method 1005. Burn-in is per MIL-STD-883 Method 1015 test condition (B). 4709F +V -16.5V +16.5V O1mF P 9 470pF AD6G4 TOP VIEW {Not to Scale) 3 & [' x # Ts " | rt olf} fe] [= | O-5Y SQ WAVE +SV O.1pF T i FIELEIEIEIE NC = NO CONNECT JL o-sv so wave 8-42 DIGITAL-TO-ANALOG CONVERTERS REV. CAD664 Table 2. Digital Timing Specifications Limit 55C to +25C | +125C Parameter Symbol | (Min) | (Min) Units Data Input (Figure 1) CS Pulse Width Lowe 80 100 ns Data Setup Ts 0 0 ns Data Hold tpn 15 15 ns Address Setup Tas 0 0 ns Address Hold tan 15 1s ns LS Setup ts 0 0 ns LS Hold tla 15 1 ns Data Input (Figure 3) Data Setup Ups 0 0 ns Data Hold lpn 0 0 ns LS Width ti 60 80 ns LS Setup tis! 0 0 ns CS Hold tcH 30 50 ns Address Setup las 0 0 ns Address Hold tan 0 0 ns Mode Select ( Figure 5) MS Setup IMs 0 0 ns Address Setup ts! 0 0 ns Data Setup tps 0 0 ns LS Width tLe 60 70 ns CS Hold Gu 70 80 ns Data Hold toy 0 0 ns MS Hold tan 0 0 ms Mode Select (Figure 7) MS Setup tvs 0 0 ns MS Hold thn ts 15 ns LS Setup ths 0 0 ns Data Setup tos 0 a ns CS Width ty 80 100 ns LS Hold tly 15 15 ns Data Hold tou 15 15 ns Readback (Figure 8, 10) Address Setup tas 0 0 ns Address Hold tay 0 0 ns RD Setup tas 0 0 ns RD Hold tex 0 0 ns MS Setup ims 0 0 ns MS Hold tw 0 0 ns Data Access lpy i50 180 ns Data Release tor 60 75 ns Transparent Operation (Figure 11) (44-Pin Version Only) Address Setup tas 0 0 ns Quad Select Setup tas 0 0 ns Transparent Setup trs 0 0 ns Transparent Width try 80 90 ns Chip Select Hold tow % 110 ns Data Hold tow 0 0 ns Quad Select Hold tou 0 0 ns Asynchronous Reset (Figure 12) Reset Width taw 80 100 ns NOTES For t_5>0, the width of LS must be increased by the same amount that Is is greater than 0 ns. Timing specifications are relative to CS. Veg = +15 V, Veg = Refer to Figures 1-12. REV. C -15 V, Veer = +10 V, Vig = 2.4 V, Viz. = 0.4 V. Specifications are guaranteed but not tested. DATA INPUT/OUTPUT DATA VALID BITS ef tos fe be ton _ ADDRES: i , OSI, ADDRESS VALID 050, DS1 [rts tan be Ea > tun kao Figure 1. Preload First Rank of a DAC nesnosrne \ LLL SL amtsas | W/L ET, DSO, DS1 =!1 TH. D.AST 9 tow = BONE MIN (100n8 AT Twins - Tax) aie 1 cs 0 Figure 2. Update Second Rank of a DAC BATA INPUT'OUTPUT DATA VALID BITS Sl a ADDR! $8 0 T agroet SZ ADDRESS VALID 0S0,DS1 A ts > tan fee ts tw a - bee tors \_ Figure 3. Update Output of a Single DAC = 8 Oe DSo, 081 mneuTroutrut Figure 4. Update All DAC Outputs MS | tus > > tran L. DATA MODE SELECT on tos > f | be ton coo ere +uP a ke ts Figure 5. Load and Update Mode of One DAC DIGITAL-TO-ANALOG CONVERTERS 8-43 DIGITAL-TO-ANALOG CONVERTERS aAD664 DATA ! INPUT/OUTPUT | | eITs DATA , INPUTOUTPUT own vauo DATA, VALID x DATA, VALID J DATA, VALID I 7 7 ADDRESS _ De a BI X- ae Gs ass _X ONE K eRe k THREE x FOUR a ee LIAL OF [ ts { j \ / \_/ L/ Figure 9. Preload First Rank Registers tw 7 ( | Figure 6. Load and Update Multiple DACs $0, QS1 we tas > tan =e fA te ms / iru tao fo bet as a hm we ~ |_ ss ATA a DATA = HIGH z4 CATA So nichz ae tov nal >| tor L Figure 7. Prelaad Mode Select Register Figure 10. Mode Select Readback ADDRESS _ ey 3 ols be tm DATA nour if aD \ LL OUTPUT BITS + DATA VALID tC _ tos a + ton 2 oir +H a cs js fos >{ ton srl) Ta tw InpuTiOuTeUT ~HIGH 2 {OUI S on 2 >!trs je bettors no" ws TN wl Fe Figure 8. DAC Input Code Readback Figure 11. Fully Transparent Mode Table 3. AD664 Truth Table Function DS1, DSo | CS | MS | TR QS0, 1, 7 RD | cs | RST Load Ist Rank DACA 00 0 |1 |1 | Select Quad} 1 f 10] 1 tw = 90ns MIN DACB 01 0 ] 1 Select Quad | 1 1-0 | 1 DACC 10 0 1 1 Select Quad | 1 1-0} 1 DACD 1 071 L | Select Quad] 1 | 10] 1 AST Load 2nd Rank | XX 1 1 1 XXX 1 1-0} 1 ' t Read 2nd Rank | Select D/A] X | 1 1 Select Quad | 0 1-0] 1 Reset XX x |x |xxx x Ix 0 Figure 12. Asynchronous Reset Operation Transparent! All DACs XX 1 1 0 000 1 1-0) 1 DACA 00 0 1 0 000 1 1-0} 1 DACB 01 0 1 0 000 1 10] 1 DACC 10 Q 1 0 000 1 1-0] 1 DACD 1 0 I 0 000 1 1-0) 1 Made Select: 2 ist Rank XX 0 0 00X 1 10] 1 2nd Rank XX 1 0 XXX 1 1-0 f 1 Readback Mode! | XX xX |0 1 00X 0 1>0/)1 NOTES X=Don't care. For 44-pin versions only. &44 DIGITAL-TO-ANALOG CONVERTERS For MS, TR, LS=0, a MS Ist write occurs. REV. C