R0201-BS62LV1027 Revision 2.1
Jan. 2004
1
POWER DISSIPATION
SPEED
(ns) STANDBY
(ICCSB1, Max) (ICC, Max)
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE PKG TYPE
BS62LV1027SC SOP-32
BS62LV1027TC TSOP-32
BS62LV1027STC STSOP-32
BS62LV1027PC PDIP-32
BS62LV1027JC SOJ-32
BS62LV1027DC
+0 O C to +70 O C 2.4V ~ 5.5V 55/70 8.0uA 14mA
DICE
BS62LV1027SI SOP-32
BS62LV1027TI TSOP-32
BS62LV1027STI STSOP-32
BS62LV1027PI PDIP-32
BS62LV1027JI SOJ-32
BS62LV1027DI
-40 O C to +85 O C2.4V ~ 5.5V 55/70 20uA 15mA
DICE
Very Low Power/Voltage CMOS SRAM
128K X 8 bit
• Wide Vcc operation voltage : 2.4V ~ 5.5V
• Very low power consumption :
Vcc = 3.0V C-grade : 17mA (@55ns) operating current
I- grade : 18mA (@55ns) operating current
C-grade : 14mA (@70ns) operating current
I- grade : 15mA (@70ns) operating current
0.1uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade : 46mA (55ns) operating current
I- grade : 47mA (55ns) operating current
C-grade : 38mA (70ns) operating current
I- grade : 39mA (70ns) operating current
0.6uA (Typ.) CMOS standby current
• High speed access time :
-55 55ns
-70 70ns
• Automatic power down when chip is deselected
The BS62LV1027 is a high performance, very low power CMOS
Static Random Access Memory organized as 131,072 words by 8 bits
and operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.1uA at 3V/25oC and maximum access time of 55ns at 3V/85oC.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
The BS62LV1027 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV1027 is available in DICE form , JEDEC standard 32 pin
450mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP,8mm x13.4
mm STSOP and 8mmx20mm TSOP.
DESCRIPTION
FEATURES
BLOCK DIAGRAM
PRODUCT FAMILY
PIN CONFIGURATIONS
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
BS62LV1027
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
•
BS62LV1027SC
BS62LV1027SI
BS62LV1027PC
BS62LV1027PI
BS62LV1027JC
BS62LV1027JI
A7
Address
Input
Buffer
Row
Decoder
Memory Array
1024 x 1024
Column I/O
Write Driver
Sense Amp
Column Decoder
Data
Buffer
Output
Address Input Buffer
A3 A2 A1 A0 A10
Data
Buffer
Input
Control
Gnd
Vdd
OE
WE
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
A14
A9
A11
A8
A13
A12
A6
8
8
8
8
14
128
1024
1024
20
A16
A15
A4
A5
CE2
BSI
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
•
BS62LV1027TC
BS62LV1027STC
BS62LV1027TI
BS62LV1027STI
• Easy expansion with CE2, CE1, and OE options
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
Vcc=5.0V Vcc=3.0V 70ns
1.3uA
2.5uA
38mA
39mA
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
55ns : 3.0~5.5V
70ns : 2.7~5.5V
Operating
70ns
Vcc=3V Vcc=5V
R0201-BS62LV1027 Revision 2.1
Jan. 2004
2
BSI BS62LV1027
SYMBOL PARAMETER CONDITIONS MAX. UNIT
CIN Input
Capacitance VIN=0V 6 pF
CDQ Input/Output
Capacitance VI/O=0V 8 pF
ABSOLUTE MAXIMUM RATINGS(1) OPERATING RANGE
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
1. This parameter is guaranteed and not 100% tested.
SYMBOL PARAMETER RATING UNITS
VTERM Terminal Voltage with
Respect to GND
-0.5 to
Vcc+0.5 V
TBIAS Temperature Under Bias -40 to +85 O C
TSTG Storage Temperature -60 to +150 O C
PTPower Dissipation 1.0 W
IOUT DC Output Current 20 mA
RANGE AMBIENT
TEMPERATURE Vcc
Commercial 0 O C to +70 O C2.4V ~ 5.5V
Industrial -40 O C to +85 O C2.4V ~ 5.5V
TRUTH TABLE
PIN DESCRIPTIONS
Name Function
A0-A16 Address Input These 17 address inputs select one of the 131,072 x 8-bit words in the RAM
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
DQ0-DQ7 Data Input/Output
Ports
These 8 bi-directional ports are used to read data from or write data into the RAM.
Vcc Power Supply
Gnd Ground
MODE WE CE1 CE2 OE I/O OPERATION Vcc CURRENT
XHXX
Not selected
(Power Down) XXLX High Z ICCSB, I CCSB1
Output Disabled H L H H High Z ICC
Read H L H L DOUT ICC
Write L L H X DIN ICC
R0201-BS62LV1027 Revision 2.1
Jan. 2004
3
BSI BS62LV1027
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC .
4. IccSB1_Max. is 1.3uA/8.0uA at Vcc=3.0V/5.0V and TA=70oC.
5. Icc_Max. is 18mA(@3V)/ 47mA(@5V) under 55ns operation.
DATA RETENTION CHARACTERISTICS ( TA = -40oC to + 85oC )
1. Vcc = 1.5V, TA= + 25OC
2. tRC = Read Cycle Time
3. IccDR_MAX. is 0.2uA at TA=70OC.
DC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC )
LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
CE1
Data Retention Mode
Vcc
tCDR
Vcc
tR
VIHVIH
Vcc VDR 1.5V
≥
CE1 Vcc - 0.2V
≥
LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS
VDR Vcc for Data Retention CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V,
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V 1.5 -- -- V
ICCDR
(3) Data Retention Current CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V,
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V -- 0.05 0.3 uA
tCDR Chip Deselect to Data
Retention Time 0 -- -- ns
tR Operation Recovery Time
See Retention Waveform
TRC
(2) -- -- ns
CE2
Data Retention Mode
Vcc
tCDR
Vcc
tR
VIL
VIL
Vcc VDR ≧1.5V
CE2 ≦0.2V
PARAMETER
NAME PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS
Vcc=3.0V
VIL Guaranteed Input Low
Voltage(2) Vcc=5.0V -0.5 -- 0.8 V
Vcc=3.0V 2.0
VIH Guaranteed Input High
Voltage(2) Vcc=5.0V 2.2 -- Vcc+0.3 V
IIL Input Leakage Current Vcc = Max, VIN = 0V to Vcc -- -- 1 uA
ILO Output Leakage Current Vcc = Max, CE1= VIH, CE2= VIL, or
OE = VIH, VI/O = 0V to Vcc -- -- 1 uA
Vcc=3.0V
VOL Output Low Voltage Vcc = Max, IOL = 2.0mA Vcc=5.0V -- -- 0.4 V
Vcc=3.0V
VOH Output High Voltage Vcc = Min, IOH = -1.0mA Vcc=5.0V 2.4 -- -- V
Vcc=3.0V -- -- 15
ICC(5) Operating Power Supply
Current
CE1 = VIL, or CE2 = VIH,
IDQ = 0mA, F = Fmax(3) 70ns
Vcc=5.0V -- -- 39
mA
Vcc=3.0V -- -- 0.5
ICCSB Standby Current-TTL
CE1 = VIH, or CE2 = VIL,
IDQ = 0mA Vcc=5.0V -- -- 1.0
mA
Vcc=3.0V -- 0.1 2.5
ICCSB1(4) Standby Current-CMOS
CE1≧Vcc-0.2V or CE2≦0.2V,
VIN≧Vcc-0.2V or VIN≦0.2V Vcc=5.0V -- 0.6 20 uA
R0201-BS62LV1027 Revision 2.1
Jan. 2004
4
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
BSI BS62LV1027
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
1V/ns
Input and Output
Timing Reference Level
0.5Vcc
Output Load
CL = 30pF+1TTL
CL = 100pF+1TTL
AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC )
READ CYCLE
JEDEC
PARAMETER
NAME NAME DESCRIPTION UNIT
tAVAX tRC Read Cycle Time 55 -- -- 70 -- -- ns
tAVQV tAA Address Access Time -- -- 55 -- -- 70 ns
tE1LQV tACS1 Chip Select Access Time (CE1) -- -- 55 -- -- 70 ns
tE2HOV tACS2 Chip Select Access Time (CE2) -- -- 55 -- -- 70 ns
tGLQV tOE Output Enable to Output Valid -- -- 30 -- -- 40 ns
tE1LQX tCLZ1 Chip Select to Output Low Z (CE1) 10 -- -- 10 -- -- ns
tE2HOX tCLZ2 Chip Select to Output Low Z (CE2) 10 -- -- 10 -- -- ns
tGLQX tOLZ Output Enable to Output in Low Z 10 -- -- 10 -- -- ns
tE1HQZ tCHZ1 Chip Deselect to Output in High Z (CE1) -- -- 35 -- -- 40 ns
tE2HQZ tCHZ2 Chip Deselect to Output in High Z (CE2) -- -- 35 -- -- 40 ns
tGHQZ tOHZ Output Disable to Output in High Z -- -- 30 -- -- 35 ns
tAXOX tOH Data Hold from Address Change 10 -- -- 10 -- -- ns
PARAMETER CYCLE TIME : 55ns
MIN. TYP. MAX.
(Vcc = 3.0~5.5V)
MIN. TYP. MAX.
(Vcc = 2.7~5.5V)
CYCLE TIME : 70ns
R0201-BS62LV1027 Revision 2.1
Jan. 2004
5
BSI BS62LV1027
READ CYCLE3 (1,4)
READ CYCLE2 (1,3,4)
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = VIL .
5. The parameter is guaranteed but not 100% tested.
tCLZ
(5)
D OUT
CE2
CE1
(5)
tACS2
tACS1
tOH
t RC
tOE
tCLZ2
tCHZ2
(2,5)
D OUT
CE2
CE1
OE
ADDRESS
(5)
tCLZ1
(5) tACS1
tACS2
tCHZ1
(1,5)
tOHZ (5)
tOLZ
tAA
tCHZ1, tCHZ2
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t RC
t OH
t AA
DOUT
ADDRESS
t OH
R0201-BS62LV1027 Revision 2.1
Jan. 2004
6
BSI BS62LV1027
WRITE CYCLE1 (1)
t WR1
tWC
(3)
tCW
(11)
(11)
t CW
(2)
t WP
tAW
t OHZ
(4,10)
t AS
t WR2 (3)
t DH
t DW
DIN
D OUT
WE
CE2
CE1
OE
ADDRESS
(5)
(5)
AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC )
WRITE CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME DESCRIPTION UNIT
tAVAX tWC Write Cycle Time 55 -- -- 70 -- -- ns
tE1LWH tCW Chip Select to End of Write 55 -- -- 70 -- -- ns
tAVWL tAS Address Set up Time 0 -- -- 0 -- -- ns
tAVWH tAW Address Valid to End of Write 55 -- -- 70 -- -- ns
tWLWH tWP Write Pulse Width 35 -- -- 50 -- -- ns
tWHAX tWR1 Write Recovery Time (CE1 , WE) 0 -- -- 0 -- -- ns
tE2LAX tWR2 Write Recovery Time (CE2) 0 -- -- 0 -- -- ns
tWLOZ tWHZ Write to Output in High Z -- -- 25 -- -- 30 ns
tDVWH tDW Data to Write Time Overlap 25 -- -- 30 -- -- ns
tWHDX tDH Data Hold from Write Time 0 -- -- 0 -- -- ns
tGHOZ tOHZ Output Disable to Output in High Z -- -- 25 -- -- 30 ns
tWHQX tOW End of Write to Output Active 5 -- -- 5 -- -- ns
CYCLE TIME : 55ns
MIN. TYP. MAX. MIN. TYP. MAX.
(Vcc = 3.0~5.5V) (Vcc = 2.7~5.5V)
SWITCHING WAVEFORMS (WRITE CYCLE)
CYCLE TIME : 70ns
R0201-BS62LV1027 Revision 2.1
Jan. 2004
7
BSI BS62LV1027
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.
All signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition edge
of the signal that terminates the write.
3. TWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write
cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
10. The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE1 going low or CE2 going high to the end of write.
WRITE CYCLE2 (1,6)
t WC
tCW
(11)
(11)
t CW
(2)
t WP
tAW
t WHZ
(4,10)
t AS
t WR2
(3)
t DH
t DW
DIN
D OUT
WE
CE2
CE1
ADDRESS
(5)
(5)
t OW (7) (8)
(8,9)
R0201-BS62LV1027 Revision 2.1
Jan. 2004
8
ORDERING INFORMATION
BSI
PACKAGE DIMENSIONS
BS62LV1027
BASE METAL
WITH PLATING
cc1
SECTION A-A
b1
b
SOP -32
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.
PACKAGE
J: SOJ
S: SOP
P: PDIP
T: TSOP (8mm x 20mm)
ST: Small TSOP (8mm x 13.4mm)
D: DICE
BS62LV1027 X X ZY Y
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
R0201-BS62LV1027 Revision 2.1
Jan. 2004
9
BSI BS62LV1027
PACKAGE DIMENSIONS (continued)
TSOP - 32
STSOP - 32
R0201-BS62LV1027 Revision 2.1
Jan. 2004
10
BSI BS62LV1027
PACKAGE DIMENSIONS (continued)
PDIP - 32
SOJ - 32
