=* Semiconductor aaa Corporation Lattice ispLSI 2064VE 3.3V In-System Programmable SuperFAST High Density PLD * SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC 2000 PLD Gates ~ 64 and 32 I/O Pin Versions, Four Dedicated Inputs 64 Registers High Speed Global Interconnect ~ Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size for Random Logic 100% Functional/JEDEC Upward Compatible with ispLS! 2064V Devices * 3.3V LOW VOLTAGE 2064 ARCHITECTURE interfaces with Standard 5V TTL Devices ~ 641/0 Pin Version is Fuse Map Compatible with 5V ispLSI* 2064 and 2064E * HIGH PERFORMANCE E*CMOS* TECHNOLOGY fimax = 180 MHz Maximum Operating Frequency tpd = 5.0 ns Propagation Delay ~~ Electrically Erasable and Reprogrammabie Non-Volatile 100% Tested at Time of Manufacture Unused Product Term Shutdown Saves Poywgr * IN-SYSTEM PROGRAMMABLE 3.3V In-System Programmability (SP Boundary Scan Test Access Port (TA Open-Drain Output Option for F Y OR Bus Arbitration Logic Increased Manufacturing Market and Improved Prog Reprogram Solder vice * 100% IEEE 1149.1 BO * THE EASE OF USE AN SYSTEM SPEED OF PLDs WITH THE DENS! ND FLEXIBILITY OF FPGAS Enhanced Pin Locking Capability Three Dedicated Clock Input Pins Synchronous and Asynchronous Clocks Programmable Output Siew Rate Control Flexible Pin Placement Optimized Global Routing Pool Provides Global Interconnectivity * ispEXPERT LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING ~~ Superior Quality of Results Tightly Integrated with Leading CAE Vendor Tools Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER ~ PC and UNIX Platforms Functional Block Diagram me Globai Routing Peat {GRP} Output Routing Pool (ORP) se F Output Routing Pool (ORP) pat Bus. Q1394/2064V Description The ispLS! 2064VE is a High Density Programmable Logic Device available in 64 and 32 1/O-pin versions. The device contains 64 Registers, four Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Globai OE input pins and a Giobal Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLS! 2064VE features in-system programmability through the Boundary Scan Test Ac- cess Port (TAP) and is 100% JEEE 1149.1 Boundary Scan Testable. The ispLSI 2064VE offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLS/ 2064VE device is the Generic Logic Block (GLB). The GLBs are labeled AO, Ai .. B7 (see Figure 1). There are a total of 16 GLBs in the ispLSI 2064VE device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to tne GLB come from the GRP and dedicated inouts. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. Copyright 1998 Lattice Semiconductor Core Ail brand or product names are trademarks or registered rademarks of tneir respective holders. The specifications ard information herein are subject to change without notice LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. November 1998 Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.iatticesemi.com 75