®
1. General description
The ADC1210S is a single-channel 12-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performance and low power consumption at sample rates up to 125 Msps.
Pipelined architecture and output error correction ensure the ADC1210S is accurate
enough to guarantee zero missing codes over the entire operating range. Supplied from a
single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode
because of a separate digital output supply. It supports the Low Voltage Differential
Signalling (LVDS) Double Data Rate (DDR) output standard. An integrated
Serial Peripheral Interface (SPI) allows the user to easily configure the ADC. The device
also includes a programmable full-scale SPI to allow a flexible input voltage range from
1 V to 2 V (peak-to-peak). With excellent dynamic performance from the baseband to
input frequencies of 170 MHz or more, the ADC1210S is ideal for use in communications,
imaging and medical applications.
2. Features and benefits
3. Applications
ADC1210S series
Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;
CMOS or LVDS DDR digital outputs
Rev. 03 — 2 July 2012 Product data sheet
SNR, 70 dBFS; SFDR, 86 dBc Input bandwidth, 600 MHz
Sample rate up to 125 Msps Power dissipation, 430 mW at 80 Msps
12-bit pipelined ADC core Serial Peripheral Interface (SPI)
Clock input divided by 2 for less jitter Duty cycle stabilizer
Single 3 V supply Fast OuT-of-Range (OTR) detection
Flexible input voltage range: 1 V (p-p) to
2 V (p-p)
Offset binary, two’s complement, gray
code
CMOS or LVDS DDR digital outputs Power-down and Sleep modes
Pin compatible with the ADC1410S
series and the ADC1010S series
HVQFN40 package
Wireless and wired broadband
communications
Portable instrumentation
Spectral analysis Imaging systems
Ultrasound equipment Software defined radio
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 2 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
4. Ordering information
5. Block diagram
Table 1. Ordering information
Type number fs (Msps) Package
Name Description Version
ADC1210S125HN-C1 125 HVQFN40 plastic thermal enhanced very thin quad flat package;
no leads; 40 terminals; body 6 6 0.85 mm
SOT618-1
ADC1210S105HN-C1 105 HVQFN40 plastic thermal enhanced very thin quad flat package;
no leads; 40 terminals; body 6 6 0.85 mm
SOT618-1
ADC1210S080HN-C1 80 HVQFN40 plastic thermal enhanced very thin quad flat package;
no leads; 40 terminals; body 6 6 0.85 mm
SOT618-1
ADC1210S065HN-C1 65 HVQFN40 plastic thermal enhanced very thin quad flat package;
no leads; 40 terminals; body 6 6 0.85 mm
SOT618-1
Fig 1. Block diagram
ADC1210S
SPI INTERFACE
OUTPUT
DRIVERS
OUTPUT
DRIVERS
SYSTEM
REFERENCE AND
POWER
MANAGEMENT
ERROR
CORRECTION AND
DIGITAL
PROCESSING
ADC CORE
12-BIT
PIPELINED
T/H
INPUT
STAGE
INP
OTR
CS
SDIO/ODS
SCLK/DFS
PWD
REFT
CMOS:
D11 to D0
or
LVDS DDR:
D10_D11_M to D0_D1_M
D10_D11_P to D0_D1_P
INM
CLOCK INPUT
STAGE AND DUTY
CYCLE CONTROL
REFB
CLKMCLKP SENSE
VREF
VCM
005aaa131
OE
CMOS:
DAV
or
LVDS DDR:
DAVP
DAVM
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 3 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 2. Pin configuration with CMOS digital outputs
selected
Fig 3. Pin configuration with LVDS DDR digital
outputs selected
ADC1210S
HVQFN40
D7
D6
D5
D4
D3
D2
D1
D0
n.c.
n.c.
VDDA
INP
INM
AGND
VDDA
VCM
AGND
REFT
REFB
VDDA
CLKP
CLKM
DEC
PWD
D11
D10
D9
D8
VREF
SENSE
SDIO/ODS
SCLK/DFS
OTR
OGND
VDDO
n.c.
DAV
10 21
9 22
8 23
7 24
6 25
5 26
4 27
3 28
2 29
1 30
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
AGND
terminal 1
index area
Transparent top view
005aaa132
OE
CS
ADC1210S
HVQFN40
D6_D7_M
D6_D7_P
D4_D5_M
D4_D5_P
D2_D3_M
D2_D3_P
D0_D1_M
D0_D1_P
n.c.
n.c.
VDDA
INP
INM
AGND
VDDA
VCM
AGND
REFT
REFB
VDDA
CLKP
CLKM
DEC
PWD
D10_D11_M
D10_D11_P
D8_D9_M
D8_D9_P
VREF
SENSE
SDIO/ODS
SCLK/DFS
OTR
OGND
VDDO
DAVP
DAVM
10 21
9 22
8 23
7 24
6 25
5 26
4 27
3 28
2 29
1 30
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
AGND
terminal 1
index area
Transparent top view
005aaa133
OE
CS
Table 2. Pin description (CMOS digital outputs)
Symbol Pin Type [1] Description
REFB 1 O bottom reference
REFT 2 O top reference
AGND 3 G analog ground
VCM 4 O common-mode output voltage
VDDA 5 P analog power supply
AGND 6 G analog ground
INM 7 I complementary analog input
INP 8 I analog input
AGND 9 G analog ground
VDDA 10 P analog power supply
VDDA 11 P analog power supply
CLKP 12 I clock input
CLKM 13 I complementary clock input
DEC 14 O regulator decoupling node
OE 15 I output enable, active LOW
PWD 16 I power-down, active HIGH
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 4 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
[1] P: power supply; G: ground; I: input; O: output; I/O: input/output.
D11 17 O data output bit 11 (Most Significant Bit (MSB))
D10 18 O data output bit 10
D9 19 O data output bit 9
D8 20 O data output bit 8
D7 21 O data output bit 7
D6 22 O data output bit 6
D5 23 O data output bit 5
D4 24 O data output bit 4
D3 25 O data output bit 3
D2 26 O data output bit 2
D1 27 O data output bit 1
D0 28 O data output bit 0 (Least Significant Bit (LSB))
n.c. 29 - not connected
n.c. 30 - not connected
DAV 31 O data valid output clock
n.c. 32 - not connected
VDDO 33 P output power supply
OGND 34 G output ground
OTR 35 O out of range
SCLK/DFS 36 I SPI clock
data format select
SDIO/ODS 37 I/O SPI data IO
output data standard
CS 38 I SPI chip select
SENSE 39 I reference programming pin
VREF 40 I/O voltage reference input/output
Table 3. Pin description (LVDS DDR) digital outputs)
Symbol Pin [1] Type [2] Description
D10_D11_M 17 O differential output data D10 and D11 multiplexed, complement
D10_D11_P 18 O differential output data D10 and D11 multiplexed, true
D8_D9_M 19 O differential output data D8 and D9 multiplexed, complement
D8_D9_P 20 O differential output data D8 and D9 multiplexed, true
D6_D7_M 21 O differential output data D6 and D7 multiplexed, complement
D6_D7_P 22 O differential output data D6 and D7 multiplexed, true
D4_D5_M 23 O differential output data D4 and D5 multiplexed, complement
D4_D5_P 24 O differential output data D4 and D5 multiplexed, true
D2_D3_M 25 O differential output data D2 and D3 multiplexed, complement
D2_D3_P 26 O differential output data D2 and D3 multiplexed, true
D0_D1_M 27 O differential output data D0 and D1 multiplexed, complement
D0_D1_P 28 O differential output data D0 and D1 multiplexed, true
n.c. 29 - not connected
Table 2. Pin description (CMOS digital outputs) …continued
Symbol Pin Type [1] Description
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 5 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
[1] Pins 1 to 16 and pins 33 to 40 are the same for both CMOS and LVDS DDR outputs (see Table 2).
[2] P: power supply; G: ground; I: input; O: output; I/O: input/output.
7. Limiting values
8. Thermal characteristics
[1] Value for six layers board in still air with a minimum of 25 thermal vias.
n.c. 30 - not connected
DAVM 31 O data valid output clock, complement
DAVP 32 O data valid output clock, true
Table 3. Pin description (LVDS DDR) digital outputs) …continued
Symbol Pin [1] Type [2] Description
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VOoutput voltage pins D11 to D0 or
pins D10_D11_P to D0_D1_P
and D10_D11_M to D0_D1_M
0.4 +3.9 V
VDDA analog supply voltage 0.4 +3.9 V
VDDO output supply voltage 0.4 +3.9 V
Tstg storage temperature 55 +125 C
Tamb ambient temperature 40 +85 C
Tjjunction temperature - 125 C
Table 5. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-a) thermal resistance from junction to ambient [1] 22.5 K/W
Rth(j-c) thermal resistance from junction to case [1] 11.7 K/W
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 6 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
9. Static characteristics
Table 6. Static characteristics[1]
Symbol Parameter Conditions Min Typ Max Unit
Supplies
VDDA analog supply voltage 2.85 3.0 3.4 V
VDDO output supply voltage CMOS mode 1.65 1.8 3.6 V
LVDS DDR mode 2.85 3.0 3.6 V
IDDA analog supply current fclk =125Msps; f
i=70MHz - 210 - mA
IDDO output supply current CMOS mode; fclk =125Msps;
fi=70MHz
-12-mA
LVDS DDR mode:
fclk =125Msps; f
i=70MHz
-39-mA
P power dissipation ADC1210S125;
analog supply only
-630-mW
ADC1210S105;
analog supply only
-550-mW
ADC1210S080;
analog supply only
-430-mW
ADC1210S065;
analog supply only
-380-mW
Power-down mode - 2 - mW
Sleep mode - 40 - mW
Clock inputs: pins CLKP and CLKM
Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
Vi(clk)dif differential clock input voltage peak-to-peak - 1.6 - V
SINE wave
Vi(clk)dif differential clock input voltage peak - 3.0 - V
Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)
VIL LOW-level input voltage - - 0.3VDDA V
VIH HIGH-level input voltage 0.7VDDA --V
Logic inputs: pins PWD and OE
VIL LOW-level input voltage 0 - 0.8 V
VIH HIGH-level input voltage 2 - VDDA V
IIL LOW-level input current - 55 - A
IIH HIGH-level input current - 65 - A
Serial peripheral interface: pins CS, SDIO/ODS, SCLK/DFS
VIL LOW-level input voltage 0 - 0.3VDDA V
VIH HIGH-level input voltage 0.7VDDA -V
DDA V
IIL LOW-level input current 10 - +10 A
IIH HIGH-level input current 50 - +50 A
CIinput capacitance - 4 - pF
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 7 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
[1] Typical values measured at VDDA =3V, V
DDO =1.8V, T
amb =25C and CL= 5 pF; minimum and maximum values are across the full
temperature range Tamb =40 C to +85 C at VDDA =3V, V
DDO = 1.8 V; VINP VINM =1 dBFS; internal reference mode; applied to
CMOS and LVDS interface; unless otherwise specified.
Digital outputs, CMOS mode: pins D11 to D0, OTR, DAV
Output levels, VDDO = 3 V
VOL LOW-level output voltage OGND - 0.2VDDO V
VOH HIGH-level output voltage 0.8VDDO -V
DDO V
COoutput capacitance high impedance; OE =HIGH - 3 - pF
Output levels, VDDO = 1.8 V
VOL LOW-level output voltage OGND - 0.2VDDO V
VOH HIGH-level output voltage 0.8VDDO -V
DDO V
Digital outputs, LVDS mode: pins D11P to D0P, D11M to D0M, DAVP and DAVM
Output levels, VDDO = 3 V only, RL=100
VO(offset) output offset voltage output buffer current set to
3.5 mA
-1.2-V
VO(dif) differential output voltage output buffer current set to
3.5 mA
-350-mV
COoutput capacitance - 3 - pF
Analog inputs: pins INP and INM
IIinput current 5- +5A
Ri(dif) differential input resistance - 19.8 - k
Ci(dif) differential input capacitance - 2.8 - pF
VI(cm) common-mode input voltage VINP =V
INM 1.1 1.5 2.5 V
Biinput bandwidth - 650 - MHz
VI(dif) differential input voltage peak-to-peak 1 - 2 V
Common mode output voltage: pin VCM
VO(cm) common-mode output voltage - VDDA /2 - V
IO(cm) common-mode output current - 4 - mA
I/O reference voltage: pin VREF
VVREF voltage on pin VREF output 0.5 - 1 V
input 0.5 - 1 V
Accuracy
INL integral non-linearity - 0.25 - LSB
DNL differential non-linearity guaranteed no missing codes 0.25 0.12 +0.25 LSB
Eoffset offset error - 2- mV
EGgain error full-scale 0.5 %
Supply
PSRR power supply rejection ratio 200 mV (p-p) on VDDA; fi=DC - 54 - dB
Table 6. Static characteristics[1] …continued
Symbol Parameter Conditions Min Typ Max Unit
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ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 8 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
10. Dynamic characteristics
10.1 Dynamic characteristics
Table 7. Dynamic characteristics[1]
Symbol Parameter Conditions ADC1210S065 ADC1210S080 ADC1210S105 ADC1210S125 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Analog signal processing
2H second harmonic
level
fi= 3 MHz - 87 - - 87 - - 86 - - 88 - dBc
fi=30MHz - 86 - - 86 - - 86 - - 87 - dBc
fi=70MHz - 85 - - 85 - - 84 - - 85 - dBc
fi= 170 MHz - 82 - - 82 - - 81 - - 83 - dBc
3H third harmonic
level
fi= 3 MHz - 86 - - 86 - - 85 - - 87 - dBc
fi=30MHz - 85 - - 85 - - 85 - - 86 - dBc
fi=70MHz - 84 - - 84 - - 83 - - 84 - dBc
fi= 170 MHz - 81 - - 81 - - 80 - - 82 - dBc
THD total harmonic
distortion
fi= 3 MHz - 83 - - 83 - - 82 - - 84 - dBc
fi=30MHz - 82 - - 82 - - 82 - - 83 - dBc
fi=70MHz - 81 - - 81 - - 80 - - 81 - dBc
fi= 170 MHz - 78 - - 78 - - 77 - - 79 - dBc
ENOB effective number
of bits
fi= 3 MHz - 11.3 - - 11.3 - - 11.3 - - 11.3 - bits
fi= 30 MHz - 11.3 - - 11.3 - - 11.3 - - 11.2 - bits
fi= 70 MHz - 11.2 - - 11.2 - - 11.2 - - 11.2 - bits
fi= 170 MHz - 11.1 - - 11.1 - - 11.1 - - 11.1 - bits
SNR signal-to-noise
ratio
fi= 3 MHz - 70.0 - - 69.9 - - 69.8 - - 69.6 - dBFS
fi= 30 MHz - 69.5 - - 69.5 - - 69.5 - - 69.4 - dBFS
fi= 70 MHz - 69.2 - - 69.2 - - 69.1 - - 69.0 - dBFS
fi= 170 MHz - 68.8 - - 68.8 - - 68.7 - - 68.6 - dBFS
SFDR spurious-free
dynamic range
fi= 3 MHz - 86 - - 86 - - 85 - - 87 - dBc
fi=30MHz - 85 - - 85 - - 85 - - 86 - dBc
fi=70MHz - 84 - - 84 - - 83 - - 84 - dBc
fi= 170 MHz - 81 - - 81 - - 80 - - 82 - dBc
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 9 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
[1] Typical values measured at VDDA =3V, V
DDO =1.8V, T
amb =25C and CL= 5 pF; minimum and maximum values are across the full temperature range Tamb =40 C to +85 C
at VDDA =3V, V
DDO = 1.8 V; VINP VINM =1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified.
10.2 Clock and digital output timing
IMD Intermodulation
distortion
fi= 3 MHz - 89 - - 89 - - 88 - - 89 - dBc
fi=30MHz - 88 - - 88 - - 88 - - 88 - dBc
fi=70MHz - 87 - - 87 - - 86 - - 86 - dBc
fi= 170 MHz - 84 - - 85 - - 83 - - 84 - dBc
Table 7. Dynamic characteristics[1] …continued
Symbol Parameter Conditions ADC1210S065 ADC1210S080 ADC1210S105 ADC1210S125 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Table 8. Clock input and digital output timing characteristics[1]
Symbol Parameter Conditions ADC1210S065 ADC1210S080 ADC1210S105 ADC1210S125 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Clock timing input: pins CLKP and CLKM
fclk clock
frequency
40 - 65 60 - 80 75 - 105 100 - 125 MHz
tlat(data) data latency
time
-13.5- -13.5- -13.5- -13.5-clock
cycles
clk clock duty
cycle
DCS_EN=logic1 305070305070305070305070%
DCS_EN=logic0 455055455055455055455055%
td(s) sampling
delay time
- 0.8 - - 0.8 - - 0.8 - - 0.8 - ns
twake wake-up time -76- -76- -76- -76-s
CMOS mode timing output: pins D11 to D0 and DAV
tPD propagation
delay
DATA 13.6 14.9 16.4 11.9 12.9 14.4 8.0 10.8 12.4 8.2 9.7 11.3 ns
DAV - 4.2 - - 3.6 - - 3.3 - - 3.4 - ns
tsu set-up time - 12.5 - - 9.8 - - 6.8 - - 5.6 - ns
thhold time - 3.4 - - 3.3 - - 3.1 - - 2.8 - ns
trrise time DATA [2] 0.39 - 2.4 0.39 - 2.4 0.39 - 2.4 0.39 - 2.4 ns
DAV 0.26 - 2.40.26 - 2.40.26 - 2.40.26 - 2.4ns
tffall time DATA [2] 0.19 - 2.4 0.19 - 2.4 0.19 - 2.4 0.19 - 2.4 ns
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 10 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
[1] Typical values measured at VDDA =3V, V
DDO =1.8V, T
amb =25C and CL= 5 pF; minimum and maximum values are across the full temperature range Tamb =40 C to +85 C
at VDDA =3V, V
DDO = 1.8 V; VINP VINM =1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified.
[2] Measured between 20 % to 80 % of VDDO.
[3] Rise time measured from 50 mV to +50 mV; fall time measured from +50 mV to 50 mV.
LVDS DDR mode timing output: pins D10_D11_P to D0_D1_P, D10_D11_M to D0_D1_M, DAVP and DAVM
tPD propagation
delay
DATA 3.3 5.1 7.6 2.9 4.6 7.1 2.5 4.2 6.8 2.2 4.0 6.6 ns
DAV - 2.8 - - 2.5 - - 2.3 - - 2.2 - ns
tsu set-up time - 5.4 - - 4.1 - - 2.6 - - 1.9 - ns
thhold time - 2.2 - - 2.0 - - 1.8 - - 1.7 - ns
trrise time DATA [3] 0.5 - 5 0.5 - 5 0.5 - 5 0.5 - 5 ns
DAV 0.18 - 2.40.18 - 2.40.18 - 2.40.18 - 2.4ns
tffall time DATA [3] 0.15 - 1.6 0.15 - 1.6 0.15 - 1.6 0.15 - 1.6 ns
Table 8. Clock input and digital output timing characteristics[1] …continued
Symbol Parameter Conditions ADC1210S065 ADC1210S080 ADC1210S105 ADC1210S125 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 11 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
Fig 4. CMOS mode and clock timing
Fig 5. LDVS DDR mode and clock timing
(N − 12)
td(s)
tclk
NN + 1
N + 2
tclk
tsu
tPD
thtPD
CLKP
CLKM
DATA
DAV
005aaa060
(N − 11)(N − 13)(N − 14)
005aaa061
(N − 14)
td(s)
tclk
NN + 1
N + 2
CLKP
CLKM
DAVP
DAVM
tsu thth
tsu
tPD
tPD
Dx_Dx + 1_P
Dx_Dx + 1_M
DxDx + 1 Dx + 1 Dx + 1 Dx + 1 Dx + 1
DxDxDx
Dx
(N − 11)(N − 12)(N − 13)
tclk
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 12 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
10.3 SPI timings
[1] Typical values measured at VDDA =3V, V
DDO =1.8V, T
amb =25C and CL= 5 pF; minimum and maximum
values are across the full temperature range Tamb =40 C to +85 C at VDDA =3V, V
DDO =1.8V.
Table 9. SPI timings characteristics[1]
Symbol Parameter Conditions Min Typ Max Unit
tw(SCLK) SCLK pulse width - 40 - ns
tw(SCLKH) SCLK HIGH pulse width - 16 - ns
tw(SCLKL) SCLK LOW pulse width - 16 - ns
tsu set-up time data to SCLK HIGH - 5 - ns
CS to SCLK HIGH - 5 - ns
thhold time data to SCLK HIGH - 2 - ns
CS to SCLK HIGH - 2 - ns
fclk(max) maximum clock frequency - 25 - MHz
Fig 6. SPI timing
t
su
SDIO
SCLK
R/W W1 W0 A12 A11 D2 D1 D0
t
su
t
h
t
h
t
w(SCLK)
005aaa065
CS
t
w(SCLKL)
t
w(SCLKH)
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 13 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
10.4 Typical characteristics
Fig 7. Capacitance as a function of frequency Fig 8. Resistance as a function of frequency
T=25C; VDD =3V; f
i= 170 MHz; fs= 125 Msps
(1) DCS on
(2) DCS off
T=25C; VDD =3V; f
i= 170 MHz; fs= 125 Msps
(1) DCS on
(2) DCS off
Fig 9. SFDR as a function of duty cycle () Fig 10. SNR as a function of duty cycle ()
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 14 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
(1) Tamb =40 C/typical supply voltages
(2) Tamb =+25C/typical supply voltages
(3) Tamb =+90C/typical supply voltages
(1) Tamb =40 C/typical supply voltages
(2) Tamb =+25C/typical supply voltages
(3) Tamb =+90C/typical supply voltages
Fig 11. SFDR as a function of duty cycle () Fig 12. SNR as a function of duty cycle ()
Fig 13. SFDR as a function of common-mode input
voltage (VI(cm))
Fig 14. SNR as a function of common-mode input
voltage (VI(cm))
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 15 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
11. Application information
11.1 Device control
The ADC1210S can be controlled via SPI or directly via the I/O pins (Pin control mode).
11.1.1 SPI and Pin control modes
The device enters Pin control mode at power-up, and remains in this mode as long as pin
CS is held HIGH. In Pin control mode, the SPI pins SDIO, CS and SCLK are used as
static control pins.
SPI control mode is enabled by forcing pin CS LOW. Once SPI control mode has been
enabled, the device remains in this mode. The transition from Pin control mode to SPI
control mode is illustrated in Figure 15.
When the device enters SPI control mode, the output data standard and data format are
determined by the level on pin SDIO at the instant a transition is triggered by a falling
edge on pin CS.
11.1.2 Operating mode selection
The active ADC1210S operating mode (Power-up, Power-down or Sleep) can be selected
via the SPI interface (see Table 20) or by using pins PWD and OE in Pin control mode, as
described in Table 10.
11.1.3 Selecting the output data standard
The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface
(see Table 23) or by using pin ODS in Pin control mode. LVDS DDR is selected when
ODS is HIGH, otherwise CMOS is selected.
Fig 15. Control mode selection
R/W
SPI control mode
Pin control mode
Data format
offset binary
Data format
two's complement
LVDS DDR
SDIO/ODS
SCLK/DFS
W1 W0 A12
005aaa039
CMOS
CS
Table 10. Operating mode selection via pin PWD and OE
Pin PWD Pin OE Operating mode Output high-Z
LOW LOW Power-up no
LOW HIGH Power-up yes
HIGH LOW Sleep yes
HIGH HIGH Power-down yes
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 16 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
11.1.4 Selecting the output data format
The output data format can be selected via the SPI interface (offset binary, two’s
complement or gray code; see Table 23) or by using pin DFS in Pin control mode (offset
binary or two’s complement). Offset binary is selected when DFS is LOW. When DFS is
HIGH, two’s complement is selected.
11.2 Analog inputs
11.2.1 Input stage
The analog input of the ADC1210S supports a differential or a single-ended input drive.
Optimal performance is achieved using differential inputs with the common-mode input
voltage (VI(cm)) on pins INP and INM set to 0.5VDDA.
The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see Section 11.3 and Table 22).
The equivalent circuit of the sample and hold input stage, including Electrostatic
Discharge (ESD) protection and circuit and package parasitics, is shown in Figure 16.
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
11.2.2 Anti-kickback circuitry
Anti-kickback circuitry (R-C filter in Figure 17) is needed to counteract the effects of a
charge injection generated by the sampling capacitance.
The RC filter is also used to filter noise from the signal before it reaches the sampling
stage. The value of the capacitor should be chosen to maximize noise attenuation without
degrading the settling time excessively.
Fig 16. Input sampling circuit
005aaa043
INP
Package ESD Parasitics
Switch
Ron = 15 Ω 4 pF
4 pF
Sampling
capacitor
Sampling
capacitor
Switch
Ron = 15 Ω
INM
8
7
Internal
clock
Internal
clock
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 17 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
The component values are determined by the input frequency and should be selected so
as not to affect the input bandwidth.
11.2.3 Transformer
The configuration of the transformer circuit is determined by the input frequency. The
configuration shown in Figure 18 would be suitable for a baseband application.
The configuration shown in Figure 19 is recommended for high frequency applications. In
both cases, the choice of transformer is a compromise between cost and performance.
Fig 17. Anti-kickback circuit
Table 11. RC coupling versus input frequency, typical values
Input frequency R C
3 MHz 25 12 pF
70 MHz 12 8 pF
170 MHz 12 8 pF
005aaa073
R
R
C
INP
INM
Fig 18. Single transformer configuration suitable for baseband applications
005aaa044
100 nF100 nF
100 nF 100 nF
25 Ω
25 Ω
25 Ω
25 Ω
12 pF
INP
INM
VCM
100 nF
analog
input
ADT1-1WT
100 nF
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 18 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
11.3 System reference and power management
11.3.1 Internal/external references
The ADC1210S has a stable and accurate built-in internal reference voltage to adjust the
ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF and
SENSE (programmable in 1 dB steps between 0 dB and 6 dB via control bits
INTREF[2:0] when bit INTREF_EN = logic 1; see Table 22). See Figure 21 to Figure 24.
The equivalent reference circuit is shown in Figure 20. An external reference is also
possible by providing a voltage on pin VREF as described in Figure 23.
Fig 19. Dual transformer configuration suitable for a high intermediate frequency
application
005aaa045
100 nF100 nF
100 nF
100 nF
12 Ω
12 Ω
8.2 pF
INP
INM
VCM
50 Ω
50 Ω
50 Ω
50 Ω
ADT1-1WTADT1-1WT
analog
input
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 19 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
If bit INTREF_EN is set to logic 0, the reference voltage is determined either internally or
externally as detailed in Table 12.
[1] The voltage on pin VREF is doubled internally to generate the internal reference voltage.
Figure 21 to Figure 24 illustrate how to connect the SENSE and VREF pins to select the
required reference voltage source.
Fig 20. Reference equivalent schematic
Table 12. Reference selection
Selection SPI bit
INTREF_EN
SENSE pin VREF pin Full-scale (p-p)
internal
(Figure 21)
0 AGND 330 pF capacitor to AGND 2 V
internal
(Figure 22)
0 pin VREF connected to pin SENSE and via
a 330 pF capacitor to AGND
1 V
external
(Figure 23)
0V
DDA external voltage between
0.5 V and 1 V[1]
1 V to 2 V
internal via SPI
(Figure 24)
1 pin VREF connected to pin SENSE and via
330 pF capacitor to AGND
1 V to 2 V
EXT_ref
EXT_ref
005aaa164
REFT
REFB
SENSE
VREF
SELECTION
LOGIC
BANDGAP
REFERENCE
ADC CORE
BUFFER
REFERENCE
AMP
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 20 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
11.3.2 Programmable full-scale
The full-scale is programmable between 1 V (peak-to-peak) to 2 V (peak-to-peak)
(see Table 13).
Fig 21. Internal reference, 2 V (p-p) full-scale Fig 22. Internal reference, 1 V (p-p) full-scale
Fig 23. External reference, 1 V (p-p) to 2 V (p-p)
full-scale
Fig 24. Internal reference via SPI, 1 V (p-p) to 2 V (p-p)
full-scale
330 pF
VREF
SENSE
005aaa116
REFERENCE
EQUIVALENT
SCHEMATIC
330
pF
005aaa117
VREF
SENSE
REFERENCE
EQUIVALENT
SCHEMATIC
0.1 μF
VDDA
V
005aaa119
VREF
SENSE
REFERENCE
EQUIVALENT
SCHEMATIC
REFERENCE
EQUIVALENT
SCHEMATIC
330 pF
005aaa118
VREF
SENSE
Table 13. Reference SPI gain control
INTREF[2:0] Gain (dB) Full-scale (V (p-p))
000 0 2
001 11.78
010 21.59
011 31.42
100 41.26
101 51.12
110 61
111 reserved x
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 21 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
11.3.3 Common-mode output voltage (VO(cm))
A 0.1 F filter capacitor should be connected between pin VCM and ground to ensure a
low-noise common-mode output voltage. When AC-coupled, pin VCM can then be used to
set the common-mode reference for the analog inputs, for instance via a transformer
middle point.
11.3.4 Biasing
The common-mode input voltage (VI(cm)) on pins INP and INM should be set externally to
0.5VDDA for optimal performance and should always be between 0.9 V and 2 V.
11.4 Clock input
11.4.1 Drive modes
The ADC1210S can be driven differentially (LVPECL). It can also be driven by a
single-ended Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) signal
connected to pin CLKP (pin CLKM should be connected to ground via a capacitor) or pin
CLKM (pin CLKP should be connected to ground via a capacitor).
Fig 25. Equivalent schematic of the common-mode reference circuit
1.5 V
VCM
0.1 μF
package ESD parasitics
005aaa051
COMMON-MODE
REFERENCE
ADC core
a. Rising edge LVCMOS b. Falling edge LVCMOS
Fig 26. LVCMOS single-ended clock input
LVCMOS
clock input CLKP
CLKM
005aaa174
005aaa053
LVCMOS
clock input
CLKP
CLKM
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 22 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
11.4.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in Figure 28. The common-mode
voltage of the differential input stage is set via internal 5 k resistors.
a. Sine clock input b. Sine clock input (with transformer)
c. LVPECL clock input
Fig 27. Differential clock input
Sine
clock input
CLKP
CLKM
005aaa173
Sine
clock input CLKP
CLKM
005aaa054
LVPECL
clock input
005aaa172
CLKP
CLKM
Vcm(clk) = common-mode voltage of the differential input stage.
Fig 28. Equivalent input circuit
CLKP
CLKM
005aaa056
Package ESD Parasitics
5 kΩ5 kΩ
V
cm(clk)
SE_SEL SE_SEL
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 23 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
Single-ended or differential clock inputs can be selected via the SPI interface (see
Table 21). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control
bit SE_SEL.
If single-ended is implemented without setting bit SE_SEL to the appropriate value, the
unused pin should be connected to ground via a capacitor.
11.4.3 Duty cycle stabilizer
The duty cycle stabilizer can improve the overall performance of the ADC by
compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is
active (bit DCS_EN = logic 1; see Table 21), the circuit can handle signals with duty
cycles of between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled
(DCS_EN = logic 0), the input clock signal should have a duty cycle of between 45 % and
55 %.
11.4.4 Clock input divider
The ADC1210S contains an input clock divider that divides the incoming clock by a factor
of 2 (when bit CLKDIV = logic 1; see Table 21). This feature allows the user to deliver a
higher clock frequency with better jitter performance, leading to a better SNR result once
acquisition has been performed.
11.5 Digital outputs
11.5.1 Digital output buffers: CMOS mode
The digital output buffers can be configured as CMOS by setting bit LVDS_CMOS to
logic 0 (see Table 23).
Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS
digital output buffer is shown in Figure 29. The buffer is powered by a separate power
supply, pins OGND and VDDO, to ensure 1.8 V to 3.3 V compatibility and is isolated from
the ADC core. Each buffer can be loaded by a maximum of 10 pF.
Fig 29. CMOS digital output buffer
VDDO
ESD PackageParasitics
OGND
Dx
005aaa057
50 Ω
LOGIC
DRIVER
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 24 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
The output resistance is 50 and is the combination of an internal resistor and the
equivalent output resistance of the buffer. There is no need for an external damping
resistor. The drive strength of both data and DAV buffers can be programmed via the SPI
in order to adjust the rise and fall times of the output digital signals (see Table 30).
11.5.2 Digital output buffers: LVDS DDR mode
The digital output buffers can be configured as LVDS DDR by setting bit LVDS_CMOS to
logic 1 (see Table 23).
Each output should be terminated externally with a 100 resistor (typical) at the receiver
side (Figure 30) or internally via SPI control bits LVDS_INT_TER[2:0] (see Figure 31 and
Table 32).
The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via
the SPI (bits DAVI[1:0] and DATAI[1:0]; see Table 31) in order to adjust the output logic
voltage levels.
Fig 30. LVDS DDR digital output buffer - externally terminated
Fig 31. LVDS DDR digital output buffer - internally terminated
VDDO
3.5 mA
typ
DxP/Dx + 1P
DxM/Dx + 1M
OGND
100 Ω
−
005aaa058
+ −
+
RECEIVER
VDDO
OGND
005aaa059
D
x
P/D
x
+ 1
P
D
x
M/D
x + 1
M
100 Ω
3.5 mA
typ
+
−
+ −
RECEIVER
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 25 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
11.5.3 DAta Valid (DAV) output clock
A data valid output clock signal (DAV) can be used to capture the data delivered by the
ADC1210S. Detailed timing diagrams for CMOS and LVDS DDR modes are shown in
Figure 4 and Figure 5 respectively.
11.5.4 Out-of-Range (OTR)
An out-of-range signal is provided on pin OTR. The latency of OTR is fourteen clock
cycles. The OTR response can be speeded up by enabling Fast OTR
(bit FASTOTR = logic 1; see Table 29). In this mode, the latency of OTR is reduced to only
four clock cycles. The Fast OTR detection threshold (below full-scale) can be
programmed via bits FASTOTR_DET[2:0].
11.5.5 Digital offset
By default, the ADC1210S delivers output code that corresponds to the analog input.
However it is possible to add a digital offset to the output code via the SPI (bits
DIG_OFFSET[5:0]; see Table 25).
11.5.6 Test patterns
For test purposes, the ADC1210S can be configured to transmit one of a number of
predefined test patterns (via bits TESTPAT_SEL[2:0]; see Table 26). A custom test pattern
can be defined by the user (TESTPAT_USER[11:0]; see Table 27 and Table 28) and is
selected when TESTPAT_SEL[2:0] = 101. The selected test pattern is transmitted
regardless of the analog input.
Table 14. LVDS DDR output register 2
LVDS_INT_TER[2:0] Resistor value ()
000 no internal termination
001 300
010 180
011 110
100 150
101 100
110 81
111 60
Table 15. Fast OTR register
FASTOTR_DET[2:0] Detection level (dB)
000 20.56
001 16.12
010 11.02
011 7.82
100 5.49
101 3.66
110 2.14
111 0.86
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 26 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
11.5.7 Output codes versus input voltage
11.6 Serial peripheral interface
11.6.1 Register description
The ADC1210S serial interface is a synchronous serial communications port that allows
easy interfacing with many commonly-used microprocessors. It provides access to the
registers that control the operation of the chip.
This interface is configured as a 3-wire type (SDIO as bidirectional pin).
Pin SCLK is the serial clock input and CS is the chip select pin.
Each read/write operation is initiated by a LOW level on pin CS. A minimum of three bytes
is transmitted (two instruction bytes and at least one data byte). The number of data bytes
is determined by the value of bits W1 and W2 (see Table 18).
[1] Bit R/W indicates whether it is a read (logic 1) or a write (logic 0) operation.
[2] Bits W1 and W0 indicate the number of bytes to be transferred after the instruction byte (see Table 18).
Table 16. Output codes
VINP VINM Offset binary Two’s complement OTR pin
< 1 0000 0000 0000 1000 0000 0000 1
1.0000000 0000 0000 0000 1000 0000 0000 0
0.9995117 0000 0000 0001 1000 0000 0001 0
0.9990234 0000 0000 0010 1000 0000 0010 0
0.9985352 0000 0000 0011 1000 0000 0011 0
0.9980469 0000 0000 0100 1000 0000 0100 0
.... .... .... 0
0.0009766 0111 1111 1110 1111 1111 1110 0
0.0004883 0111 1111 1111 1111 1111 1111 0
0.0000000 1000 0000 0000 0000 0000 0000 0
+0.0004883 1000 0000 0001 0000 0000 0001 0
+0.0009766 1000 0000 0010 0000 0000 0010 0
.... .... .... 0
+0.9980469 1111 1111 1011 0111 1111 1011 0
+0.9985352 1111 1111 1100 0111 1111 1100 0
+0.9990234 1111 1111 1101 0111 1111 1101 0
+0.9995117 1111 1111 1110 0111 1111 1110 0
+1.0000000 1111 1111 1111 0111 1111 1111 0
> +1 1111 1111 1111 0111 1111 1111 1
Table 17. Instruction bytes for the SPI
MSB LSB
Bit 76543210
Description R/W[1] W1[2] W0[2] A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 27 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is increased to access subsequent addresses.
The steps involved in a data transfer are as follows:
1. A falling edge on CS in combination with a rising edge on SCLK determine the start of
communications.
2. The first phase is the transfer of the 2-byte instruction.
3. The second phase is the transfer of the data which can vary in length but is always a
multiple of 8 bits. The MSB is always sent first (for instruction and data bytes).
4. A rising edge on CS indicates the end of data transmission.
11.6.2 Default modes at start-up
During circuit initialization it does not matter which output data standard has been
selected. At power-up, the device enters Pin control mode.
A falling edge on CS triggers a transition to SPI control mode. When the ADC1210S
enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by
the level on pin SDIO (see Figure 33). Once in SPI control mode, the output data standard
can be changed via bit LVDS_CMOS in Tab le 2 3 .
When the ADC1210S enters SPI control mode, the output data format (two’s complement
or offset binary) is determined by the level on pin SCLK (gray code can only be selected
via the SPI). Once in SPI control mode, the output data format can be changed via bit
DATA_FORMAT[1:0] in Table 23.
Table 18. Number of data bytes to be transferred after the instruction bytes
W1 W0 Number of bytes transmitted
001 byte
012 bytes
103 bytes
1 1 4 bytes or more
Fig 32. SPI mode timing
SCLK
SDIO R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D3 D2 D1 D0D0 D7 D6 D5 D4
Instruction bytes Register N (data) Register N + 1 (data) 005aaa062
CS
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 28 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
Fig 33. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR
Fig 34. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS
CS
SDIO
(CMOS LVDS DDR)
SCLK
(Data format)
Offset binary, LVDS DDR
default mode at start-up 005aaa063
SDIO
(CMOS LVDS DDR)
SCLK
(Data format)
two's complement, CMOS
default mode at start-up
005aaa064
CS
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 29 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
11.6.3 Register allocation map
Table 19. Register allocation map
Addr
Hex
Register name R/W Bit definition Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bin
0005 Reset and
operating mode
R/W SW_RST RESERVED[2:0] - - OP_MODE[1:0] 0000
0000
0006 Clock R/W - - - SE_SEL DIFF_SE - CLKDIV DCS_EN 0000
0001
0008 Internal reference R/W - - - - INTREF_EN INTREF[2:0] 0000
0000
0011 Output data
standard
R/W - - - LVDS_
CMOS
OUTBUF OUTBUS_SWAP DATA_FORMAT[1:0] 0000
0000
0012 Output clock R/W - - - - DAVINV DAVPHASE[2:0] 0000
1110
0013 Offset R/W - - DIG_OFFSET[5:0] 0000
0000
0014 Test pattern 1 R/W - - - - - TESTPAT_SEL[2:0] 0000
0000
0015 Test pattern 2 R/W TESTPAT_USER[11:4] 0000
0000
0016 Test pattern 3 R/W TESTPAT_USER[3:0] - - - - 0000
0000
0017 Fast OTR R/W - - - - FASTOTR FASTOTR_DET[2:0] 0000
0000
0020 CMOS output R/W - - - - DAV_DRV[1:0] DATA_DRV[1:0] 0000
1110
0021 LVDS DDR O/P 1 R/W - - DAVI_x2_EN DAVI[1:0] DATAI_x2_EN DATAI[1:0] 0000
0000
0022 LVDS DDR O/P 2 R/W - - - - BI_BYTE_WISE LVDS_INT_TER[2:0] 0000
0000
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 30 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
Table 20. Reset and operating mode control register (address 0005h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 SW_RST R/W reset digital section
0no reset
1 performs a reset of the SPI registers
6 to 4 RESERVED[2:0] 000 reserved
3 to 2 - 00 not used
1 to 0 OP_MODE[1:0] R/W operating mode
00 normal (power-up)
01 power-down
10 sleep
11 normal (power-up)
Table 21. Clock control register (address 0006h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 5 - 000 not used
4 SE_SEL R/W single-ended clock input pin select
0CLKM
1CLKP
3 DIFF_SE R/W differential/single-ended clock input select
0 fully differential
1 single-ended
2 - 0 not used
1 CLKDIV R/W clock input divide by 2
0disabled
1 enabled
0 DCS_EN R/W duty cycle stabilizer
0 disabled
1 enabled
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 31 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
Table 22. Internal reference control register (address 0008h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - 0000 not used
3 INTREF_EN R/W programmable internal reference enable
0disable
1 active
2 to 0 INTREF[2:0] R/W programmable internal reference
000 FS = 2 V
001 FS = 1.78 V
010 FS = 1.59 V
011 FS = 1.42 V
100 FS = 1.26 V
101 FS = 1.12 V
110 FS = 1 V
111 reserved
Table 23. Output data standard control register (address 0011h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 5 - 000 not used
4 LVDS_CMOS R/W output data standard: LVDS DDR or CMOS
0CMOS
1 LVDS DDR
3 OUTBUF R/W output buffers enable
0output enabled
1 output disabled (high-Z)
2 OUTBUS_SWAP R/W output bus swapping
0 no swapping
1 output bus is swapping (MSB becomes LSB and vice
versa)
1 to 0 DATA_FORMAT[1:0] R/W output data format
00 offset binary
01 two’s complement
10 gray code
11 offset binary
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 32 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
Table 24. Output clock register (address 0012h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - 0000 not used
3 DAVINV R/W output clock data valid (DAV) polarity
0normal
1inverted
2 to 0 DAVPHASE[2:0] R/W DAV phase select
000 output clock shifted (ahead) by 6/16 tclk
001 output clock shifted (ahead) by 5/16 tclk
010 output clock shifted (ahead) by 4/16 tclk
011 output clock shifted (ahead) by 3/16 tclk
100 output clock shifted (ahead) by 2/16 tclk
101 output clock shifted (ahead) by 1/16 tclk
110 default value as defined in timing section
111 output clock shifted (delayed) by 1/16 tclk
Table 25. Offset register (address 0013h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 6 - 00 not used
5 to 0 DIG_OFFSET[5:0] R/W digital offset adjustment
011111 +31 LSB
... ...
000000 0
... ...
100000 32 LSB
Table 26. Test pattern register 1 (address 0014h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 3 - 00000 not used
2 to 0 TESTPAT_SEL[2:0] R/W digital test pattern select
000 off
001 mid scale
010 FS
011 +FS
100 toggle ‘1111..1111’/’0000..0000’
101 custom test pattern
110 ‘1010..1010.’
111 ‘010..1010’
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Product data sheet Rev. 03 — 2 July 2012 33 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
Table 27. Test pattern register 2 (address 0015h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 0 TESTPAT_USER[11:4] R/W 00000000 custom digital test pattern (bits 11 to 4)
Table 28. Test pattern register 3 (address 0016h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 TESTPAT_USER[3:0] R/W 0000 custom digital test pattern (bits 3 to 0)
3 to 0 - 0000 not used
Table 29. Fast OTR register (address 0017h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - 0000 not used
3 FASTOTR R/W fast OuT-of-Range (OTR) detection
0 disabled
1 enabled
2 to 0 FASTOTR_DET[2:0] R/W set fast OTR detect level
000 20.56 dB
001 16.12 dB
010 11.02 dB
011 7.82 dB
100 5.49 dB
101 3.66 dB
110 2.14 dB
111 0.86 dB
Table 30. CMOS output register (address 0020h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - 0000 not used
3 to 2 DAV_DRV[1:0] R/W drive strength for DAV CMOS output buffer
00 low
01 medium
10 high
11 very high
1 to 0 DATA_DRV[1:0] R/W drive strength for DATA CMOS output buffer
00 low
01 medium
10 high
11 very high
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 34 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
Table 31. LVDS DDR output register 1 (address 0021h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 6 - 00 not used
5 DAVI_x2_EN R/W double LVDS current for DAV LVDS buffer
0 disabled
1 enabled
4 to 3 DAVI[1:0] R/W LVDS current for DAV LVDS buffer
00 3.5 mA
01 4.5 mA
10 1.25 mA
11 2.5 mA
2 DATAI_x2_EN R/W double LVDS current for DATA LVDS buffer
0 disabled
1 enabled
1 to 0 DATAI[1:0] R/W LVDS current for DATA LVDS buffer
00 3.5 mA
01 4.5 mA
10 1.25 mA
11 2.5 mA
Table 32. LVDS DDR output register 2 (address 0022h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - 0000 not used
3 BIT_BYTE_WISE R/W DDR mode for LVDS output
0 bit wise (even data bits output on DAV rising edge/odd
data bits output on DAV falling edge)
1 byte wise (MSB data bits output on DAV rising edge/LSB data
bits output on DAV falling edge)
2 to 0 LVDS_INT_TER[2:0] R/W internal termination for LVDS buffer (DAV and DATA)
000 no internal termination
001 300
010 180
011 110
100 150
101 100
110 81
111 60
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 35 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
12. Package outline
Fig 35. Package outline SOT618-1 (HVQFN40)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 6.1
5.9
Dh
4.25
3.95
y1
6.1
5.9 4.25
3.95
e1
4.5
e2
4.5
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT618-1 MO-220- - - - - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT618-1
HVQFN40: plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6 x 6 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
11 20
40 31
30
21
10
1
X
D
E
C
BA
e2
01-08-08
02-10-22
terminal 1
index area
1/2 e
1/2 e
AC
CB
vM
wM
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1) E(1)
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 36 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
13. Revision history
14. Contact information
For more information or sales office addresses, please visit: http://www.idt.com
Table 33. Revision history
Document ID Release date Data sheet status Change
notice
Supersedes
ADC1210S_SER v.3 20120702 Product data sheet - ADC1210S_SER_2
ADC1210S_SER v.2 20101223 Product data sheet - ADC1210S_SER_1
Modifications: •Data sheet status changed from Preliminary to Product.
•Text and drawings updated throughout entire data sheet.
•SOT618-6 changed to SOT618-1. See Table 1 “Ordering information” and Figure 35
“Package outline SOT618-1 (HVQFN40)”.
•Section 10.4 “Typical characteristics” added to the data sheet.
ADC1210S_SER_1 20100409 Preliminary data sheet - -
ADC1210S_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 37 of 37
Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
15. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Thermal characteristics . . . . . . . . . . . . . . . . . . 5
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
10.1 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
10.2 Clock and digital output timing . . . . . . . . . . . . . 9
10.3 SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
10.4 Typical characteristics . . . . . . . . . . . . . . . . . . 13
11 Application information. . . . . . . . . . . . . . . . . . 15
11.1 Device control. . . . . . . . . . . . . . . . . . . . . . . . . 15
11.1.1 SPI and Pin control modes . . . . . . . . . . . . . . . 15
11.1.2 Operating mode selection. . . . . . . . . . . . . . . . 15
11.1.3 Selecting the output data standard . . . . . . . . . 15
11.1.4 Selecting the output data format. . . . . . . . . . . 16
11.2 Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 16
11.2.1 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
11.2.2 Anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 16
11.2.3 Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 17
11.3 System reference and power management . . 18
11.3.1 Internal/external references . . . . . . . . . . . . . . 18
11.3.2 Programmable full-scale . . . . . . . . . . . . . . . . 20
11.3.3 Common-mode output voltage (VO(cm)) . . . . . 21
11.3.4 Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
11.4 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
11.4.1 Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . 21
11.4.2 Equivalent input circuit . . . . . . . . . . . . . . . . . . 22
11.4.3 Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 23
11.4.4 Clock input divider . . . . . . . . . . . . . . . . . . . . . 23
11.5 Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . 23
11.5.1 Digital output buffers: CMOS mode . . . . . . . . 23
11.5.2 Digital output buffers: LVDS DDR mode . . . . 24
11.5.3 DAta Valid (DAV) output clock . . . . . . . . . . . . 25
11.5.4 Out-of-Range (OTR) . . . . . . . . . . . . . . . . . . . 25
11.5.5 Digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . 25
11.5.6 Test patterns . . . . . . . . . . . . . . . . . . . . . . . . . 25
11.5.7 Output codes versus input voltage. . . . . . . . . 26
11.6 Serial peripheral interface . . . . . . . . . . . . . . . 26
11.6.1 Register description . . . . . . . . . . . . . . . . . . . . 26
11.6.2 Default modes at start-up. . . . . . . . . . . . . . . . 27
11.6.3 Register allocation map . . . . . . . . . . . . . . . . . 29
12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 35
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . 36
14 Contact information . . . . . . . . . . . . . . . . . . . . 36
15 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37