K6T4008V2C, K6T4008U2C Family CMOS SRAM Document Title 512Kx8 bit Low Power and Low Voltage CMOS Static RAM Revision History Revision No. History Draft Data Remark 0.0 Initial Draft December 3, 1998 Preliminary 1.0 Finalize April 28, 1999 Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch office. 1 Revision 1.0 April 1999 K6T4008V2C, K6T4008U2C Family CMOS SRAM 512Kx8 bit Low Power and Low Voltage CMOS Static RAM FEATURES GENERAL DESCRIPTION * Process Technology: TFT * Organization: 512Kx8 * Power Supply Voltage K6T4008V2C Family: 3.0~3.6V K6T4008U2C Family: 2.7~3.3V * Low Data Retention Voltage: 2V(Min) * Three state output and TTL Compatible * Package Type: 48(36)-uBGA-6.10x8.90 The K6T4008V2C and K6T4008U2C families are fabricated by SAMSUNGs advanced CMOS process technology. The families support industrial operating temperature range and have chip scale package type for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family Operating Temperature K6T4008V2C-F Industrial(-40~85C) K6T4008U2C-F Vcc Range Speed 3.0~3.6V 70 1)/85ns 2.7~3.3V 701)/85/100ns Standby (ISB1, Max) Operating (ICC2, Max) PKG Type 20A 30mA 48(36)-uBGA 1. The paramerter is measured with 30pF test load. PIN DESCRIPTION 1 2 3 FUNCTIONAL BLOCK DIAGRAM 4 5 6 Clk gen. A A0 A1 CS2 A3 A6 A8 B I/O5 A2 WE A4 A7 I/O1 C I/O6 D Vss NC A5 Row select I/O2 Precharge circuit. Memory array 1024 rows 512x8 columns Vcc 48(36)-uBGA E Top View (Ball Down) Vcc Vss Data cont I/O1 F I/O7 G I/O8 H A9 A18 A17 OE CS1 A16 A15 I/O4 A10 A11 A12 A13 A14 I/O8 I/O3 I/O Circuit Column select Data cont CS1 Name Function Name CS2 Function WE OE CS1, CS2 Chip Select Inputs I/O1~I/O8 Data Inputs/Outputs WE Write Enable Input Vcc Power OE Output Enable Input Vss Ground NC No Connection A0~A18 Address Inputs Control logic SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 1.0 April 1999 K6T4008V2C, K6T4008U2C Family CMOS SRAM PRODUCT LIST Industrial Temp Products(-40~85C) Part Name Function K6T4008V2C-ZF70 K6T4008V2C-ZF85 48-uBGA, 70ns, 3.3V, LL 48-uBGA, 85ns, 3.3V, LL K6T4008U2C-ZF70 K6T4008U2C-ZF85 K6T4008U2C-ZF10 48-uBGA, 70ns, 3.0V, LL 48-uBGA, 85ns, 3.0V, LL 48-uBGA, 100ns, 3.0V, LL FUNCTIONAL DESCRIPTION CS1 CS2 OE WE I/O Mode Power H X1) X1) X1) High-Z Deselected Standby X1) L X1) X1) High-Z Deselected Standby L H H H High-Z Output Disabled Active L H L H Dout Read Active L Din Write Active L H 1) X 1. X means dont care (Must be in low or high state) ABSOLUTE MAXIMUM RATINGS1) Item Symbol Ratings Unit Remark VIN,VOUT -0.5 to VCC+0.5 V - Voltage on Vcc supply relative to Vss VCC -0.3 to 4.6 V - Power Dissipation PD 1.0 W - TSTG -65 to 150 C - TA -40 to 85 C K6T4008V2C-P, K6T4008U2C-P Voltage on any pin relative to Vss Storage temperature Operating Temperature 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3 Revision 1.0 April 1999 K6T4008V2C, K6T4008U2C Family CMOS SRAM RECOMMENDED DC OPERATING CONDITIONS1) Item Symbol Product Min Typ Max Unit Supply voltage Vcc K6T4008V2C Family K6T4008U2C Family 3.0 2.7 3.3 3.0 3.6 3.3 V Ground Vss All Family 0 0 0 Input high voltage VIH K6T4008V2C, K6T4008U2C Family 2.2 - Vcc+0.3 Input low voltage VIL K6T4008V2C, K6T4008U2C Family -0.33) - 0.6 V V 2) V Note: 1. Industrial Product: TA=-40 to 85C, otherwise specified 2. Overshoot: VCC +2.0V in case of pulse width 30ns 3. Undershoot: -2.0V in case of pulse width 30ns 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f=1MHz, TA=25C) Symbol Test Condition Min Max Unit Input capacitance Item CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 10 pF 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Item Symbol Test Conditions Min Typ Max Unit Input leakage current ILI VIN=Vss to Vcc -1 - 1 A Output leakage current ILO CS1=VIH or CS2=VIL or OE=VIH or WE=VIL VIO=Vss to Vcc -1 - 1 A Operating power supply current ICC IIO=0mA, CS1=VIL, CS2=VIH, WE=VIH, VIN=VIL or VIH - - 4 mA ICC1 Cycle time=1s, 100% duty, IIO=0mA CS10.2V, CS2Vcc-0.2V, VIN0.2V or VINVcc-0.2V - - 4 mA Average operating current ICC2 Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH , VIN=VIH or VIL - - 30 mA Output low voltage VOL IOL=2.1mA - - 0.4 V Output high voltage VOH IOH=-1.0mA 2.2 - - V Standby Current(TTL) ISB CS1=VIH, CS2=VIL, Other inputs = VIL or VIH - - 0.3 mA Standby Current (CMOS) ISB1 CS1Vcc-0.2V, CS2 Vcc-0.2V or CS2 0.2V, Other inputs=0~Vcc - - 20 A 4 Revision 1.0 April 1999 K6T4008V2C, K6T4008U2C Family CMOS SRAM AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Input/Output Reference) Input pulse level : 0.4 to 2.2V Input rising and falling time : 5ns Input and output reference voltage :1.5V Output load(see right) : CL=100pF+1TTL CL1)=30pF+1TTL CL1) 1. Including scope and jig capacitance 1. 70ns products AC CHARACTERISTICS (TA=-40 to 85C, K6T4008V2C Family: 3.0~3.6V, K6T4008U2C Family: 2.7~3.3V) Speed Bins Parameter List Symbol Units 100ns Min Max Min Max Min Max tRC 70 - 85 - 100 - ns Address access time tAA - 70 - 85 - 100 ns Chip select to output tCO1, tCO2 - 70 - 85 - 100 ns tOE - 35 - 40 - 50 ns Chip select to low-Z output tLZ 10 - 10 - 10 - ns tOLZ 5 - 5 - 5 - ns Chip disable to high-Z output tHZ 0 25 0 25 0 30 ns Output disable to high-Z output tOHZ 0 25 0 25 0 30 ns Output hold from address change tOH 10 - 10 - 15 - ns Write cycle time tWC 70 - 85 - 100 - ns Chip select to end of write tCW 60 - 70 - 80 - ns Address set-up time tAS 0 - 0 - 0 - ns Address valid to end of write tAW 60 - 70 - 80 - ns Write pulse width tWP 55 - 55 - 70 - ns Write recovery time tWR 0 - 0 - 0 - ns Write to output high-Z tWHZ 0 25 0 25 0 30 ns Data to write time overlap tDW 30 - 35 - 40 - ns Data hold from write time tDH 0 - 0 - 0 - ns End write to output low-Z tOW 5 - 5 - 5 - ns Output enable to low-Z output Write 85ns Read cycle time Output enable to valid output Read 70ns DATA RETENTION CHARACTERISTICS Item Symbol Test Condition Vcc for data retention VDR CS 1Vcc-0.2V1) Data retention current IDR Vcc=3.0V, CS 1Vcc-0.2V Data retention set-up time tSDR Recovery time tRDR 1) See data retention waveform Min Typ Max Unit 2.0 - 3.6 V A - 0.5 20 0 - - 5 - - ms 1. CS1 Vcc-0.2V, CS2 Vcc-0.2V(CS1 controlled) or CS2 0.2V(CS2 controlled) 5 Revision 1.0 April 1999 K6T4008V2C, K6T4008U2C Family CMOS SRAM TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2 =WE=VIH ) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tOH tAA tCO1 CS1 tHZ(1,2) CS2 tCO2 tOE OE Data out High-Z tOHZ tOLZ tLZ Data Valid NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 Revision 1.0 April 1999 K6T4008V2C, K6T4008U2C Family TIMING WAVEFORM OF WRITE CYCLE(1) CMOS SRAM (WE Controlled) tWC Address tCW(2) tWR(4) CS1 tAW CS2 tCW(2) tWP(1) WE tAS(3) tDW tDH Data Valid Data in tWHZ Data out tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled) tWC Address tCW(2) tAS(3) tWR(4) CS1 tAW CS2 tWP(1) WE tDW Data in Data out tDH Data Valid High-Z High-Z 7 Revision 1.0 April 1999 K6T4008V2C, K6T4008U2C Family TIMING WAVEFORM OF WRITE CYCLE(3) CMOS SRAM (CS2 Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS 1 tAW CS 2 tCW(2) tWP(1) WE tDW Data in Data out tDH Data Valid High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low, CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS1 going low or CS2 going high to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR1 applied in case a write ends as CS1 or WE going high tWR2 applied in case a write ends as CS2 going to low. DATA RETENTION WAVE FORM CS1 controlled VCC tSDR Data Retention Mode tRDR 3.0/2.7V 2.2V VDR CS1VCC - 0.2V CS1 GND CS2 controlled Data Retention Mode VCC 3.0/2.7V CS2 tSDR tRDR VDR CS 20.2V 0.4V GND 8 Revision 1.0 April 1999 K6T4008V2C, K6T4008U2C Family CMOS SRAM PACKAGE DIMENSIONS Units: millimeters 48 BALL MICRO BALL GRID ARRAY- 0.75mm ball pitch Top View Ball #A1 Bottom View B B 6 5 4 3 2 1 C/2 C/2 A B Ball #A1 C C C C1 D E F G H B1 B/2 B/2 SRAM Die Elastomer Side View Detail A 0.25/Typ. Detail A E2 D A Y Min Typ Max A - 0.75 - B 6.00 6.10 6.20 B1 - 3.75 - C 8.80 8.90 9.00 C1 - 5.25 - D 0.30 0.35 0.40 E - 0.93 0.94 E1 - 0.68 - E2 - 0.25 - Y - - 0.08 0.45/Typ. 0.68/Typ. E1 E C Elastomer Die 0.3/Typ. Notes. 1. Bump counts : 48(8row x 6column) 2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. All tolerence are +/-0.050 unless otherwise specified. 4. Typ : Typical 5. Y is coplanarity: 0.08(Max) 9 Revision 1.0 April 1999