This document is a general product descriptio n and is subject to change wit hout noti ce. Hyni x does no t assume an y respon sibilit y for
use of circuits described. No patent licenses are implied.
Rev 0.2 / Dec. 2003 1
HY62KF16403E Series
256Kx16bit full CMOS SRAM
Document Title
256K x 16bit 2.7 ~ 3.6V Super low Power FCMOS Slow SRAM
Revision History
Revision No. History Draft Date Remark
0.0 Initial Draft Dec.26.2001 Preliminary
0.1 Absolute Maximum Ratings
- Vcc changed -0.3V to 4.6V -> -0.3V to 4.0V
DC Electric Characteristics
- ICC changed 4mA -> 3mA
- ICC1 changed 25mA at 55ns -> 20mA at 55ns
- ICC1 changed 20mA at 70ns -> 15mA at 70ns
- ICC1 changed 3mA at 1us -> 2mA at 1us
AC Test Conditions
- Output Load changed 5pF -> 30pF
Data Retention Electric Characteristics
- ICCDR changed 10uA -> 6uA
Marking Information
- Part Name changed HY62KF6403E
-> HY62KF16403E
Nov.14.2002 Final
0.2 Add 44-Pin Padpitch to TSOPII Package Information Dec.26.2003 Final
This document is a general product descriptio n and is subject to change wit hout noti ce. Hyni x does no t assume an y respon sibilit y for
use of circuits described. No patent licenses are implied.
Rev 0.2 / Dec. 2003 2
HY62KF16403E Series
256Kx16bit full CMOS SRAM
DESCRIPTION
The HY62KF16403E is a high speed, super low power and 4Mbit full CMOS SRAM organized as 256K words by 16bits.
The HY62KF16403E uses high performance full CMOS process technology and is designed for high sp eed and low power
circuit technology. It is particularly well-suited for the high density low power system application.
This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2 V.
FEATURES
● Fully static operation and Tri-state output
● TTL compatible inputs and outputs
● Battery backup
- 1.2V(min) data retention
● Standard pin configuration
- 44pin 400mil TSOP-II (Forward)
16M Pseudo SRAM PRODUCT FAMILY
Note 1) I : Industrial Temperature.
2) Current value is max.
Part Number Voltage Speed Operation
Current/Icc
Standby Current Temp.(oC)
SL LL
HY62KF16403E-I 2.7~3.6 (V) 55/70 (ns) 3mA 6uA 15uA -40 ~ 85
Rev 0.2 / Dec. 2003 3
HY62KF16403E Series
256Kx16bit full CMOS SRAM
PIN CONNECTION
PAD DESCRIPTION
SYMBOL DESCRIPTION
CS Chip Select
WE Wri te Enable
OE Output Enable
LB Lower Byte Control (IO1~IO8)
UB Upper Byte Control (IO9~IO16)
I/O1 ~ I/O16 Data Inputs/Outputs
A0 ~ A17 Address Inputs
VDD Power(2.7V~3.6V)
VSS Ground
NC No connection
1
12
13
22
44
33
32
23
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O13
Vss
Vcc
Vcc
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
A12
A4
A3
A2
A1
A0
CS
I/O3
I/O4
Vss
Vcc
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
I/O1
I/O2
A17
A16
TSOPII
(Forward)
Rev 0.2 / Dec. 2003 4
HY62KF16403E Series
256Kx16bit full CMOS SRAM
FUNCTIONAL BLOCK DIAGRAM
256K x 16bit Super low Power FCMOS Slow SRAM
MEMORY
ARRAY
256K x 16
ROW
DECODER
SENSE AMP WRITE DRIVER
DATA I/O
BUFFER
I/O1
I/O8
I/O9
I/O16
COLUMN
DECODER BLOCK
DECODER
PRE DECODER
ADD INPUT
BUFFER
A0
A17
/CS
/OE
/LB
/UB
/WE
DATA I/O
BUFFER
A0
CS
LB
UB
WE
Rev 0.2 / Dec. 2003 5
HY62KF16403E Series
256Kx16bit full CMOS SRAM
ORDERING INFORMATION
Note 1) I : Industrial -40 ~ 85 oC
ABSOLUTE MAXIMUM RATING1)
Note1) Stresses greater than th os e li sted under ABSOLUTE MAXIMU M RATINGS may cause permanent damage to th e devi ce. Th is is
stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation
of this specification is not implied.
Exposure to the absolute maximum rati ng conditions for ext ended period may affect reliability.
TRUTH TABLE
Note 1). H=VIH, L=VIL, X=Don't Care(VIL or VIH)
2). UB, LB(Upper, Lower Byte enable)
These active LOW inputs allow individual bytes to be written or read.
When LB is LOW, data is written or read to the lower byte, I/O1 - I /O 8.
When UB is LOW, data is written or read to the upper byte, I/O9 - I/O16.
Part Number Speed Power Temparature Package
HY62KF16403E-SD(I) 55/70 SL-Part I1) TSOP-II
HY62KF16403E-DD(I) 55/70 LL-Part I1) TSOP-II
Parameter Symbol Rating Unit
Input/Output Voltage VIN, VOUT -0.3 to VCC+0.3V V
Power Supply VDD -0.3 to 4.0 V
Ambient Temperature TA-40 to 85 oC
Storage Temperature TSTG -55 to 150 oC
Power Dissipation PD1.0 W
Ball Soldering Temperature & Time TSOLDER 260 . 10 oC . Sec
MODE CS WE OE LB UB I/O POWER
I/O1 ~ I/O8 I/O9 ~ I/O16
Deselected H X X X X High-Z High-Z Standby
Output Disabled L X X H H High-Z High-Z Active
L H H X X High-Z High-Z
Read L H L LHD
OUT High-Z Active HLHigh-Z D
OUT
LLDOUT DOUT
Write L L X LHD
IN High-Z Active HLHigh-Z D
IN
LLDIN DIN
Rev 0.2 / Dec. 2003 6
HY62KF16403E Series
256Kx16bit full CMOS SRAM
DC OPERATING CONDITION (TA= -40 to 85 oC )
Note : 1) VIL=-1.5V for Pulse Width less th en 30ns.
Undershoot is sampled, not 100% tested.
DC CHARACTERISTICS (VDD= 2.7V ~ 3.6V, TA= -40 to 85oC)
Parameter Symbol Min Typ Max Unit
Power Supply Vo ltage VDD 2.7 3.0 or 3.3 3.6 V
Gruond VSS 0-0V
Input High Voltage VIH 2.2 -VCC+0.3 V
Input Low Voltage VIL -0.31) -0.6 V
Parameter Symbol Test Condition Speed Unit
Min Tpy. Max
Input Leakage Current ILI VSS ≤VIN ≤VCC -1 1
uA
Output Leakage Current ILO VSS ≤VOUT ≤VCC
CS=VIH or
OE=VIH or WE=VIL -1 1
Operating Power Supply
Current ICC CS=VIL,
VIN=VIH or VIL, II/O=0mA -3
mA
Average Operating Current ICC1
CS=VIL,
VIN=VIH or VIL,
Cycle Time= min.
100% Duty, II/O=0mA
55ns 20
70ns 15
CS ≤0.2V,
VIN ≤0.2V or VCC-0.2V ≤ VIN,
Cycle Time=1us.
100% Duty, II/O=0mA
-2
TTL Standby Current ISB CS=VIH,
VIN=VIH or VIL - 300
uA
Standby Current
(CMOS Input) ISB1 VCC-0.2V ≤ CS,
VCC-0.2V ≤ VIN or
VIN ≤VSS+0.2V
3.0 ~
3.6 V -0.26
-0.215
2.7 ~
3.3 V -0.26
-0.212
Output Low Voltage VOL IOL= 2.1mA - - 0.4 V
Output High Voltage VOH IOH= -1.0mA 2.4 - - V
Rev 0.2 / Dec. 2003 7
HY62KF16403E Series
256Kx16bit full CMOS SRAM
AC OPERATING TEST CONDITION (TA= -40 to 85 oC)
AC TEST LOADS
Note 1) Including jig and scope capacitance.
CAPACITANCE (Temp.= 25 oC, f=1.0MHz)
Note : These parameters are sampled and no t 100% tested.
Parameter Value
Input Pulse Level 0.4 to 2.2V
Input Rising and Fall Time 5ns
Input and Output Timing Reference Level 1.5V
Output Load tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, tOW CL = 30pF + 1TTL Load
Others CL = 30pF + 1TTL Load
Parameter Symbol Condition Max. Unit
Input Capacitance (Add, CS, WE, OE)CIN VIN = 0V 8 pF
Output Capacitance (I/O) COUT VI/O = 0V 10 pF
D
OUT
1728 O hm
CL(1)
1029 O hm
V
TM
=2.8V
Rev 0.2 / Dec. 2003 8
HY62KF16403E Series
256Kx16bit full CMOS SRAM
AC CHARACTERISTICS (AC operating conditions unless otherwise specified)
Parameter Symbol 55ns 75ns Unit
Min Max Min Max
Read Cycle
Read Cycle Time tRC 55 - 75 - ns
Address Access Time tAA -55-75ns
Chip Select Access Time tACS -55-75ns
Output Enable to Output Valid tOE -30-35ns
LB, UB Access Time tBA -55-75ns
Chip Select to Output in Low Z tCLZ 10 - 10 - ns
Output Enable to Output in Low Z tOLZ 5-5-ns
LB, UB Enable to Output in Low Z tBLZ 10 - 10 - ns
Chip Disable to Output in High Z tCHZ 020025ns
Out Disable to Output in High Z tOHZ 020025ns
LB, UB Disable to Output in High Z tBHZ 020025ns
Output Hold from Address Change tOH 10 - 10 - ns
Write Cycle
Write Cycle Time tWC 55 - 75 - ns
Chip Selection to End of Write tCW 50 - 60 - ns
Address Valid to End of Write tAW 50 - 60 - ns
LB, UB Valid to End of Write tBW 50 - 60 - ns
Address Set-up Time tAS 0-0-ns
Write Pulse Width tWP 45 - 50 - ns
Write Recovery Time tWR 0-0-ns
Write to Output in High Z tWHZ 020020ns
Data to Write Time Overlap tDW 25 - 30 - ns
Data Hold from Write Time tDH 0-0-ns
Output Active from End of Write tOW 5-5-ns
Rev 0.2 / Dec. 2003 9
HY62KF16403E Series
256Kx16bit full CMOS SRAM
READ CYCLE 1 ( Note 1, 4 )
READ CYCLE 2 ( Note 1, 2, 4 )
READ CYCLE 3 ( Note 1, 2, 4 )
ADD
CS
UB, LB
OE
Data Out High-Z
t
RC
t
AA
t
ACS
t
BA
t
OE
t
OLZ
(3)
t
BLZ
(3)
t
CLZ
(3)
t
OH
t
CHZ
(3)
t
BHZ
(3)
t
OHZ
(3)
Data Valid
ADD
Data Out Data Valid
t
RC
Previous Data
t
OH
t
AA
t
OH
CS
Data Out Data Valid
t
CLZ
(3)
t
ACS
t
CHZ
(3)
UB, LB
Rev 0.2 / Dec. 2003 10
HY62KF16403E Series
256Kx16bit full CMOS SRAM
Notes : 1. A read occurs during the overlap of a low OE, a high WE, a low CS and UB and /or LB .
2. OE = VIL
3. tCHZ and tOHZ are defined as the time at which the outpu ts achi eve the open circuit conditions and are not referenced
to output voltage levels.
4. CS in high for the standby, low for active.
UB and LB in high for the standby, low for active.
Rev 0.2 / Dec. 2003 11
HY62KF16403E Series
256Kx16bit full CMOS SRAM
WRITE CYCLE 1 ( Note 1, 4, 8 ) ( WE Controlled )
WRITE CYCLE 2 ( Note 1, 4, 8 ) ( CS Controlled )
ADD
CS
UB, LB
WE
Data Out
DataIn
t
WC
t
CW
t
BW
t
WP
t
WR
(2)
Data Valid
t
AW
t
AS
High-Z t
DW
t
DH
t
WHZ
(3,7)
t
OW
(5) (6)
ADD
CS
UB, LB
WE
Data Out
DataIn
t
WC
t
CW
t
BW
t
WP
t
WR
(2)
Data Valid
t
AW
High-Z
t
DW
t
DH
High-Z
t
AS
Rev 0.2 / Dec. 2003 12
HY62KF16403E Series
256Kx16bit full CMOS SRAM
Notes : 1. A write occurs during the overlap of a low WE, a low CS and a low UB and/or LB .
2. tWR is measured from the earlier of CS, LB, UB, or WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of op posite phase to the out p ut must
not be applied.
4. If the CS, LB and UB low transition occur simultaneously with the WE low transition or after the WE transition,
outputs remain in a high impedance state.
5. Q(data out) is the invalid data.
6. Q(data out) is the read data of the next address.
7. CS in high for the standby, low for active UB and LB in high for the standby, low for active.
DATA RETENTION ELECTRIC CHARACTERISTIC (TA= -40 to 85 oC)
Notes : 1. Typical values are under the condition of TA = 25oC.
2. Typical value are sampled and not 100% tested.
DATA RETENTION TIMING DIAGRAM
Symbol Parameter Test Condition Min Typ.1) Max Unit
VDR Vcc for Data Retention VCC-0.2V ≤ CS,
VCC-0.2V ≤ VIN or
VIN ≤VSS+0.2V 1.2 - 3.6 V
Iccdr Data Retention Current
VCC=1.5V
VCC-0.2V ≤ CS or
VCC-0.2V ≤ VIN or
VIN ≤VSS+0.2V
SL - 0.1 3.0
uA
LL - 0.1 6.0
tCDR Chip Deselect to Data
Retention Time See Data Retention
Timing Diagram
0--
ns
tROperating Recovery
Time tRC - -
CS
VDR
CS >V
CC
-0.2V
t
CDR
t
R
VSS
VCC
2.7V
VIH
DATA RETENTION MODE
Rev 0.2 / Dec. 2003 13
HY62KF16403E Series
256Kx16bit full CMOS SRAM
PACKAGE INFORMATION
44pin 400mil Thin Small Outline Package Forward (D)
0.4700 (11.938)
0.4620 (11.735)
0.729(18.517)
0.4040 (10.262)
0.3960 (10.058)
0.4040 (10.262)
5deg
0deg 0.0235 (0.597)
0.0160 (0.406) 0.0083 (0.210)
0.0047 (0.120)
0.0235 (0.597)
0.0160 (0.406) 0.0083 (0.210)
0.0047 (0.120)
0.0315 (0.80)
0.047 (1.194)
0.039 (0.991)
0.0059 (0.150)
0.002 (0.050)
0.016 (0.4)
0.0320 (0.805)
0.012 (0.3)
UNIT : Inch (mm) Max
Min
(BSC) (BSC)
