MTC-20146 ADSL DMT Transceiver with ATM Framer and integrated controller Preliminary Information Data Sheet Rev. 1.0 - January 1999 Features General Description * DMT modem and embedded controller, ATM framer * Supports ANSI TI.413 issue 2, ITU G.992.1, and G.992.2 standards * Power consumption 1.3 Watt at 3.3V * Standard Utopia level 1 and level 2 ATM interfaces * Parallel or serial modem control interface (CTRLE) for glueless connection to management entities * Supports code download * External Bus Interface for 16-bit SDRAM * Packages 176 TQFP Package 208 DQFP Package The MTC-20146 is the DMT modem, ATM Framer and controller chip of the MTK-20140 Rate adaptive ADSL DynaMiTe chipset. When used in conjunction with the MTC-20144 analog front-end, the product supports ANSI TI.413 release 2 ADSL specification and is SW upgradeable to ITU G.992.1 and G.992.2 (G.Lite). The MTC-20146 may be used in both central office (ATU-C) and remote (ATU-R) applications. It provides both a cell based UTOPIA Level 1 and 2 ATM data interface. Ordering Information Part number Package Temp MTC-20146TQ-I MTC-20146TQ-C MTC-20146DQ-i MTC-20146DQ-C 176 176 208 208 -40 + 85C 0 + 70C -40 + 85C 0 + 70C Can also be ordered using kit number MTK-20140 pin pin pin pin TQFP TQFP DQFP DQFP Fig.1: MTC-20146 Block diagram 2 Parallel I/O General Purpose I/Os RS232 TIMER ROM DSP Front-end UART Peripherals ARM Microcore Microcontroller AFE Interface Mapper/ Demapper Rotor CTRLE Reed/ Solomon Generic TC ATM Specific TC VCXO FEPROM (optional) SDRAM Utopia SLAP local Bus Interface Module 8 data 9 address Control Bus Interface Logic CTRL Data buffer RAM Trellis coding FFT/ IFFT Data Symbol Timing Unit Clock MTC-20146 External Bus Interface MTC-20146 Functional Description DSP Front-End Figure 1 shows the global block diagram of the MTC-20146. The functions can be grouped into the following: - Microcontroller - External Bus Interface - Control Interface (CTRLE) - DMT modem - AFE interface - Utopia interface - Peripherals - Miscellaneous The DSP Front-End contains 4 parts in the receive direction: the Input Selector, the Analog Front-End Interface, the Decimator and the Time Equalizer. The input selector is used internally to enable test loopbacks inside the chip. The Analog Front-End Interface transfers 1 6-bits word, multiplexed on 4 input/output signals. As a result, 4 clock cycles are needed to transfer 1 word. The Decimator receives the 16-bits samples at 8.8 MHz (as sent by the Analog Front-End chip) and reduces thisrate to 2.2 MHz. The Time Equalizer (TEQ) module is an FIR filter with programmable coefficients. Microcontroller The microcontroller block includes an ARM-based microcore and its associated internal memory. 16 Kbytes on internal RAM and 128 x 32-bit words of ROM are foreseen. The ROM essentially contains the boot sequence needed for code download at startup. The use of the ROM by the microcore is defined by the state of the TROM pin during reset. External Bus Interface The External Bus Interface extends the internal microcontroller bus for connection of external devices. In particular, the bus is used to connect to the external SDRAM (and optional FEEPROM). The CTRLE functional block implements the ADSL modem command and data buffer and the interface logic supporting the various physical interfaces of the CTRLE: - Parallel 8-bit data/ 9-bit address bus (Intel or Motorola compatible) - Serial bus (SPI-Like) Its main purpose is to reduce the effect of Inter-Symbol Interferences (ISI) by shortening the channel impulse response. Both the Decimator and TEQ can be bypassed. In the transmit direction, the DSP Front-End includes: sidelobe filtering, clipping, delay equalization and interpolation. The sidelobe filtering and delay equalization are implemented by IIR filters, reducing the effect of echo in FDM systems. Clipping is a statistical process limiting the amplitude of the output signal, optimizing the dynamic range of the AFE. The interpolator receives data at 2.2 MHz and generates samples at a rate of 8.8 MHz. Bypass Analog Interface IN AFE Select I/F Fig.2: DSP Front-End DMT Modem Description The following essentially describes the sequence of actions for the receive direction, corresponding functions for the transmit direction are readily derived. 3 DEC To DMT TEQ modem MTC-20146 DMT Modem This computational module is a programmable DSP unit. Its instruction set enables functions like FFT, IFFT, Scaling, Rotor and Frequency Equalization (FEQ). This block implements the core of the DMT algorithm as specified in ANSI T1.413. In the RX path, the 512-point FFT transforms the time-domain DMT symbol into a frequency domain representation which can be further decoded by the subsequent demapping stages. After the first stage time -domain equalization and FFT block an essentially ICI (InterCarrier Interference)free carrier information stream has been obtained. This stream is still affected by carrierspecific channel distortion resulting in an attenuation of the signal amplitude and a rotation of the signal phase. To compensate for these effects, the FFT is followed by a Frequency domain equalizer (FEQ) and a Rotor (phase shifter). In the TX path, the IFFT transforms the DMT symbol generated in the frequency domain by the mapper into a time domain representation. The IFFT block is preceded by a Fine Tune Gain and a Rotor stage, allowing for a compensation of the possible frequency mismatch between the master clock frequency and the transmitter clock frequency (which may be locked to another reference). Trelis coding From DSP PE FFT FEQ Rotor Demapper Monitor FEQ Coefficients FEQ Update Monitor Indications Fig.3: DMT Modem DPLL The Digital PLL module receives a metric for the phase error of the pilot tone. In general, the clock frequencies at the transmitter and receiver do not match exactly. The phase error is filtered and integrated by a low pass filter, yielding an estimation of the frequency offset. Various processes can use this estimate to deal with the frequency mismatch. In particular, small accumulated phase error can be compensated in the frequency domain by a rotation of the received code constellation (Rotor). Larger errors are compensated in the time domain by inserting or deleting clock cycles in the sample input sequence. The FFT module is a slave DSP engine controlled by the transceiver controller. It works off line and communicates with the other blocks via buffers controlled by the DSTU block. The DSP executes a program stored in a RAM area, a very flexible implementation open for future enhancements. 4 Mapper/Demapper, Monitor, Trellis Coding, FEQ Update The Demapper converts the constellation points computed by the FFT to a block of bits. This essentially consists in identifying a point in a 2D QAM constellation plane. The Demapper supports trellis coded demodulation and provides a Viterbi maximum likelihood estimator. When the trellis is active, the Demapper receives an indication for the most likely constellation subset to be used. In the transmit direction, the Mapper performs the inverse operation, mapping a block of bits into one constellation point (in a complex x+jy representation) which is passed to the IFFT block. The Trellis Encoder generates redundant bits to improve the robustness of the transmission, using a 4-Dimensional Trellis Coded Modulation scheme. The Monitor computes error parameters for carriers specified in the Demapper process. Those parameters can be used for updates of adaptive filters coefficients, clock phase adjustments, error detection,etc. A series of values is constantly monitored, such as signal power, pilot phase deviations, symbol erasures generation, loss of frame,etc. MTC-20146 Generic TC Layer Functions These functions relate to byte oriented data streams. They are completely described in ANSI T1.413. Additions described in the Issue 2 of this specification are also supported. The data received from the demapper is split into two paths, one dedicated to an interleaved data flow, the other one for a non-interleaved data flow. These data flows are also referred to as slow and fast data flows. The interleaving/deinterleaving is used to increase the error correcting capability of block codes for error bursts. After deinterleaving (if applicable), the data flow enters a Reed-Solomon error correcting code decoder, able to correct a number of bytes containing bit errors. The decoder also uses the information of previous receiving stages that may have detected the errored bytes and have labelled them with an "erasure" indication. Each time the RS decoder detects and corrects errors in a RS codeword, an RS correction event is generated. The occurrence of such events can be signalled to the management layer. After leaving the RS decoder, the corrected byte stream is descrambled in the PMD (Physical Medium Dependent) descramblers. Two descramblers are used, for interleaved and non-interleaved data flows. These are defined in ANSI T1.413. After descrambling, the data flows enter the Deframer that extracts and processes bytes to support Physical layer related functions according to ANSI T1.413. The ADSL frames indeed contain physical layer-related information in addition to the data passed to the higher layers. In particular, the deframer extracts the EOC (Embedded Operations Channel), the AOC (ADSL Overhead Control) and the indicators bits and passes them to the appropriate processing unit (e.g. the transceiver controller). Indications bits AOC EOC Fast From F Demapper RS Deinter PMD Detramer descrambler To ATM TC coding I PMD descrambler Fig.4: Generic TC Layer Functions The deframer also performs a CRC check (Cyclic Redundancy Check ) on the received frame and generates events in case of error detection. Event counters can be read by management processes. The outputs of the deframer are an interleaved and a fast data streams. These data streams can either carry ATM cells or another type of traffic. In the latter case, the ATM specific TC layer functional block, described hereafter, is bypassed and the data stream is directly presented at the input of the Interface module. ATM Specific TC Layer Functions The 2 bytes streams (fast and slow) are received from the byte-based processing unit. When ATM cells are transported, this block provides basic cell functions such as cell synchronization, cell payload descrambling, idle/unassigned cell filter, cell Header Error Correction (HEC) and detection. The cell processing happens according to ITU-T I.163 standard. Provision is also made for BER measurements at this ATM cell level. When non cell oriented byte streams are transported, the cell processing unit is not active. BER Fast Cell Descrambler Synchronizer From Generic HEC Cell filter To Interface Module TC Cell Descrambler Synchronizer Slow HEC Cell filter BER Fig.5: ATM Specific TC Layer Functions 5 MTC-20146 Interface Module The DSTU interfaces with various modules, like DSP Front-End, FFT/IFFT, Mapper/Demapper, RS , Monitor and Transceiver Controller. It consists of a real time and a scheduler modules. The real time unit generate a timebase for the DMT symbols (sample counter), superframes (symbol counter) and hyperframes (sync counter). The timebases can be modified by various control features. They are continuously fine-tuned by the DPLL module. The DSTU schedulers execute a program, controlled by program opcodes and a set of variables, the most important of which are real time counters.The transmit and receive sequencers are completely independent and run different programs. An independent set of variables is assigned to each of them. The sequencer programs can be updated in real time. The interface module collects cells (from the cell-based function module) or a byte stream (from the deframer). Cells are stored in FIFO's ( 424 bytes or 8 cells wide, transmit buffers have the same size), from which they are extracted by 2 interface submodules, one providing an Utopia level 1 interface and the other an Utopia level 2 interface. Only one type of interface can be enabled in a specific configuration. DMT Symbol Timing Unit (DSTU) Interfaces Analog Front-End Control Interface The DSTU interfaces with various modules, like DSP Front-End, FFT/IFFT, Mapper/Demapper, RS , Monitor and Transceiver Controller. It consists of a real time and a scheduler modules. The real time unit generate a timebase for the DMT symbols (sample counter), superframes (symbol counter) and hyperframes (sync counter). The timebases can be modified by various control features. They are continuously fine-tuned by the DPLL module. The DSTU schedulers execute a program, controlled by program opcodes and a set of variables, the most important of which are real time counters.The transmit and receive sequencers are completely independent and run different programs. An independent set of variables is assigned to each of them. The sequencer programs can beupdated in real time. The Analog Front-End Interface is designed to be connected to the MTC20144 Analog Front-End component. Transmit Interface The 16 bit words are multiplexed on 4 AFTXD output signals. As a result 4 cycles are needed to transfer 1 word. Refer to Table 1 for the bit/pin allocation for the 4 cycles. The first of 4 cycles is identified by the CLWD signal. Refer to Figure 6. The MTC-20146 fetches the 16 bit word to be multiplexed on AFTXD from the Tx Digital Front-End module. OUT Fig.6: Timing Diagram Table 1: Transmitted Bits Assigned to Signal/Time Slot Cycle 0 Cycle 1 Cycle 2 Cycle 3 AFTXD [0] b0 b4 b8 b12 AFTXD [1] b1 b5 b9 b13 AFTXD [0] b2 b6 b10 b14 AFTXD [0] b3 b7 b11 b15 GP_OUT t0 t1 t2 t3 6 MTC-20146 Receive Interface The 16 bit receive word is multiplexed on 4 AFRXD input signals. As a result 4 cycles are needed to transfer 1 word. Refer to Table 2 for the bit/pin allocation for the 4 cycles. The first of 4 cycles is identified by the CLWD signal. Refer to Figure 7. The CLWD must repeat after 4 MCLK cycles. AFTXED Master Clock ( MCLK ) Analog Front End Interface Timing. Fig.7: Receive Word Timing Diagram Table 2: Transmitted Bits Assigned to Signal/Time Slot Cycle 0 Cycle 1 Cycle 2 Cycle 3 AFRXD [0] b0 b4 b8 b12 AFRXD [1] b1 b5 b9 b13 AFRXD [0] b2 b6 b10 b14 AFRXD [0] b3 b7 b11 b15 Table 3: MCLK, AC Electrical Characteristics Symbol Parameter Test Cond. Min Typ Max Unit F Clock Frequency 35,328 MHz Tp Clock Period 28,3 ns Tn Clock data cycle 40 7 60 % MTC-20146 Transmit Interface Fig. 8 : Transmit Interface Table 4: AFTXD, AFTXED CLWD, AC Electrical Characterisitics Symbol Parameter Tv Data valid time Tc Data valid time Test Cond. Min Typ Max Unit 0 10 ns 0 10 ns Max Unit Receive Interface Fig. 9: Receive Interface Table 5: AFTXD, AFTXED CLWD, AC Electrical Characterisitics Symbol Parameter Test Cond. Min Ts Data setup time 5 10 ns Th Data hold time 5 10 ns 8 Typ MTC-20146/20156 Digital Interface Utopia Level 2 Interface The ATM forum takes the ATM layer chip as a reference. It defines the direction from ATM to physical layer as the Transmit direction. The direction from physical layer to ATM as the Receive direction is referred to as the receive direction. Figure 10 shows the interconnection between ATM and PHY layer devices, the optional signals are not supported and not shown. The UTOPIA interface transfers one byte in a single clock cycle, as a result cells are transferred in 53 clock cycles. Both transmit and receive interfaces are synchronized on clocks generated by the ATM layer chip, and no specific relationship between Receive and Transmit clock is assumed, they must be regarded as mutually asynchronous clocks. Flow control signals are available to match the bandwidth constraints of the physical layer and the ATM layer. The UTOPIA level 2 supports point to multi point configurations by introducing an addressing capability and by making a distinction between polling and selecting a device : - the ATM chip polls a specific physical layer chip by putting its address on the address bus when the Enb line is asserted. The addressed physical layer answers the next cycle via a Clav line reflecting its status at that time. - the ATM chip selects a specific physical layer chip by putting its address on the address bus when the Enb line is deasserted and asserting the Enb line on the next cycle. The addressed physical layer chip will be the target or source of the next cell transfer. Reference Spec: Utopia Specification Level 2, Version 1.0, June 95. See www.atmforum.com Fig. 10: Signals at Utopia Level 2 interface MTC-20146 Table 6: Signal Definitions for the Utopia Receive Path Name Meaning Usage Remark RxClav Receive Cell available Signals that the ATM chip that the physical layer chip has a call ready for transfer. Remains active for the entire cell transfer. notRxEnb Receive Enable (Active low) Signals to the physical layer chip that the ATM layer chip will sample and accept data during next clock cycle. RxData and RxSOC could be tristate when notRxEnb is inactive (high). RxCx Receive Byte Clock Give the timing signal for the transfer, generated by ATM layer chip. RxData Receive Data ATM cell data from physical layer chip to ATM chip, byte wide. RxSOC Receive Start Of Cell Identifies the cell boudary on RxData RxAddr Receive Adress Use to select the port that will be active or polled UTOPIA Level 2 Signals MTC-20146 Utopia Level 2 MPHY Operation PHY Device Identification The physical layer chip sends cell data towards the ATM layer chip. The ATM layer chip polls the status of the FIFO of the physical layer chip. Refer to Table 6 for a list of interface signals. The cell exchange proceeds like : a) The physical layer chip signals the availability of a cell by asserting RxClav when polled by the ATM chip. Utopia level 2 MPHY operation can be done by various interface schemes. The MTC-20146 supports only the required mode, this mode is referred to as operation with 1 TxClav and 1 RxClav. The MTC-20146 holds 2 PHY layer Utopia ports, one is dedicated to the fast data channel, the other one to the interleaved data channel. The associated PHY address is specified by the PHY_ADDR_x fields the Utopia PHY address register. Beware that an incorrect address configuration may lead to bus conflicts. A feature is defined to disable (tri-state) all outputs of the Utopia interface. It is enabled by the TRI_STATE_EN bit in the Rx_Interface control register. Utopia Level 1 Data Flow Selection In this mode the MTC-20146 can only support one data flow (either fast or interleaved). The selection between fast or interleaved is under control of the Transceiver Controller. Utopia Level 1 Configuration MTC-20146 Reference Spec: Utopia Specification Level 1, Version 2.0, March 94. See www.atmforum.com b) The ATM chips selects a physical layer chip, then starts the transfer by asserting notRxEnb. c) If the physical layer chip has data to send, it puts them on the RxData line the cycle after it sampled notRxEnb active. It also advances the offset in the cell. If the data transferred is the first byte of a cell, RxSOC is 1b at the time of the data transfer, 0b otherwise. d) The ATM chip accepts the data when they are available. If RxSOC was 1b during the transfer, it resets its internal offset pointer to the value 1, otherwise it advances the offset in the cell. 10 MTC-20146 Table 7: Signal Definitions for the Utopia Transmit Path Name Meaning Usage TxClav Transmit Cell available Signals to the ATM chip that the physical layer chip is ready to accept a call. notTxEnb Transmit Enable (Active low) Signals to the physical layer chip that TxData and TxSOC are valid. TxCx Transmit Byte Clock Gaves the timing signal for the transfer, generated by ATM layer chip. TxData Transmit Data ATM cell data from ATM chip to physical layer chip, byte wide. TxSOC Transmit Start Of Cell Identifies the cell boudary on TxData TxAddr Transmit Adress Use to select the port that will be Fig. 11: Signals at Utopia Level 1 interface Utopia Level 1 Handshake Protocol PHY->ATM. The MTC-20146 supports a cell level handshake protocol only. The ATM layer indicates it wants to read data by asserting the notRxEnb signal. The PHY layer dumps 53 bytes (1 cell) on the RxDATA bus, a cell start indication is available on the RxSOC signal. Refer to Figures 12. Fig.12a: Utopia Level 1 Functional Timing Diagram (PHY -> ATM) 11 MTC-20146 Fig.12b: Utopia Level 1 Functional Timing Diagram (ATM -> PHY) Table 8: Utopia level 1 Pinout Name signal Type Pin RxData 0 U_RxData RxSOC 0 U_RxSOC notRxEnb 1 U_RxENBB RxClav 0 U_RxCLAV RxClk 1 U_RxCLK Table 9: U_TxCLK, U_RxCLK, AC Electrical Characteristics Symbol F Tc Tj Trf L Parameter Clock Frequency Clock duty cycle Clock peak to peak jitter Clock rise/fall time Load Test Cond. Fig.13: Utopia Timing Diagram 12 Min 1.5 40 Typ Max 25 60 5 4 100 Unit MHz % % ns pF MTC-20146 Table 10: U_RxADDR AC Electrical Characteristics Symbol Parameter Min Typ Max Unit T5 Input setup time to U_RxCLK 10 ns T Hold time time to U_RxCLK 1 ns L load 100 pf Table 11: U_RxData, U_RxSOC, U_RxClav AC Electrical Characteristics Symbol Parameter Min Typ Max Unit T7 Input setup time to U_TxCLK 10 ns T8 Hold time time to U_TxCLK 1 ns T9 Signal going low impedance to U_RxCLK 10 ns T10 Signal going high impedance to U_RxCLK 0 ns T11 Signal going low impedance to U_RxCLK 1 ns T12 Signal going high impedance to U_RxCLK 1 ns L Load 100 pf Table 12: U_RxADDR AC Electrical Characteristics Symbol Parameter Min Typ Max Unit T7 Input setup time to U_TxCLK 10 ns T8 Hold time time to U_TxCLK 1 ns T9 Signal going low impedance to U_RxCLK 10 ns T10 Signal going high impedance to U_RxCLK 0 ns T11 Signal going low impedance to U_RxCLK 1 ns T12 Signal going high impedance to U_RxCLK 1 ns L Load 100 pf Peripherals The peripherals block includes two UARTS for RS232 interfacing to external systems and two general purpose parallel I/O lines. 13 MTC-20146 Miscellaneous This includes the clock circuitry, reset circuitry, test functions and configuration control signals. SDRAM The SDRAM interface allows a glueless interconnection of 1 SDRAM 1Mx16, of type uPD4516161 or compatible. Following features are provided for SDRAM access. -16 bit databus and 12 bit address bus. -Control signals : S_nCS, S_nRAS, S_nCAS, S_nWE, S_DQM[1:0} Control signal timing All SDRAM actions are triggered at the rising edge of its clock. Timing diagrams for a burst of four 16-bit accesses to 16-bit SDRAM (Figure 14 and Figure 15) show the basic behavior of the control signals. Fig. 14: SDRAM read access (CAS latency=3; Burst length=4) Memory Following features are provided for memory access (SRAM or FEPROM) : - 16 bit databus and 20 bit address bus giving 1Mbyte address space per chip select - Control signals : E_nCS[0:1], E_nOE, E_nWE0, E_nWE1 - Setup and wait state insertion - 8, 16 and 32 bit access by MTC-20146 to 8 or 16 bit memory according to little endian convention Fig. 15: SDRAM write access (CAS latency=3; Burst length=4) EBI Interface Timing All timing parameters are specified at a load of 100 pF, all the electrical levels are CMOS compatible. Fig. 16: EBI memory access (32-bit Word R/W to 16 bit memory), maximum speed timing 14 MTC-20146 CTRLE The Ctrl-E interface is an ADSL-oriented mailbox system to exchange control and status messages between MTC20146 and an external controller. It consists of a mailbox and a physical interface. The mailbox has two 8-bit command registers to pass commands from the MTC-20146 internal controller bus (ASB) to Ctrl-E (RxCommand) and from Ctrl-E to ASB (TxCommand), and two status registers (RxComAv and TxComAv) to indicate the status of the command register. Data associated with a command can be exchanged using a common CtrleDataBuffer. A hardware semaphore mechanism is provided to allow control of data consistency of the CtrleDataBuffer. The Ctrl-E physical interface between the mailbox and an external controller can be used in one of two modes : as a dedicated serial bus interface or as a generic parallel bus interface. Selection between serial and parallel mode is done with an external mode strap, IO pins are shared. Fig.17: Ctrl-E Interface Controller principle Ctrl-E Mailbox The Ctrl-E Mailbox occupies a 512 byte memory map accessible by the Ctrl-E physical interface and by the ASB bus. The mailbox memory map is given in Table 13. An external interrupt can be generated by the Mailbox interrupt controller. A full description of the CTRLE protocol and use of the CTRLE mailbox is available in the "Modem control Interface Specifications" documents, available separately. Ctrl-E Semaphore A simple semaphore mechanism is provided to allow control of the data consistency of the CtrleDataBuffer. One mailbox address is defined as a two-bit semaphore register protected by control logic to prevent unallowed write accesses to this register. Before the databuffer is read or written by one of the two interfaces (ASB or Ctrl-E) this interface should perform a 'P-operation' on the semaphore. After a 15 MTC-20146 Table 13: Ctrl-E controller memory map: Field ACC Mailbox Address MA[8:0] Size (bit) Initial TxCommand Rw RxCommand 000h 8 00h Command written by Ctrl-E, read by ASB Rw 001h 8 00h Command written by ASB, read by Ctrl-E TxComAv Rw 002h 1 0lb 1-bit register: 1 if TX command available RxComAv Rw 003h 1 0lb 1-bit register: 1 if RX command available Semaphore PV 004h 2 00b Semaphore for access read by Ctrl-E 005h-1FFh 8 00h 507x8 bit data buffer CtrleDataBuffer Rw Function Table 14: Semaphore Pand V operations: new value after write by ASB or Ctrl-E Semaphore operation originator write value previous semaphore value semaphore free P V semaphore taken by ASB Ctrl-E 00b 01b 11b ASB 01b 01b 01b 11b Ctrl-E 11b 11b 01b 11b ASB 00b 00b 00b 11b 16 MTC-20146 read or write of the databuffer the interface should do a 'V-operation' releasing the semaphore. P and V operations are performed by write and read accesses to the semaphore register. The semaphore will be updated as shown in Table 14. Each semaphore operation (P or V) consists of two consecutive actions that don't have to be atomic : a) Write the correct value to the semaphore address (see Table 14) b) Read the value in the semaphore address. If the value read is different from the value writen the P or V operation was not succesfull and should be tried again. The databuffers can be accessed without using the semaphore mechanism if data consistency is guaranteed in another way. If other values are written to the semaphore address than the values listed the write will not be performed. Ctrl-E Physical Interface A generic parallel interface with 9 bit Address and 8 bit Data bus is implemented two parallel bus modes are defined to support both Motorolacompatible and Intel-compatible timing and control signals. This interface specifi-cation is compliant to Utopia Level 2 Parallel Management Interface. bus mode is done with the C_Mode input pin : Table 15: Ctrl-E interface signals in parallel interface modes Signal name Type Function PIN C_A[8:0] I address bus C_A[8:0] C_D[7:0] I0 byte wide bidirectional data bus C_D[7:0] C_notCS I chip select C_notCS C_notnt 0Z Interrupt output, derived from CtrleInt1 signal from Mailbox: low when CtrleInt1 is low, else tristated C_notnt Mode 0: Motorola-compatible mode C_Mode[1:0] I 0Db C_Mode[1:0] C_Rd/notWr I read acces if 1, write acces if 0 C_notWr C_not DS I Data Strobe C_notRd C_not DtAcx OZ Bus cycle ready indication, indicates that data on bus can be sampled or removed C_notRdy Mode 1: Intel-compatible mode C_Mode[1:0] I 01b C_Mode[1:0] C_notWr I write cycle indication C_notWr C_notRd I read cycle indication C_notRd C_notRdy OZ Bus cycle ready indication, indicates that data on bus can be sampled or removed, same as in mode 0 C_notRdy Generic Parallel Interface The two parallel bus modes differ only in the definition of 3 control signals : busmode 0 provides a read/write selector, a data strobe and a ready acknowledge. Busmode 1 provides a read strobe, a write strobe and a ready acknowledge. The signal definition is shown in following table : 17 MTC-20146 Fig. 18: Ctrl-E Interface write cycle timing in parallel modes 0 and 1 Table 16: Ctrl-E interface signals in parallel interface modes Symbol Description Min t1 C_A Setup to C_notDS (C_notWr) low 0 ns t2 C_notCS, C_Rd/notWr setup to C_notDS (C_notWr) low 0 ns t3 C_notDS (C_notWr) pulse width 215 ns t4 C_D setup to C_notDS (C_notWr) high 15 ns t5 C_A, C_D hold from C_notDS (C_notWr) high 5 ns t6 C_notDtAck (C_notRdy) valid from C_notDS (C_notWr) low 15 ns t7 C_notDtAck (C_notRdy) tri-state from C_notDS (C_notWr) high 15 ns t8 C_notCS, C_Rd/notWr hold from C_notDS (C_notWr) high 0 ns t9 C_notCS high to C_notCS Low 100 ns 18 Max Unit MTC-20146 Fig. 19: Ctrl-E Interface read cycle timing in parallel modes 0 and 1 Table 17: Read cycle timing in parallel modes 0 and 1 Symbol Description Min Max t1 C_A Setup to C_notDS (C_notRd) low 0 ns t2 C_notCS, C_Rd/notWr setup to C_notDS (C_notRd) low 0 ns t3 C_notDS (C_notRd) pulse width 215 ns t4 C_D valid from C_notDtAck (C_notRdy) low t5 C_A, hold from C_notDS (C_notRd) high t6 C_notDtAck (C_notRdy) valid from C_notDS (C_notRd) high 15 ns t7 C_notDtAck (C_notRdy) tri-state from C_notDS (C_notRd) high 10 ns t8 C_notCS, C_Rd/notWr hold from C_notDS (C_notRd) high 10 t9 Data tri-state from C_notDS (C_notRd) high 90 100 ns t10 Data tri-state from C_notCS high 5 15 ns t11 C_notCS high to C_notCS low (Min. time between 2 Accesses) 100 10 0 19 Unit ns ns ns ns MTC-20146 Electrical Specifications Generic The values presented in the following table apply for all inputs and/or outputs unless specified otherwise. Specifically they are not influenced by the choice between CMOS or TTL levels. Table 18: IO buffers generic DC characteristics MTC-20146 DC Electrical Characteristics All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device Symbol Parameter Test Conditions LN Input leakage current VIN = VSS.VDD.no pull up/pull down LOZ Tristate leakage current lPU Min type Max Unit 1 1 A VIN = VSS.VDD.no pull up/pull down 1 1 A Pull up current VIN = VSS 25 66 125 A lPD Pull down current VIN = VDD 25 66 125 A APU Pull up resistance VIN = VSS 50 kOhm APU Pull down resistance VIN = VDD 50 kOhm Table 19: IO buffers dynamic characteristics MTC-20146 DC Electrical Characteristics All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device Symbol Parameter Test Conditions CIN Input capacitance @f=1MHz dl/dt Current derivative 8 mA driver, slow rate control 8 mA driver, no slow rate control lpeak COUT Peak current Output capacitance (also bidirectional and tristate driver) Min 8 mA driver, slow rate control 8 mA driver, no slow rate control @f=1MHz type Max Unit 5 pF 23,5 mA/ns 89 mA/ns 85 mA 100 mA 7 20 pf MTC-20146 Input/Output CMOS Generic Characteristics The values presented in the following table apply for all CMOS inputs and/ or outputs unless specified otherwise. Table 20: CMOS IO buffers generic characterisitics MTC-20146 DC Electrical Characteristics All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device Symbol Parameter Test Conditions Min VIL Low level input voltage VIH High level input voltage VHY Schmitt triger hysteresis slow edge < 1 V/ms, only for SCHMITx VOL Low level output voltage LOUT = XmaI VOH High level output voltage LOUT = XmaI Typ Max Unit 0,2'' VDD V 0,8*VDD V 0.8 V 0.4 0.85*VDD V V Input/Output TTL Generic Characteristics The values presented in the following table apply for all TTL inputs and/or outputs unless specified otherwise. Table 21: TTL IO buffers generic characterisitics MTC-20146 DC Electrical Characteristics All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device Symbol Parameter Test Conditions Min VIL Low level input voltage VIH High level input voltage 2.0 VILHY Low level threshold, falling slow edge < 1 V/ms 0.9 1.35 V VIHHY High level threshold, rising slow edge < 1 V/ms 1.3 1.9 V VHY Schmitt trigger hysteresis slow edge < 1 V/ms 0.4 0.7 V VOL Low level output voltage LOUT = Xma1 0.4 V VOH High level output voltage LOUT = -Xma1 2.4 21 Typ Max Unit 0.8 V V V MTC-20146 Operating Conditions Table 22: Operating Conditions DC Electrical Characteristics All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device Symbol Parameter VDD -IO Test Conditions Min Typ Max Unit Supply voltage IO 3.0 3.3 3.6 V TA Ambient temperature Tm/s airflow .40 +85 C P Power dissipation 300 400 mW 3.3 3.6 V VDD-CORE 3 22 MTC-20146 Package and Pinning TQFP176 NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Pin Name TDI CARM_RESETN nCS_0 VSS_IO VDD_IO T_ACK T_REQB T_REQA TROM PA[1] PA[0] VSS_CORE VDD_CORE PA14 PA15 E_CLK S_nWE S_nRAS VSS_IO VDD_IO S_nCAS S_nLDQM S_nUDQM E_A[15] E_A[14] VSS_IO VDD_IO E_A[13] E_A[12] E_A[11] E_A[10] E_A[9] VSS_CORE VDD_CORE E_A[8] E_A[7] E_A[6] E_A[5] E_A[4] VSS_IO VDD_IO E_A[3] E_A[2] E_A[1] E_A[0] E_D[0] E_D[1] VSS_IO VDD_IO E_D[2] E_D[3] E_D[4] E_D[5] Dir funct in in out out in in in inout inout inout inout inout out out out out out inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout Dir test in inout inout inout pad type IBUFUQ SCHMITC B8CR VSSI VDDI B4CR IBUFDQ IBUFDQ SCHMITC BD4CR BD4CR VSSI VDDI BD4CR BD4CR BD8CR B8CR B8CR VSSI VDDI B8CR B8CR B8CR BD8CR BD8CR VSSI VDDI BD8CR BD8CR BD8CR BD8CR BD8CR VSSI VDDI BD8CR BD8CR BD8CR BD8CR BD8CR VSSI VDDI BD8CR BD8CR BD8CR BD8CR BD8SCRDQ BD8SCRDQ VSSI VDDI BD8SCRDQ BD8SCRDQ BD8SCRDQ BD8SCRDQ 23 Description test data in carm reset signal, active low CS signal for flash eprom IO ground IO +3.3V power supply test acknowledge test request signal test request signal boot from test Rom select port A bit[1] port A bit[0] CORE ground CORE +3.3V power supply download mode select (CTRL-E or UART1) download mode select (UART baudrate) EBI clock control signal SDRAM control signal SDRAM IO ground IO +3.3V power supply control signal SDRAM control signal SDRAM control signal SDRAM adress bus / testbus MSB adress bus / testbus MSB IO ground IO +3.3V power supply adress bus / testbus MSB adress bus / testbus MSB adress bus / testbus MSB adress bus / testbus MSB adress bus / testbus MSB IO ground IO +3.3V power supply adress bus / testbus MSB adress bus / testbus MSB adress bus / testbus MSB adress bus / testbus MSB adress bus / testbus MSB IO ground IO +3.3V power supply adress bus / testbus MSB adress bus / testbus MSB adress bus / testbus MSB adress bus / testbus MSB data bus / testbus LSB data bus / testbus LSB IO ground IO +3.3V power supply data bus / testbus LSB data bus / testbus LSB data bus / testbus LSB data bus / testbus LSB MTC-20146 NO. 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 Pin Name E_D[6] VSS_CORE VDD_CORE E_D[7] E_D[8] E_D[9] E_D[10] E_D[11] VSS_IO VDD_IO E_D[12] E_D[13] E_D[14] E_D[15] S_nOE S_CS VSS_IO VDD_IO AFTXD[3] AFTXD[2] AFTXD[1] AFTXD[0] IDDq VSS_CORE VDD_CORE CTRLDATA MCLK CLWD AFRXD[3] AFRXD[2] VSS_IO VDD_IO AFRXD[1] AFRXD[0] POWER_LOWB U_TxADDR[0] U_TxData[0] U_TxData[1] VSS_IO VDD_IO U_TxData[2] U_TxData[3] U_TxData[4] U_TxData[5] U_TxData[6] VSS_CORE VDD_CORE U_TxData[7] U_TxENBB U_TxCLAV U_TxSOC U_TxCLK VSS_IO VDD_IO U_RxENBB U_RxCLAV U_RxSOC Dir funct inout inout inout inout inout inout inout inout inout inout out out out out out out in inout in in in in in in inout in in in in in in in in in in inout in in in inout inout Dir test pad type BD8SCRDQ VSSI VDDI BD8SCRDQ BD8SCRDQ BD8SCRDQ BD8SCRDQ BD8SCRDQ VSSI VDDI BD8SCRDQ BD8SCRDQ BD8SCRDQ BD8SCRDQ B8CR B8CR VSSI VDDI B8 B8 B8 B8 IBUF VSSI VDDI BD4CR SCHMITC IBUF IBUF IBUF VSSI VDDI IBUF IBUF BD4CR IBUFDQ IBUF IBUF VSSI VDDI IBUF IBUF IBUF IBUF IBUF VSSI VDDI IBUF IBUF BD8SCR IBUF IBUF VSSI VDDI IBUF BD8SCR BD8SCR 24 Description data bus / testbus LSB CORE ground CORE +3.3V power supply data bus / testbus LSB data bus / testbus LSB data bus / testbus LSB data bus / testbus LSB data bus / testbus LSB IO ground IO +3.3V power supply data bus / testbus LSB data bus / testbus LSB data bus / testbus LSB data bus / testbus LSB output enable chip select signal (SDRAM) IO ground IO +3.3V power supply transmit data nibble transmit data nibble transmit data nibble transmit data nibble test pin, active high CORE ground CORE +3.3V power supply serial data transmit channel master clock start of word indication receive data nibble receive data nibble IO ground IO +3.3V power supply receive data nibble receive data nibble Power down analog front end utopia tx adress bit utopia tx data bus utopia tx data bus IO ground IO +3.3V power supply utopia tx data bus utopia tx data bus utopia tx data bus utopia tx data bus utopia tx data bus CORE ground CORE +3.3V power supply utopia tx data bus Utopia Tx enable Utopia Tx cell available transmit interface start of cell indication transmit interface utopia clock IO ground IO +3.3V power supply Utopia Rx enable Utopia Rx cell available receive interface start of cell indication MTC-20146 NO. 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 Pin Name U_RxCLK U_TxRefB U_RxRefB VSS_IO VDD_IO U_RxADDR[0] U_RxData[7] U_RxData[6] U_RxData[5] U_RxData[4] VSS_CORE VDD_CORE U_RxData[3] U_RxData[2] U_RxData[1] U_RxData[0] SACHEM_RESETB VSS_IO VDD_IO C_A[8] C_A[7] C_A[6] C_A[5] C_A[4] C_A[3] VSS_IO VDD_IO C_A[2] C_A[1] C_A[0] C_D[7] C_D[6] VSS_CORE VDD_CORE C_D[5] C_D[4] C_D[3] C_D[2] C_D[1] VSS_IO VDD_IO C_D[0] C_clk C_notCS C_notWr C_notRd VSS_IO VDD_IO C_notRdy C_notInt MODE[1] MODE[0] SCAN_CLK VSS_CORE VDD_CORE TESTSE RSRXD1 Dir funct in in inout Dir test in outZ outZ outZ outZ outZ outZ outZ outZ in inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout in in in inout out_Hiz out_Hiz in in in in inout in pad type IBUF IBUFDQ BD4CR VSSI VDDI IBUFDQ BD8SCR BD8SCR BD8SCR BD8SCR VSSI VDDI BD8SCR BD8SCR BD8SCR BD8SCR IBUF VSSI VDDI BD8CR BD8CR BD8CR BD8CR BD8CR BD8CR VSSI VDDI BD8CR BD8CR BD8CR BD8CR BD8CR VSSI VDDI BD8CR BD8CR BD8CR BD8CR BD8CR VSSI VDDI BD8CR SCHMITC SCHMITC SCHMITC BD4CR VSSI VDDI BT4CR BT4CR IBUF IBUF SCHMITC VSSI VDDI SCHMITCDQ BD4CR 25 Description receive interface utopia clock 8 kHz clock from network 8 kHz clock to ATM device IO ground IO +3.3V power supply Utopia rx adress bit Utopia rx data bus Utopia rx data bus Utopia rx data bus Utopia rx data bus CORE ground CORE +3.3V power supply Utopia rx data bus Utopia rx data bus Utopia rx data bus Utopia rx data bus sachem hard reset, active low IO ground IO +3.3V power supply Ctrl_E adress bus Ctrl_E adress bus Ctrl_E adress bus Ctrl_E adress bus Ctrl_E adress bus Ctrl_E adress bus IO ground IO +3.3V power supply Ctrl_E adress bus Ctrl_E adress bus Ctrl_E adress bus Ctrl_E data bus Ctrl_E data bus CORE ground CORE +3.3V power supply Ctrl_E data bus Ctrl_E data bus Ctrl_E data bus Ctrl_E data bus Ctrl_E data bus IO ground IO +3.3V power supply Ctrl_E data bus Ctrl_E serial input clock Ctrl_E chip select Ctrl_E write indication Ctrl_E read indication IO ground IO +3.3V power supply Ctrl_E ready indication Ctrl_E interface interrupt select functionnal and test mode select functionnal and test mode scan clock CORE ground CORE +3.3V power supply test scan enable serial Rx port MTC-20146 NO. 168 169 170 171 172 173 174 175 176 Pin Name RSTXD1 C_mode[0] GP TCK VSS_IO VDD_IO nTRST TMS TDO Dir funct inout in inout in Dir test in in in out in in out pad type BD4CR SCHMITCDQ BD4CR IBUFUQ VSSI VDDI IBUFDQ IBUFUQ BT4CR 26 Description serial Tx port Ctrl-E mode signal : 0=motorola, 1=intel carm iddq pin jtag clock IO ground IO +3.3V power supply reset jtag interface test mode select test data o MTC-20146 DQFP208 NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Pin Name TDI CARM_RESETN nCS_0 VSS_IO VDD_IO T_ACK open open T_REQB T_REQA TROM PA[1] PA[0] VSS_CORE VDD_CORE PA14 PA15 E_CLK open open S_nWE S_nRAS VSS_IO VDD_IO S_nCAS S_nLDQM S_nUDQM E_A[15] E_A[14] VSS_IO VDD_IO open open E_A[13] E_A[12] E_A[11] E_A[10] E_A[9] VSS_CORE VDD_CORE E_A[8] E_A[7] E_A[6] E_A[5] E_A[4] open open VSS_IO VDD_IO E_A[3] E_A[2] Dir funct in in out Dir test in pad type IBUFUQ SCHMITC B8CR VSSI VDDI B4CR Description test data in carm reset signal, active low CS signal for flash eprom IO ground IO +3.3V power supply test acknowledge IBUFDQ IBUFDQ SCHMITC BD4CR BD4CR VSSI VDDI BD4CR BD4CR BD8CR test request signal test request signal boot from test Rom select port A bit[1] port A bit[] CORE ground CORE +3.3V power supply download mode select (CTRL-E or UART1) download mode select (UART baudrate) EBI clock B8CR B8CR VSSI VDDI B8CR B8CR B8CR BD8CR BD8CR VSSI VDDI control signal SDRAM control signal SDRAM IO ground IO +3.3V power supply control signal SDRAM control signal SDRAM control signal SDRAM adress bus / testbus MSB adress bus / testbus MSB IO ground IO +3.3V power supply inout inout inout inout inout BD8CR BD8CR BD8CR BD8CR BD8CR VSSI VDDI BD8CR BD8CR BD8CR BD8CR BD8CR adress bus / testbus MSB adress bus / testbus MSB adress bus / testbus MSB adress bus / testbus MSB adress bus / testbus MSB CORE ground CORE +3.3V power supply adress bus / testbus MSB adress bus / testbus MSB adress bus / testbus MSB adress bus / testbus MSB adress bus / testbus MSB inout inout VSSI VDDI BD8CR BD8CR IO ground IO +3.3V power supply adress bus / testbus MSB adress bus / testbus MSB out in in in inout inout inout inout inout inout inout inout out out out out out inout inout inout inout inout inout inout 27 MTC-20146 NO. 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Pin Name E_A[1] E_A[0] E_D[0] E_D[1] VSS_IO VDD_IO E_D[2] E_D[3] E_D[4] E_D[5] E_D[6] VSS_CORE VDD_CORE open open E_D[7] E_D[8] E_D[9] E_D[10] E_D[11] VSS_IO VDD_IO E_D[12] E_D[13] E_D[14] E_D[15] open open S_nOE S_CS VSS_IO VDD_IO AFTXD[3] AFTXD[2] AFTXD[1] AFTXD[0] IDDq_Sachem VSS_CORE VDD_CORE open CTRLDATA MCLK CLWD AFRXD[3] AFRXD[2] U_TxADDR[1] VSS_IO VDD_IO U_TxADDR[3] U_TxADDR[4] AFRXD[1] AFRXD[0] POWER_LOWB Dir funct inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout out out out out out out inout in in in in in in inout Dir test pad type BD8CR BD8CR BD8SCRDQ BD8SCRDQ VSSI VDDI BD8SCRDQ BD8SCRDQ BD8SCRDQ BD8SCRDQ BD8SCRDQ VSSI VDDI Description adress bus / testbus MSB adress bus / testbus MSB data bus / testbus LSB data bus / testbus LSB IO ground IO +3.3V power supply data bus / testbus LSB data bus / testbus LSB data bus / testbus LSB data bus / testbus LSB data bus / testbus LSB CORE ground CORE +3.3V power supply BD8SCRDQ BD8SCRDQ BD8SCRDQ BD8SCRDQ BD8SCRDQ VSSI VDDI BD8SCRDQ BD8SCRDQ BD8SCRDQ BD8SCRDQ data bus / testbus LSB data bus / testbus LSB data bus / testbus LSB data bus / testbus LSB data bus / testbus LSB IO ground IO +3.3V power supply data bus / testbus LSB data bus / testbus LSB data bus / testbus LSB data bus / testbus LSB B8CR B8CR VSSI VDDI B8 B8 B8 B8 output enable chip select signal (SDRAM) IO ground IO +3.3V power supply transmit data nibble transmit data nibble transmit data nibble transmit data nibble VSSI VDDI CORE ground CORE +3.3V power supply BD4CR SCHMITC IBUF IBUF IBUF serial data transmit channel master clock start of word indication receive data nibble receive data nibble VSSI VDDI IO ground IO +3.3V power supply IBUF IBUF BD4CR receive data nibble receive data nibble Power down analog front end 28 MTC-20146 NO. 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 Pin Name U_TxADDR[0] U_TxData[0] U_TxData[1] VSS_IO VDD_IO U_TxADDR[2] open U_TxData[2] U_TxData[3] U_TxData[4] U_TxData[5] U_TxData[6] VSS_CORE VDD_CORE U_TxData[7] U_TxENBB U_TxCLAV U_TxSOC U_TxCLK VSS_IO VDD_IO U_RxENBB U_RxCLAV U_RxSOC U_RxCLK U_TxRefB U_RxRefB open U_RxADDR[1] VSS_IO VDD_IO U_RxADDR[3] U_RxADDR[4] U_RxADDR[0] U_RxData[7] U_RxData[6] U_RxData[5] U_RxData[4] VSS_CORE VDD_CORE U_RxADDR[2] U_RxData[3] U_RxData[2] U_RxData[1] U_RxData[0] open SACHEM_RESETB VSS_IO VDD_IO C_A[8] C_A[7] C_A[6] C_A[5] Dir funct in in in Dir test pad type IBUFDQ IBUF IBUF VSSI VDDI Description utopia tx adress bit utopia tx data bus utopia tx data bus IO ground IO +3.3V power supply IBUF IBUF IBUF IBUF IBUF VSSI VDDI IBUF IBUF BD8SCR IBUF IBUF VSSI VDDI IBUF BD8SCR BD8SCR IBUF IBUFDQ BD4CR utopia tx data bus utopia tx data bus utopia tx data bus utopia tx data bus utopia tx data bus CORE ground CORE +3.3V power supply utopia tx data bus Utopia Tx enable Utopia Tx cell available transmit interface start of cell indication transmit interface utopia clock IO ground IO +3.3V power supply Utopia Rx enable Utopia Rx cell available receive interface start of cell indication receive interface utopia clock 8 kHz clock from network 8 kHz clock to ATM device VSSI VDDI IO ground IO +3.3V power supply in outZ outZ outZ outZ IBUFDQ BD8SCR BD8SCR BD8SCR BD8SCR VSSI VDDI Utopia rx adress bit Utopia rx data bus Utopia rx data bus Utopia rx data bus Utopia rx data bus CORE ground CORE +3.3V power supply outZ outZ outZ outZ BD8SCR BD8SCR BD8SCR BD8SCR Utopia Utopia Utopia Utopia in IBUF VSSI VDDI BD8CR BD8CR BD8CR BD8CR sachem hard reset, active low IO ground IO +3.3V power supply Ctrl_E adress bus Ctrl_E adress bus Ctrl_E adress bus Ctrl_E adress bus in in in in in in in inout in in in inout inout in in inout inout inout inout inout inout inout inout inout 29 rx rx rx rx data data data data bus bus bus bus MTC-20146 NO. 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Pin Name C_A[4] C_A[3] VSS_IO VDD_IO open open C_A[2] C_A[1] C_A[0] C_D[7] C_D[6] VSS_CORE VDD_CORE C_D[5] C_D[4] C_D[3] C_D[2] C_D[1] open open VSS_IO VDD_IO C_D[0] C_clk C_notCS C_notWr C_notRd C_mode[1] VSS_IO VDD_IO C_notRdy open C_notInt MODE[1] MODE[0] SCAN_CLK VSS_CORE VDD_CORE TESTSE RSRXD1 RSTXD1 open open C_mode[0] IDDq_CARM TCK VSS_IO VDD_IO nTRST TMS TDO Dir funct inout inout Dir test inout inout pad type BD8CR BD8CR VSSI VDDI Description Ctrl_E adress bus Ctrl_E adress bus IO ground IO +3.3V power supply inout inout inout inout inout inout inout inout inout inout inout inout inout inout BD8CR BD8CR BD8CR BD8CR BD8CR VSSI VDDI BD8CR BD8CR BD8CR BD8CR BD8CR Ctrl_E adress bus Ctrl_E adress bus Ctrl_E adress bus Ctrl_E data bus Ctrl_E data bus CORE ground CORE +3.3V power supply Ctrl_E data bus Ctrl_E data bus Ctrl_E data bus Ctrl_E data bus Ctrl_E data bus inout in in in inout VSSI VDDI BD8CR SCHMITC SCHMITC SCHMITC BD4CR IO ground IO +3.3V power supply Ctrl_E data bus Ctrl_E serial input clock Ctrl_E chip select Ctrl_E write indication Ctrl_E read indication out_Hiz VSSI VDDI BT4CR IO ground IO +3.3V power supply Ctrl_E ready indication BT4CR IBUF IBUF SCHMITC VSSI VDDI SCHMITCDQ BD4CR BD4CR Ctrl_E interface interrupt select functionnal and test mode select functionnal and test mode scan clock CORE ground CORE +3.3V power supply test scan enable serial Rx port serial Tx port SCHMITCDQ Ctrl-E mode signal : =motorola, 1=intel IBUFUQ VSSI VDDI IBUFDQ IBUFUQ BT4CR jtag clock IO ground IO +3.3V power supply reset jtag interface test mode select test data out inout inout out_Hiz in in in in inout inout in in in in in in out in in out 30 MTC-20146 31 MTC-20146 Alcatel Microelectronics acknowledges the trademarks of all companies referred to in this document. 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