1.5 GHz, Ultrahigh Speed Op Amp
Data Sheet AD8000
Rev. C Document Feedback
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FEATURES
High speed
1.5 GHz, −3 dB bandwidth (G = +1)
650 MHz, full power bandwidth (G = +2, VO = 2 V p-p)
Slew rate: 4100 V/μs
0.1% settling time: 12 ns
Excellent video specifications
0.1 dB flatness: 170 MHz
Differential gain: 0.02%
Differential phase: 0.01°
Output overdrive recovery: 22 ns
Low noise: 1.6 nV/√Hz input voltage noise
Low distortion over wide bandwidth
75 dBc SFDR at 20 MHz
62 dBc SFDR at 50 MHz
Input offset voltage: 1 mV typical
High output current: 100 mA
Wide supply voltage range: 4.5 V to 12 V
Supply current: 13.5 mA
Power-down mode
APPLICATIONS
Professional video
High speed instrumentation
Video switching
IF/RF gain stage
CCD imaging
GENERAL DESCRIPTION
The AD8000 is an ultrahigh speed, high performance, current
feedback amplifier. Using Analog Devices, Inc., proprietary
eXtra Fast Complementary Bipolar (XFCB) process, the ampli-
fier can achieve a small signal bandwidth of 1.5 GHz and a slew
rate of 4100 V/μs.
The AD8000 has low spurious-free dynamic range (SFDR) of
75 dBc at 20 MHz and input voltage noise of 1.6 nV/√Hz. The
AD8000 can drive over 100 mA of load current with minimal
distortion. The amplifier can operate on +5 V to ±6 V. These
specifications make the AD8000 ideal for a variety of applica-
tions, including high speed instrumentation.
With a differential gain of 0.02%, differential phase of 0.01°, and
0.1 dB flatness out to 170 MHz, the AD8000 has excellent video
specifications, which ensure that even the most demanding
video systems maintain excellent fidelity.
CONNECTION DIAGRAMS
05321-001
POWER DOWN
FEEDBACK
–IN
+IN
OUTPUT
+V
S
NC
–V
S
AD8000
TOP VIEW
(Not to Scale)
NOTES
1. NC = NO CO NNE CT .
2. THE EXPOSED PADDLE IS CO NNECT E D T O GR O UND.
3
4
1
2
6
5
8
7
Figure 1. 8-Lead AD8000, 3 mm × 3 mm LFCSP (CP-8-13)
05321-002
NOTES
1. NC = NO CO NNECT .
2. THE EXPO SE D PADDLE IS CO NNECTED T O G RO UND.
FEEDBACK 1
–IN 2
+IN 3
–V
S
4
POW ER DOWN
8
+V
S
7
OUTPUT
6
NC
5
AD8000
TOP VI EW
(No t to Scale)
Figure 2. 8-Lead AD8000 SOIC_N_EP (RD-8-1)
The AD8000 power-down mode reduces the supply current to
1.3 mA. The amplifier is available in a tiny 8-lead LFCSP package,
as well as in an 8-lead SOIC package. The AD8000 is rated to work
over the extended industrial temperature range (−40°C to +125°C).
A triple version of the AD8000 (AD8003) is underdevelopment.
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
NORMALIZED GAIN (dB)
05321-003
FREQUENCY (MHz)
1 10010 1000
VS = 5V
RL = 150
VOUT = 2V p-p
G = +2, RF = 432
Figure 3. Large Signal Frequency Response
AD8000 Data Sheet
Rev. C | Page 2 of 17
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Connection Diagrams ...................................................................... 1
Revision History ............................................................................... 2
Specifications with ±5 V Supply ..................................................... 3
Specifications with +5 V Supply ..................................................... 4
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
Maximum Power Dissipation ..................................................... 5
ESD Caution .................................................................................. 5
Typical Performance Characteristics ............................................. 6
Test Circuits ..................................................................................... 13
Applications Information .............................................................. 14
Circuit Configurations .............................................................. 14
Video Line Driver ....................................................................... 14
Low Distortion Pinout ............................................................... 15
Exposed Paddle ........................................................................... 15
Printed Circuit Board Layout ................................................... 15
Signal Routing ............................................................................. 15
Power Supply Bypassing ............................................................ 15
Grounding ................................................................................... 16
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 17
REVISION HISTORY
5/16—Rev. B to Rev. C
Changed CP-8-2 to CP-8-13 ........................................ Throughout
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 17
3/13—Rev. A to Rev. B
Changes to Figure 1 and Figure 2 ................................................... 1
Change to Table 1 ............................................................................. 3
Changes to Table2 ............................................................................. 4
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 17
3/10—Rev. 0 to Rev. A
Changes to Figure 1 and Figure 2 ................................................... 1
Changes to Table 3 ............................................................................ 5
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 17
1/05—Rev. 0: Initial Version
Data Sheet AD8000
Rev. C | Page 3 of 17
SPECIFICATIONS WITH ±5 V SUPPLY
At TA = 25°C, VS = ±5 V, RL = 150 Ω, Gain = +2, RF = RG = 432 Ω, unless otherwise noted. Connect the exposed paddle to ground.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth G = +1, VO = 0.2 V p-p, SOIC/LFCSP 1580/1350 MHz
G = +2, VO = 2 V p-p, SOIC/LFCSP 650/610 MHz
Bandwidth for 0.1 dB Flatness VO = 2 V p-p, SOIC/LFCSP 190/170 MHz
Slew Rate G = +2, VO = 4 V step 4100 V/μs
Settling Time to 0.1% G = +2, VO = 2 V step 12 ns
NOISE/HARMONIC PERFORMANCE
Second/Third Harmonic VO = 2 V p-p, f = 5 MHz, LFCSP only 86/89 dBc
Second/Third Harmonic VO = 2 V p-p, f = 20 MHz, LFCSP only 75/79 dBc
Input Voltage Noise f = 100 kHz 1.6 nV/√Hz
Input Current Noise f = 100 kHz, −IN 26 pA/√Hz
f = 100 kHz, +IN 3.4 pA/√Hz
Differential Gain Error NTSC, G = +2 0.02 %
Differential Phase Error NTSC, G = +2 0.01 Degree
DC PERFORMANCE
Input Offset Voltage 1 10 mV
Input Offset Voltage Drift 11 μV/°C
Input Bias Current (Enabled) +IB −5 +4 μA
−IB −3 +45 μA
Transimpedance 570 890 1600 kΩ
INPUT CHARACTERISTICS
Noninverting Input Impedance 2/3.6 MΩ/pF
Input Common-Mode Voltage Range −3.5 to +3.5 V
Common-Mode Rejection Ratio VCM = ±2.5 V −52 −54 −56 dB
Overdrive Recovery G = +1, f = 1 MHz, triangle wave 30 ns
POWER DOWN PIN
Power-Down Input Voltage Power-down < +VS – 3.1 V
Enabled > +VS – 1.9 V
Turn-Off Time 50% of power-down voltage to
10% of VOUT final, VIN = 0.3 V p-p
150 ns
Turn-On Time 50% of power-down voltage to
90% of VOUT final, VIN = 0.3 V p-p
300 ns
Input Bias Current
Enabled −1.1 +0.17 +1.4 μA
Power-Down −300 −235 −160 μA
OUTPUT CHARACTERISTICS
Output Voltage Swing RL = 100 Ω ±3.7 ±3.9 V
Output Voltage Swing RL = 1 kΩ ±3.9 ±4.1 V
Linear Output Current VO = 2 V p-p, second HD < −50 dBc 100 mA
Overdrive Recovery G = + 2, f = 1 MHz, triangle wave 45 ns
G = +2, VIN = 2.5 V to 0 V step 22 ns
POWER SUPPLY
Operating Range 4.5 12 V
Quiescent Current 12.7 13.5 14.3 mA
Quiescent Current (Power-Down) 1.1 1.3 1.65 mA
Power Supply Rejection Ratio −PSRR/+PSRR −56/−61 −59/−63 dB
AD8000 Data Sheet
Rev. C | Page 4 of 17
SPECIFICATIONS WITH +5 V SUPPLY
At TA = 25°C, VS = 5 V, RL = 150 Ω, Gain = +2, RF = RG = 432 Ω, unless otherwise noted. Connect the exposed paddle to ground.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth G = +1, VO = 0.2 V p-p 980 MHz
G = +2, VO = 2 V p-p 477 MHz
G = +10, VO = 0.2 V p-p 328 MHz
Bandwidth for 0.1 dB Flatness VO = 0.2 V p-p 136 MHz
V
O = 2 V p-p 136 MHz
Slew Rate G = +2, VO = 2 V step 2700 V/μs
Settling Time to 0.1% G = +2, VO = 2 V step 16 ns
NOISE/HARMONIC PERFORMANCE
Second/Third Harmonic VO = 2 V p-p, 5 MHz, LFCSP only 71/71 dBc
Second/Third Harmonic VO = 2 V p-p, 20 MHz, LFCSP only 60/62 dBc
Input Voltage Noise f = 100 kHz 1.6 nV/√Hz
Input Current Noise f = 100 kHz, −IN 26 pA/√Hz
f = 100 kHz, +IN 3.4 pA/√Hz
Differential Gain Error NTSC, G = +2 0.01 %
Differential Phase Error NTSC, G = +2 0.06 Degree
DC PERFORMANCE
Input Offset Voltage 1.3 10 mV
Input Offset Voltage Drift 18 μV/°C
Input Bias Current (Enabled) +IB −5 +3 μA
−IB −1 +45 μA
Transimpedance 440 800 1500 kΩ
INPUT CHARACTERISTICS
Noninverting Input Impedance 2/3.6 MΩ/pF
Input Common-Mode Voltage Range 1.5 to 3.6 V
Common-Mode Rejection Ratio VCM = ±2.5 V −51 −52 −54 dB
Overdrive Recovery G = +1, f = 1 MHz, triangle wave 60 ns
POWER DOWN PIN
Power-Down Input Voltage Power-down < +VS − 3.1 V
Enable > +VS − 1.9 V
Turn-Off Time 50% of power-down voltage to
10% of VOUT final, VIN = 0.3 V p-p
200 ns
Turn-On Time 50% of power-down voltage to
90% of VOUT final, VIN = 0.3 V p-p
300 ns
Input Current
Enabled −1.1 +0.17 +1.4 μA
Power-Down −50 −40 −30 μA
OUTPUT CHARACTERISTICS
Output Voltage Swing RL = 100 Ω 1.1 to 3.9 1.05 to 4.1 V
R
L = 1 kΩ 1 to 4.0 0.85 to 4.15 V
Linear Output Current VO = 2 V p-p, second HD < −50 dBc 70 mA
Overdrive Recovery G = +2, f = 100 kHz, triangle wave 65 ns
POWER SUPPLY
Operating Range 4.5 12 V
Quiescent Current 11 12 13 mA
Quiescent Current (Power-Down) 0.7 0.95 1.25 mA
Power Supply Rejection Ratio −PSRR/+PSRR −55/−60 −57/−62 dB
Data Sheet AD8000
Rev. C | Page 5 of 17
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage 12.6 V
Power Dissipation See Figure 4
Common-Mode Input Voltage Range −VS − 0.7 V to +VS + 0.7 V
Differential Input Voltage VS
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +125°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any
other conditions above those indicated in the operational section of
this specification is not implied. Operation beyond the maximum
operating conditions for extended periods may affect product
reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is speci-
fied for device soldered in the circuit board for surface-mount
packages.
Table 4. Thermal Resistance
Package Type θJA θ
JC Unit
8-Lead SOIC 80 30 °C/W
3 mm × 3 mm LFCSP 93 35 °C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation for the AD8000 is limited
by the associated rise in junction temperature (TJ) on the die. At
approximately 150C, which is the glass transition temperature,
the properties of the plastic change. Even temporarily exceeding
this temperature limit can change the stresses that the package
exerts on the die, permanently shifting the parametric performance
of the AD8000. Exceeding a junction temperature of 175C for
an extended period of time can result in changes in silicon de-
vices, potentially causing degradation or loss of functionality.
The power dissipated in the package (PD) is the sum of the qui-
escent power dissipation and the power dissipated in the die
due to the AD8000 drive at the output. The quiescent power is
the voltage between the supply pins (VS) times the quiescent
current (IS).
PD = Quiescent Power + (Total Drive Power − Load Power)
L
2
OUT
L
OUTS
SS
DR
V
–
R
V
2
V
IVP
Consider the RMS output voltages. If RL is referenced to −VS, as
in single-supply operation, the total drive power is VS × IOUT. If
the rms signal levels are indeterminate, consider the worst case,
when VOUT = VS/4 for RL to midsupply.
L
S
SS
DR
/V
IVP
2
4
In single-supply operation with RL referenced to −VS, worst case
is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA. Also,
more metal directly in contact with the package leads and exposed
paddle from metal traces, through holes, ground, and power
planes reduces θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the exposed paddle
SOIC (80°C/W) and the LFCSP (93°C/W) package on a JEDEC
standard 4-layer board. θJA values are approximations.
0
0.5
1.0
1.5
2.0
2.5
3.0
MAXIMUM POWER DISSIPATION (W)
05321-063
–30 –20 –10 0 10 20 40 8030 50 60 70 10090 120110
AMBIENT TEMPERATURE (C)
SOIC
LFCSP
–40
Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
AD8000 Data Sheet
Rev. C | Page 6 of 17
TYPICAL PERFORMANCE CHARACTERISTICS
NORMALIZED GAIN (dB)
FREQUENCY (MHz)
101 100 1000
05321-006
–7
–6
–5
–4
–3
–2
–1
0
1
2
3V
S
= 5V
R
L
= 150
V
OUT
= 200mV p-p G = +1, R
F
= 432
G = +2, R
F
= 432, R
G
= 432
G = +10, R
F
= 357, R
G
= 40.2
Figure 5. Small Signal Frequency Response vs. Various Gains
NORMALIZED GAIN (dB)
FREQUENCY (MHz)
101 100 1000
05321-007
–7
–6
–5
–4
–3
–2
–1
0
1
2
3V
S
= 5V
R
L
= 150
V
OUT
= 200mV p-p
G = –1, R
F
= R
G
= 249
G = –2, R
F
= 432, R
G
= 215
G = –10, R
F
= 432, R
G
= 43.2
Figure 6. Small Signal Frequency Response vs. Various Gains
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
NORMALIZED GAIN (dB)
05321-008
FREQUENCY (MHz)
1 10010 1000
VS = 5V
RL = 150
VOUT = 2V p-p
G = +1, RF = 432
G = +2, RF = RG = 432
G = +4, RF = 357, RG = 121
G = +10, RF = 357, RG = 40.2
Figure 7. Large Signal Frequency Response vs. Various Gains
–3
0
3
6
9
GAIN (dB)
FREQUENCY (MHz)
101 100 1000
05321-011
V
S
= 5V
G = +2
R
L
= 150
V
OUT
= 200mV p-p
LFCSP
R
F
= 392
R
F
= 432
R
F
= 487
Figure 8. Small Signal Frequency Response vs. RF
–3
0
3
6
9
GAIN (dB)
FREQUENCY (MHz)
101 100 1000
05321-012
R
F
= 392
R
F
= 432
R
F
= 487
V
S
= 5V
G = +2
R
L
= 150
V
OUT
= 2V p-p
LFCSP
Figure 9. Large Signal Frequency Response vs. RF
TRANSIMPEDANCE (k)
05321-027
FREQUENCY (MHz)
PHASE (Degrees)
0.1
1
10
100
1000
0.1 1 10 100 1000 10000
TZ
PHASE
50
0
50
100
150
100
200
V
S
= 5V
R
L
= 100
Figure 10. Transimpedance and Phase vs. Frequency
Data Sheet AD8000
Rev. C | Page 7 of 17
GAIN (dB)
05321-010
FREQUENCY (MHz)
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
0.1 1 10 100 1000
R
L
= 1k
G = +1
R
F
= 432
V
OUT
= 200mV p-p
LFCSP
V
S
= +5V, R
S
= 0
V
S
= 5V, R
S
= 50
V
S
= +5V, R
S
= 50
V
S
= 5V, R
S
= 0
Figure 11. Small Signal Frequency Response vs. Supply Voltage
–9
–6
–3
0
3
6
9
GAIN (dB)
FREQUENCY (MHz)
101 100 1000
05321-009
R
L
= 150
G = +1
R
F
= 432
V
OUT
= 200mV p-p
LFCSP V
S
= 5V
V
S
= +5V
Figure 12. Small Signal Frequency Response vs. Supply Voltage
5.5
5.6
5.7
5.8
5.9
6.0
6.1
6.2
6.3
6.4
6.5
GAIN (dB)
05321-013
FREQUENCY (MHz)
1 10010
VS = 5V
RL = 150
VOUT = 2V p-p
G = +2
RF = 432
SOIC
LFCSP
Figure 13. 0.1 dB Flatness
–3
0
3
6
9
GAIN (dB)
FREQUENCY (MHz)
101 100 1000
05321-014
V
S
= 5V
G = +2
R
L
= 150
V
OUT
= 200mV p-p
LFCSP
–40C
+125C
+25C
Figure 14. Small Signal Frequency Response vs. Temperature
–3
0
3
6
9
GAIN (dB)
FREQUENCY (MHz)
101 100 1000
05321-015
V
S
= 5V
G = +2
R
L
= 1k
V
OUT
= 200mV p-p
LFCSP
–40C
+125C
+25C
Figure 15. Small Signal Frequency Response vs. Temperature
–3
0
3
6
9
GAIN (dB)
FREQUENCY (MHz)
101 100 1000
05321-016
V
S
= 5V
G = +2
R
L
= 150
V
OUT
= 2V p-p
LFCSP
+125C
+25C
–40C
Figure 16. Large Signal Frequency Response vs. Temperature
AD8000 Data Sheet
Rev. C | Page 8 of 17
–3
0
3
6
9
GAIN (dB)
FREQUENCY (MHz)
101 100 1000
05321-017
V
S
= 5V
G = +2
R
L
= 150
LFCSP
V
OUT
= 1V p-p
V
OUT
= 4V p-p
V
OUT
= 2V p-p
Figure 17. Large Signal Frequency Response vs. Various Outputs
–120
–110
–100
–90
–80
–70
DISTORTION (dBc)
–60
–50
–40
05321-040
FREQUENCY (MHz)
1 10 100
SECOND HD
THIRD HD
VS = 5V
VOUT = 2V p-p
G = +1
RL = 150
LFCSP
Figure 18. Harmonic Distortion vs. Frequency
–120
–110
–100
–90
–80
–70
DISTORTION (dBc)
–60
–50
–40
05321-039
FREQUENCY (MHz)
1 10 100
SECOND HD
THIRD HD
V
S
= 5V
G = +10
V
OUT
= 2V p-p
R
L
= 1k
LFCSP
Figure 19. Harmonic Distortion vs. Frequency
–120
–110
–100
–90
–80
–70
DISTORTION (dBc)
–60
–50
–
40
05321-042
FREQUENCY (MHz)
1 10 100
SECOND HD
THIRD HD
V
S
= 5V
V
OUT
= 2V p-p
G = +1
R
L
= 1k
LFCSP
Figure 20. Harmonic Distortion vs. Frequency
–100
–90
–80
–70
–60
–50
DISTORTION (dBc)
–40
–30
–20
05321-041
FREQUENCY (MHz)
1 10 100
SECOND HD
THIRD HD
V
S
= 5V
V
OUT
= 4V p-p
G = +1
R
L
= 1k
LFCSP
Figure 21. Harmonic Distortion vs. Frequency
–100
–90
–80
–70
DISTORTION (dBc)
–60
–50
–
40
05321-043
FREQUENCY (MHz)
1 10 100
V
S
= 5V
V
OUT
= 2V p-p
G = +2
R
L
= 150
SOIC SECOND HD
LFCSP SECOND HD
LFCSP THIRD HD
SOIC THIRD HD
Figure 22. Harmonic Distortion vs. Frequency
Data Sheet AD8000
Rev. C | Page 9 of 17
DISTORTION (dBc)
05321-044
FREQUENCY (MHz)
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
1 10 100
V
S
= 5V
V
OUT
= 2V p-p
G = +2
R
L
= 150
LFCSP SECOND HD
THIRD HD
Figure 23. Harmonic Distortion vs. Frequency
–100
–90
–80
–70
–60
–50
DISTORTION (dBc)
–40
–30
–20
05321-045
FREQUENCY (MHz)
1 10 100
V
S
= 5V
V
OUT
= 2V p-p
G = +2
R
L
= 1k
LFCSP
SECOND HD
THIRD HD
Figure 24. Harmonic Distortion vs. Frequency
DISTORTION (dBc)
05321-047
FREQUENCY (MHz)
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
1 10 100
V
S
= 5V
V
OUT
= 2V p-p
G = +2
R
L
= 1k
LFCSP
SECOND HD
THIRD HD
Figure 25. Harmonic Distortion vs. Frequency
DISTORTION (dBc)
05321-048
FREQUENCY (MHz)
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
1 10 100
SECOND HD
THIRD HD
V
S
= 2.5V
V
OUT
= 2V p-p
G = –1
R
L
= 150
LFCSP
Figure 26. Harmonic Distortion vs. Frequency
DISTORTION (dBc)
05321-049
FREQUENCY (MHz)
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
1 10 100
SECOND HD
THIRD HD
V
S
= 5V
V
OUT
= 2V p-p
G = –1
R
L
= 1k
LFCSP
Figure 27. Harmonic Distortion vs. Frequency
–110
–100
–90
–80
–70
DISTORTION (dBc)
–60
–50
–40
05321-050
FREQUENCY (MHz)
1 10 100
V
S
= 5V
V
OUT
= 2V p-p
G = –1
R
L
= 150
LFCSP
SECOND HD
THIRD HD
Figure 28. Harmonic Distortion vs. Frequency
AD8000 Data Sheet
Rev. C | Page 10 of 17
–120
–110
–100
–90
–80
–70
DISTORTION (dBc)
–60
–50
–
40
05321-051
FREQUENCY (MHz)
1 10 100
SECOND HD
THIRD HD
V
S
= 5V
V
OUT
= 2V p-p
G = –1
R
L
= 1k
LFCSP
Figure 29. Harmonic Distortion vs. Frequency
0.01
0.1
1
10
100
1k
IMPEDANCE (
)
FREQUENCY (MHz)
10.1 10 100 1000
05321-023
V
S
= 5V
V
IN
= 0.2V p-p
R
F
= 432
LFCSP
G = +1
OR G = +2
Figure 30. Output Impedance vs. Frequency
2.35
2.40
2.45
2.50
2.55
2.60
2.65
RESPONSE (V)
0 5 10 15 20 25 30 35 40 45 50
TIME (ns)
05321-072
G = +2
G = +1
V
S
= 5V
R
F
= 432
R
S
= 0
R
L
= 100
Figure 31. Small Signal Transient Response
PSRR (dB)
FREQUENCY (MHz)
10.1 10 100
05321-021
–75
–70
–60
–40
–30
–20
–15
–10
–50
–65
–45
–35
–25
–55
V
S
= 5V
V
IN
= 2V p-p
R
L
= 100
G = +1
R
F
= 432–PSRR
+PSRR
Figure 32. Power Supply Rejection Ratio (PSRR) vs. Frequency
CMRR (dB)
05321-031
FREQUENCY (MHz)
10.1 10 100 1000
–60
–40
–30
–50
–65
–45
–35
–25
–55
V
S
= 5V
V
IN
= 1V p-p
R
L
= 100
LFCSP
Figure 33. Common-Mode Rejection Ratio vs. Frequency
–0.150
–0.125
–0.075
0.025
0.075
0.125
0.150
0.175
–0.025
–0.100
0
0.050
0.100
–0.050
RESPONSE (V)
TIME (ns)
05321-066
–0.175 0 5 10 15 20 25 30 35 40 45 50
G = +1
G = +2
VS = 5V
RF = 432
RS = 0
RL = 100
Figure 34. Small Signal Transient Response
Data Sheet AD8000
Rev. C | Page 11 of 17
–1.50
–1.25
–0.75
0.25
0.75
1.25
1.50
1.75
–0.25
–1.00
0
0.50
1.00
–0.50
RESPONSE (V)
TIME (ns)
0 5 10 15 20 25 30 35 40 45 50
05321-067
–1.75
G = +1
G = +2
VS = 5V
RF = 432
RS = 0
RL = 100
Figure 35. Large Signal Transient Response
–0.5
–0.4
–0.3
–0.2
–0.1
0
SETTLING TIME (%)
0.1
0.2
0.3
V
CM
(V)
05321-068
–5 –4 –3 –2 –1 0 1 2 3
0.4
0.5
V
IN
G = +2
5ns/DIV
t
= 0s
1V
Figure 36. Settling Time
0
1k
2k
3k
4k
5k
6k
SR (V/s)
01234567
V
OUT
(V p-p)
05321-018
G = +2
R
F
= 432
R
L
= 150
LFCSP, V
S
= +5V
SOIC, V
S
= 5V
LFCSP, V
S
= 5V
SOIC, V
S
= +5V
Figure 37. Slew Rate vs. Output Level
–5
–4
–3
–2
–1
0
1
2
3
4
5
OUTPUT VOLTAGE (V)
0 200 400 600 800 1000
TIME (ns)
05321-019
G = +1
R
L
= 150
R
F
= 432
V
S
= 2.5V, V
OUT
V
S
= 2.5V, V
IN
V
S
= 5V, V
OUT
V
S
= 5V, V
IN
Figure 38. Input Overdrive
–6
–4
–2
–3
–5
0
–1
OUTPUT VOLTAGE (V)
2
1
4
3
6
5
0 200 400 600 800 1000
TIME (ns)
05321-020
G = +2
R
L
= 150
R
F
= 432
V
S
= 2.5V, V
OUT
V
S
= 2.5V, 2 V
IN
V
S
= 5V, V
OUT
V
S
= 5V, 2 V
IN
Figure 39. Output Overdrive
INPUT VOLTAGE NOISE (nV/ Hz)
05321-058
FREQUENCY (Hz)
0.1
10
1
100
100k10k100 1k10 1M 10M 100M
V
S
= 5V
G = +10
R
F
= 432
R
N
= 47.5
Figure 40. Input Voltage Noise
AD8000 Data Sheet
Rev. C | Page 12 of 17
INPUT CURRENT NOISE (pA/ Hz)
05321-055
FREQUENCY (Hz)
0.1
1
10
100
1000
100k10k100 1k10 1M 10M 100M 1G
V
S
= 5V
INVERTING CURRENT NOISE, R
F
= 1k
NONINVERTING CURRENT NOISE, R
F
= 432
Figure 41. Input Current Noise
–20
–15
–10
–5
0
5
V
OS
(mV)
10
15
20
V
CM
(V)
05321-024
–5 –4 –3 –2 –1 0 1 2 3 4 5
V
S
= +5V
V
S
= 5V
Figure 42. Input VOS vs. Common-Mode Voltage
–25
–20
–15
–10
–5
0
5
10
15
20
25
I
B
(
A)
–5 –4 –3 –2 –1 0 1 2 3 4 5
V
OUT
(V)
05321-069
V
S
= +5V
V
S
= 5V
Figure 43. Input Bias Current vs. Output Voltage
–5 –4 –3 –2 –1 0 1 2 3 4 5
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
I
B
(A)
05321-070
V
CM
(V)
V
S
= +5V
V
S
= 5V
Figure 44. Input Bias Current vs. Common-Mode Voltage
S22 (dB)
05321-065
FREQUENCY (MHz)
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
10 100 1000
R
BACK
TERM = 50
V
S
= 5V
G = +2
P
OUT
= –10dBm
SOIC
Figure 45. Output Voltage Standing Wave Ratio (S22)
S11 (dB)
05321-064
FREQUENCY (MHz)
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
10 100 1000
INPUT R
S
= 0
V
S
= 5V
P
OUT
= –10dBm
SOIC
G = +10
G = +1
G = +2
Figure 46. Input Voltage Standing Wave Ratio (S11)
Data Sheet AD8000
Rev. C | Page 13 of 17
TEST CIRCUITS
AD8000
50
TRANSMISSION
LINE
200
R
F
432
432
200
10F
0.1F
49.9
–V
S
0.1F
10F
05321-028
50
TRANSMISSION
LINE
+V
S
49.9
60.4
V
IN
Figure 47. CMRR
49.9
TERMINATION
50
0.1F
10F
–V
S
V
P
= V
S
+ V
IN
R
F
432
R
G
432
49.9
AD8000
49.9
50
TRANSMISSION
LINE
05321-029
50
TRANSMISSION
LINE
TERMINATION
50
Figure 48. Positive PSRR
49.9TERMINATION
50
+V
S
V
N
=–V
S
+ V
IN
R
F
432
R
G
432
49.9
AD8000
49.9
10F
0.1F
50
TRANSMISSION
LINE
05321-030
50
TRANSMISSION
LINE
T
ERMINATION
50
Figure 49. Negative PSRR
AD8000 Data Sheet
Rev. C | Page 14 of 17
APPLICATIONS INFORMATION
All current feedback amplifier operational amplifiers are affected
by stray capacitance at the inverting input pin. As a practical
consideration, the higher the stray capacitance on the inverting
input to ground, the higher RF needs to be to minimize peaking
and ringing.
CIRCUIT CONFIGURATIONS
Figure 50 and Figure 51 show typical schematics for noninverting
and inverting configurations. For current feedback amplifiers,
the value of feedback resistance determines the stability and
bandwidth of the amplifier. The optimum performance values
are shown in Table 5 and should not be deviated from by more
than ±10% to ensure stable operation. Figure 8 shows the influence
varying RF has on bandwidth. In noninverting unity-gain
configurations, it is recommended that an RS of 50 Ω be used,
as shown in Figure 50.
Table 5 provides a quick reference for the circuit values, gain,
and output voltage noise.
FB
AD8000
10F
0.1F
R
G
R
S
+V
S
V
O
V
IN
R
L
–
+V
O
+V
–V
S
–V
10F
0.1F
R
F
+
+
NONINVERTING
05321-035
Figure 50. Noninverting Configuration
FB
AD8000
10F
0.1F
RG
+VS
VO
V
IN
RL
–
+VO
+V
–VS
–V
10F
0.1F
RF+
+
05321-036
Figure 51. Inverting Configuration
VIDEO LINE DRIVER
The AD8000 is designed to offer outstanding performance as a
video line driver. The important specifications of differential
gain (0.02%), differential phase (0.01°), and 650 MHz bandwidth at
2 V p-p meet the most exacting video demands. Figure 52 shows a
typical noninverting video driver with a gain of +2.
432
432
75
CABLE
75
75VOUT
+VS
–VS
V
IN
0.1F
4.7F
AD8000
0.1F
4.7F
75
CABLE
75
+
+
+
05321-071
FB
Figure 52. Video Line Driver
Table 5. Typical Values (LFCSP/SOIC)
Gain
Component
Values (Ω)
−3 dB SS Bandwidth
(MHz)
−3 dB LS Bandwidth
(MHz)
Slew Rate
(V/μs)
Output Noise
(nV/√Hz)
Total Output Noise Including
Resistors (nV/√Hz)
RF R
G LFCSP SOIC LFCSP SOIC
1 432 1380 1580 550 600 2200 10.9 11.2
2 432 432 600 650 610 650 3700 11.3 11.9
4 357 120 550 550 350 350 3800 10 12
10 357 40 350 365 370 370 3200 18.4 19.9
Data Sheet AD8000
Rev. C | Page 15 of 17
LOW DISTORTION PINOUT
The AD8000 LFCSP features Analog Devices low distortion
pinout. The new pinout lowers the second harmonic distortion
and simplifies the circuit layout. The close proximity of the
non-inverting input and the negative supply pin creates a source
of second harmonic distortion. Physical separation of the non-
inverting input pin and the negative power supply pin reduces
this distortion significantly, as seen in Figure 22.
By providing an additional output pin, the feedback resistor can
be connected directly across Pin 2 and Pin 3. This greatly simplifies
the routing of the feedback resistor and allows a more compact
circuit layout, which reduces its size and helps to minimize
parasitics and increase stability.
The SOIC also features a dedicated feedback pin. The feedback
pin is brought out on Pin 1, which is typically a no connect on
standard SOIC pinouts.
Existing applications that use the standard SOIC pinout can
take full advantage of the performance offered by the AD8000.
For drop-in replacements, ensure that Pin 1 is not connected to
ground or to any other potential because this pin is connected
internally to the output of the amplifier. For existing designs,
Pin 6 can still be used for the feedback resistor.
EXPOSED PADDLE
The AD8000 features an exposed paddle, which can lower the
thermal resistance by 25% compared to a standard SOIC plastic
package. The paddle can be soldered directly to the ground plane
of the board. Figure 53 shows a typical pad geometry for the LFCSP,
the same type of pad geometry can be applied to the SOIC package.
Thermal vias or heat pipes can also be incorporated into the design
of the mounting pad for the exposed paddle. These additional
vias improve the thermal transfer from the package to the PCB.
Using a heavier weight copper on the surface to which the exposed
paddle of the amplifier is soldered also reduces the overall
thermal resistance seen by the AD8000.
05321-034
Figure 53. LFCSP Exposed Paddle Layout
PRINTED CIRCUIT BOARD LAYOUT
Laying out the printed circuit board (PCB) is usually the last
step in the design process and often proves to be one of the
most critical. A brilliant design can be rendered useless because
of a poor or sloppy layout. Because the AD8000 can operate
into the RF frequency spectrum, high frequency board layout
considerations must be taken into account. The PCB layout,
signal routing, power supply bypassing, and grounding all must
be addressed to ensure optimal performance.
SIGNAL ROUTING
The AD8000 LFCSP features the new low distortion pinout with a
dedicated feedback pin and allows a compact layout. The dedicated
feedback pin reduces the distance from the output to the inverting
input, which greatly simplifies the routing of the feedback network.
To minimize parasitic inductances, use ground planes under
high frequency signal traces. However, remove the ground
plane from under the input and output pins to minimize the
formation of parasitic capacitors, which degrades phase margin.
Run signals that are susceptible to noise pickup on the internal
layers of the PCB, which can provide maximum shielding.
POWER SUPPLY BYPASSING
Power supply bypassing is a critical aspect of the PCB design
process. For best performance, the AD8000 power supply pins
need to be properly bypassed.
A parallel connection of capacitors from each of the power supply
pins to ground works best. Paralleling different values and sizes
of capacitors helps to ensure that the power supply pins see a
low ac impedance across a wide band of frequencies. This is
important for minimizing the coupling of noise into the amplifier.
Starting directly at the power supply pins, place the smallest
value and sized component on the same side of the board as the
amplifier, and as close as possible to the amplifier, and connected
to the ground plane. Repeat this process for the next larger value
capacitor. It is recommended for the AD8000 that a 0.1 μF ceramic
0508 case be used. The 0508 offers low series inductance and
excellent high frequency performance. The 0.1 μF case provides
low impedance at high frequencies. Place a 10 μF electrolytic
capacitor in parallel with the 0.1 μF. The 10 μF capacitor provides
low ac impedance at low frequencies. Smaller values of electrolytic
capacitors can be used, depending on the circuit requirements.
Additional smaller value capacitors help to provide a low
impedance path for unwanted noise out to higher frequencies
but are not always necessary.
Placement of the capacitor returns (grounds), where the capacitors
enter into the ground plane, is also important. Returning the
capacitors grounds close to the amplifier load is critical for
distortion performance. Keeping the capacitors distance short,
but equal from the load, is optimal for performance.
AD8000 Data Sheet
Rev. C | Page 16 of 17
In some cases, bypassing between the two supplies can help to
improve PSRR and to maintain distortion performance in
crowded or difficult layouts. This is as another option to
improve performance.
Minimizing the trace length and widening the trace from the
capacitors to the amplifier reduce the trace inductance. A series
inductance with the parallel capacitance can form a tank circuit,
which can introduce high frequency ringing at the output. This
additional inductance can also contribute to increased distor-
tion due to high frequency compression at the output. Minimize
the use of vias in the direct path to the amplifier power supply
pins because vias can introduce parasitic inductance, which can
lead to instability. When required, use multiple large diameter
vias because this lowers the equivalent parasitic inductance.
GROUNDING
The use of ground and power planes is encouraged as a method
of proving low impedance returns for power supply and signal
currents. Ground and power planes can also help to reduce
stray trace inductance and to provide a low thermal path for the
amplifier. Do not use ground and power planes under any of the
pins of the AD8000. The mounting pads and the ground or
power planes can form a parasitic capacitance at the amplifiers
input. Stray capacitance on the inverting input and the feedback
resistor form a pole, which degrades the phase margin, leading
to instability. Excessive stray capacitance on the output also
forms a pole, which degrades phase margin.
Data Sheet AD8000
Rev. C | Page 17 of 17
OUTLINE DIMENSIONS
COM P LIANT TO JEDEC STANDARDS MS- 0 12- AA
06-02-2011-B
1.27
0.40
1.75
1.35
2.29
2.29
0.356
0.457
4.00
3.90
3.80
6.20
6.00
5.80
5.00
4.90
4.80
0.10 MAX
0.05 NOM
3.81 RE F
0.25
0.17
8°
0°
0.50
0.25
45°
COPLANARITY
0.10
1.04 REF
8
14
5
1.27 BS C
S
EATING
PLANE
FOR PROPE R CONNE CTI ON O F
THE EXPOSED PAD, REFER TO
THE P I N CO NFI G U RAT I ON AND
FUNCT IO N DE SCRIPTI ONS
SECTION OF THIS DATA SHEET.
BOTTOM VIEW
TOP VI EW
0.51
0.31
1.65
1.25
Figure 54. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]
Narrow Body
(RD-8-1)
Dimensions shown in millimeters
TOP VIEW
8
1
5
4
0.30
0.25
0.20
BOTTOM VIEW
PIN 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.55
1.45
1.35
1.84
1.74
1.64
0.203 REF
0.05 MAX
0.02 NOM
0.50 BSC
EXPOSED
PAD
3.10
3.00 SQ
2.90
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS MO-229-WEED
12-07-2010-A
PIN1
INDICATOR
(R0.15)
Figure 55. 8-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-8-13)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Branding Ordering Quantity
AD8000YRDZ –40°C to +125°C 8-Lead SOIC_N_EP RD-8-1 1
AD8000YRDZ-REEL7 –40°C to +125°C 8-Lead SOIC_N_EP RD-8-1 1,000
AD8000YCPZ-R2 –40°C to +125°C 8-Lead LFCSP CP-8-13 HNB 250
AD8000YCPZ-REEL –40°C to +125°C 8-Lead LFCSP CP-8-13 HNB 5,000
AD8000YCPZ-REEL7 –40°C to +125°C 8-Lead LFCSP CP-8-13 HNB 1,500
1 Z = RoHS Compliant Part.
©2005–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05321-0-5/16(C)
