Product Folder Order Now Technical Documents Support & Community Tools & Software LMK00105 SNAS579G - MARCH 2012 - REVISED DECEMBER 2014 LMK00105 Ultra-Low Jitter LVCMOS Fanout Buffer and Level Translator With Universal Input 1 Features 3 Description * * The LMK00105 is a high-performance, low-noise LVCMOS fanout buffer which can distribute five ultralow jitter clocks from a differential, single-ended, or crystal input. The LMK00105 supports synchronous output enable for glitch-free operation. The ultra lowskew, low-jitter, and high PSRR make this buffer ideally suited for various networking, telecom, server and storage area networking, RRU LO reference distribution, medical and test equipment applications. 1 * * * * * * * 5 LVCMOS Outputs, DC to 200 MHz Universal Input - LVPECL - LVDS - HCSL - SSTL - LVCMOS and LVTTL Crystal Oscillator Interface - Crystal Input Frequency: 10 to 40 MHz Output Skew: 6 ps Additive Phase Jitter - 30 fs at 156.25 MHz (12 kHz to 20 MHz) Low Propagation Delay Operates With 3.3 or 2.5-V Core Supply Voltage Adjustable Output Power Supply - 1.5 V, 1.8 V, 2.5 V, and 3.3 V for Each Bank 24-Pin WQFN Package (4.0 mm x 4.0 mm x 0.8 mm) The core voltage can be set to 2.5 or 3.3 V, while the output voltage can be set to 1.5, 1.8, 2.5 or 3.3 V. The LMK00105 can be easily configured through pin programming. Device Information(1) PART NUMBER LMK00105 PACKAGE BODY SIZE (NOM) WQFN (24) 4.00 mm x 4.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Functional Block Diagram 2 Applications * * * * * * * * LO Reference Distribution for RRU Applications SONET, Ethernet, Fibre Channel Line Cards Optical Transport Networks GPON OLT/ONU Server and Storage Area Networking Medical Imaging Portable Test and Measurement High-End A/V 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMK00105 SNAS579G - MARCH 2012 - REVISED DECEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Diagrams.......................... Specifications......................................................... 1 1 1 2 4 5 6.1 6.2 6.3 6.4 6.5 6.6 5 5 5 5 6 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 9 7.1 7.2 7.3 7.4 Overview ................................................................... 9 Functional Block Diagram ......................................... 9 Feature Description................................................... 9 Device Functional Modes........................................ 11 8 Application and Implementation ........................ 12 8.1 Application Information............................................ 12 8.2 Typical Applications ................................................ 14 9 Power Supply Recommendations...................... 20 9.1 Power Supply Filtering ............................................ 20 9.2 Power Supply Ripple Rejection............................... 20 9.3 Power Supply Bypassing ........................................ 21 10 Layout................................................................... 21 10.1 Layout Guidelines ................................................. 21 10.2 Layout Example .................................................... 22 10.3 Thermal Management ........................................... 22 11 Device and Documentation Support ................. 23 11.1 11.2 11.3 11.4 Documentation Support ........................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 23 23 24 24 12 Mechanical, Packaging, and Orderable Information ........................................................... 24 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (May 2013) to Revision G * Page Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Changes from Revision E (February 2013) to Revision F Page * Added device name to title of document. ............................................................................................................................... 1 * Changed all LLP and QFN packages to WQFN throughout document.................................................................................. 1 * Deleted optional from CLKin* pin description. And changed complimentary to complementary. .......................................... 4 * Added max limit to Output Skew parameter and added tablenote to parameter in Electrical Characteristics Table............. 6 * Changed typical value for both conditions of Propagation Delay in the Electrical Characteristics Table. ............................. 6 * Added Min/Max limits to both conditions of Propagation Delay parameter in Electrical Characteristics Table. .................... 6 * Changed unit value for the first condition of Part-to-part Skew from ps to ns in the Electrical Characteristics Table. .......... 6 * Changed both Max values of each Part-to-part Skew condition in Electrical Characteristics Table...................................... 6 * Changed the Typ value of each Rise/Fall Time condition in the Electrical Characteristics Table. ....................................... 6 * Deleted VIL table note. ............................................................................................................................................................ 7 * Added VI_SE parameter and spec limits with corresponding table note to Electrical Characteristics Table. .......................... 7 * Added CLKin* column to CLKin Input vs. Output States table. Also added fourth row starting with Logic Low under CLKin column. ...................................................................................................................................................................... 10 * Changed table title from CLKin input vs. Output States to OSCin Input vs. Output States ................................................. 10 * Changed third paragraph in Driving the Clock Inputs section to include CLKin* and LVCMOS text. Removed extra references to other figures. Revised to better correspond with information in Electrical Characteristics Table. ................. 12 * Deleted Figure 10 (Near End termination) and Figure 11 (Far End termination) from Driving the Clock Inputs section..... 12 * Changed bypass cap text to signal attenuation text of the fourth paragraph in Driving the Clock Inputs section. .............. 12 * Changed Single-Ended LVCMOS Input, DC Coupling with Common Mode Biasing image with revised graphic............... 13 * Deleted sentence in reference to two deleted images. ........................................................................................................ 13 2 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: LMK00105 LMK00105 www.ti.com * SNAS579G - MARCH 2012 - REVISED DECEMBER 2014 Changed link from National packaging site to TI packaging site.......................................................................................... 22 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: LMK00105 3 LMK00105 SNAS579G - MARCH 2012 - REVISED DECEMBER 2014 www.ti.com 5 Pin Configuration and Diagrams 24 23 22 21 20 19 OE Vdd SEL CLKin CLKin* GND 24-Pin WQFN Package Top View 1 2 3 4 5 6 DAP 18 17 16 15 14 13 Vddo CLKout4 GND CLKout3 Vddo CLKout2 GND Vdd OSCin OSCout GND GND 7 8 9 10 11 12 GND Vddo CLKout0 GND CLKout1 Vddo Pin Functions PIN (1) 4 NAME NO DAP DAP TYPE DESCRIPTION -- The DAP should be grounded Vddo 2, 6 Power Power Supply for Bank A (CLKout0 and CLKout 1) CLKout pins. CLKout0 3 Output LVCMOS Output GND 1,4,7,11, 12, 16,19 GND CLKout1 5 Output LVCMOS Output Vdd 8,23 Power Supply for operating core and input buffer OSCin 9 Input Input for Crystal Ground OSCout 10 Output Output for Crystal CLKout2 13 Output LVCMOS Output Vddo 14,18 Power Power Supply for Bank B (CLKout2 to CLKout 4) CLKout pins CLKout3 15 Output LVCMOS Output CLKout4 17 Output LVCMOS Output CLKin* 20 Input Complementary input pin CLKin 21 Input Input Pin SEL 22 Input Input Clock Selection. This pin has an internal pulldown resistor. (1) OE 24 Input Output Enable. This pin has an internal pulldown resistor. (1) CMOS control input with internal pulldown resistor. Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: LMK00105 LMK00105 www.ti.com SNAS579G - MARCH 2012 - REVISED DECEMBER 2014 6 Specifications 6.1 Absolute Maximum Ratings (1) MIN MAX UNIT Vdd Core Supply Voltage -0.3 3.6 V Vddo Output Supply Voltage -0.3 3.6 V VIN Input Voltage -0.3 Vdd + 0.3 V TL Lead Temperature (solder 4 s) 260 C TJ Junction Temperature 125 C Tstg Storage temperature 150 C (1) -65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2500 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) 1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions MIN TA Ambient Temperature Vdd Core Supply Voltage Vddo Output Supply Voltage (1) (1) TYP MAX UNIT -40 25 85 C 2.375 3.3 3.45 V 1.425 3.3 Vdd V Vddo should be less than or equal to Vdd (Vddo Vdd) 6.4 Thermal Information LMK00105 THERMAL METRIC (1) RTW UNIT 24 PINS RJA Junction-to-ambient thermal resistance 46.7 RJC(top) Junction-to-case (top) thermal resistance 50.3 RJB Junction-to-board thermal resistance 25.5 JT Junction-to-top characterization parameter 1.9 JB Junction-to-board characterization parameter 25.6 RJC(bot) Junction-to-case (bottom) thermal resistance 13.6 (1) C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: LMK00105 5 LMK00105 SNAS579G - MARCH 2012 - REVISED DECEMBER 2014 www.ti.com 6.5 Electrical Characteristics (2.375 V Vdd 3.45 V, 1.425 Vddo Vdd, -40 C TA 85 C, Differential inputs. Typical values represent most likely parametric norms at Vdd = Vddo = 3.3 V, TA = 25 C, at the Recommended Operation Conditions at the time of product characterization and are not ensured). Test conditions are: Ftest = 100 MHz, Load = 5 pF in parallel with 50 unless otherwise stated. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TOTAL DEVICE CHARACTERISTICS Vdd Core Supply Voltage 2.375 2.5 or 3.3 3.45 V Vddo Output Supply Voltage 1.425 1.5, 1.8, 2.5, or 3.3 Vdd V No CLKin 16 25 IVdd Core Current Vddo = 3.3 V, Ftest = 100 MHz 24 Vddo = 2.5 V, Ftest = 100 MHz 20 IVddo[n] Current for Each Output IVdd + IVddo Total Device Current with Loads on all outputs Vddo = 2.5 V, OE = High, Ftest = 100 MHz 5 Vddo= 3.3 V, OE = High, Ftest = 100 MHz 7 OE = Low 0.1 OE = High @ 100 MHz 48 OE = Low 16 mA mA mA POWER SUPPLY RIPPLE REJECTION (PSRR) 100 kHz, 100 mVpp Ripple Injected on Vdd, Vddo = 2.5 V Ripple Induced Phase Spur Level PSRR OUTPUTS Measured between outputs, referenced to CLKout0 (2) Output Skew tPD Propagation Delay CLKin to CLKout (2) tPD, PP fCLKout tRise Part-to-part Skew (2) (3) Output Frequency (4) Rise/Fall Time VCLKoutLow Output Low Voltage VCLKoutHigh Output High Voltage RCLKout Output Resistance (1) (2) (3) (4) 6 dBc (1) Skew tj -44 RMS Additive Jitter 6 25 ps CL = 5 pF, RL = 50 Vdd = 3.3 V; Vddo = 3.3 V 0.85 1.4 2.2 ns CL = 5 pF, RL = 50 Vdd = 2.5 V; Vddo = 1.5 V 1.1 1.8 2.8 ns CL = 5 pF, RL = 50 Vdd = 3.3 V; Vddo = 3.3 V 0.35 ns CL = 5 pF, RL = 50 Vdd = 2.5 V; Vddo = 1.5 V 0.6 ns 200 MHz DC Vdd = 3.3 V, Vddo = 1.8 V, CL = 10 pF 250 Vdd = 2.5 V, Vddo = 2.5 V, CL = 10 pF 275 Vdd = 3.3 V, Vddo = 3.3 V, CL = 10 pF 315 ps 0.1 Vddo-0.1 fCLKout = 156.25 MHz, CMOS input slew rate 2 V/ns CL = 5 pF, BW = 12 kHz to 20 MHz V 50 ohm 30 fs AC Parameters for CMOS are dependent upon output capacitive loading Parameter is specified by design, not tested in production. Part-to-part skew is calculated as the difference between the fastest and slowest tPD across multiple devices. Specified by characterization. Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: LMK00105 LMK00105 www.ti.com SNAS579G - MARCH 2012 - REVISED DECEMBER 2014 Electrical Characteristics (continued) (2.375 V Vdd 3.45 V, 1.425 Vddo Vdd, -40 C TA 85 C, Differential inputs. Typical values represent most likely parametric norms at Vdd = Vddo = 3.3 V, TA = 25 C, at the Recommended Operation Conditions at the time of product characterization and are not ensured). Test conditions are: Ftest = 100 MHz, Load = 5 pF in parallel with 50 unless otherwise stated. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS (OE, SEL0, SEL1) VLow Input Low Voltage VHigh Input High Voltage IIH High Level Input Current IIL Low Level Input Current Vdd = 2.5 V 0.4 Vdd = 2.5 V 1.3 Vdd = 3.3 V 1.6 V 50 -5 5 uA CLKin/CLKin* INPUT CLOCK SPECIFICATIONS (5) (6) IIH High Level Input Current VCLKin = Vdd IIL Low Level Input Current VCLKin = 0 V VIH Input High Voltage VIL Input Low Voltage Differential Input Common Mode Input Voltage (7) VCM 20 -20 uA uA Vdd GND V VID = 150 mV 0.5 Vdd1.2 VID = 350 mV 0.5 Vdd1.1 VID = 800 mV 0.5 Vdd0.9 0.3 2 0.15 1.5 V DC 200 MHz 10 40 MHz VI_SE Single-Ended Input Voltage Swing (2) CLKinX driven single-ended (AC or DC coupled), CLKinX* AC coupled to GND or externally biased within VCM range VID Differential Input Voltage Swing CLKin driven differentially V Vpp OSCin/OSCout PINS (4) fOSCin Input Frequency fXTAL Crystal Frequency Input Range COSCin Shunt Capacitance VIH Input High Voltage (5) (6) (7) (8) Single-Ended Input, OSCout floating Fundamental Mode Crystal ESR < 200 ( fXtal 30 MHz ) ESR < 120 ( fXtal > 30 MHz ) (4) (8) 1 Single-Ended Input, OSCout floating pF 2.5 V See Differential Voltage Measurement Terminology for definition of VOD and VID. Refer to application note AN-912 Common Data Transmission Parameters and their Definitions for more information. When using differential signals with VCM outside of the acceptable range for the specified VID, the clock must be AC coupled. The ESR requirements stated are what is necessary in order to ensure that the Oscillator circuitry has no start up issues. However, lower ESR values for the crystal might be necessary in order to stay below the maximum power dissipation requirements for that crystal. Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: LMK00105 7 LMK00105 SNAS579G - MARCH 2012 - REVISED DECEMBER 2014 www.ti.com 6.6 Typical Characteristics Unless otherwise specified: Vdd = Vddo = 3.3 V, TA = 20 C, CL = 5 pF, CLKin driven differentially, input slew rate 2 V/ns. 450 RMS JITTER (fs) 400 -40 C 25 C 85 C CLKin Source -140 Fclk-100 MHz Int. BW=1-20 MHz NOISE FLOOR (dBc/Hz) 500 350 300 250 200 150 100 -145 -40 C 25 C 85 C CLKin Source Fclk=100 MHz Foffset=20 MHz -150 -155 -160 -165 50 0 -170 0.5 1.0 1.5 2.0 2.5 3.0 DIFFERENTIAL INPUT SLEW RATE (V/ns) Figure 1. RMS Jitter vs. CLKin Slew Rate @ 100 MHz 0.5 1.0 1.5 2.0 2.5 3.0 DIFFERENTIAL INPUT SLEW RATE (V/ns) Figure 2. Noise Floor vs. CLKin Slew Rate @ 100 MHz 3.5 Vddo=1.5 V Vddo=1.8 V Vddo=2.5 V Vddo=3.3 V OUTPUT SWING (V) 3.0 LVCMOS Output CLKin Source 2.5 Rterm=50 2.0 1.5 1.0 0.5 0.0 Test conditions: LVCMOS Input, slew rate 2 V/ns, CL = 5 pF in parallel with 50 , BW = 1 MHz to 20 MHz Figure 3. LVCMOS Phase Noise @ 100 MHz CURRENT (mA) 15 0 200 400 600 800 1000 FREQUENCY (MHz) Figure 4. LVCMOS Output Swing vs. Frequency Vddo = 1.5 V Vddo = 1.8 V Vddo = 2.5 V Vddo = 3.3 V Cload = 10 pF 10 5 0 0 100 150 200 250 FREQUENCY (MHz) Figure 5. Iddo per Output vs Frequency 8 50 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: LMK00105 LMK00105 www.ti.com SNAS579G - MARCH 2012 - REVISED DECEMBER 2014 7 Detailed Description 7.1 Overview The LMK00105 is a 5 output LVCMOS clock fanout buffer with low additive jitter that can operate up to 200 MHz. It features a 2:1 input multiplexer with a crystal oscillator input, single supply or dual supply (lower power) operation, and pin-programmable device configuration. The device is offered in a 24-pin WQFN package. 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Vdd and Vddo Power Supplies Separate core and output supplies allow the output buffers to operate at the same supply as the Vdd core supply (3.3 V or 2.5 V) or from a lower supply voltage (3.3 V, 2.5 V, 1.8 V, or 1.5 V). Compared to single-supply operation, dual supply operation enables lower power consumption and output-level compatibility. Bank A (CLKout0 and CLKout1) and Bank B (CLKout2 to CLKout4) may also be operated at different Vddo voltages, provided neither Vddo voltage exceeds Vdd. NOTE Care should be taken to ensure the Vddo voltage does not exceed the Vdd voltage to prevent turning-on the internal ESD protection circuitry. DO NOT DISCONNECT OR GROUND ANY OF THE Vddo PINS because the Vddo pins are internally connected within an output bank. 7.3.2 Clock Input The LMK00105 has one differential input, CLKin/CLKin* and OSCin, that can be driven in different manners that are described in the following sections. 7.3.2.1 Selection of Clock Input Clock input selection is controlled using the SEL pin as shown in Table 1. Refer to Clock Inputs for clock input requirements. When CLKin is selected, the crystal circuit is powered down. When OSCin is selected, the crystal oscillator will start-up and its clock will be distributed to all outputs. Refer to Crystal Interface for more information. Alternatively, OSCin may be driven by a single ended clock, up to 200 MHz, instead of a crystal. Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: LMK00105 9 LMK00105 SNAS579G - MARCH 2012 - REVISED DECEMBER 2014 www.ti.com Table 1. Input Selection SEL Input 0 CLKin, CLKin* 1 OSCin (Crystal Mode) 7.3.2.1.1 CLKin/CLKin* Pins The LMK00105 has a differential input (CKLin/CLKin*) which can be driven single-ended or differentially. It can accept AC or DC coupled 3.3V/2.5V LVPECL, LVDS, or other differential and single ended signals that meet the input requirements in Electrical Characteristics and when using differential signals with VCM outside of the acceptable range for the specified VID, the clock must be AC coupled. Refer to Clock Inputs for more details on driving the LMK00105 inputs. In the event that a Crystal mode is not selected and the CLKin pins do not have an AC signal applied to them, Table 2 following will be the state of the outputs. Table 2. CLKin Input vs. Output States CLKin CLKin* Output State Open Open Logic Low Logic Low Logic Low Logic Low Logic High Logic Low Logic High Logic Low Logic High Logic Low 7.3.2.1.2 OSCin/OSCout Pins The LMK00105 has a crystal oscillator which will be powered up when OSCin is selected. Alternatively, OSCin may be driven by a single ended clock, up to 200 MHz, instead of a crystal. Refer to Crystal Interface for more information. If Crystal mode is selected and the pins do not have an AC signal applied to them, Table 3 will be the state of the outputs. If Crystal mode is selected an open state is not allowed on OSCin, as the outputs may oscillate due to the crystal oscillator circuitry. Table 3. OSCin Input vs. Output States OSCin Output State Open Not Allowed Logic Low Logic High Logic High Logic Low 7.3.3 Clock Outputs The LMK00105 has 5 LVCMOS outputs. 7.3.3.1 Output Enable Pin When the output enable pin is held High, the outputs are enabled. When it is held Low, the outputs are held in a Low state as shown in Table 4. Table 4. Output Enable Pin States OE Outputs Low Disabled (Hi-Z) High Enabled The OE pin is synchronized to the input clock to ensure that there are no runt pulses. When OE is changed from Low to High, the outputs will initially have an impedance of about 400 to ground until the second falling edge of the input clock and starting with the second falling edge of the input clock, the outputs will buffer the input. If the OE pin is taken from Low to High when there is no input clock present, the outputs will either go high or low and stay a that state; they will not oscillate. When the OE pin is taken from High to Low the outputs will be Low after the second falling edge of the clock input and then will go to a Disabled (Hi-Z) state starting after the next rising edge. 10 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: LMK00105 LMK00105 www.ti.com SNAS579G - MARCH 2012 - REVISED DECEMBER 2014 7.3.3.2 Using Less than Five Outputs Although the LMK00105 has 5 outputs, not all applications will require all of these. In this case, the unused outputs should be left floating with a minimum copper length to minimize capacitance. In this way, this output will consume minimal output current because it has no load. NOTE For best soldering practices, the minimum trace length should extend to include the pin solder mask. This way during reflow, the solder has the same copper area as connected pins. This allows for good, uniform fillet solder joints helping to keep the IC level during reflow. 7.4 Device Functional Modes LMK00105 can be driven by a clock input or a crystal according to SEL pin. Refer to Selection of Clock Input for more information. Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: LMK00105 11 LMK00105 SNAS579G - MARCH 2012 - REVISED DECEMBER 2014 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information 8.1.1 Clock Inputs The LMK00105 has a differential input (CLKin/CLKin*) that can accept AC or DC coupled 3.3V/2.5V LVPECL, LVDS, and other differential and single ended signals that meet the input requirements specified in Electrical Characteristics. The device can accept a wide range of signals due to its wide input common mode voltage range (VCM) and input voltage swing (VID)/dynamic range. AC coupling may also be employed to shift the input signal to within the VCM range. To achieve the best possible phase noise and jitter performance, it is mandatory for the input to have a high slew rate of 2 V/ns (differential) or higher. Driving the input with a lower slew rate will degrade the noise floor and jitter. For this reason, a differential input signal is recommended over single-ended because it typically provides higher slew rate and common-mode noise rejection. While it is recommended to drive the CLKin/CLKin* pair with a differential signal input, it is possible to drive it with a single-ended clock provided it conforms to the Single-Ended Input specifications for CLKin pins listed in the Electrical Characteristics. For large single-ended input signals, such as 3.3 V or 2.5 V LVCMOS, a 50 load resistor should be placed near the input for signal attenuation to prevent input overdrive as well as for line termination to minimize reflections. The CLKin input has an internal bias voltage of about 1.4 V, so the input can be AC coupled as shown in Figure 6. The output impedance of the LVCMOS driver plus Rs should be close to 50 to match the characteristic impedance of the transmission line and load termination. RS 0.1 PF 0.1 PF 50: Trace 50: CMOS Driver LMK Input 0.1 PF Figure 6. Preferred Configuration: Single-Ended LVCMOS Input, AC Coupling A single-ended clock may also be DC coupled to CLKin as shown in Figure 7. A 50- load resistor should be placed near the CLKin input for signal attenuation and line termination. Because half of the single-ended swing of the driver (VO,PP / 2) drives CLKin, CLKin* should be externally biased to the midpoint voltage of the attenuated input swing ((VO,PP / 2) x 0.5). The external bias voltage should be within the specified input common voltage (VCM) range. This can be achieved using external biasing resistors in the k range (RB1 and RB2) or another lownoise voltage reference. This will ensure the input swing crosses the threshold voltage at a point where the input slew rate is the highest. 12 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: LMK00105 LMK00105 www.ti.com SNAS579G - MARCH 2012 - REVISED DECEMBER 2014 Application Information (continued) CMOS Driver VO,PP Rs VO,PP/2 VCC 50: Trace VBB ~ (VO,PP/2) x 0.5 50: LMK Input RB1 VCC RB2 0.1 PF Figure 7. Single-Ended LVCMOS Input, DC Coupling With Common Mode Biasing If the crystal oscillator circuit is not used, it is possible to drive the OSCin input with an single-ended external clock as shown in Figure 8. The input clock should be AC coupled to the OSCin pin, which has an internally generated input bias voltage, and the OSCout pin should be left floating. While OSCin provides an alternative input to multiplex an external clock, it is recommended to use either differential input (CLKin) since it offers higher operating frequency, better common mode, improved power supply noise rejection, and greater performance over supply voltage and temperature variations. Figure 8. Driving OSCin With a Single-Ended External Clock 8.1.2 Clock Outputs The LMK00105 LVCMOS driver output impedance (Ro) is nominally 50 ohms and well-matched to drive a 50 ohm transmission line (Zo), as shown as below. If driving a transmission line with higher characteristic impedance than 50 ohms, a series resistor (Rs) should be placed near the driver to provide source termination, where Rs = Zo - Ro. The LMK00105 has two output banks, Bank A and Bank B, which are separately powered by independent Vddo supply pins. The Vddo supply pins for Bank A and Bank B are not connected together internally, and may be supplied with different voltages. This allows the LMK00105 outputs to easily interface to multiple receivers with different input threshold or input supply voltage (Vddi) requirements without the need for additional voltage divider networks. Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: LMK00105 13 LMK00105 SNAS579G - MARCH 2012 - REVISED DECEMBER 2014 www.ti.com Application Information (continued) Figure 9. LMK00105 Output Termination 8.2 Typical Applications 8.2.1 Typical Application Block Diagram Figure 10. Typical Application Block Diagram 14 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: LMK00105 LMK00105 www.ti.com SNAS579G - MARCH 2012 - REVISED DECEMBER 2014 Typical Applications (continued) 8.2.1.1 Design Requirements In the example application shown in Figure 10, the LMK00105 is used to fan-out a 3.3-V LVCMOS oscillator to three receiver devices with the following characteristics: * The CPU input accepts a DC-coupled 3.3-V LVCMOS input clock. The LMK00105 has an internal 50- series termination, thus the receiver is connected directly to the output. * The FPGA input also requires a 3.3-V LVCMOS input clock, like the CPU. * The PLL input requires a single-ended voltage swing less than 2 Vpp, so 1.8-V LVCMOS input signaling is needed. The PLL receiver requires AC coupling since it has internal input biasing to set its own common mode voltage level. 8.2.1.2 Detailed Design Procedure Refer to Clock Inputs to properly interface the 3.3-V LVCMOS oscillator output to the CLKin input buffer of the LMK00105. See Figure 9 for output termination schemes depending on the receiver application. Since the CPU/FPGA inputs and PLL input require different input voltage levels, the LMK00105 output banks are supplied from separate Vddo rails of 3.3 V and 1.8 V for CLKout0/1 (Bank A) and CLKout2 (Bank B), respectively. Unused outputs can be left floating. See Power Supply Recommendations for recommended power supply filtering and decoupling/bypass techniques. 8.2.1.3 Application Curves The LMK00105 was tested using multiple low-jitter XO clock sources to evaluate the impact of the buffer's additive phase noise/jitter. The plots on the left show the phase noise of the clock source, while the plots on the right show the total output phase noise from LMK00105 contributed by both the clock source noise and buffer additive noise. Note that the phase noise "hump" around 80 kHz offset on the phase noise plots is correlated to the XO source, which is attributed to power supply noise at this frequency. Figure 11. Phase Noise of 125-MHz Clock Source Figure 12. LMK00105 Clock Output A low-noise 125 MHz XO clock source with 45.6 fs RMS jitter (Figure 11) was used to drive the LMK00105, resulting in in a total output phase jitter of 81.6 fs RMS (Figure 12) integrated from 12 kHz to 20 MHz. The resultant additive jitter of the buffer is 67.7 fs RMS computed using the "Square-Root of the Difference of Squares" method. Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: LMK00105 15 LMK00105 SNAS579G - MARCH 2012 - REVISED DECEMBER 2014 www.ti.com Typical Applications (continued) Figure 13. Phase Noise of 100-MHz Clock Source Figure 14. LMK00105 Clock Output A low-noise 100 MHz XO clock source with 43.5 fs RMS jitter (Figure 13) was used to drive the LMK00105, resulting in a total output phase jitter of 103.1 fs RMS (Figure 14) integrated from 12 kHz to 20 MHz. The resultant additive jitter of the buffer is 93.4 fs RMS computed using the "Square-Root of the Difference of Squares" method. Figure 15. Phase Noise of 50-MHz Clock Source Figure 16. LMK00105 Clock Output A divide-by-2 circuit was used with the low-noise 100-MHz XO to generate a 50-MHz clock source with 174.9fs RMS jitter (Figure 15), resulting in a total output phase jitter of 201.6 fs RMS (Figure 16) integrated from 12 kHz to 20 MHz. In this case, the total output phase noise/jitter is highly correlated to the clock source phase noise and jitter, which prevents us from computing the true additive jitter of the buffer using the "Square-Root of the Difference of Squares" method. To accurately specify the additive jitter of the buffer at this frequency, a clock source with lower noise (compared to the DUT) would be needed for this measurement. 16 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: LMK00105 LMK00105 www.ti.com SNAS579G - MARCH 2012 - REVISED DECEMBER 2014 Typical Applications (continued) Figure 17. Phase Noise of 25-MHz Clock Source Figure 18. LMK00105 Clock Output A divide-by-4 circuit was used with the low-noise 100 MHz XO to generate a 25-MHz clock source with 134.5 fs RMS (Figure 17), resulting in a total output phase jitter of 138.2 fs RMS (Figure 18) integrated from 12 kHz to 5 MHz. In this case, the total output phase noise and jitter is highly correlated to the clock source phase noise and jitter, which prevents us from computing the true additive jitter of the buffer using the "Square-Root of the Difference of Squares" method. To accurately specify the additive jitter of the buffer at this frequency, a clock source with lower noise (compared to the DUT) would be needed for this measurement. Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: LMK00105 17 LMK00105 SNAS579G - MARCH 2012 - REVISED DECEMBER 2014 www.ti.com Typical Applications (continued) 8.2.2 Crystal Interface C1 OSCin XTAL RLIM OSCout LMK00105 The LMK00105 has an integrated crystal oscillator circuit that supports a fundamental mode, AT-cut crystal. The crystal interface is shown in Figure 19. C2 Figure 19. Crystal Interface 8.2.2.1 Design Requirements The value of capacitor and resistor depend on the crystal. Each crystal is specified with a load capacitance and resistor is used to avoid over driving the crystal. The example crystal specifications are given in Table 5. Table 5. Example 25-MHz Crystal Electrical Specifications NO. ITEM SYMBOL ELECTRICAL SPECIFICATION MIN F0 TYP MAX 25 UNIT 1 Nominal Frequency MHz 2 Mode of Vibration 3 Frequency Tolerance 4 Load Capacitance CL 9 5 Drive Level DL 6 Equivalent Series Resistance R1 7 Shunt Capacitance C0 2.1 15% pF 8 Motional Capacitance C1 9.0 15% fF Fundamental F/F0 9 Motional Inductance L 10 Frequency Stability TC 11 C0/C1 Rate -15 15 ppm 100 300 W 9 50 pF 4.6 15% -20 mH 20 ppm 250 Based on the OSCin shunt capacitance and stray capacitance, C1 and C2 are chosen as 6.8 pF to make the load capacitance (CL) to be 9 pF. Suggested value of RLIM is 1.5 k. Refer to Detailed Design Procedure for the derivation. 8.2.2.2 Detailed Design Procedure The load capacitance (CL) is specific to the crystal, but usually on the order of 18 to 20 pF. While CL is specified for the crystal, the OSCin input capacitance (CIN = 1 pF typical) of the device and PCB stray capacitance (CSTRAY ~ 1 to 3 pF) can affect the discrete load capacitor values, C1 and C2. For the parallel resonant circuit, the discrete capacitor values can be calculated as follows: CL = (C1 * C2) / (C1 + C2) + CIN + CSTRAY (1) Typically, C1 = C2 for optimum symmetry, so Equation 1 can be rewritten in terms of C1only: CL = C12 / (2 * C1) + CIN + CSTRAY (2) Finally, solve for C1: C1 = (CL - CIN - CSTRAY) * 2 18 (3) Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: LMK00105 LMK00105 www.ti.com SNAS579G - MARCH 2012 - REVISED DECEMBER 2014 Electrical Characteristics provides crystal interface specifications with conditions that ensure start-up of the crystal, but it does not specify crystal power dissipation. The designer will need to ensure the crystal power dissipation does not exceed the maximum drive level specified by the crystal manufacturer. Overdriving the crystal can cause premature aging, frequency shift, and eventual failure. Drive level should be held at a sufficient level necessary to start-up and maintain steady-state operation. The power dissipated in the crystal, PXTAL, can be computed by: PXTAL = IRMS2 * RESR * (1 + C0 / CL)2 (4) Where: * IRMS is the RMS current through the crystal. * RESR is the maximum equivalent series resistance specified for the crystal. * CL is the load capacitance specified for the crystal. * C0 is the minimum shunt capacitance specified for the crystal. IRMS can be measured using a current probe (e.g. Tektronix CT-6 or equivalent) placed on the leg of the crystal connected to OSCout with the oscillation circuit active. As shown in Figure 19, an external resistor, RLIM, can be used to limit the crystal drive level if necessary. If the power dissipated in the selected crystal is higher than the drive level specified for the crystal with RLIM shorted, then a larger resistor value is mandatory to avoid overdriving the crystal. However, if the power dissipated in the crystal is less than the drive level with RLIM shorted, then a zero value for RLIM can be used. As a starting point, a suggested value for RLIM is 1.5 k. Figure 20 shows the LMK00105 output phase noise performance in crystal mode with the 25-MHz crystal specified in Table 5. 8.2.2.3 Application Curves Figure 20. Output Phase Noise in Crystal Mode with 25-MHz Crystal (230.6 fs RMS jitter, 12 kHz to 5 MHz) Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: LMK00105 19 LMK00105 SNAS579G - MARCH 2012 - REVISED DECEMBER 2014 www.ti.com 9 Power Supply Recommendations 9.1 Power Supply Filtering It is recommended, but not required, to insert a ferrite bead between the board power supply and the chip power supply to isolate the high-frequency switching noises generated by the clock driver, preventing them from leaking into the board supply. Choosing an appropriate ferrite bead with very low DC resistance is important, because it is imperative to provide adequate isolation between the board supply and the chip supply. It is also imperative to maintain a voltage at the supply terminals that is greater than the minimum voltage required for proper operation. Figure 21. Power-Supply Decoupling 9.2 Power Supply Ripple Rejection In practical system applications, power supply noise (ripple) can be generated from switching power supplies, digital ASICs or FPGAs, etc. While power supply bypassing will help filter out some of this noise, it is important to understand the effect of power supply ripple on the device performance. When a single-tone sinusoidal signal is applied to the power supply of a clock distribution device, such as LMK00105, it can produce narrow-band phase modulation as well as amplitude modulation on the clock output (carrier). In the singleside band phase noise spectrum, the ripple-induced phase modulation appears as a phase spur level relative to the carrier (measured in dBc). For the LMK00105, power supply ripple rejection (PSRR), was measured as the single-sideband phase spur level (in dBc) modulated onto the clock output when a ripple signal was injected onto the Vddo supply. The PSRR test setup is shown in Figure 22. Ripple Source Vcco Clock Source Power Supplies Bias-Tee IN+ IC IN- Vcc OUT Limiting Amp DUT Board OUT Phase Noise Analyzer Scope Measure 100 mVPP ripple on Vcco at IC Measure single sideband phase spur power in dBc Figure 22. PSRR Test Setup A signal generator was used to inject a sinusoidal signal onto the Vddo supply of the DUT board, and the peak-topeak ripple amplitude was measured at the Vddo pins of the device. A limiting amplifier was used to remove amplitude modulation on the differential output clock and convert it to a single-ended signal for the phase noise analyzer. The phase spur level measurements were taken for clock frequencies of 100 MHz under the following power supply ripple conditions: 20 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: LMK00105 LMK00105 www.ti.com SNAS579G - MARCH 2012 - REVISED DECEMBER 2014 Power Supply Ripple Rejection (continued) * * Ripple amplitude: 100 mVpp on Vddo = 2.5 V Ripple frequency: 100 kHz Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as follows: DJ (ps pk-pk) = [(2 * 10(PSRR/20)) / ( * fclk)] * 1012 (5) 9.3 Power Supply Bypassing The Vdd and Vddo power supplies should have a high frequency bypass capacitor, such as 100 pF, placed very close to each supply pin. Placing the bypass capacitors on the same layer as the LMK00105 improves input sensitivity and performance. All bypass and decoupling capacitors should have short connections to the supply and ground plane through a short trace or via to minimize series inductance. 10 Layout 10.1 Layout Guidelines 10.1.1 Ground Planes Solid ground planes are recommended as they provide a low-impedance return paths between the device and its bypass capacitors and its clock source and destination devices. Avoid return paths of other system circuitry (for example, high-speed/digital logic) from passing through the local ground of the device to minimize noise coupling, which could induce added jitter and spurious noise. 10.1.2 Power Supply Pins Follow the power supply schematic and layout example described in Power Supply Bypassing. 10.1.3 Differential Input Termination * Place input termination resistors as close as possible to the CLKin/CLKin* pins. * Avoid or minimize vias in the 50- input traces to minimize impedance discontinuities. Intra-pair skew should be also be minimized on the differential input traces. * If not used, CLKin/CLKin* inputs may be left floating. 10.1.4 Output Termination * Place series termination resistors as close as possible to the CLKoutX outputs at the launch of the controlled impedance traces. * Avoid or minimize vias in the 50- traces to minimize impedance discontinuities. * Any unused CLKoutX output should be left floating and not routed. Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: LMK00105 21 LMK00105 SNAS579G - MARCH 2012 - REVISED DECEMBER 2014 www.ti.com 10.2 Layout Example 2.6 mm, min 0.2 mm, typ 1.0 mm, typ Figure 23. Recommended Land and Via Pattern 10.3 Thermal Management For reliability and performance reasons the die temperature should be limited to a maximum of 125C. That is, as an estimate, TA (ambient temperature) plus device power consumption times JA should not exceed 125C. The package of the device has an exposed pad that provides the primary heat removal path as well as excellent electrical grounding to a printed circuit board. To maximize the removal of heat from the package a thermal land pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package. A recommended land and via pattern is shown in Figure 23. More information on soldering WQFN packages and gerber footprints can be obtained: www.ti.com/packaging. To minimize junction temperature it is recommended that a simple heat sink be built into the PCB (if the ground plane layer is not exposed). This is done by including a copper area of about 2 square inches on the opposite side of the PCB from the device. This copper area may be plated or solder coated to prevent corrosion but should not have conformal coating (if possible), which could provide thermal insulation. The vias shown in Figure 23 should connect these top and bottom copper layers and to the ground layer. These vias act as "heat pipes" to carry the thermal energy away from the device side of the board to where it can be more effectively dissipated. 22 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: LMK00105 LMK00105 www.ti.com SNAS579G - MARCH 2012 - REVISED DECEMBER 2014 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Differential Voltage Measurement Terminology The differential voltage of a differential signal can be described by two different definitions causing confusion when reading datasheets or communicating with other engineers. This section will address the measurement and description of a differential signal so that the reader will be able to understand and discern between the two different definitions when used. The first definition used to describe a differential signal is the absolute value of the voltage potential between the inverting and noninverting signal. The symbol for this first measurement is typically VID or VOD depending on if an input or output voltage is being described. The second definition used to describe a differential signal is to measure the potential of the noninverting signal with respect to the inverting signal. The symbol for this second measurement is VSS and is a calculated parameter. Nowhere in the IC does this signal exist with respect to ground, it only exists in reference to its differential pair. VSS can be measured directly by oscilloscopes with floating references, otherwise this value can be calculated as twice the value of VOD as described in the first section Figure 24 illustrates the two different definitions side-by-side for inputs and Figure 25 illustrates the two different definitions side-by-side for outputs. The VID and VOD definitions show VA and VB DC levels that the noninverting and inverting signals toggle between with respect to ground. VSS input and output definitions show that if the inverting signal is considered the voltage potential reference, the noninverting signal voltage potential is now increasing and decreasing above and below the noninverting reference. Thus the peak-to-peak voltage of the differential signal can be measured. VID and VOD are often defined in volts (V) and VSS is often defined as volts peak-to-peak (VPP). VID Definition VSS Definition for Input Noninverting Clock VIH VCM VSS VID VIL Inverting Clock VID = | VIH VIL | VSS = 2*VID GND Figure 24. Two Different Definitions for Differential Input Signals VOD Definition VSS Definition for Output Noninverting Clock VOH VOS VOL VSS VOD Inverting Clock VOD = | VOH - VOL | VSS = 2*VOD GND Figure 25. Two Different Definitions for Differential Output Signals 11.2 Trademarks All trademarks are the property of their respective owners. Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: LMK00105 23 LMK00105 SNAS579G - MARCH 2012 - REVISED DECEMBER 2014 www.ti.com 11.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.4 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 24 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: LMK00105 LMK00105 www.ti.com SNAS579G - MARCH 2012 - REVISED DECEMBER 2014 PACKAGE OUTLINE RTW0024A WQFN - 0.8 mm max height SCALE 3.000 PLASTIC QUAD FLATPACK - NO LEAD 4.1 3.9 A B PIN 1 INDEX AREA 4.1 3.9 C 0.8 MAX SEATING PLANE 0.05 0.00 0.08 C 2X 2.5 7 20X 0.5 6 13 2X 2.5 25 2.6 0.1 1 18 24X PIN 1 ID (OPTIONAL) (0.1) TYP EXPOSED THERMAL PAD 12 24 19 0.5 24X 0.3 0.3 0.2 0.1 0.05 C A B C 4222815/A 03/2016 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: LMK00105 25 LMK00105 SNAS579G - MARCH 2012 - REVISED DECEMBER 2014 www.ti.com EXAMPLE BOARD LAYOUT RTW0024A WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 2.6) SYMM 24 19 24X (0.6) 1 18 24X (0.25) (1.05) 25 SYMM (3.8) 20X (0.5) (R0.05) TYP 13 6 ( 0.2) TYP VIA 7 12 (1.05) (3.8) LAND PATTERN EXAMPLE SCALE:15X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4222815/A 03/2016 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). www.ti.com 26 Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: LMK00105 LMK00105 www.ti.com SNAS579G - MARCH 2012 - REVISED DECEMBER 2014 EXAMPLE STENCIL DESIGN RTW0024A WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD 4X ( 1.15) (0.675) TYP (R0.05) TYP 24 19 24X (0.6) 1 18 24X (0.25) (0.675) TYP SYMM 25 20X (0.5) (3.8) 13 6 METAL TYP 7 12 SYMM (3.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 25: 78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X 4222815/A 03/2016 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com Submit Documentation Feedback Copyright (c) 2012-2014, Texas Instruments Incorporated Product Folder Links: LMK00105 27 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LMK00105SQ/NOPB ACTIVE WQFN RTW 24 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 K00105 LMK00105SQE/NOPB ACTIVE WQFN RTW 24 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 K00105 LMK00105SQX/NOPB ACTIVE WQFN RTW 24 4500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 K00105 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 9-Oct-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LMK00105SQ/NOPB WQFN RTW 24 LMK00105SQE/NOPB WQFN RTW LMK00105SQX/NOPB WQFN RTW SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 24 250 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 9-Oct-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMK00105SQ/NOPB WQFN RTW 24 1000 210.0 185.0 35.0 LMK00105SQE/NOPB WQFN RTW 24 250 210.0 185.0 35.0 LMK00105SQX/NOPB WQFN RTW 24 4500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES "AS IS" AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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