ISOSMART Half Bridge Driver Chipsets Features 1200 V or greater low- to high-side isolation. Drives Power Systems Operating on up to 575 V AC mains dv/dt immunity of greater than +50V/ns Proprietary low- to high-side level- transiation and communication On-chip negative gate-drive supply to ensure Power MOSFET or IGBT Type Description Package Temperature Range IXBD4410PI_ | Full-Feature Low-Side Driver | 16-Pin P-DIP -40 to +85C IXBD4411PI | Full-Feature High-Side Driver! 16-Pin P-DIP -40 to +85C IXBD4410SI | Full-Feature Low-Side Driver | 16-Pin SO -40 to +85C IXBD4411S} | Full-Feature High-Side Driver] 16-Pin SO -40 to +85C IXBD4412P! | Basic Low-Side Driver 8-Pin P-DIP -40 to +85C IXBD4413PI | Basic High-Side Driver 8-Pin P-DIP -40 to +85C IXBD4410KIT| Full-Feature Chipset Eval. Kit) PCB 0 to +70C IXBD4412KIT| Basic Chipset Evaluation Kit | PCB 0 to +70C The IXBD4410/IXBD4411 and the IXBD4412/1XBD4413 ISOSMART chipsets are designed to control the gates of two Power MOSFETs, or Power IGBTs, that are connected in a half-bridge (phaseleg) configuration for driving multiple-phase motors, or used in applications that require half-bridge power circuits. The IXBD4410/ IXBD4411 is a full-feature chipset consisting of two 16-Pin-DIP or SO devices interfaced and isolated by two small-signal ferrite pulse transformers. The IXBD4412/1XBD4413 is a basic, low-cost chipset consisting of two 8-Pin- DIP devices interfaced and isolated by a single pulse transformer. The smail- signal transformers in both chipsets provide greater than 1200 V isolation. Even with commutating noise ambients greater than +50 V/ns and up to 1200 V potentials, these chipsets establish error-free two-way communications between the system ground-reference IXBD4410 resp. IXBD4412 and the inverter output-reference IXBD4411 resp. IXBD4413. They incorporate undervoltage V,,, or V_. lockout, and overcurrent or desaturation shutdown to protect the IGBT or Power MOSFET devices from damage. Both chipsets provide the necessary gate drive signals to fully control the grounded-source low-side power device, as well as the floating-source high-side power device. Additionally, the IXBD4410/4411 chipset provides a negative-going, off-state gate drive signal for improved turn-off of IGBTs, or Power MOSFETs, and a system logic- compatible status fault output, FLT, to indicate overcurrent or desaturation, and undervoltage V,,, or V_,.. During a status fault, both chipsets keep their respective gate drive outputs off; at V_. for the IXBD4410/4411 and at 0 V for the |XBD4412/4413. turn-off e 5 V logic compatible HCMOS inputs with hysteresis e Available in either the 16-Pin DIP or the 16-Pin wide-body, small-outline plastic package (IXBD4410/4411) 20 ns switching time with 1000 pF load; 100 ns switching time with 10000 pF load 100 ns propagation delay time 2 Apeak output drive capability Self shut-down of output in response to over-current or short-circuit e Under-voltage and over-voltage V,, lockout protection e Protection from cross conduction of the half bridge e@ Logic compatible fault indication from both low and high-side driver (XBD4410/4411). Applications e 1- or 3-Phase Motor Controls e@ Switch Mode Power Supplies (SMPS) e Uninterruptible Power Supplies (UPS) e Induction Heating and Welding Systems e@ Switching Amplifiers e General Power Conversion Circuits FULL FEATURED ISOSMART <=> COMMANDS DRIVER CHIPSET nme 1XBD4411 PROTECTION <7 tt ld yy +15V db S sFauLts C +15 IXBD4410 J*/~ ORVE ==> PROTECTION <Q 540 V- BASIC, LOWER COST ISOSMART T_| tans i) > COMMANDS DRIVER CHIPSET 540 V- PROTECTION < LOAD (XBD ( ) AA12 DRIVE > os PROTECTION < IXYS reserves the right to change limits, test conditions and dimensions. 4 MB 4666226 0002423 T83Symbol Definition Maximum Ratings Dimensions in inch (1" = 25.4 mm) VoolVee Supply Voltage 4410/4411 05.24 vy | 1&Pinso V,,>/GND 4412/4413 -0.5 ... 24 Vv fei i Ru i : in Input Voltage (INH, INL) -0.5..V,,+0.5 V | bia Input Current (INL, INH, IM) +10 mA I, (rev) Peak Reverse Output Current (OUT) 2 A P, Maximum Power Dissipation 600 mW T, Operating Ambient Temperature -40...85 C Toy Maximum Junction Temperature 150 C Tag Storage Temperature Range -55...150 C T, Lead Soldering Temperature for 10 s 300 C Recommended Operating Conditions VoolV ce Supply Voltage 4410/4411 10... 20 Vv V,,/GND 4412/4413 10... 20 Vv Vi p/LG 10...16.5 Vv Lotte: Maximum Common Mode dv/dt +50 V/ns Symbol Definition/Condition Characteristic Values ~ (T, = 25C, V,,, = 15 V, unless otherwise specified) min. | typ. | max. 16-Pin Plastic DIP PIN NO. 1 t INL, INH Inputs (referred to LG) i 130, V.. Positive-Going Threshold 3.5 Vv ae ost R v.. Negative-Going Threshold 1 Vv Vin input Hysteresis 1 Vv ae Ln Input Leakage Current/V,=V., or LG -1 1 pA Vie. Cc, Input Capacitance 10 pF : for A 120 Open Drain Fault Output (referred to LG for 4410/4411) 1 Von HI Output/R,,,, = 10 kQ to V,,, V5p70.05 Vv 100" WP Vu LO Output/l, = 4 mA 0.3 0.5 V Cross view for both packages OUT Output (referred to LG) LL ae 29) Von H! Output/l, = -10 mA V5p-0.05 Vv qh rh Vi LO Output/l, = 10 mA V..+0.05 Vv ; a] 5-910 TK R, Output HI Res./l, = -0.1 A 3 5 Q O30: 1 R, Output LO Res/, = 0.1 A 3 4 Q Z Vox Peak Output Current/C, = 10 nF 1.5 2 A 32g | IM input (referred to KG for 4410/4411 and to LG for 4412/4413) Vv. Positive-Going Threshold 0.24 0.3 0.45 Vv C,, Input Capacitance 10 pF R, Shorting Device Output Resistance 50 75 100 Q VEE Supply (referred to LG for 4410/4411) _ az Vee Output Voltage/l, = 1 mA, C, = 1 uF 5 6.5 | -7.5 V 7 lout Output Current/V,, = 0.85 * V,_. -20 -25 mA 4 7 8r vr fy Inverting Frequency 600 kHz ue Vier Undervoltage Fault Indication -3 -4.8 Vv t -100 TYP MH 4646226 COOP424 JLT oe 6Symbol Definition/Condition Characteristic Values (T, = 25C, V,, = 15 V, unless otherwise specified) min. | typ. | max. Vp Undervoltage Lockout Vu Drop Out 9.5 10.5 11.5 Vv Von Hysteresis 0.1 0.15 0.3 Vv Quiescent Power Supply Current Ino Vpp Current/V_=V_, or LG, 1, = 0 20, mA . (1XBD4410/4412) INL and INH Inputs (Fig. 1a - 1) INL [_ 50% taom Turn-on delay time; = C, =1nF 110 175 ns Lo 4410/4412 +ISV 90% t, Rise time; C, =10 nF 70 100 ns Low SIDE C, =1 nF 15 20 ns coer ov | ft, 10% tarot Turn-off delay time = C,=1nF 70 150 ons (xpbaaio) Sv J _| Ltr | oe 4410/4412 | re | b- td(off) . d{on) t Fall time C, =10nF 70 150 ons (1xBD4410/4412) C, =1nF 15 20 ns INH Tanotn 4410/4412 ol Turn-on delay time vs. +15V 4411/4413 C, =1nF 60 150 ns HIGH SIDE Turn-off delay time (IXBD4413) OV tanyon) 4410/4412 (XBD4411) 5V * Turn-on delay time vs. _ m tartt(on) 4411/4413 C, =1nF 60 150 ns taitt(ort) Turn-off delay time Fig. 1: Output signal waveform Fault Output Delay for any Fault Conditions (4410/4411) tes FLT Delay/R,,=2kQ C, = 20 pF 200 | 300 ns Overcurrent Protection Delay te Driver-Off delay time C, = 1 nF | 200 | 300 ns + 15V =15V T Pde 4 Vdd Vdd OUT 15 D o WF 4 Fur + slay cal _ + tu U2 Q 7 aral + Fo IXBD4411 10 i te Vint |XBD vad }8 al (HIGH SIDE opp 2 T 0 tur Zinn =94413 our 5 A ) 7 3} -) (HD) enojs Lone ute T+ Tt R- Re 1N4148) O4uF [4 7uF s RG) Th wren $seon . 7 T T+ . | Jy Loag) Lona) Cape) corm | . sons 4700pF AR ue vad Re RT i b A700pF | Le or | 47ur| + a 6 _ = 3 Pe ] an air apa oa NS > Yin. IXBD_ vad {8 cal? T 9 tur > 2iwe =64412 our [7 Db . a, (LOW SIDE) ot 3}-) (LD) enole _ | tone > 2 we 1N4148] oUF [4 7uF Ay 1(+) im} LG KG im wo [u [re Ie + dy. vO Lb Fig. 1a: IXBD4410/4411 Switching time test circuit Figure 1b: IXBD4412/4413 Switching time test circuit 6 MM 4b4b22b O002425 456Chipset Overview The ISOSMART chipsets are pairs of integrated circuits providing isolated high- and low-side drivers for phaseleg motor control, or any other application which utilizes a half bridge, 2- or 3- phase drive configuration. They consist of two drive control inputs (INL and INH) for two Power-MOSFET/IGBT gate-drive outputs. Both inputs operate from a common ground, and are activated by HCMOS compatible logic levels. The low-side output operates near input ground, while the high-side output operates from a floating ground that is nominally the source connection of the high-side phaseleg power device. Both outputs typically provide 2 A of transient current drive for fast switching of the phaseleg power device. IXBD4410/XBD4411 The full featured ISOSMART driver chipset incorporates a IXBD4410 as the low-side driver (Fig. 3) and a IXBD4411 as the high-side driver (Fig. 2). When input "INL" is set to a positive logic level, the low-side gate output goes high (turns on); when "INH" is set to a positive logic level, the high-side gate drive output goes high. The high-side IC is isolated from the low-side IC by a magnetic barrier, across which the turn on/off signal is transmitted to the high- side gate drive. In the case of the IXBD4410/4411 chipset, the IXBD4411 fault signal is also transmitted back to the IXBD4410 driver. This isolation only depends on the low cost communica- tions transformer, which is designed to withstand 1200 V or more. There are two magnetic transmission channels between the low- and high- side IC's for bi-directional communi- cation (IXBD4410/4411). One sends a signal from the low-side IXBD4410 IC up to the high-side IXBD4411 IC, and the other sends a signal back from the high-side to the low-side IC. The signal that is sent up controls the IXBD4411 gate-drive output. The signal sent from the IXBD4411 back to the IXBD4410 indicates a high-side fault has occurred (overcurrent, or under-voltage of the high-side +power supplies). This is detected at the IXBD4410 driver and sets "FLT" pin low, to indicate the high- side fault. The fault signal that is returned from the IXBD4411 is strictly for status; any gate-drive shutdown because of a high-side fault is done 7O+ RESET HI-SIDE FAULT LEVEL GATE OUT Rx rT Prec) 15 6OS SENSE SHIFT DRIVE RESET Von UNDER | SHUT RESET Ly [| SENSE FAULT [oy T VEE Locic ffoc | O14 REF CA 5 OW CROSS OVER v 13 Tx COND CURR Fe cB 40+ Lock SENSE GEN. | 12 he fT KG Fig. 2: IXBD4411, high-side driver block diagram Fig. 3: 1XBD4410, low-side driver block diagram HIGH SIDE voc tt~~S D Q OVER CURRENT Pr Sf R INH ST HIiGHSIDE VDD UNDER: OUTPUT ENABLE VOLTAGE VEE UNDER VOLTAGE LOW SIDE VCC D Q OVER CURRENT Po Sf | oj} R INL >] LOW-SIDE VDD UNDER OUTPUT CNAGLCE VOLTAGE VEE UNDER VOLTAGE Fig. 4: Logic representation of 1XBD4410 FLT signal MB 4b4beeb OOOe4eb 74elocally within the high-side IXBD4411. The IXBD4411 gate-drive will turn-off the power device whenever an overcurrent or under voltage condition arises. The overcurrent sensing is active only while the gate driver output is "high" (on). The overcurrent fault condition is latched and is reset on the next INH gate input positive transition. The FLT (pin 8) of the IXBD4411 is not used and should be grounded. The low-side IXBD4410 driver provides an output pin 8 (FLT) to indicate a high- side (IXBD4411) or a low-side (IXBD4410) fault. This output pin is an open-drain" output. The IXBD4410 low-side driver fault indications are similar to the IXBD4411 high-side driver indications as outlined above. A "graphic" logic diagram of the chipset's FLT function is presented in Fig.4. Note that this diagram presents the logic of this function at the "low-side" IXBD4410 driver and is not the actual circuit. It describes the combined logic of the "fault logic" and "hi-side fault sense" blocks in both the IXBD4410 and IXBD4411 as shown in Fig. 2 and 3. IXBD4412/XBD4413 The basic, lower cost |ISOSMART chipset consists of a pair of 8 Pin P-DIP ICs: IXBD4412 (low-side driver) and the IXBD4413 (high-side driver). It operates similarly to the IXBD4410/4411 pair, but does not include the negative drive or the fault indications option. This pair requires only a single magentic isolated trans- mission channel. The most efficient method of providing power for the high-side driver is by bootstrapping. This method is illustrated in the functional drawing on page 4 and in the application example (Fig. 6 and 9) by diode D1 and capacitor C1. Using this method, the power is drawn through a high-voltage diode onto a reservoir capacitor whenever the floating high-side ground returns to near the real ground of the low-side driver; when the high-side gate is turned on, and the floating ground moves towards a higher potential, the bootstrapping diode back-biases, and the high-side driver draws its power solely from the reservoir capacitor. Power may also be provided via any isclated power supply (usually an extra secondary on the system housekeeping supply switching transformer). Both the IXBD4410 and IXBD4411 contain on-board negative charge pumps to provide negative gate drive, which ensures turn-off of the high- or low-side power device in the presence of currents induced by power device Miller capaci- tance or from inductive ground transients. a a a otal Widows IEE de ae oly Mee aie . re Ties ee x These charge pumps provide -5 V relative to the local driver ground when V,,, is at +15 V, and at rated average currents of 25 mA. The charge pump requires two external capacitors (C7 and C11 in Fig. 6). The charge pump frequency is nominally 600 kHz. The charge pump clock is turned off whenever the difference between the Vop and V_, supplies exceed 20 V, to prevent exceeding the breakdown rating of the IC. Both the 1XBD4410 and IXBD4411 drivers possess two local grounds each, a common logic ground, and "Kelvin" ground. The Kelvin ground and logic grounds are first connected directly to each other, and then to the Kelvin-source of the power device for accurate over- current measurement in the presence of inductive transients on the power device source terminal. Power MOSFET or IGBT overcurrent sensing utilizes an on -chip comparator with a typical 300 mV threshold. Ina typical application, the current mirror pin of the Power MOSFET or IGBT is con- nected to a grounded, low-value resistor, and to the overcurrent comparator input on the high- or low-side driver. The comparator will respond typically within 150 ns to an overcurrent condition to shutdown the driver output. The power switches could be protected also by desa- turation detection (see Fig. 6, 7 and 9). To assure maximum protection for the phaseleg power devices, the chipset incorporates the following Power MOSFET and IGBT protection circuits: e Power device overcurrent or desa- turation protection. The IXBD4410/ 4411 or 4412/4413 will turn off the driven device within 150 ns of sensing an output overcurrent, or desaturation condition. e Gate-drive lockout circuitry to prevent cross conduction (simultaneous conduction of the low- and high-side phaseleg power devices), either under normal operating conditions or when a fault occurs. e During power-up, the chipset's gate- drive outputs will be low (off), until the voltage reaches the under-voltage trip point. e Under-voltage gate-drive lockout on the low- and/or high- side driver when- ever the respective positive power supply falls below 9.5 V typically. e Under-voltage gate-drive lockout on the low- and high- side driver whenever the respective negative power supply rises above -3 V typically (IXBD4410/4411). Pin Description IXBD4410 (Low-Side Driver) < 3 Qo VDD OUT VEE CA cB ike KG INL INH awWas + b+ 00 4 9 0 IXBD4410 Ionnrinr al Sym. Pin Description of IXBD 4410/4411 Positive power supply. Logic input signal referenced to LG (logic ground). In the IXBD4410. A "high" to this pin turns on its gate drive output and resets its fault logic. A "low" to this pin turns off the gate drive output. In the 1XBD4411 this pin is not used and should be connected to its ground (LG). No Connection (IXBD 4411) Logic input signal referenced to LG (logic ground). In the 1XBD4410, this signal is transmitted to the IXBD4411 "high-side" driver through pins 4 and 5 (T- and T+). A "high" to this pin turns on the IXBD4411 gate drive output and resets its fault logic. A tow to this pin turns off the IXBD4411 gate drive output. In the IXBD4411 this pin is not used and should be connected to its ground (LG). No Connection (IXBD 4411) ee is 4} Transmitter output complemen- Te 5 | tary drive signals. Direct drive of =e ce the low signal transformer, which a gh is connected to the receiver of San the chipset's companion device. In the IXBD4410, this signal transmits the on/off command to its companion IXBD4411. In the IXBD4411, this signal transmits the fault indication to its Tun companion IXBD4410 driver. Receiver input complementary signal. Directly connected to the low signal transformer, which is driven by the chipset's compa- nion device. In the IXBD4410, this input receives the fault indication from its companion IXBD4411 driver. In the IXBD4411, this input receives the on/off command from its companion IXBD4410 driver. 8 MM 4b8b2e2b 0002427 bet weey, Se Pa Pin Description IXBD4411 (High-Side Driver) Pin Description 1XBD4412 (Low-Side Driver) Pin Description IXBD4413 (High-Side Driver) XY VDD 1 16 VDD NC C42 _ 15F9 OUT NG CJ3 vv 1450 VEE T Oy4 + 13-5 CA T Cs + 12 CB R o6 a 1D Le Re 7 mM 10F> KG Nc cya as 9 IM Description of IXBD 4410/4411 Low/high side fault output. In the (XBD4410, this output indicates a fault condition of either device of the chipset. A high indicates no fault, A "low" indicates that either overcurrent, V_, or Vee under-voltage occurred. In case of overcurrent, this output will remain active "low" until the next input cycle of the respective driver. In case of under-voitage, this output will remain low until the proper voltage is restored. The IXBD4411 does not have a FLT output,and its pin 8 should be tied to LG No Connection (IXBD 4411) Current sense or desaturation detection input. This input is active only while the OUT pin is "high" (on). When the OUT pin is "low" (off) this input is pulled to ground through a 70 Q resistor. Any voltage at this pin above the threshold of .3 V typical, will turn the output (pin 15) off. This pin is used for power device overcurrent protection. Kelvin ground. This ground is used as Kelvin connection for overcurrent or desaturation sensing. Logic and power ground. Capacitor terminals for negative charge pump (V,..); "+ terminal is CB (pin 12). Negative supply terminal. Gate drive output. In the IXBD4410 this output responds ngs eg ea whee 2 Eo INL "NH VOD OUT GND ot OO UUdgU T+ IXBD4412 q Description of IXBD 4412 Logic input signal referenced to GND. A "high" to this pin turns on the gate drive output and resets the fault logic. A "low" to this pin turns off the gate drive output. Logic input signal referenced to GND. A high to this pin is transmitted to the "high-side" driver (IXBD4413), turns on the high-side gate drive output and resets its fault logic. A "low" to this pin is transmitted to the "high-side" driver (IXBD4413) and turns off its gate drive output. Transmitter output comple- mentary signal. Direct drive of the low signal transformer, which is connected to the receiver of the companion IXBD4413 "high- side" driver. This signal transmits the on/off command to the companion driver. Current sense or desaturation detection input. This input is active only while the OUT pin is "high" (on). When the OUT pin is "low" (off) this input is pulled to ground through a 50 resistor. Any voltage at this pin, above the threshold of 0.3 V typical, will turn the output (pin 7) off. This pin is used for power device overcurrent protection. Logic and power ground. Gate drive output. This output responds to the INL signal. A high" at INL will turn it on high), A low" will turn it off V7 ne Ch 8 vod Nc Ch2 75 our R Cy3 S 6 ano R+ C4 Se 5{ iM Description of IXBD 4413 Not used. Connect to GND (pin 6). Not used. Connect to GND (pin 6). Receiver input complementary signal. Directly connected to the low signal transformer, which is driven by the companion IXBD4412 low-side" driver. This input receives the on/off command from its companion "low-side" IXBD4412 driver. Current sense or desaturation detection input. This input is active only while the OUT pin is "high" (on). When the OUT pin is "low" (off) this input is pulled to ground through a 70 Q resistor. Any voltage at this pin, above the threshold of 0.3 V typical, will turn the output (pin 7) off. This pin is used for power device overcurrent protection. Logic and power ground. Gate drive output. This output responds to the transmitted signal from the companion IXBD4412 "low-side" driver. A high at INH of the "low-side" driver (IXBD44 12) will turn this output on ("high"), A "low" will turn off ("low"). Any fault condition will also turn this output off (low"). B Positive power supply. ("low"). Any fault condition will also turn this output off ("low"). | to the INL signal. A "high" at INL _ i will turn it on ("high"), a "low" will be turn it off ("low"). In the me {XBD4411, this output responds to the transmitted signal from the ~ companion IXBD4410. A "high" at INH of the IXBD4410 drives will turn it on (high). A "low" will turn it off (ow"). This output will turn off ("low") also in response to any fault condition. ME 4b8b22b OO0e42S 5bS 5I . ci t * . * Coe RS y > Xe Fug eh Soe a y 2 es AXBD4470 AXBD4442- sor. XBD4411 | IXBD4413 Application The IXBD4410/4411 or IXBD 4412/ 4413 chipset devices are specifically designed as MOS-gated transistor drivers in half-bridge power converters, 1- and 3-phase motor controls, and UPS applications. The phaseleg PWM command is normally generated by previous (user provided) circuitry. It must be decomposed into two separate logic signals, one for the high-side and one for the low-side power transistors, with appropriate deadtime for each state transition. The deadtime insures non-overlapping conduction even if the turn-on and turn-off delay times of the power devices are unequal. The minimum deadtime should be greater than tan: A separate circuit, or an IC device like the IXYS deadtime generator IXDP630, can be used to perform this function. The ISOSMART chipset family of devices do not generate deadtime, although there is an internal lockout that prohibits one device form being commanded "on" before the other is commanded "off". This simpli- fies start-up and shutdown protection circuitry, preventing logic error during power-up from turning on both high-and low-side transistors simultaneously. Negative V_, Charge Pump Circuit Design The on-chip V,,. generator provided in the IXBD4410/4411 generates a nega- tive power supply, regulated at 20 V below the positive V_,, rail. (Note: this circuit is not present in the lower-cost IXBD441 2/4413 chipset).if V., is +10 V, Veg will be -10 V. If V,, is +15 V, V_, will be -5 V. This negative drive potential in the off-state is either desirable or required in many instances. When switching a clamped inductive load (Fig. 5), the turn-on of Q2 will commutate the freewheeling diode around Q1. Whether this diode is intrinsic (as in a MOSFET) or extrinsic (IGBT or bipolar), its reverse recovery is critical to proper circuit operation. At high turn-on di/dt in Q2, and near its rated voltage, the recovery of D1 can get quite "snappy" (the di/at in the second half of the recovery process, after the diode has begun to recover its blocking capability, can get very large), creating a very high dv/dt across Q1. This dv/dt is impressed across the Miller capacitance of Q1, forcing a large CMILLER rde-- Rout! D1 ed a1 [Ae CMILLER rdF--4 Roul! 4 _ > JF p2 v D1 Reverse Recovery __! Q1 Turn-on Fig. 5: Switching a clamped inductive load current to flow out the gate terminal of the device. If this current pulse causes a high enough voltage drop across the output impedance of the gate drive circuit, R,,, Q1 will be turned on. out? The Q1 conduction in every instance Q2 is turned on (and Vice Versa), aside from degrading efficiency, can lead to catastrophic failure of both power transistors. At high temperature, where the -6 to -7 mV/C temperature coefficient of IGBT/MOSFET threshold reduces the voltage required to create a failure, this problem is even more likely to occur. In an industrial module package (e.g.: a 150 A/1200 V IGBT phaseleg module), the series inductance contributed by the long gate leads and connectors further compli- cate the design. In a heavily snubbered converter, or in a power supply design with low trans- former leakage inductance, the design problem is relatively simple and nega- tive drive is seldom required. In these applications, the |IXBD4412/4413 is adequate. However, in a modern snubberless or lightly snubbered converter design, it is important to keep the gate drive impedance high enough during transistor turnoff to limit the reapplied dv/dt (the transistor is its own active snubber). This is always impor- tant for EMI control, and in the case of IGBT may be required to achieve the necessary RBSOA. At the same time, it is mandatory to keep the off-state gate drive impedance very low to assure the transistor remain off during induced dv/dt (including diode recovery dv/dt). In some instances, it is simply not possible to satisfy both criteria with O V applied in the off-state. In these cases the IXBD4410/4411 with V,,. negative bias generator must be used. The internal V_, generator is a charge pump circuit. Referring to Fig. 6, an external charge pump capacitor is required between the CA and CB +B800V OC IXFH12N100 | R10 the (A Vad vad our HS 18 i) 4 4 RS O00 u2 tm(S_0.022uF 0 o22ur cith go C2 Slt CA a7 ety iets sour o1uF si, Batt 1 3 68 ast ootrl ca Ri 218 pin DIP {Rt ins (16 pin DIP) glo o, ate 47K y 100 } tig Veel14 u -5SvV T+ Tre KOPP e (4. |? tool cio os RS D3 she a L oo22uFT 7222 form rc fp aa 1N4148 0 1uF 10uF 1200V ISOLATION BARRIER | toa) | fers 0 02auF | oy la! rie] LES a 4 1 20, 478 .Opaurl 2 RS IXFH12N100 9 o20uF ye] COs 4] 228 Rts 5 18 15 roa (\4f) gam +15V RRS T+ q 1M a2 tos Jcis L|vdd OUT R12 Ar O1uF | 10uF g/ ui im 2 +> 10K SIFT iypnaaig CATI2 RB deli BBQ R14 1 (16 pin DIP) 11 + 62 47K PWM 1/3 LZ Sling cpl2 F 8\\, 0.01uF JUL 16L ppezo LS ZJINL Vee is - =5v oF, 9 Ra LG KG us [10 #8 " Yor. +013 + Cit T82pF iN4148 [OQ tur [+ GND Fig. 6: IXBD4410/4411 Detailed one phase circuit with dead time generator IXDP 630 10 MM 4686226 0002429 4TlIXBD4410 IXBD4412 : 1XBD4411__IXBD4413 terminals (C7, C11), and an output b reservoir capacitor between V,. and GND (C10, C14). A0.1 uF charge pump capacitor (C7, C11) is recom- _IE _| = mended. The voltage regulation IM AW IM AA method used in the [XBD4410/4411 2 R, aS = R, allows a 1 to 2 V ripple frequency KG KG depends on the size of the V,,. output GND 4, GND 4 reservoir capacitor (C10, C14) and the average load current. The minimum recommended output reservoir (C10, C14) is 4.7 wF tantalum, or 10 pF if aluminium electrolytic construction is chosen. Note that this reservoir capa- citor is in addition to a good quality high frequency bypass capacitor (0.1 UF) that should be placed from VEE to GND (C9, C13). A small resistor in series with the charge pump capacitor, (R7, R8) reduces the peak charging currents of the charge pump. A value or 68 or greater is recommended, as illustrated in the applications example in Fig. 6. Current Sense / Desaturation Detection Circuit All members of the ISOSMART driver family provide a very flexible overcurrent/short circuit protection capability that works with both standard three-terminal power transistors, and with 4- and 5-terminal current sensing power devices. Overcurrent detection is accomplished as illustrated in Fig. 7a (for a current mirror power device) and Fig. 7b (for a standard three terminal power transistor). Desaturation detec- tion is accomplished with the same internal circuits by measuring the voltage across the power transistor in the on-state with an external resistor divider (Fig. 7c). The |M input trip point V_,,, typically 300 mV, is referenced to the Kelvin ground pin KG. Current Mirror MOSFET and IGBT allow good control of peak let-thru currents and excellent short circuit protection when combined with the ISOSMART driver family of devices. The sense resistor is chosen to develop 300 mV at the desired peak transistor current, assuming a mirror ration of 1400:1, and a trip point of 30 Ais desired: R,= 300 mV 1400/30 A= 14.9 (use 15 2 CC). It is important to realize that C,., per unit area of the mirror cells is much MM 4b486b22b 0002430 113 With Current Mirror With Standard MOSFET/IGBT Desaturation Detection with Standard MOSFET/IGBT Fig. 7: Alternative overcurrent protection circuits larger that C,.. per unit area of the bulk of the chip (due to periphery effects). This causes a large transient current pulse at the mirror output whenever the transistor switches (C * dv/dt currents), which can cause false overcurrent trigger. The RC filter indicated in Fig. 7a will eliminate this problem. Standard three-terminal MOSFET and IGBT devices (in discrete as well as modern industrial single transistor and phaseleg modules) can also be protected from short circuit with the ISOSMART driver family devices. In discrete device designs, where the source/emitter terminal is available, overcurrent protection with an external power resistor can be implemented. The resistor is placed in series with the device emitter, with the full device current flowing through it (Fig. 7b). The sense resistor is again selected to develop 300 mV at the desired peak transistor current, assuming a trip point of 30 Ais desired: R,= 300 mV /30 A= 10 mQ {use 10 MQ, non-inductive current sense resistor). It is important to recognize that "non- inductive" is a relative term, especially when applied to current sense resistor construction and characterization. There is always significant series inductance inserted with the sense resistor, and Le di/dt voltage transients can cause false overcurrent trigger. The RC filter indicated in Figure 7b will eliminate this problem. Choosing the RC pole at the current sense resistor RL zero should exactly compensate for series inductance. Because the exact value is not normally known (and can vary depending on PC layout and component lead dress) this is not normally a good idea. Usually, the RC time constant should be two to ten times longer than the suspected RL time constant. Desaturation detection as in Figure 7c is probably the most common method of short circuit protection in use today. While not strictly an overcurrent detector, if the power transistor gain, and consequently short circuit let-thru current, is well controlied (as with modern MOSFET and IGBT) this methodology offers very effective protection. Both the IXBD4410/4411 one-phase (half-bridge) circuits in Fig. 6 and the IXBD4412/4413 circuit in Fig. 9 uses desaturation detection. In Fig. 6, the voltage across the two Power MOSFET devices (or IGBTs) are monitored by two sets of voltage-divider networks, R10 and R11 for the high-side gate driver, and R13 and R14 for the low- side gate driver. The dividers are set to trip the IM input comparators when either Power MOSFET device V,,, exceeds a reasonable value, perhaps 50 V (usually a value of 10 % of the nominal DC bus voltage works well). R10 or R13 are chosen to tolerate the applied steady state DC bus voltage at an acceptable power dissipation. Dielectric withstand capability, power handling, temperature rise, and PC board creep and strike spacings, must all be carefully considered in the design of the voltage-divider networks. In the off-state, the voltage across the Power MOSFET device may go as high as the DC bus potential. To keep this normal condition from setting the internal fault flip-flop of the IXBD4410 or the IXBD4411, an internal CMOS switch is turned on and placed across IM and KG pins shorting them together. This effectively discharges C8 or C12 in Fig. 6 and maintains zero potential with respect to KG at IM. 11When the command arrives to switch on the Power MOSFET device, the CMOS switch shorting IM to KG is turned off. The driven Power MOSFET device is switched on approximately 100 ns to 1 us later, and with typical toad conditions, its drain-to-source potential, V,, may take an additional 10 us of delay to collapse to the normal on-state voltage level. To prevent false triggering due to this, C8 or C12 in paraliel combination with R10 and R11, or R13 and R14, delays the IM input signal. During this turn-on interval, the voltageacross C8 or C12 will rise until the Power MOSFET device finally comes on and pulls the voltage across C8 or C12 back down. If the MOSFET device load circuit is shorted, its Vos voltage cannot callapse at turn-on. In this case, the voltage across C8 or C12 rises rapidly until it reaches 300 mV, tripping the fault flip-flop and shutting down the driver output. At the same time, C8 or Ci2 must be kept small enough that the added delay does not slow down the detection of a short circuit event so much that the Power MOSFET device fails before the driver realizes that it is in trouble. The desa- turation detection circuit in Fig. 9 functions identically to the one in Fig. 6 as just described. Current limit or desaturation detection is latched, and reset on a cycle-by-cycle basis with the rising edge of the respective input command. Three Phase Motor Controls Fig. 8 is a block diagram of a typical 3- phase PWM voltage-source inverter motor control. The power circuit consists of six power switching transistors with freewheeling diodes around each of them. The control function may be performed digitally by a microprocessor, microcontroller, DSP chip, or user custom IC; or it may be 15v 1200 V Lt L ISOSMART PHASELEG HIGH/LOW {2 DEVICE 5V ORIVER CIRCUIT Pwm [IxDP630 4 ISOSMART| PHASELEG 4} bean [iH /Low BaYeE fy LOAD TIME DRIVER CIRCUIT GEN ' aa 7 iSOSMART| PHASELEG HIGH /LOW DEVICE ORIVER CIRCUIT gt + Fig. 8: Typical 3-phase motor control system block diagram performed by a PC board full of random logic and analog circuits. In any of these cases, the PWM command for all six power transistors is generated in one circuit, and this circuit is usually referred to system ground potential - the bottom terminal of the power bridge. The ISOSMART family of drivers is the interface between the world of con- trol logic and the world of power, 5 V input logic commands precisely control actions at high voltage and current (1200 V and 100 Ain a typical applica- tion). Fig. 6 is a detailed schematic of one phase of three 3-phase motor control, showing the interconnection of the IXBD4410/4411 and its associated circuitry. This application utilizes the full feature set of the IXBD4410/4411 family of devices in a 460 V~ line operated inverter. In situations that would not benefit from the negative gate drive, and do not require the fault status output, the IXBD4412/4413 chipset may prove adequate. Fig. 9 isa complete schematic of one phase of a 3-phase inverter using the lower cost IXBD4412/4413 chipset. Notice the reduction in total parts count. With the smaller 8-pin packages of the devices themselves, the IXBD4412/4413 chipset offers a 70 % reduction in PC board real estate for a modest reduction in feature set compared to the IXBD4410/4411 devices. PCB Layout Considerations The IXBD4410/4411 or IXBD4412/4413 is intended to be used in high voltage, high speed, high dv/dt applications. To ensure proper operation, great care must be taken in laying out the printed circuit board. The layout critical areas include the communication links, current sense, gate drive, and supply bypassing. The communication path should be as short as possible. Added inductance disturbs the frequency response of the signal path, and these distortions may cause false triggering in the receiver. The transformer should be placed between the two |Cs with the orien- tation of one IC reversed (Fig. 10). Capacitance between the high- and low-side should be minimized. No signal trace should run underneath the communication path, and high- and low-side traces should be separated on the PCB. The dv/dt of the high-side during power stage switching may cause false logic transitions in low-side circuits due to capacitive coupling. The low signal pulse transformer provides the isolation between high-and +800V DC ciol fei od ct 0-022uF 0.022uF wichsiog OTHEL LA TUF Pr b00 [RA IXFH12N100) 1000 @ 01 R10} 1 IXBD A d aw Sey INL vaal) , ty 441 36.7 1Z 109 (}4 1M 2109 rind 441 Sour nt) 31M ] 4] RC) eno R4 R(+) Im u2 Re > C6 0 O1uF 47K 4 3 rer 1200V ISOLATION BARRIER_ taal | LEI L c3 1 2, [50 0.022uF FT 222 } +15V e tur + gs F elu fu IXFH12N10 Lh 4 iss bs fa BD vaale Re Jit SSL 17 2 4412 7 100 (|4t) = 1M T _9| DP630 INH OUT J w om a2 ; T(-) GND R7 U3 {10 c2 TH yy os | Re aS = 4.7K Torr 0.01 uF GND Fig. 9: Lower cost IXBD4412/4413 single phase circuit with deadtime generator IXDP630 12 gm ybab22b 0002431 OSTox: ' boa ago re) 5 cr? _ 1XBDAaIO XBAI po es AXBD4411 . IXBD4413.~ low-side circuits. For 460 V~ line operation, a spacing of 4 mm is recommended between low- and high- side circuits, and a transformer HIPOT specification of at least 1500 V~ is required. This creep spacing is usually adequate to control leakage currents on the PCB with up to 1200 V~ applied after 10 to 15 years of accumulated dust and particulates in a standard industrial environment. In other environ- ments, or at other line voltages, this spacing should be appropriately modified. Low Side High Side Fig. 10: Suggested IC Orientation The current sense/desaturation detect input is noise sensitive. The 300 mV trip point is referred to the KG (Keivin ground) pin, and the applied signal must be kept as clean as possible, A filter is recommended, preferably a monolithic ceramic capacitor placed as close to the IC as possible directly between |M and KG. To preserve maximum noise immunity, the KG pin should first be connected directly to the LG pin, and the pair then sent directly to the power transistor source/emitter terminal, or (if a desaturation detection circuit is used) to the bottom of the divider resistor chain. All supply pins must be bypassed with a low impedance capacitor (preferably monolithic ceramic construction) with minimum lead length. The output driver stage draws 2 A (typical) currents during transitions at di/dt values in excess of 100 A/us. Supply line induc- tance will cause supply and ground bounce on the chip that can cause problems (logic oscillations and, in severe cases, possible latchup failure) without proper bypassing. These bypass elements are in addition to the reservoir capacitors required for the negative Vee supply and the high-side bootstrapped supply if these features are used. Power Circuit Noise Considerations In a typical transistor inverter, the output MOSFET may switch on or off with di/dt >500 A/us. Referring to Fig.11 and assuming that the MOSFET source terminal has a one inch path on the PCB to system ground, a voltage as high as V = 27 nH 500 A/is = 13.5 V can be developed. If the MOSFET switched 25 A, the transient will last as long as (25/500) us or 50 ns, which is more than the typical 6 or 7 ns propa- gations or of a 74HC series gate. three traces while positioning the transistors next to their heat sink and meeting UL/VDE voltage spacings is just too difficult. Grounding the gate driver as in option (a) in Fig. 11 solves the MOSFET turn on problem by eliminating LS1 from the source feedback loop. Now, unfor- tunately, the gate driver will oscillate every time it is turned on or off. As the IXDP630 output goes "high", the gate drive output follows (after its propaga- tion delay) and the MOSFET starts to IXBD4410/4412 75 Vee 1 /AW 1% MF Rp 220pF L cp 7 SOV FILM | (a) | ) Qi LS1 | Q2 _| Q3 LS2 (S3 (PC trace stray inductance) IXDP630 ae System GND Fig. 11: Potential layout problems that create functional problems Fig. 11 illustrates an example layout problem. The power circuit consists of three power transistors (MOSFETs in this example). With the ISOSMART gate driver chipset grounded as in option (b) in Fig. 11, the communication path from the IXDP630 will operate without errors. The PC trace induced voltages are not common with the digital path, so the input of the gate driver will not see or respond to them. Unfortunately, the MOSFET will not operate properly. The voltage induced across LS1 when Q1 is turned on, acts as source degeneration, modifying the turn-on behavior of the MOSFET. If LS1= 27 nH, and V,,, is 15 V (assuming the gate plateau of the MOSFET is 6 V), the di/dt at turn-on will be regulated by the driver/MOSFET/LS1 loop to about 200 A/us; quite a surprise when your circuit requires 500 A/us to operate correctly. It is possible to make use of this behavior to create a turn-on or turn-off di/dt limiter (perhaps to snub the upper free wheeling diode reverse recovery). While possible, this is normally not desirable or practical where two or more transistors are controlled. Equalizing the parasitic impedances of conduct. The voltage transient induced across LS1 (V =LS1 di/dt) raises the local ground (point a) until it exceeds V, (630) - V, (4410/4412) and the driver (after its propagation delay) turns the MOSFET off. Now the MOSFET current falls, V(LS1) drops, point (a) drops to system ground (or slightly below), and the driver detects a "1" at its input. After its propagation delay, it again turns the MOSFET on, continuing the oscillation for one more cycle. To eliminate this problem, a ground level transformation circuit must be added, that rejects this common mode transient. The simplest is a de-coupling circuit, also illustrated in Fig. 11. The capacitor voltage (on C,,) remains constant while the transient voltage is dropped across R, and the driver detects no input transition, eliminating the oscillation. This circuit does add significantly to turn-on and turn-off delay time, and cannot be used if the transient lasts longer than the allowable delays. Delay times must be consi- dered in selection of system dead time. The most complex (and most effective) method of eliminating the effects of transients between grounds is isolation. MB 4b4beecb 0002432 Tb 13\ r : Moss . , : . are . y . Roo , i ed Siw: . OP oof Optocouplers and pulse transformers are the most commonly used isolation techniques, and work very well in this case. The IXDP630/631 has been specifically designed to directly drive a high speed optocoupler like the Hewlett Packard HCPL22XX family or the General Instrument 740L60XX optologic family. These optos are especially well suited to motor control and power conversion equipment due to their very high common mode dv/dt rejection capabilities. Transformer Considerations The transformer is the communication link and isolation barrier between the high- and low-side !Cs. The high-side gate and fault signals are transmitted through the transformer while main- taining the proper isolation. The transmitter signal is in the form of a square wave, but the receiver responds only to the logic edges. This allows for much smaller transformer designs, since a 10 kHz switching frequency does not require a 10 kHz pulse transformer. 130 146 a Fig. 12: Ferrite bead dimensions The recommended transformer for this ISOSMART driver chipset is fabricated using a very smail ferrite shield bead (see Fig. 12), onto which a six-turn primary and a two-turn secondary winding of 36 AWG magnet wire are made. The two windings are segment wound to achieve primary-to- secondary isolation of up to 2500 V~. The six-turn primaries are connected to the respective IXBD4410/4411 transmitter outputs and the two-turn secondaries are connected to their respective receiver inputs. 14 MM 4b4b22b 0002433 Fee = The nominal electrical specifications of the transformer are as follows: @ Open circuit inductance (100 kHz; 20 mV): 3 WH e Interwinding capacitance: 2 pF e Primary leakage inductance: 0.1 wH @ Turns ratio: 6:2 e Primary-to-secondary isolation (Amin): 1500 V~ e@ Core permeability (u): 125 The recommended ferrite bead is Fair Rite Products' part number 2661000101. It is manufactured by: Fair-Rite Products Corp. Wallkill, NY Phone: (914) 895-2055 Several transformer manufacturers have produced custom transformers for the IXBD4410/4411 and IXBD 4412/4413 chip set, to the above specifications: 1) 12 Pin DIP outtine- Part Number 500 - 1914 BH Electronics Buinsville, MN Phone: (612) 894-9690 2) 8 Pin DIP outline- Part Number 2327129 Fil-Mag San Diego, CA Phone: (619) 569-6577 3) Transformer, type 232119 for IXBD 4412/4413 and 232129 for IXBD 4410/4411 FEE, Rodgau/Germany Phone: +49-6106-2011 Fax: +49-6106-24286 As seen in the application drawings (Fig. 6, 9 and 13) a coupling capacitor (22 nF) and a damping resistor (22 Q) are added in series with the primary side of the transformer. The capacitor will control the small amount of energy needed to transfer the signal to the companion driver. The resistor will control the damping of the signal and limitthe peak transmitter output current. The receiver is designed to operate over a wide common mode input range. To reduce noise pickup, the receiver has +250 mV of input hysteresis. If the signal is being distorted at the transmitter, the transmitter is probably running into current limit. A decrease in the coupling capacitance or an increase in the damping resistance should solve this problem. The receiver operates over a wide input range. The minimum amplitude for one side of the receiver is about 1 V and a maximum of about 3 V. It is critical that there be no overshoot on the transformer secondary wave- form. Each signal should be slightly overdamped. If significant overshoot exists, the received signal may be logically inverted. An increase of the damping resistor will solve this problem. 4410 Low Side + 15Vv 0.022uF 5 | + ss 222 * | ov_ | + 15Vv ov L 4411 High Side vec + 1.5V Vf 1.5V Fig. 13: Transmitter/Receiver Waveforms