Crystal-to-HCSL 156.25MHz or 155.52MHz Clock Synthesizer ICS841S104I-02 DATA SHEET General Description Features The ICS841S104I-02 is a PLL-based clock synthesizer specifically designed for Ethernet and SONETTM Clock applications. This device generates either a 156.25MHz or 155.52MHz differential HCSL clock from an input reference of either 25MHz or 19.44MHz. The input reference may be derived from an external source or by the addition of a 25MHz or a 19.44MHz crystal to the on-chip crystal oscillator. An external reference may be applied to the XTAL_IN pin with the XTAL_OUT pin left floating. An I2C bus interface is used to enable or disable each individual clock output. The ICS841S104I-02 is available in a lead-free 24-Lead package. * * * * Four 0.7V current mode differential HCSL output pairs * * * * * Cycle-to-cycle jitter: 25ps (maximum) Crystal oscillator interface: 25MHz or 19.44MHz Output frequency: 156.25MHz or 155.52MHz RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.691ps (typical) I2C support with readback capabilities up to 400kHz 3.3V operating supply mode -40C to 85C ambient operating temperature Available lead-free (RoHS 6) package Block Diagram Pin Assignment 4 XTAL_IN OSC PLL XTAL_OUT FREQ_SEL Divider Network SRCT[1:4] 4 SRCC[1:4] Pulldown SDATA Pullup SCLK Pullup I2C Logic 4 IREF SRCT3 SRCC3 VSS VDD SRCT2 SRCC2 SRCT1 SRCC1 VSS VDD VSS IREF 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 SRCC4 SRCT4 VDD SDATA SCLK XTAL_OUT XTAL_IN VDD VSS FREQ_SEL VDDA VSS ICS841S104I-02 24-Lead TSSOP 4.4mm x 7.8mm x 0.925mm package body G Package Top View ICS841S104BGI-02 REVISION A JUNE 18, 2010 1 (c)2010 Integrated Device Technology, Inc. ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER Table 1. Pin Descriptions Number Name 1, 2 SRCT3, SRCC3 Output Type Differential output pair. HCSL interface levels. Description 3, 9, 11, 13, 16 VSS Power Power supply ground. 4, 10, 17, 22 VDD Power Positive supply pins. 5, 6 SRCT2, SRCC2 Output Differential output pair. HCSL interface levels. 7, 8 SRCT1, SRCC1 Output Differential output pair. HCSL interface levels. 12 IREF Input An external fixed precision resistor (475) from this pin to ground provides a reference current used for differential current-mode SRCCx, SRCTx clock outputs. 14 VDDA Power Analog supply for PLL. 15 FREQ_SEL Input 18, 19 XTAL_IN, XTAL_OUT Input 20 SCLK Input Pullup I2C compatible SCLK. This pin has an internal pullup resistor. LVCMOS/LVTTL interface levels. 21 SDATA I/O Pullup I2C compatible SDATA. This pin has an internal pullup resistor. Open drain. LVCMOS/LVTTL interface levels. 23, 24 SRCT4, SRCC4 Output Pulldown Selects output frequency and I2C address (See Table 3). Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Differential output pair. HCSL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 2 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k Function Tables Table 3. FREQ_SEL I2C Address FREQ_SEL Required Crystal (MHz) Output Frequency Configuration 0 25 156.25MHz 11010100 (D4h) 1 19.44 155.52MHz 11010110 (D6h) NOTE: The slave receiver address is 11010100 (D4h) or 11010110 (D6h) based on the setting of the FREQ_SEL pin. ICS841S104BGI-02 REVISION A JUNE 18, 2010 2 (c)2010 Integrated Device Technology, Inc. ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal I2C serial interface is provided. Through the Serial Data Interface, various device functions, such as clock output buffers, can be individually enabled or disabled. The registers associated with the serial interface initialize to their default settings upon power-up, and therefore, use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 4A. The block write and block read protocol is outlined in Table 4B, while Table 4C outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010100 (D4h) or 11010110 (D6h) based on the setting of the FREQ_SEL pin. Table 4A.Command Code Definition Bit 7 Description 0 = Block read or block write operation, 1 = Byte read or byte write operation 6:5 Chip select address, set to "00" to access device 4:0 Byte offset for byte read or byte write operation. For block read or block write operations, these bits must be "00000". Table 4B. Block Read and Block Write Protocol Bit 1 2:8 Description = Block Write Start Slave address - 7 bits Bit Description = Block Read 1 Start 2:8 Slave address - 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 11:18 Command Code - 8 bits 11:18 Command Code - 8 bits 19 Acknowledge from slave 19 Acknowledge from slave 20 Repeat start 20:27 28 29:36 37 38:45 46 Byte Count - 8 bits Acknowledge from slave 21:27 Slave address - 7 bits Data byte 1 - 8 bits 28 Read = 1 Acknowledge from slave 29 Acknowledge from slave Data byte 2 - 8 bits Acknowledge from slave Data Byte/Slave Acknowledges Data Byte N - 8 bits Acknowledge from slave Stop 30:37 Byte Count from slave - 8 bits 38 Acknowledge 39:46 Data Byte 1 from slave - 8 bits 47 Acknowledge 48:55 Data Byte 2 from slave - 8 bits 56 Acknowledge Data Bytes from Slave/Acknowledge Data Byte N from slave - 8 bits Not Acknowledge ICS841S104BGI-02 REVISION A JUNE 18, 2010 3 (c)2010 Integrated Device Technology, Inc. ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER Table 4C. Byte Read and Byte Write Protocol Bit Description = Byte Write 1 Start 2:8 Bit 1 Slave address - 7 bits 2:8 Description = Byte Read Start Slave address - 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 11:18 Command Code - 8 bits 11:18 Command Code - 8 bits 19 20:27 Acknowledge from slave 19 Acknowledge from slave Data Byte- 8 bits 20 Repeat start 28 Acknowledge from slave 29 Stop 21:27 Slave address - 7 bits 28 Read 29 Acknowledge from slave 30:37 Data from slave - 8 bits 38 Not Acknowledge 39 Stop Control Registers Table 4D. Byte 0: Control Register 0 Bit @Pup Name 7 0 Reserved 6 1 5 1 Table 4E. Byte 1: Control Register 1 Description Bit @Pup Name Description Reserved 7 0 Reserved Reserved SRC[T/C]4 Output Enable 0 = Disable (Hi-Z) 1 = Enable 6 0 Reserved Reserved SRC[T/C]4 5 0 Reserved Reserved 4 0 Reserved Reserved SRC[T/C]3 SRC[T/C]3 Output Enable 0 = Disable (Hi-Z) 1 = Enable 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved 4 1 SRC[T/C]2 SRC[T/C]2 Output Enable 0 = Disable (Hi-Z) 1 = Enable 3 1 SRC[T/C]1 SRC[T/C]1 Output Enable 0 = Disable (Hi-Z) 1 = Enable 2 1 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved Table 4F. Byte 2: Control Register 2 NOTE: Pup denotes power-up. ICS841S104BGI-02 REVISION A JUNE 18, 2010 4 Bit @Pup Name Description 7 1 Reserved Reserved 6 1 Reserved Reserved 5 1 Reserved Reserved 4 0 Reserved Reserved 3 1 Reserved Reserved 2 0 Reserved Reserved 1 1 Reserved Reserved 0 0 Reserved Reserved (c)2010 Integrated Device Technology, Inc. ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER Table 4G. Byte 3:Control Register 3 Table 4J. Byte 6: Control Register 6 Bit @Pup Name Description 7 1 Reserved Reserved 6 0 Reserved Reserved 5 1 Reserved Reserved 4 0 Reserved Reserved 3 1 Reserved Reserved 2 1 Reserved 1 1 0 1 Bit @Pup Name Description 7 0 TEST_SEL REF/N or Hi-Z Select 0 = Hi-Z, 1 = REF/N TEST Clock Mode Entry Control 0 = Normal Operation, 1 = REF/N or Hi-Z Mode 6 0 TEST_MODE Reserved 5 0 Reserved Reserved Reserved Reserved 4 1 Reserved Reserved Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 1 Reserved Reserved 0 1 Reserved Reserved NOTE: Pup denotes power-up. Table 4H. Byte 4: Control Register 4 Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved Bit @Pup 0 Revision Code Bit 3 Table 4K. Byte 7: Control Register 7 Name Description 4 0 Reserved Reserved 7 3 0 Reserved Reserved 6 0 Revision Code Bit 2 2 0 Reserved Reserved 5 0 Revision Code Bit 1 1 0 Reserved Reserved 4 0 Revision Code Bit 0 Reserved 3 0 Vendor ID Bit 3 2 0 Vendor ID Bit 2 1 0 Vendor ID Bit 1 0 1 Vendor ID Bit 0 0 1 Reserved Table 4I. Byte 5: Control Register 5 Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved ICS841S104BGI-02 REVISION A JUNE 18, 2010 5 (c)2010 Integrated Device Technology, Inc. ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, JA 77.5C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 5A. Power Supply DC Characteristics, VDD = 3.3V 5%, TA = -40C to 85C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Positive Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage VDD - 0.21 3.3 VDD V IDD Power Supply Current 71 mA IDDA Analog Supply Current 21 mA Maximum Units NOTE: The device has a power sequence requirement, refer to the Applications Section. Table 5B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V 5%, TA = -40C to 85C Symbol Parameter Test Conditions Minimum Typical VIH Input High Voltage 2.2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current IIL Input Low Current SDATA, SCLK VDD = VIN = 3.465V 10 A FREQ_SEL VDD = VIN = 3.465V 150 A SDATA, SCLK VDD = 3.465V, VIN = 0V -150 A FREQ_SEL VDD = 3.465V, VIN = 0V -10 A Table 6. Crystal Characteristics Parameter Test Conditions Minimum Typical Mode of Oscillation Fundamental Frequency 19.44 or 25 Maximum Units MHz Equivalent Series Resistance (ESR) 50 Shunt Capacitance 7 pF NOTE: Characterized using an 18pF parallel resonant crystal. ICS841S104BGI-02 REVISION A JUNE 18, 2010 6 (c)2010 Integrated Device Technology, Inc. ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER AC Electrical Characteristics Table 7. AC Characteristics, VDD = 3.3V 5%, TA = -40C to 85C Symbol Parameter fMAX Output Frequency tjit(O) Phase Jitter, RMS (Random); NOTE 1 Test Conditions Minimum Units 156.25 MHz Using 19.44MHz Crystal 155.52 MHz 19.44MHz crystal, = 155.52MHz, Integration Range: 12kHz - 20MHz 0.849 ps 25MHz crystal, = 156.25MHz, Integration Range: 12kHz - 20MHz 0.691 ps Output Skew; NOTE 2, 3 tjit(cc) Cycle-to-Cycle Jitter; NOTE 2 tL PLL Lock Time VRB Ring-back Voltage Margin; NOTE 4, 5 VMAX Voltage High; NOTE 6, 7 VMIN Voltage Low; NOTE 6, 8 -300 VCROSS Absolute Crossing Voltage; NOTE 6, 9, 10 250 VCROSS Total Variation of VCROSS over all edges; NOTE 6, 9, 11 odc Maximum Using 25MHz Crystal tsk(o) Rise/Fall Edge Rate; NOTE 6, 12 Typical PLL Mode -100 Measured between 150mV to +150mV Output Duty Cycle 30 ps 25 ps 100 ms 100 mV 1150 mV mV 550 mV 150 mV 0.6 4.0 V/ns 48 52 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Characterized using 19.44MHz and 25MHz crystals. NOTE 1: Refer to phase jitter plot. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. NOTE 4: Measurement taken from differential waveform. NOTE 5: TSTABLE is the time the differential clock must maintain a minimum 150mV differential voltage after rising/falling edges before it is allowed to drop back into the VRB 100mV differential range. NOTE 6: Measurement taken from single-ended waveform. NOTE 7: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section. NOTE 8: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section. NOTE 9: Measured at crossing point where the instantaneous voltage value of the rising edge of SRCT equals the falling edge of SRCC. NOTE 10: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. NOTE 11: Defined as the total variation of all crossing voltages of rising SRCT and falling SRCC, This is the maximum allowed variance in Vcross for any particular system. NOTE 12: Measured from -150mV to +150mV on the differential waveform (SRCT minus SRCC). The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. ICS841S104BGI-02 REVISION A JUNE 18, 2010 7 (c)2010 Integrated Device Technology, Inc. ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER Noise Power dBc Hz Typical Phase Noise at 155.52MHz Offset Frequency (Hz) Noise Power dBc Hz Typical Phase Noise at 156.25MHz Offset Frequency (Hz) ICS841S104BGI-02 REVISION A JUNE 18, 2010 8 (c)2010 Integrated Device Technology, Inc. ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER Parameter Measurement Information 3.3V5% 3.3V5% 3.3V5% SCOPE 3.3V5% 50 VDD 50 33 VDD Measurement Point VDDA VDDA HCSL 49.9 HCSL 50 33 IREF 50 2pF IREF Measurement Point GND 475 GND 49.9 2pF 475 0V This load condition is used for IDD, tjit(cc), tsk(o) and tjit(O) measurements. 0V 3.3V HCSL Output Load AC Test Circuit 3.3V HCSL Output Load AC Test Circuit Noise Power Phase Noise Plot SRCC[1:4] SRCT[1:4] tcycle n tcycle n+1 tjit(cc) = |tcycle n - tcycle n+1| 1000 Cycles f1 Offset Frequency f2 RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers Cycle-to-Cycle Jitter RMS Phase Jitter SRCCx Rise Edge Rate Fall Edge Rate SRCTx +150mV SRCCy 0.0V -150mV SRCTy SRCC SRCT tsk(o) Output Skew ICS841S104BGI-02 REVISION A JUNE 18, 2010 Differential Measurement Points for Rise/Fall Edge Rate 9 (c)2010 Integrated Device Technology, Inc. ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER Parameter Measurement Information, continued TSTABLE Clock Period (Differential) VRB Positive Duty Cycle (Differential) +150mV VRB = +100mV 0.0V VRB = -100mV -150mV Negative Duty Cycle (Differential) 0.0V SRCT SRCC SRCT SRCC VRB TSTABLE Differential Measurement Points for Ringback Differential Measurement Points for Duty Cycle/Period SRCC VMAX = 1.15V SRCC VCROSS_MAX = 550mV VCROSS_DELTA = 150mV VCROSS_MIN = 250mV SRCT SRCT VMIN = -0.30V Single-ended Measurement Points for Absolute Cross Point and Swing ICS841S104BGI-02 REVISION A JUNE 18, 2010 Single-ended Measurement Points for Delta Cross Point 10 (c)2010 Integrated Device Technology, Inc. ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER Applications Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS841S104I-02 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and 0.01F bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin. 3.3V VDD .01F 10 .01F 10F VDDA Figure 1. Power Supply Filtering Power Supply Sequence Requirement Power Sequence: The ICS841S104I-02 has a power supply sequence requirement. This device requires that VDD and VDDA are powered simultaneously. This device has been characterized using the recommended power supply filtering techniques in Figure 1. 1. VDD and VDDA Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins Differential Outputs All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. All unused differential outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. ICS841S104BGI-02 REVISION A JUNE 18, 2010 11 (c)2010 Integrated Device Technology, Inc. ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER Crystal Input Interface The ICS841S104I-02 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_IN C1 15pF X1 18pF Parallel Crystal XTAL_OUT C2 22pF Figure 2. Crystal Input Interface Overdriving the XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3A. The XTAL_OUT pin can be left floating. The maximum amplitude of the input signal should not exceed 2V and the input edge rate can be as slow as 10ns. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. 3.3V 3.3V R1 100 Ro ~ 7 Ohm C1 Zo = 50 Ohm XTAL_IN RS 43 R2 100 Driv er_LVCMOS 0.1uF XTAL_OUT Cry stal Input Interf ace Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface VCC=3.3V C1 Zo = 50 Ohm XTAL_IN R1 50 Zo = 50 Ohm 0.1uF XTAL_OUT LVPECL Cry stal Input Interf ace R2 50 R3 50 Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface ICS841S104BGI-02 REVISION A JUNE 18, 2010 12 (c)2010 Integrated Device Technology, Inc. ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER Recommended Termination Figure 4A is the recommended termination for applications which require the receiver and driver to be on a separate PCB. All traces should be 50 impedance. Figure 4A. Recommended Termination Figure 4B is the recommended termination for applications which require a point to point connection and contain the driver and receiver on the same PCB. All traces should all be 50 impedance. Figure 4B. Recommended Termination ICS841S104BGI-02 REVISION A JUNE 18, 2010 13 (c)2010 Integrated Device Technology, Inc. ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER Schematic Layout Figure 5 shows an example of ICS841S104I-02 application schematic. In this example, the device is operated at VDD = 3.3V. The 18pF parallel resonant 25MHz crystal is used. The C1 =18pF and C2 = 33pF are recommended for frequency accuracy. For different board layouts, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. Two examples of HCSL termination are shown in this schematic. The decoupling capacitors should be located as close as possible to the power pin. Logic Control Input Examples Set Logic Input to '1' VDD Set Logic Input to '0' VDD RU1 1K Zo = 50 R7 SRCC1 To Logic Input pins + VDD 33 VDD - TL5 R8 50 IREF RD2 1K Zo = 50 R9 50 Recommended for PCI Express Add-In Card 12 11 10 9 8 7 6 5 4 3 2 1 RD1 Not Install 33 TL3 RU2 Not Install To Logic Input pins R5 SRCT1 U1 IR EF VSS VD D VSS SR C C 1 SR C T 1 SR C C 2 SR C T 2 VD D VSS SR C C 3 SR C T 3 R13 475 Ohm HCSL Termination 13 14 15 16 17 18 19 20 21 22 23 24 VSS VD D A F R EQ_SEL VSS VD D XT AL_IN XT AL_OU T SC LK SD AT A VD D SR C T 4 SR C C 4 VDD=3.3V R3 10 C3 C4 0.01u 10uF 25MHz C2 33pF SRCC4 J1 5 SDA 4 3 2 SCL 1 R8 R9 Zo = 50 - TL7 X1 VDD C1 18pF R6 SP + TL6 R11 50 F p 8 1 VDD VDD Zo = 50 R7 SP VDD (U1-4) 0 0 R12 50 Recommended for PCI Express Point-to-Point Connection SC LK SD AT A VDDA F R EQ_SEL SRCT4 VDD VDD C5 0.1uF (U1-10) C6 0.1uF (U1-17) C7 0.1uF (U1-22) C8 0.1uF Figure 5. ICS841S104I-02 Application Schematic. ICS841S104BGI-02 REVISION A JUNE 18, 2010 14 (c)2010 Integrated Device Technology, Inc. ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER Power Considerations This section provides information on power dissipation and junction temperature for the ICS841S104I-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS841S104I-02 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. The maximum current at 85C is as follows: IDD_MAX = 65mA IDDA_MAX = 20mA * Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V *(65mA + 20mA) = 294.525mW * Power (outputs)MAX = 44.5mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 44.5mW = 178mW Total Power_MAX = 294.525mW + 178mW = 472.525mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125C. Limiting the internal transistor junction temperature, Tj, to 125C ensures that the bond wire and bond pad temperature remains below 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 77.5C/W per Table 8 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.473W * 77.5C/W = 121.6C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 8. Thermal Resistance JA for 24 Lead TSSOP, Forced Convection JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS841S104BGI-02 REVISION A JUNE 18, 2010 0 1 2.5 77.5C/W 73.2C/W 71.0C/W 15 (c)2010 Integrated Device Technology, Inc. ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 6. VDD IOUT = 17mA VOUT RREF = 475 1% RL 50 IC Figure 6. HCSL Driver Circuit and Termination HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation, use the following equations which assume a 50 load to ground. The highest power dissipation occurs when VDD_MAX. Power = (VDD_MAX - VOUT) * IOUT, since VOUT - IOUT * RL = (VDD_MAX - IOUT * RL) * IOUT = (3.465V - 17mA * 50) * 17mA Total Power Dissipation per output pair = 44.5mW ICS841S104BGI-02 REVISION A JUNE 18, 2010 16 (c)2010 Integrated Device Technology, Inc. ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER Reliability Information Table 9. JA vs. Air Flow Table for a 24 Lead TSSOP JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 77.5C/W 73.2C/W 71.0C/W Transistor Count The transistor count for ICS841S104I-02 is: 11,360 Package Outline and Package Dimensions Package Outline - G Suffix for 24 Lead TSSOP Table 10. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 24 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.90 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0 8 aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS841S104BGI-02 REVISION A JUNE 18, 2010 17 (c)2010 Integrated Device Technology, Inc. ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER Ordering Information Table 11. Ordering Information Part/Order Number 841S104BGI-02LF 841S104BGI-02LFT Marking ICS1S104BI02L ICS1S104BI02L Package "Lead-Free" 24 Lead TSSOP "Lead-Free" 24 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Temperature -40C to 85C -40C to 85C NOTE: Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS841S104BGI-02 REVISION A JUNE 18, 2010 18 (c)2010 Integrated Device Technology, Inc. ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER We've Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT's sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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