DATA SHEET
ICS841S104BGI-02 REVISION A JUNE 18, 2010 1 ©2010 Integrated Device Technology, Inc.
Crystal-to-HCSL 156.25MHz or
155.52MHz Clock Synthesizer
ICS841S104I-02
General Description
The ICS841S104I-02 is a PLL-based clock synthesizer specifically
designed for Ethernet and SONET™ Clock applications. This device
generates either a 156.25MHz or 155.52MHz differential HCSL clock
from an input reference of either 25MHz or 19.44MHz. The input
reference may be derived from an external source or by the addition
of a 25MHz or a 19.44MHz crystal to the on-chip crystal oscillator.
An external reference may be applied to the XTAL_IN pin with the
XTAL_OUT pin left floating. An I2C bus interface is used to enable or
disable each individual clock output. The ICS841S104I-02 is
available in a lead-free 24-Lead package.
Features
•Four 0.7V current mode differential HCSL output pairs
•Crystal oscillator interface: 25MHz or 19.44MHz
•Output frequency: 156.25MHz or 155.52MHz
•RMS phase jitter @ 156.25MHz (12kHz – 20MHz):
0.691ps (typical)
•Cycle-to-cycle jitter: 25ps (maximum)
•I2C support with readback capabilities up to 400kHz
•3.3V operating supply mode
•-40°C to 85°C ambient operating temperature
•Available lead-free (RoHS 6) package
OSC PLL Divider
Network
I2C
Logic
SDATA
SCLK
IREF
Pullup
Pullup
SRCT[1:4]
SRCC[1:4]
XTAL_IN
XTAL_OUT
FREQ_SEL Pulldown
4
4
4
ICS841S104I-02
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm package body
G Package
Top View
V
SS
V
DD
V
DD
V
SS
SRCC1
SRCT1
SRCC2
SRCT2
V
SS
SRCC3
SRCT3
IREF
SRCC4
SRCT4
SDATA
SCLK
FREQ_SEL
XTAL_OUT
XTAL_IN
V
DD
V
DD
V
DDA
V
SS
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Pin Assignment
Block Diagram
ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER
ICS841S104BGI-02 REVISION A JUNE 18, 2010 2 ©2010 Integrated Device Technology, Inc.
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Function Tables
Table 3. FREQ_SEL
NOTE: The slave receiver address is 11010100 (D4h) or 11010110 (D6h) based on the setting of the FREQ_SEL pin.
Number Name Type Description
1, 2 SRCT3, SRCC3 Output Differential output pair. HCSL interface levels.
3, 9, 11,
13, 16 VSS Power Power supply ground.
4, 10,
17, 22 VDD Power Positive supply pins.
5, 6 SRCT2, SRCC2 Output Differential output pair. HCSL interface levels.
7, 8 SRCT1, SRCC1 Output Differential output pair. HCSL interface levels.
12 IREF Input
An external fixed precision resistor (475Ω) from this pin to ground provides a
reference current used for differential current-mode SRCCx, SRCTx clock
outputs.
14 VDDA Power Analog supply for PLL.
15 FREQ_SEL Input Pulldown Selects output frequency and I2C address (See Table 3).
18,
19
XTAL_IN,
XTAL_OUT Input Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
20 SCLK Input Pullup I2C compatible SCLK. This pin has an internal pullup resistor.
LVCMOS/LVTTL interface levels.
21 SDATA I/O Pullup I2C compatible SDATA. This pin has an internal pullup resistor. Open drain.
LVCMOS/LVTTL interface levels.
23, 24 SRCT4, SRCC4 Output Differential output pair. HCSL interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CIN Input Capacitance 2pF
RPULLUP Input Pullup Resistor 51 kΩ
RPULLDOWN Input Pulldown Resistor 51 kΩ
FREQ_SEL Required Crystal (MHz) Output Frequency Configuration I2C Address
0 25 156.25MHz 11010100 (D4h)
1 19.44 155.52MHz 11010110 (D6h)
ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER
ICS841S104BGI-02 REVISION A JUNE 18, 2010 3 ©2010 Integrated Device Technology, Inc.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a
two-signal I2C serial interface is provided. Through the Serial Data
Interface, various device functions, such as clock output buffers, can
be individually enabled or disabled. The registers associated with the
serial interface initialize to their default settings upon power-up, and
therefore, use of this interface is optional. Clock device register
changes are normally made upon system initialization, if any are
required.
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block
write and block read operations from the controller. For block
write/read operation, the bytes must be accessed in sequential order
from lowest to highest byte (most significant bit first) with the ability to
stop after any complete byte has been transferred. For byte write and
byte read operations, the system controller can access individually
indexed bytes. The offset of the indexed byte is encoded in the
command code, as described in Table 4A.
The block write and block read protocol is outlined in Table 4B, while
Table 4C outlines the corresponding byte write and byte read
protocol. The slave receiver address is 11010100 (D4h) or
11010110 (D6h) based on the setting of the FREQ_SEL pin.
Table 4A.Command Code Definition
Table 4B. Block Read and Block Write Protocol
Bit Description
7 0 = Block read or block write operation, 1 = Byte read or byte write operation
6:5 Chip select address, set to “00” to access device
4:0 Byte offset for byte read or byte write operation. For block read or block write operations, these bits must be “00000”.
Bit Description = Block Write Bit Description = Block Read
1 Start 1 Start
2:8 Slave address - 7 bits 2:8 Slave address - 7 bits
9 Write 9 Write
10 Acknowledge from slave 10 Acknowledge from slave
11:18 Command Code - 8 bits 11:18 Command Code - 8 bits
19 Acknowledge from slave 19 Acknowledge from slave
20:27 Byte Count - 8 bits 20 Repeat start
28 Acknowledge from slave 21:27 Slave address - 7 bits
29:36 Data byte 1 - 8 bits 28 Read = 1
37 Acknowledge from slave 29 Acknowledge from slave
38:45 Data byte 2 - 8 bits 30:37 Byte Count from slave - 8 bits
46 Acknowledge from slave 38 Acknowledge
Data Byte/Slave Acknowledges 39:46 Data Byte 1 from slave - 8 bits
Data Byte N - 8 bits 47 Acknowledge
Acknowledge from slave 48:55 Data Byte 2 from slave - 8 bits
Stop 56 Acknowledge
Data Bytes from Slave/Acknowledge
Data Byte N from slave - 8 bits
Not Acknowledge
ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER
ICS841S104BGI-02 REVISION A JUNE 18, 2010 4 ©2010 Integrated Device Technology, Inc.
Table 4C. Byte Read and Byte Write Protocol
Control Registers
Table 4D. Byte 0: Control Register 0
NOTE: Pup denotes power-up.
Table 4E. Byte 1: Control Register 1
Table 4F. Byte 2: Control Register 2
Bit Description = Byte Write Bit Description = Byte Read
1Start 1 Start
2:8 Slave address - 7 bits 2:8 Slave address - 7 bits
9 Write 9 Write
10 Acknowledge from slave 10 Acknowledge from slave
11:18 Command Code - 8 bits 11:18 Command Code - 8 bits
19 Acknowledge from slave 19 Acknowledge from slave
20:27 Data Byte- 8 bits 20 Repeat start
28 Acknowledge from slave 21:27 Slave address - 7 bits
29 Stop 28 Read
29 Acknowledge from slave
30:37 Data from slave - 8 bits
38 Not Acknowledge
39 Stop
Bit @Pup Name Description
7 0 Reserved Reserved
6 1 SRC[T/C]4
SRC[T/C]4 Output Enable
0 = Disable (Hi-Z)
1 = Enable
5 1 SRC[T/C]3
SRC[T/C]3 Output Enable
0 = Disable (Hi-Z)
1 = Enable
4 1 SRC[T/C]2
SRC[T/C]2 Output Enable
0 = Disable (Hi-Z)
1 = Enable
3 1 SRC[T/C]1
SRC[T/C]1 Output Enable
0 = Disable (Hi-Z)
1 = Enable
2 1 Reserved Reserved
1 0 Reserved Reserved
0 0 Reserved Reserved
Bit @Pup Name Description
7 0 Reserved Reserved
6 0 Reserved Reserved
5 0 Reserved Reserved
4 0 Reserved Reserved
3 0 Reserved Reserved
2 0 Reserved Reserved
1 0 Reserved Reserved
0 0 Reserved Reserved
Bit @Pup Name Description
7 1 Reserved Reserved
6 1 Reserved Reserved
5 1 Reserved Reserved
4 0 Reserved Reserved
3 1 Reserved Reserved
2 0 Reserved Reserved
1 1 Reserved Reserved
0 0 Reserved Reserved
ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER
ICS841S104BGI-02 REVISION A JUNE 18, 2010 5 ©2010 Integrated Device Technology, Inc.
Table 4G. Byte 3:Control Register 3
NOTE: Pup denotes power-up.
Table 4H. Byte 4: Control Register 4
Table 4I. Byte 5: Control Register 5
Table 4J. Byte 6: Control Register 6
Table 4K. Byte 7: Control Register 7
Bit @Pup Name Description
7 1 Reserved Reserved
6 0 Reserved Reserved
5 1 Reserved Reserved
4 0 Reserved Reserved
3 1 Reserved Reserved
2 1 Reserved Reserved
1 1 Reserved Reserved
0 1 Reserved Reserved
Bit @Pup Name Description
7 0 Reserved Reserved
6 0 Reserved Reserved
5 0 Reserved Reserved
4 0 Reserved Reserved
3 0 Reserved Reserved
2 0 Reserved Reserved
1 0 Reserved Reserved
0 1 Reserved Reserved
Bit @Pup Name Description
7 0 Reserved Reserved
6 0 Reserved Reserved
5 0 Reserved Reserved
4 0 Reserved Reserved
3 0 Reserved Reserved
2 0 Reserved Reserved
1 0 Reserved Reserved
0 0 Reserved Reserved
Bit @Pup Name Description
7 0 TEST_SEL REF/N or Hi-Z Select
0 = Hi-Z, 1 = REF/N
60TEST_MODE
TEST Clock
Mode Entry Control
0 = Normal Operation,
1 = REF/N or Hi-Z Mode
5 0 Reserved Reserved
4 1 Reserved Reserved
3 0 Reserved Reserved
2 0 Reserved Reserved
1 1 Reserved Reserved
0 1 Reserved Reserved
Bit @Pup Name Description
7 0 Revision Code Bit 3
6 0 Revision Code Bit 2
5 0 Revision Code Bit 1
4 0 Revision Code Bit 0
3 0 Vendor ID Bit 3
2 0 Vendor ID Bit 2
1 0 Vendor ID Bit 1
0 1 Vendor ID Bit 0
ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER
ICS841S104BGI-02 REVISION A JUNE 18, 2010 6 ©2010 Integrated Device Technology, Inc.
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 5A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
NOTE: The device has a power sequence requirement, refer to the Applications Section.
Table 5B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Table 6. Crystal Characteristics
NOTE: Characterized using an 18pF parallel resonant crystal.
Item Rating
Supply Voltage, VDD 4.6V
Inputs, VI
XTAL_IN
Other Inputs
0V to VDD
-0.5V to VDD + 0.5V
Outputs, VO-0.5V to VDD + 0.5V
Package Thermal Impedance, θJA 77.5°C/W (0 mps)
Storage Temperature, TSTG -65°C to 150°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Positive Supply Voltage 3.135 3.3 3.465 V
VDDA Analog Supply Voltage VDD – 0.21 3.3 VDD V
IDD Power Supply Current 71 mA
IDDA Analog Supply Current 21 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH Input High Voltage 2.2 VDD + 0.3 V
VIL Input Low Voltage -0.3 0.8 V
IIH Input High Current SDATA, SCLK VDD = VIN = 3.465V 10 µA
FREQ_SEL VDD = VIN = 3.465V 150 µA
IIL Input Low Current SDATA, SCLK VDD = 3.465V, VIN = 0V -150 µA
FREQ_SEL VDD = 3.465V, VIN = 0V -10 µA
Parameter Test Conditions Minimum Typical Maximum Units
Mode of Oscillation Fundamental
Frequency 19.44 or 25 MHz
Equivalent Series Resistance (ESR) 50 Ω
Shunt Capacitance 7pF
ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER
ICS841S104BGI-02 REVISION A JUNE 18, 2010 7 ©2010 Integrated Device Technology, Inc.
AC Electrical Characteristics
Table 7. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Characterized using 19.44MHz and 25MHz crystals.
NOTE 1: Refer to phase jitter plot.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 4: Measurement taken from differential waveform.
NOTE 5: TSTABLE is the time the differential clock must maintain a minimum ± 150mV differential voltage after rising/falling edges before it is
allowed to drop back into the VRB ±100mV differential range.
NOTE 6: Measurement taken from single-ended waveform.
NOTE 7: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 8: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 9: Measured at crossing point where the instantaneous voltage value of the rising edge of SRCT equals the falling edge of SRCC.
NOTE 10: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement.
NOTE 11: Defined as the total variation of all crossing voltages of rising SRCT and falling SRCC, This is the maximum allowed variance in
Vcross for any particular system.
NOTE 12: Measured from -150mV to +150mV on the differential waveform (SRCT minus SRCC). The signal must be monotonic through the
measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fMAX Output Frequency Using 25MHz Crystal 156.25 MHz
Using 19.44MHz Crystal 155.52 MHz
tjit(Ø) Phase Jitter, RMS (Random);
NOTE 1
19.44MHz crystal, ƒ = 155.52MHz,
Integration Range: 12kHz – 20MHz 0.849 ps
25MHz crystal, ƒ = 156.25MHz,
Integration Range: 12kHz – 20MHz 0.691 ps
tsk(o) Output Skew; NOTE 2, 3 30 ps
tjit(cc) Cycle-to-Cycle Jitter; NOTE 2 PLL Mode 25 ps
tLPLL Lock Time 100 ms
VRB
Ring-back Voltage Margin;
NOTE 4, 5 -100 100 mV
VMAX Voltage High; NOTE 6, 7 1150 mV
VMIN Voltage Low; NOTE 6, 8 -300 mV
VCROSS
Absolute Crossing Voltage;
NOTE 6, 9, 10 250 550 mV
∆VCROSS
Total Variation of VCROSS over
all edges; NOTE 6, 9, 11 150 mV
Rise/Fall Edge Rate;
NOTE 6, 12
Measured between
150mV to +150mV 0.6 4.0 V/ns
odc Output Duty Cycle 48 52 %
ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER
ICS841S104BGI-02 REVISION A JUNE 18, 2010 8 ©2010 Integrated Device Technology, Inc.
Typical Phase Noise at 155.52MHz
Typical Phase Noise at 156.25MHz
Noise Power dBc
Hz
Offset Frequency (Hz)
Noise Power dBc
Hz
Offset Frequency (Hz)
ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER
ICS841S104BGI-02 REVISION A JUNE 18, 2010 9 ©2010 Integrated Device Technology, Inc.
Parameter Measurement Information
3.3V HCSL Output Load AC Test Circuit
Cycle-to-Cycle Jitter
Output Skew
3.3V HCSL Output Load AC Test Circuit
RMS Phase Jitter
Differential Measurement Points for Rise/Fall Edge Rate
475Ω
Measurement
Point
33Ω50Ω
50Ω
33Ω
Measurement
Point
49.9Ω
49.9Ω
HCSL
GND
2pF
2pF
0V
IREF
VDDA
VDD
3.3V±5%
3.3V±5%
➤
➤
➤
➤
tcycle n tcycle n+1
tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
SRCT[1:4]
SRCC[1:4]
tsk(o)
SRCTx
SRCCx
SRCTy
SRCCy
475Ω
50Ω
50Ω
HCSL
GND
0V
SCOPE
IREF
This load condition is used for IDD, tjit(cc), tsk(o) and tjit(Ø)
measurements.
3.3V±5%
VDDA
3.3V±5%
VDD
Offset Frequency
f1f2
Phase Noise Plot
RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers
Noise Power
-150mV
+150mV
0.0V
Fall Edge RateRise Edge Rate
SRCC -
SRCT
ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER
ICS841S104BGI-02 REVISION A JUNE 18, 2010 10 ©2010 Integrated Device Technology, Inc.
Parameter Measurement Information, continued
Differential Measurement Points for Ringback
Single-ended Measurement Points for Absolute Cross
Point and Swing
Differential Measurement Points for Duty Cycle/Period
Single-ended Measurement Points for Delta Cross Point
TSTABLE
V
RB
-150mV
V
RB
= -100mV
V
RB
= +100mV
+150mV
0.0V
V
RB
TSTABLE
SRCT -
SRCC
V
CROSS_MAX
= 550mV
V
CROSS_MIN
= 250mV
V
MAX
= 1.15V
V
MIN
= -0.30V
SRCC
SRCT
0.0V
Clock Period (Differential)
Positive Duty
Cycle (Differential)
Negative Duty
Cycle (Differential)
SRCT -
SRCC
V
CROSS_DELTA
= 150mV
SRCC
SRCT
ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER
ICS841S104BGI-02 REVISION A JUNE 18, 2010 11 ©2010 Integrated Device Technology, Inc.
Applications Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS841S104I-02 provides
separate power supplies to isolate any high switching noise from the
outputs to the internal PLL. VDD and VDDA should be individually
connected to the power supply plane through vias, and 0.01µF
bypass capacitors should be used for each pin. Figure 1 illustrates
this for a generic VDD pin and also shows that VDDA requires that an
additional 10Ω resistor along with a 10µF bypass capacitor be
connected to the VDDA pin.
Figure 1. Power Supply Filtering
Power Supply Sequence Requirement
The ICS841S104I-02 has a power supply sequence requirement.
This device requires that VDD and VDDA are powered simultaneously.
This device has been characterized using the recommended power
supply filtering techniques in Figure 1.
Power Sequence:
1. VDD and VDDA
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
Outputs:
Differential Outputs
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
V
DD
V
DDA
3.3V
10Ω
10µF.01µF
.01µF
ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER
ICS841S104BGI-02 REVISION A JUNE 18, 2010 12 ©2010 Integrated Device Technology, Inc.
Crystal Input Interface
The ICS841S104I-02 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in Figure
2 below were determined using a 25MHz, 18pF parallel resonant
crystal and were chosen to minimize the ppm error. The optimum C1
and C2 values can be slightly adjusted for different board layouts.
Figure 2. Crystal Input Interface
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3A. The XTAL_OUT pin can be left floating. The
maximum amplitude of the input signal should not exceed 2V and the
input edge rate can be as slow as 10ns. This configuration requires
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the signal in
half. This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50Ω
applications, R1 and R2 can be 100Ω. This can also be
accomplished by removing R1 and making R2 50Ω. By overdriving
the crystal oscillator, the device will be functional, but note, the device
performance is guaranteed by using a quartz crystal.
Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface
Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface
XTAL_IN
XTAL_OUT
X1
18pF Parallel Crystal
C1
15pF
C2
22pF
R2
100
R1
100
RS 43
Ro ~ 7 Ohm
Driver_LVCMOS
Zo = 50 Ohm C1
0.1uF
3.3V
3.3V
Cry stal Input Interf ace
XTA L _ I N
XTA L _ O U T
Cry stal Input Interface
XTAL_IN
XTAL_OUT
R3
50
C1
0.1uF
R2
50
R1
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
VCC=3.3V
ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER
ICS841S104BGI-02 REVISION A JUNE 18, 2010 13 ©2010 Integrated Device Technology, Inc.
Recommended Termination
Figure 4A is the recommended termination for applications which
require the receiver and driver to be on a separate PCB. All traces
should be 50Ω impedance.
Figure 4A. Recommended Termination
Figure 4B is the recommended termination for applications which
require a point to point connection and contain the driver and receiver
on the same PCB. All traces should all be 50Ω impedance.
Figure 4B. Recommended Termination
ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER
ICS841S104BGI-02 REVISION A JUNE 18, 2010 14 ©2010 Integrated Device Technology, Inc.
Schematic Layout
Figure 5 shows an example of ICS841S104I-02 application
schematic. In this example, the device is operated at VDD = 3.3V. The
18pF parallel resonant 25MHz crystal is used. The C1 =18pF and C2
= 33pF are recommended for frequency accuracy. For different board
layouts, the C1 and C2 may be slightly adjusted for optimizing
frequency accuracy. Two examples of HCSL termination are shown
in this schematic. The decoupling capacitors should be located as
close as possible to the power pin.
Figure 5. ICS841S104I-02 Application Schematic.
+
-
C1
18pF
TL5
Zo = 50
R12
50
VDD
18pF
VDD
SCLK
TL6
Zo = 50
VDD
VDD
SRCC4
Recommended for PCI
Express Add-In Card
R7 33
RD1
Not Install
Logic Control Input Examples
VDD=3.3V
To Logic
Input
pins
VDD
C4
0.01u
VDDA
R8 0
RU2
Not Install
C6
0.1uF
C3
10uF
C5
0.1uF
SDATA
R8
50
TL3
Zo = 50
RU1
1K
RD2
1K
(U1-10)
IREF
C8
0.1uF
R5 33
R3
10
VDD
VDD
SDA
HCSL Termination
SCL
C2
33pF
SRCC1
FREQ_SEL
J1
1
2
3
4
5
Recommended for PCI
Express Point-to-Point
Connection
SRCT4
(U1-17)
+
-
R9 0
X125MHz
R9
50
(U1-4)
To Logic
Input
pins
VDD
U1
1
2
3
4
5
6
7
8
9
10
11
1213
14
15
16
17
18
19
20
21
22
23
24 SRCT3
SRCC3
VSS
VDD
SRCT2
SRCC2
SRCT1
SRCC1
VSS
VDD
VSS
IREFVSS
VDDA
FREQ_SEL
VSS
VDD
XTAL_IN
XTAL_OUT
SCLK
SDATA
VDD
SRCT4
SRCC4
C7
0.1uF
R13
475 Ohm
Set Logic
Input to
'0'
R6
SP
VDD
TL7
Zo = 50
VDD
R11
50
(U1-22)
SRCT1
Set Logic
Input to
'1'
R7
SP
ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER
ICS841S104BGI-02 REVISION A JUNE 18, 2010 15 ©2010 Integrated Device Technology, Inc.
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS841S104I-02.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS841S104I-02 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
The maximum current at 85°C is as follows:
IDD_MAX = 65mA
IDDA_MAX = 20mA
• Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V *(65mA + 20mA) = 294.525mW
• Power (outputs)MAX = 44.5mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 44.5mW = 178mW
Total Power_MAX = 294.525mW + 178mW = 472.525mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 77.5°C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.473W * 77.5°C/W = 121.6°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 8. Thermal Resistance θJA for 24 Lead TSSOP, Forced Convection
θJA vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 77.5°C/W 73.2°C/W 71.0°C/W
ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER
ICS841S104BGI-02 REVISION A JUNE 18, 2010 16 ©2010 Integrated Device Technology, Inc.
3. Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.
HCSL output driver circuit and termination are shown in Figure 6.
Figure 6. HCSL Driver Circuit and Termination
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation,
use the following equations which assume a 50Ω load to ground.
The highest power dissipation occurs when VDD_MAX.
Power = (VDD_MAX – VOUT) * IOUT
,
since VOUT – IOUT * RL
= (VDD_MAX – IOUT * RL) * IOUT
= (3.465V – 17mA * 50Ω) * 17mA
Total Power Dissipation per output pair = 44.5mW
V
DD
V
OUT
R
L
50Ω
IC
➤
I
OUT = 17mA
R
REF =
475
Ω
± 1%
ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER
ICS841S104BGI-02 REVISION A JUNE 18, 2010 17 ©2010 Integrated Device Technology, Inc.
Reliability Information
Table 9. θJA vs. Air Flow Table for a 24 Lead TSSOP
Transistor Count
The transistor count for ICS841S104I-02 is: 11,360
Package Outline and Package Dimensions
Package Outline - G Suffix for 24 Lead TSSOP Table 10. Package Dimensions
Reference Document: JEDEC Publication 95, MO-153
θJA vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 77.5°C/W 73.2°C/W 71.0°C/W
All Dimensions in Millimeters
Symbol Minimum Maximum
N24
A1.20
A1 0.05 0.15
A2 0.80 1.05
b0.19 0.30
c0.09 0.20
D7.70 7.90
E6.40 Basic
E1 4.30 4.50
e0.65 Basic
L0.45 0.75
α0° 8°
aaa 0.10
ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER
ICS841S104BGI-02 REVISION A JUNE 18, 2010 18 ©2010 Integrated Device Technology, Inc.
Ordering Information
Table 11. Ordering Information
NOTE: Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Part/Order Number Marking Package Shipping Packaging Temperature
841S104BGI-02LF ICS1S104BI02L “Lead-Free” 24 Lead TSSOP Tube -40°C to 85°C
841S104BGI-02LFT ICS1S104BI02L “Lead-Free” 24 Lead TSSOP 2500 Tape & Reel -40°C to 85°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support
devices or critical medical instruments.
ICS841S104I-02 Data Sheet CRYSTAL-TO-HCSL 156.25MHZ or 155.52MHz CLOCK SYNTHESIZER
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
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