 
  
FEATURES APPLICATIONS
DESCRIPTION
ADS7887
ADS7888
SLAS468 – JUNE 2005
10-/8-Bit, 1.25-MSPS, MICRO-POWER, MINIATURESAR ANALOG-TO-DIGITAL CONVERTERS
•Base Band Converters in Radio Communi-•1.25-MHz Sample Rate Serial Device
cation•10-Bit Resolution – ADS7887
•Motor Current/Bus Voltage Sensors in Digital•8-Bit Resolution – ADS7888
Drives•Zero Latency
•Optical Networking (DWDM, MEMS Based•25-MHz Serial Interface
Switching)•Supply Range: 2.35 V to 5.25 V
•Optical Sensors•Battery Powered Systems•Typical Power Dissipation at 1.25 MSPS:
•Medical Instrumentations– 3.8 mW at 3-V V
DD
•High-Speed Data Acquisition Systems– 8 mw at 5-V V
DD
•High-Speed Closed-Loop Systems• ± 0.35 LSB INL, DNL – ADS7887• ± 0.15 LSB INL, ±0.1 LSB DNL – ADS7888•61dB SINAD, -84 dB THD – ADSA7887•49.5 dB SINAD, -67.5 dB THD – ADS7888•Unipolar Input Range: 0 V to V
DD•Power Down Current: 1 µA•Wide Input Bandwidth: 15 MHz at 3 dB•6-Pin SOT23 and SC70 Packages
The ADS7887 is a 10-bit, 1.25-MSPS analog-to-digital converter (ADC), and the ADS7888 is a 8-bit, 1.25-MSPSADC. The devices include a capacitor based SAR A/D converter with inherent sample and hold. The serialinterface in each device is controlled by the CS and SCLK signals for glueless connections with microprocessorsand DSPs. The input signal is sampled with the falling edge of CS, and SCLK is used for conversion and serialdata output.
The devices operate from a wide supply range from 2.35 V to 5.25 V. The low power consumption of the devicesmake them suitable for battery-powered applications. The devices also include a power saving powerdownfeature for when the devices are operated at lower conversion speeds.
The high level of the digital input to the device is not limited to device V
DD
. This means the digital input can go ashigh as 5.25 V when device supply is 2.35 V. This feature is useful when digital signals are coming from othercircuit with different supply levels. Also this relaxes restriction on power up sequencing.
The ADS7887 and ADS7888 are available in 6-pin SOT23 and SC70 packages and are specified for operationfrom -40°C to 125°C.
Micro-Power Miniature SAR Converter Family
BIT < 300 KSPS 300 KSPS – 1.25 MSPS
12-Bit ADS7866 (1.2 V
DD
to 3.6 V
DD
) ADS7886 (2.35 V
DD
to 5.25 V
DD
)10-Bit ADS7867 (1.2 V
DD
to 3.6 V
DD
) ADS7887 (2.35 V
DD
to 5.25 V
DD
)8-Bit ADS7868 (1.2 V
DD
to 3.6 V
DD
) ADS7888 (2.35 V
DD
to 5.25 V
DD
)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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SCLK
+IN
VDD
CDAC
SAR
COMPARATOR
OUTPUT
LATCHES
&
3−STATE
DRIVERS
CONVERSION
&
CONTROL
LOGIC
SDO
ADS7887/ADS7888 CS
ADS7887
ADS7888
SLAS468 – JUNE 2005
2
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ABSOLUTE MAXIMUM RATINGS
(1)
ADS7887
ADS7888
SLAS468 – JUNE 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the deviceplaced in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PACKAGE/ORDERING INFORMATION
(1)
MAXIMUM MAXIMUM NO MISSING
PACK-INTEGRAL DIFFEREN- CODES AT PACK- TRANSPORTAGE TEMPERATURE PACKAGE ORDERINGDEVICE LINEARITY TIAL RESOLUTION AGE MEDIADESIG- RANGE MARKING INFORMATION(LSB) LINEARITY (BIT) TYPE QUANTITYNATOR(LSB)
Tape andBAWQ ADS7887SDBVT
reel 2506-Pin
DBVSOT23
Tape andBAWQ ADS7887SDBVR
reel 3000ADS7887 ±0.75 ±0.5 10 –40 °C to 125 °C
Tape andBNI ADS7887SDCKT
reel 2506-Pin
DCKSC70
Tape andBNI ADS7887SDCKR
reel 3000
Tape andBAZQ ADS7888SDBVT
reel 2506-Pin
DBVSOT23
Tape andBAZQ ADS7888SDBVR
reel 3000ADS7888 ±0.3 ±0.3 8 –40 °C to 125 °C
Tape andBNH ADS7888SDCKT
reel 2506-Pin
DCKSC70
Tape andBNH ADS7888SDCKR
reel 3000
(1) For most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com.
UNIT
+IN to AGND –0.3 V to +V
DD
+0.3 V+V
DD
to AGND –0.3 V to 7.0 VDigital input voltage to GND –0.3V to (7.0 V)Digital output to GND –0.3 V to (+V
DD
+ 0.3 V)Operating temperature range –40 °C to 125 °CStorage temperature range –65 °C to 150 °CJunction temperature (T
J
Max) 150°CPower dissipation, SOT23 and SC70 packages (T
J
Max–T
A
)/ θ
JA
SOT23 295.2 °C/Wθ
JA
Thermal impedance
SC70 351.3 °C/WVapor phase (60 sec) 215 °CLead temperature, soldering
Infrared (15 sec) 220 °C
(1) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolutemaximum conditions for extended periods may affect device reliability.
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ADS7887 SPECIFICATIONS
ADS7887
ADS7888
SLAS468 – JUNE 2005
+V
DD
= 2.35 V to 5.25 V, T
A
= –40 °C to 125 °C, f
sample
= 1.25 MHz
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Full-scale input voltage span
(1)
0 V
DD
VAbsolute input voltage range +IN –0.20 V
DD
+0.20 VC
i
Input capacitance
(2)
21 pFI
Ilkg
Input leakage current T
A
= 125 °C 40 nA
SYSTEM PERFORMANCE
Resolution 10 BitsNo missing codes 10 BitsINL Integral nonlinearity –0.75 ±0.35 0.75 LSB
(3)
DNL Differential nonlinearity –0.5 ±0.35 0.5 LSBE
O
Offset error
(4) (5) (6)
–1.5 ±0.5 1.5 LSBE
G
Gain error
(5)
–1 ±0.5 1 LSB
SAMPLING DYNAMICS
Conversion time 25-MHz SCLK 530 560 nsAcquisition time 260 nsMaximum throughput rate 25-MHz SCLK 1.25 MHzAperture delay 5 nsStep Response 160 nsOvervoltage recovery 160 ns
DYNAMIC CHARACTERISTICS
THD Total harmonic distortion
(7)
100 kHz –84 –72 dBSINAD Signal-to-noise and distortion 100 kHz 60.5 61 dBSFDR Spurious free dynamic range 100 kHz 73 81 dBFull power bandwidth At –3 dB 15 MHz
DIGITAL INPUT/OUTPUT
Logic family — CMOS
VDD = 2.35 V to 5.25 V V
DD
– 5.25V
IH
High-level input voltage V0.4V
DD
= 5 V 0.8V
IL
Low-level input voltage VV
DD
= 3 V 0.4V
OH
High-level output voltage At I
source
= 200 µA V
DD
–0.2
VV
OL
Low-level output voltage At I
sink
= 200 µA 0.4
POWER SUPPLY REQUIREMENTS
+V
DD
Supply voltage 2.35 3.3 5.25 VAt V
DD
= 2.35 V to 5.25 V, 1.25-MHz throughput 2Supply current (normal mode) mAAt V
DD
= 2.35 V to 5.25 V, static state 1.5SCLK off 1Power down state supply current µASCLK on (25 MHz) 200V
DD
= 5 V 8 10Power dissipation at 1.25 MHz
mWthroughput
V
DD
= 3 V 3.8 6
(1) Ideal input span; does not include gain or offset error.(2) Refer Figure 36 for details on sampling circuit(3) LSB means least significant bit(4) Measured relative to an ideal full-scale input(5) Offset error and gain error ensured by characterization.(6) First transition of 000H to 001H at 0.5 × (V
ref
/2
10
)(7) Calculated on the first nine harmonics of the input frequency
4
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ADS7887
ADS7888
SLAS468 – JUNE 2005
ADS7887 SPECIFICATIONS (continued)+V
DD
= 2.35 V to 5.25 V, T
A
= –40 °C to 125 °C, f
sample
= 1.25 MHz
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
DD
= 5 V 5.5 7.5Power dissipation in static state mWV
DD
= 3 V 3 4.5Power down time 0.1 µsPower up time 0.8 µsInvalid conversions after power up 1
TEMPERATURE RANGE
Specified performance –40 125 °C
5
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ADS7888 SPECIFICATIONS
ADS7887
ADS7888
SLAS468 – JUNE 2005
+V
DD
= 2.35 V to 5.25 V, T
A
= –40 °C to 125 °C, f
sample
= 1.25 MHz
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Full-scale input voltage span
(1)
0 V
DD
VAbsolute input voltage range +IN –0.20 V
DD
+0.20 VC
i
Input capacitance
(2)
21 pFI
Ilkg
Input leakage current T
A
= 125 °C 40 nA
SYSTEM PERFORMANCE
Resolution 8 BitsNo missing codes 8 BitsINL Integral nonlinearity –0.3 ±0.15 0.3 LSB
(3)
DNL Differential nonlinearity –0.3 ±0.1 0.3 LSBE
O
Offset error
(4) (5) (6)
–0.5 ±0.15 0.5 LSBE
G
Gain error
(5)
–0.5 ±0.15 0.5 LSB
SAMPLING DYNAMICS
Conversion time 25-MHz SCLK 450 480 nsAcquisition time 1.5 MSPS mode, Figure 3 206 nsMaximum throughput rate 25-MHz SCLK 1.25 MHzAperture delay 5 nsStep Response 160 nsOvervoltage recovery 160 ns
DYNAMIC CHARACTERISTICS
THD Total harmonic distortion
(7)
100 kHz –67.5 –65 dBSINAD Signal-to-noise and distortion 100 kHz 49 49.5 dBSFDR Spurious free dynamic range 100 kHz 65 77 dBFull power bandwidth At –3 dB 15 MHz
DIGITAL INPUT/OUTPUT
Logic family — CMOSV
IH
High-level input voltage V
DD
= 2.35 V to 5.25 V V
DD
–0.4 5.25 VV
DD
= 5 V 0.8V
IL
Low-level input voltage VV
DD
= 3 V 0.4V
OH
High-level output voltage At I
source
= 200 µA V
DD
–0.2
VV
OL
Low-level output voltage At I
sink
= 200 µA 0.4
POWER SUPPLY REQUIREMENTS
+V
DD
Supply voltage 2.35 3.3 5.25 VAt V
DD
= 2.35 V to 5.25 V, 1.25-MHz 2throughputSupply current (normal mode) mAAt V
DD
= 2.35 V to 5.25 V, static state 1.5SCLK off 1Power down state supply current µASCLK on (25 MHz) 200V
DD
= 5 V 8 10Power dissipation at 1.25 MHz
mWthroughput
V
DD
= 3 V 3.8 6
(1) Ideal input span; does not include gain or offset error.(2) Refer Figure 36 for details on sampling circuit(3) LSB means least significant bit(4) Measured relative to an ideal full-scale input(5) Offset error and gain error ensured by characterization.(6) First transition of 000H to 001H at (V
ref
/2
8
)(7) Calculated on the first nine harmonics of the input frequency
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TIMING REQUIREMENTS (see Figure 1 )
ADS7887
ADS7888
SLAS468 – JUNE 2005
ADS7888 SPECIFICATIONS (continued)+V
DD
= 2.35 V to 5.25 V, T
A
= –40 °C to 125 °C, f
sample
= 1.25 MHz
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
DD
= 5 V 5.5 7.5Power dissipation in static state mWV
DD
= 3 V 3 4.5Power down time 0.1 µsPower up time 0.8 µsInvalid conversions after power up 1
TEMPERATURE RANGE
Specified performance –40 125 °C
All specifications typical at T
A
= –40 °C to 125 °C, V
DD
= 2.35 V to 5.25 V, unless otherwise specified.
PARAMETER TEST CONDITIONS
(1)
MIN TYP MAX UNIT
V
DD
= 3 V 14 ×t
SCLKADS7887
V
DD
= 5 V 14 ×t
SCLKt
conv
Conversion time nsV
DD
= 3 V 12 ×t
SCLKADS7888
V
DD
= 5V 12 ×t
SCLK
V
DD
= 3 V 40Minimum quiet time needed from bus 3-state to startt
q
nsof next conversion
V
DD
= 5 V 40V
DD
= 3 V 15 25t
d1
Delay time, CS low to first data (0) out nsV
DD
= 5 V 13 25V
DD
= 3 V 10t
su1
Setup time, CS low to SCLK low nsV
DD
= 5 V 10V
DD
= 3 V 15 25t
d2
Delay time, SCLK falling to SDO nsV
DD
= 5 V 13 25V
DD
< 3 V 7t
h1
Hold time, SCLK falling to data valid
(2)
nsV
DD
> 5 V 5.5V
DD
= 3 V 10 25t
d3
Delay time, 16th SCLK falling edge to SDO 3-state nsV
DD
= 5 V 8 20V
DD
= 3 V 25 40t
w1
Pulse duration, CS nsV
DD
= 5 V 25 40V
DD
= 3 V 17 30t
d4
Delay time, CS high to SDO 3-state, Figure 3 nsV
DD
= 5 V 15 25V
DD
= 3 V 0.4 ×t
SCLKt
wH
Pulse duration, SCLK high nsV
DD
= 5 V 0.4 ×t
SCLK
V
DD
= 3 V 0.4 ×t
SCLKt
wL
Pulse duration, SCLK low nsV
DD
= 5 V 0.4 ×t
SCLK
V
DD
= 3 V 25Frequency, SCLK MHzV
DD
= 5 V 25Delay time, second falling edge of clock and CS to V
DD
= 3 V -2 5t
d5
enter in powerdown (use min spec not to accidently nsV
DD
= 5 V -2 5enter in powerdown) Figure 4Delay time, CS and 10th falling edge of clock to V
DD
= 3 V 2 -5t
d6
enter in powerdown (use max spec not to accidently nsV
DD
= 5 V 2 -5enter in powerdown) Figure 4
(1) 3-V Specifications apply from 2.35 V to 3.6 V, and 5-V specifications apply from 4.75 V to 5.25 V.(2) With 50-pf load.
7
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DEVICE INFORMATION
3
2
4
6
1
VDD
GND
VIN
CS
SCLK
SDO
5
ADS7887 NORMAL OPERATION
12 4 5614 15
CS
SCLK
SDO 00 0 D9 D8 D1 D0
13
0 0
16
td1 td2 th1
tconv
1/throughput
tq
td3
tw1
b
tsu1
a
ADS7887
ADS7888
SLAS468 – JUNE 2005
SOT23/SC70 PACKAGE
(TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNAME NO.
V
DD
1 – Power supply input also acts like a reference voltage to ADC.GND 2 – Ground for power supply, all analog and digital signals are referred with respect to this pin.VIN 3 I Analog signal inputSCLK 4 I Serial clockSDO 5 O Serial data outCS 6 I Chip select signal, active low
The cycle begins with the falling edge of CS. This point is indicated as ain Figure 1 . With the falling edge of CS,the input signal is sampled and the conversion process is initiated. The device outputs data while the conversionis in progress. The data word contains 4 leading zeros, followed by 10-bit data in MSB first format and padded by2 lagging zeros.
The falling edge of CS clocks out the first zero, and a zero is clocked out on every falling edge of the clock untilthe third edge. Data is in MSB first format with the MSB being clocked out on the 4th falling edge. Data is paddedwith two lagging zeros as shown in Figure 1 . On the 16th falling edge of SCLK, SDO goes to the 3-statecondition. The conversion ends on the 14th falling edge of SCLK. The device enters the acquisition phase on thefirst rising edge of SCLK after the 13th falling edge. This point is indicated by bin Figure 1 .
CS can be asserted (pulled high) after 16 clocks have elapsed. It is necessary not to start the next conversion bypulling CS low until the end of the quiet time (t
q
) after SDO goes to 3-state. To continue normal operation, it isnecessary that CS is not pulled high until point b. Without this, the device does not enter the acquisition phaseand no valid data is available in the next cycle. (Also refer to power down mode for more details.) CS going highany time after the conversion start aborts the ongoing conversion and SDO goes to 3-state.
The high level of the digital input to the device is not limited to device V
DD
. This means the digital input can go ashigh as 5.25 V when the device supply is 2.35 V. This feature is useful when digital signals are coming fromanother circuit with different supply levels. Also, this relaxes the restriction on power up sequencing. However,the digital output levels (V
OH
and V
OL
) are governed by V
DD
as listed in the SPECIFICATIONS table.
Figure 1. ADS7887 Interface Timing Diagram
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ADS7888 NORMAL OPERATION
12 4 5612 15
CS
SCLK
SDO 00 0 D7 D6 D1 D0
11
00
16
td1 td2 th1
tconv
1/throughput
tq
td3
tw1
b
tsu1
a
0
12 4 5612
CS
SCLK
SDO 00 0 D7 D6 D1 D0
11
td1 td2 th1
tconv
1/throughput
tq
th1
tw1
b
tsu1
a
td4
POWER DOWN MODE
ADS7887
ADS7888
SLAS468 – JUNE 2005
The cycle begins with the falling edge of CS . This point is indicated as ain Figure 2 . With the falling edge of CS,the input signal is sampled and the conversion process is initiated. The device outputs data while the conversionis in progress. The data word contains 4 leading zeros, followed by 8-bit data in MSB first format and padded by4 lagging zeros.
The falling edge of CS clocks out the first zero, and a zero is clocked out on every falling edge of the clock untilthe third edge. Data is in MSB first format with the MSB being clocked out on the 4th falling edge. Data is paddedwith four lagging zeros as shown in Figure 2 . On the 16th falling edge of SCLK, SDO goes to the 3-statecondition. The conversion ends on the 12th falling edge of SCLK. The device enters the acquisition phase on thefirst rising edge of SCLK after the 11th falling edge. This point is indicated by bin Figure 2 .
CS can be asserted (pulled high) after 16 clocks have elapsed. It is necessary not to start the next conversion bypulling CS low until the end of the quiet time (t
q
) after SDO goes to 3-state. To continue normal operation, it isnecessary that CS is not pulled high until point b. Without this, the device does not enter the acquisition phaseand no valid data is available in the next cycle. (Also refer to power down mode for more details.) CS going highany time after the conversion start aborts the ongoing conversion and SDO goes to 3-state.
The high level of the digital input to the device is not limited to device V
DD
. This means the digital input can go ashigh as 5.25 V when the device supply is 2.35 V. This feature is useful when digital signals are coming fromanother circuit with different supply levels. Also, this relaxes the restriction on power up sequencing. However,the digital output levels (V
OH
and V
OL
) are governed by V
DD
as listed in the SPECIFICATIONS section.
Figure 2. ADS7888 Interface Timing Diagram
As shown in Figure 3 , the ADS7888 can achieve 1.5-MSPS throughput. CS can be pulled high after the 12thfalling edge (with a 25-MHz SCLK). SDO goes to 3-state after the LSB (as CS is high). CS can be pulled low atthe end of the quiet time (t
q
) after SDO goes to 3-state.
Figure 3. ADS7888 Interface Timing Diagram, Data Transfer with 12-Clock Frame
The device enters power down mode if CS goes high anytime after the 2nd SCLK falling edge to before the 10thSCLK falling edge. Ongoing conversion stops and SDO goes to 3-state under this power down condition asshown in Figure 4 .
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1 2 3 4 5 9 10 16
CS
SCLK
SDO
td5 td6
Invalid Data Valid Data
SDO
1 5432 6 10987 131211 161514 1 5432 6 10987 131211 161514
SCLK
Device Fully
Powered-Up
Device Starts
Powering Up
CS
ADS7887
ADS7888
SLAS468 – JUNE 2005
Figure 4. Entering Power Down Mode
A dummy cycle with CS low for more than 10 SCLK falling edges brings the device out of power down mode. Forthe device to come to the fully powered up condition it takes 0.8 µs. CS can be pulled high any time after the10th falling edge as shown in Figure 5 . It is not necessary to continue until the 16th clock if the next conversionstarts 0.8 µs after CS going low of the dummy cycle and the quiet time (t
q
) condition is met.
Figure 5. Exiting Power Down Mode
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TYPICAL CHARACTERISTICS ADS7887, ADS7888
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0 50 100 150 200 250 300 350 400 450
IDD − Supply Current − mA
fs − Sample Rate − KSPS
VDD = 5 V,
fSCLK = 25 MHz,
TA = 25C,
Power Down SCLK = Free Running
0
0.20
0.40
0.60
0.80
1
1.20
1.40
1.60
1.80
0 5 10 15 20 25
IDD − Supply Current − mA
fSCLK − SCLK Frequency − MHz
5 V VDD
2.35 V VDD
TA = 25C
30
20
10
0
−10
−20
−30
−40
−40 −20 20 8060 120
@ 5 V Input
@ 0 V Input
Leakage Current − nA
TA− Free-Air Temperature − C
040 100
ADS7887
ADS7888
SLAS468 – JUNE 2005
SUPPLY CURRENT SUPPLY CURRENT SUPPLY CURRENTvs vs vsSUPPLY VOLTAGE SCLK FREQUENCY SAMPLE RATE
Figure 6. Figure 7. Figure 8.
ANALOG INPUTLEAKAGE CURRENT
vsFREE-AIR TEMPERATURE
Figure 9.
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TYPICAL CHARACTERISTICS ADS7887
60.5
60.7
60.9
61.1
61.3
61.5
61.7
61.9
1 10 100 1000
fi − Input Frequency − kHz
SINAD − Signal-to-Noise and Distortion − dB
fs = 1.25 MSPS,
TA = 25C,
VDD = 5 V
61
61.1
61.2
61.3
61.4
61.5
61.6
61.7
61.8
61.9
62
2.35 3.075 3.8 4.525 5.25
fs = 1.25 MSPS,
fi = 100 kHz,
TA = 25C
SINAD − Signal-to-Noise and Distortion − dB
VDD − Supply Voltage − V
−90
−89
−88
−87
−86
−85
−84
−83
−82
−81
−80
1 10 100
fi − Input Frequency − kHz
fs = 1.25 MSPS,
TA = 25C,
VDD = 5 V
THD − Total Harmonic Distortion − dB
80
80.5
81
81.5
82
82.5
83
83.5
84
84.5
85
2.35 3.075 3.8 4.525 5.25
SFDR − Spurious Free Dynamic Range − dB
fs = 1.25 MSPS,
fi = 100 kHz,
TA = 25C
VDD − Supply Voltage − V
−90
−89
−88
−87
−86
−85
−84
−83
−82
−81
−80
2.35 3.075 3.8 4.525 5.25
fs = 1.25 MSPS,
fi = 100 kHz,
TA = 25C
THD − Total Harmonic Distortion − dB
VDD − Supply Voltage − V
80
80.5
81
81.5
82
82.5
83
83.5
84
84.5
85
110 100
SFDR − Spurious Free Dynamic Range − dB
fi − Input Frequency − kHz
fs = 1.25 MSPS,
TA = 25C,
VDD = 5 V
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
2.35 3.075 3.8 4.525 5.25
EG− Gain Error − LSBs
fs = 1.25 MSPS,
TA = 25C
VDD − Supply Voltage − V
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
−40 −20 0 20 40 60 80 100 120
EO− Offset Error − LSBs
fs = 1.25 MSPS,
VDD = 5 V
TA − Free-Air Temperature − °C
ADS7887
ADS7888
SLAS468 – JUNE 2005
SIGNAL-TO-NOISE SIGNAL-TO-NOISE TOTAL HARMONIC DISTORTIONAND DISTORTION AND DISTORTION vsvs vs INPUT FREQUENCYINPUT FREQUENCY SUPPLY VOLTAGE
Figure 10. Figure 11. Figure 12.
TOTAL HARMONIC DISTORTION SPURIOUS FREE DYNAMIC RANGE SPURIOUS FREE DYNAMIC RANGEvs vs vsSUPPLY VOLTAGE INPUT FREQUENCY SUPPLY VOLTAGE
Figure 13. Figure 14. Figure 15.
OFFSET ERROR OFFSET ERROR GAIN ERRORvs vs vsSUPPLY VOLTAGE FREE-AIR TEMPERATURE SUPPLY VOLTAGE
Figure 16. Figure 17. Figure 18.
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−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
−40 −20 0 20 40 60 80 100 120
EG− Gain Error − LSBs
TA − Free-Air Temperature − °C
fs = 1.25 MSPS,
VDD = 5 V
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
0 256 512 768 1024
DNL − LSBs
Output Code
VDD = 2.35 V,
fs = 1.25 MSPS,
TA = 25C
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
0 256 512 768 1024
Output Code
INL − LSBs
VDD = 2.35 V,
fs = 1.25 MSPS,
TA = 25C
ADS7887
ADS7888
SLAS468 – JUNE 2005
TYPICAL CHARACTERISTICS ADS7887 (continued)
GAIN ERROR
vsFREE-AIR TEMPERATURE
Figure 19.
DNL
Figure 20.
INL
Figure 21.
13
www.ti.com
−140
−120
−100
−80
−60
−40
−20
0
0 125000 250000 375000 500000 625000
Amplitude − dB
fi − Input Frequency − kHz
VDD = 2.35 V,
fs = 1.25 MSPS,
TA = 25C
fi = 100 kHz,
8192 Points
ADS7887
ADS7888
SLAS468 – JUNE 2005
TYPICAL CHARACTERISTICS ADS7887 (continued)
FFT
Figure 22.
14
www.ti.com
TYPICAL CHARACTERISTICS ADS7888
−70
−69.5
−69
−68.5
−68
−67.5
−67
−66.5
−66
−65.5
−65
1 10 100
THD − Total Harmonic Distortion − dB
VDD = 5 V,
fs = 1.25 MSPS,
TA = 25C
fi − Input Frequency − kHz
−70
−69.5
−69
−68.5
−68
−67.5
−67
−66.5
−66
−65.5
−65
2.35 3.075 3.8 4.525 5.25
THD − Total Harmonic Distortion − dB
VDD − Supply Voltage − V
fi = 100 kHz,
fs = 1.25 MSPS,
TA = 25C
75
76
77
78
79
80
81
82
83
84
85
2.35 3.075 3.8 4.525 5.25
SFDR − Spurious Free Dynamic Range − dB
VDD − Supply Voltage − V
fi = 100 kHz,
fs = 1.25 MSPS,
TA = 25C
75
75.5
76
76.5
77
77.5
78
78.5
79
79.5
80
1 10 100
SFDR − Spurious Free Dynamic Range − dB
VDD = 5 V,
fs = 1.25 MSPS,
TA = 25C
fi − Input Frequency − kHz
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
2.35 3.075 3.8 4.525 5.25
EG− Gain Error − LSBs
fs = 1.25 MSPS,
TA = 25C
VDD − Supply Voltage − V
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
2.35 3.075 3.8 4.525 5.25
EO− Offset Error − LSBs
fs = 1.25 MSPS,
TA = 25C
VDD − Supply Voltage − V
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
−40 −7 26 59 92 125
EO− Offset Error − LSBs
fs = 1.25 MSPS,
VDD = 5 V
TA − Free-Air Temperature − °C
ADS7887
ADS7888
SLAS468 – JUNE 2005
SIGNAL-TO-NOISE SIGNAL-TO-NOISE TOTAL HARMONIC DISTORTIONAND DISTORTION AND DISTORTION vsvs vs INPUT FREQUENCYINPUT FREQUENCY SUPPLY VOLTAGE
Figure 23. Figure 24. Figure 25.
TOTAL HARMONIC DISTORTION SPURIOUS FREE DYNAMIC RANGE SPURIOUS FREE DYNAMIC RANGEvs vs vsSUPPLY VOLTAGE INPUT FREQUENCY SUPPLY VOLTAGE
Figure 26. Figure 27. Figure 28.
OFFSET ERROR OFFSET ERROR GAIN ERRORvs vs vsSUPPLY VOLTAGE FREE-AIR TEMPERATURE SUPPLY VOLTAGE
Figure 29. Figure 30. Figure 31.
15
www.ti.com
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
−40 −7 26 59 92 125
EG− Gain Error − LSBs
fs = 1.25 MSPS,
TA = 25C
TA − Free-Air Temperature − °C
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
0 64 128 192 256
DNL − LSBs
Output Code
VDD = 2.35 V,
fs = 1.25 MSPS,
TA = 25C
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
0 64 128 192 256
Output Code
INL − LSBs
VDD = 2.35 V,
fs = 1.25 MSPS,
TA = 25C
ADS7887
ADS7888
SLAS468 – JUNE 2005
TYPICAL CHARACTERISTICS ADS7888 (continued)
GAIN ERROR
vsFREE-AIR TEMPERATURE
Figure 32.
DNL
Figure 33.
INL
Figure 34.
16
www.ti.com
−120
−100
−80
−60
−40
−20
0
0 125000 250000 375000 500000 625000
Amplitude − dB
fi − Input Frequency − kHz
TA = 25C
fi = 100 kHz,
8192 Points
ADS7887
ADS7888
SLAS468 – JUNE 2005
TYPICAL CHARACTERISTICS ADS7888 (continued)
FFT
Figure 35.
17
www.ti.com
APPLICATION INFORMATION
60
60 16 pF
20
5 pF
VDD
IN
GND
Driving the VIN and V
DD
Pins of the ADS7887 and ADS7888
VDD
VIN
GND
CS
SDO
SCLK
10 nF1 F
VDD
VDD
VIN
GND
CS
SDO
SCLK
10 nF1 F
GND
IN
OUT 3 V
1 F
5 V REF3030
ADS7887
ADS7888
SLAS468 – JUNE 2005
Figure 36. Typical Equivalent Sampling Circuit
The VIN input to the ADS7887 and ADS7888 should be driven with a low impedance source. In most casesadditional buffers are not required. In cases where the source impedance exceeds 200 Ω, using a buffer wouldhelp achieve the rated performance of the converter. The THS4031 is a good choice for the driver amplifierbuffer.
The reference voltage for the ADS7887 and ADS7888 A/D converters are derived from the supply voltageinternally. The devices offer limited low-pass filtering functionality on-chip. The supply to these converters shouldbe driven with a low impedance source and should be decoupled to the ground. A 1-µF storage capacitor and a10-nF decoupling capacitor should be placed close to the device. Wide, low impedance traces should be used toconnect the capacitor to the pins of the device. The ADS7887 and ADS7888 draw very little current from thesupply lines. The supply line can be driven by either:•Directly from the system supply.•A reference output from a low drift and low drop out reference voltage generator like REF3030 or REF3130.The ADS7887 and ADS7888 can operate off a wide range of supply voltages. The actual choice of thereference voltage generator would depend upon the system. Figure 38 shows one possible applicationcircuit.
•A low-pass filtered version of the system supply followed by a buffer like the zero-drift OPA735 can also beused in cases where the system power supply is noisy. Care should be taken to ensure that the voltage atthe V
DD
input does not exceed 7 V (especially during power up) to avoid damage to the converter. This canbe done easily using single supply CMOS amplifiers like the OPA735. Figure 39 shows one possibleapplication circuit.
Figure 37. Supply/Reference Decoupling Capacitors
Figure 38. Using the REF3030 Reference
18
www.ti.com
VDD
VIN
GND
CS
SDO
SCLK
10 nF1 F
1 F
7 V
_
+
R1
C1
R2
5 V
10
ADS7887
ADS7888
SLAS468 – JUNE 2005
APPLICATION INFORMATION (continued)
Figure 39. Buffering with the OPA735
19
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
ADS7887SDBVR ACTIVE SOT-23 DBV 6 3000 Pb-Free (RoHS
Exempt) CU SN Level-2-260C-1 YEAR -40 to 125 BAWQ
ADS7887SDBVT ACTIVE SOT-23 DBV 6 250 Pb-Free (RoHS
Exempt) CU SN Level-2-260C-1 YEAR -40 to 125 BAWQ
ADS7887SDBVTG4 ACTIVE SOT-23 DBV 6 TBD Call TI Call TI -40 to 125
ADS7887SDCKR ACTIVE SC70 DCK 6 3000 Pb-Free (RoHS
Exempt) CU SN Level-2-260C-1 YEAR -40 to 125 BNI
ADS7887SDCKT ACTIVE SC70 DCK 6 250 Pb-Free (RoHS
Exempt) CU SN Level-2-260C-1 YEAR -40 to 125 BNI
ADS7887SDCKTG4 ACTIVE SC70 DCK 6 TBD Call TI Call TI -40 to 125
ADS7888SDBVR ACTIVE SOT-23 DBV 6 3000 Pb-Free (RoHS
Exempt) CU SN Level-2-260C-1 YEAR -40 to 125 BAZQ
ADS7888SDBVT ACTIVE SOT-23 DBV 6 250 Pb-Free (RoHS
Exempt) CU SN Level-2-260C-1 YEAR -40 to 125 BAZQ
ADS7888SDBVTG4 ACTIVE SOT-23 DBV 6 TBD Call TI Call TI -40 to 125
ADS7888SDCKR ACTIVE SC70 DCK 6 3000 Pb-Free (RoHS
Exempt) CU SN Level-2-260C-1 YEAR -40 to 125 BNH
ADS7888SDCKT ACTIVE SC70 DCK 6 250 Pb-Free (RoHS
Exempt) CU SN Level-2-260C-1 YEAR -40 to 125 BNH
ADS7888SDCKTG4 ACTIVE SC70 DCK 6 TBD Call TI Call TI -40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 2
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ADS7887 :
•Military: ADS7887M
NOTE: Qualified Version Definitions:
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS7887SDBVR SOT-23 DBV 6 3000 177.8 9.7 3.2 3.1 1.39 4.0 8.0 Q3
ADS7887SDBVT SOT-23 DBV 6 250 177.8 9.7 3.2 3.1 1.39 4.0 8.0 Q3
ADS7887SDCKR SC70 DCK 6 3000 177.8 9.7 2.3 2.52 1.2 4.0 8.0 Q3
ADS7887SDCKT SC70 DCK 6 250 177.8 9.7 2.3 2.52 1.2 4.0 8.0 Q3
ADS7888SDBVR SOT-23 DBV 6 3000 177.8 9.7 3.2 3.1 1.39 4.0 8.0 Q3
ADS7888SDBVT SOT-23 DBV 6 250 177.8 9.7 3.2 3.1 1.39 4.0 8.0 Q3
ADS7888SDCKR SC70 DCK 6 3000 177.8 9.7 2.3 2.52 1.2 4.0 8.0 Q3
ADS7888SDCKT SC70 DCK 6 250 177.8 9.7 2.3 2.52 1.2 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jan-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS7887SDBVR SOT-23 DBV 6 3000 184.0 184.0 50.0
ADS7887SDBVT SOT-23 DBV 6 250 184.0 184.0 50.0
ADS7887SDCKR SC70 DCK 6 3000 184.0 184.0 50.0
ADS7887SDCKT SC70 DCK 6 250 184.0 184.0 50.0
ADS7888SDBVR SOT-23 DBV 6 3000 184.0 184.0 50.0
ADS7888SDBVT SOT-23 DBV 6 250 184.0 184.0 50.0
ADS7888SDCKR SC70 DCK 6 3000 184.0 184.0 50.0
ADS7888SDCKT SC70 DCK 6 250 184.0 184.0 50.0
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jan-2013
Pack Materials-Page 2
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