ANALOG LC?M0S DEVICES 12-Bit 5 pus ADC AD7572 1.1 Scope. This specification covers the detail requirements for a monolithic CMOS successive approximation 12-bit analog-to-digital converter with an on chip buried Zener reference and converting in 5 or 12 ys. 1.2 Part Number. The complete part number per Tables 1 and 2 of this specification are as follows: Device Part Number -1 AD7572S(X)05/883B and AD7572S(X)12/883B -2 AD7572T(X)05/883B and AD7572T(X)12/883B ~3 AD7572U(X)05/883B and AD7572U(X)12/883B 1.2.3 Case Outline. See Appendix 1 of General Specification ADI-M-1000: package outline: (X) Package Description Q Q-24 24-Pin Cerdip E E-28A 28-Contact LCC 1.3 Absolute Maximum Ratings. (T, = +25C, unless otherwise noted) Vpp toDGND .. 0... eee ete een et ene teen e nee nees -0.3.V,+7V Vg tO DGND 20. ec ee eee ene ene eee teen eaee +0.3V,-17V AGND to DGND 2... cece ete teeter eee re nenes -0.3 V, Vpp +0.3 V AIN to AGND 2... ee eee nn tree eee eee eee n enna -15V, +15 V Digital Input Voltage to DGND ww... ee eee et tees -0.3 V, Vpp +0.3 V Digital Output Voltage to DGND 2... ke eee ee ee eens 0.3 V, Vpp +0.3 V Power Dissipation (to +75C) 0... cece ce cee ene eee eet eee ees 1000 mW Derates above +75C oo. eee teen tee tenet eee ete neee 10 mW/C Operating Temperature Range ...... 2... ccc ee eee eee eee eens 55C to +125C Storage Temperature 2.0... ce cee cee eee eee eee een tenn eeae 65C to + 150C Lead Temperature (Soldering 10 sec) 2... 2... ee cee eee teenies +300C 1.5 Thermal Characteristics. Thermal Resistance 8j = 35C/W for Q-24 and E-28A y4 = 120C/W for Q-24 and E-28A REV. A ANALOG-TO-DIGITAL CONVERTERS 6-8 ANALOG-TO-DIGITAL CONVERTERS |AD7572SPECIFICATIONS Table 1. Design Sub Sub Sub Limit Group | Group | Group Test Symbol | Device | Tyis-Toax | 1 2,3 4 Test Condition! Units Resolution RES -1,2,3 | 12 Minimum Resolution for Which | Bits No Missing Codes Are Guaranteed Integral Nonlinearity INL ~1,2 1 1 1 +LSB max 3 3/4 1 3/4 1/2 Differential Nonlinearity DNL | -1,2,3 | 1 1 1 +LSB max Offset Error OE -1 6 4 6 +LSB max -2 5 4 5 3 =3 4 4 4 Full-Scale Error FSE -1 15 +LSB max -2,3 1S 10 Full-Scale Temp Co? FSTC -t 45 45 +ppm/C max -2,3 25 25 Analog Input Current -1,2,3 | 3.5 3.5 3.5 mA max Vaer Output Vaer ~1,2,3 -5.25 +1% V max Var Temp Co REFTC | -1 40 40 +ppm/C mex -2,3 20 20 Output Current Sink Capability -1,2,3 | 550 550 550 External Load Should Not Change | 1A max : During Conversion Digital Input Low Voltage Vir -1,2,3 | 0.8 0.8 0.8 V max Digital Input High Voltage Vim -1,2,3 | 24 2.4 2.4 V min Input Capacitance Coy ~1,2,3 | 10 pF max Input Current 1 Iny ~1,2,3 | 10 10 10 CS, RD, HBEN +pA max Input Current 2 ling ~1,2,3 | 20 20 20 CLKIN +yA max Digital Output Low Voltage Vor ~1,2,3 | 0.4 0.4 0.4 loin = 1.6 mA V max Digital Output High Voltage Vou -1,2,3 | 4.0 4.0 4.0 Isource = 200 pA V min Floating State Leakage Current lour ~1,2,3 | 10 10 10 pA max Floating State Output Capacitance | Copy ~1,2,3 | 15 pF max Supply Current fron: Vpp Top -1,2,3 | 7 7 7 mA max Supply Current from Vss Iss -1,2,3 | -12 ~12 -12 mA max Conversion Time* tconv -1,2,3 | 5 5 5 fork = 2.5 MHz ps max Synchronous Clock 12.5 12.5 12.5 12.5 fork = 1 MHz Conversion Time* tconv -1,2,3 | 48 4.8 4.8 forx = 2.5 MHz ps min Asynchronous Clock 5.2 5.2 5.2 ps max Conversion Time* lconv -1,2,3 [12 12 12 forx = 1 MHz ps min Asynchronous Clock 13 13 13 ps max NOTES Wop = +5 V + 5%, Veg = 15 V + 5%. Includes Internal Vgep Error. Includes Internal Vagp Drift. Order either AD7572YX05/883B or AD7572YX 12/883B. 6-86 ANALOG-TO-DIGITAL CONVERTERS REV. AAD7572 3.2.1 Functional Block Diagram and Terminal Assignments. AGND Ver AIN GG) (2) 1 NH 2.5k 24) Vi ae 12-BIT DAC + * BURIED ZENER 23) Vss REFERENCE SUCCESSIVE APPROXIMATION REGISTER AD7572 12-8IT LATCH 22) BUSY 4 8 21)cS CONTROL LoGic a = 20) RD 8 8 MULTIPLEXER 19) HBEN THREE-STATE THREE-STATE cLOcK 18) CLK OUT OUTPUT OUTPUT OSCILLATOR DRIVERS DRIVERS 17) CLK IN D118 DB? Da DGND 03/11 DOS Q Package E Package (DIP) (LCC) NA 2 > an [i j24] Yoo Sfz45 228 q@>dq2> > |a Vv 2 23] v. wer [2] [23] Ves 4 3 2 1 26 27 26 AGNO | 3 22] BUSY RA p11 iz 21] s p11 5 B10 [s 20| RD O10 6 AD7572 oo 7 os [6] 19] HBEN AD7572 TOP VIEW NC 8 ps C7 (Not to Seale) [va] CLK OUT TOP VIEW ps 9 (Not to Scale) { 8 7] CLKIN D7 D7 10 D6 [ 9 6] poe D 11 05 {io 5] p19 D4 {a 14] p20 12:13 14 15 16 17:18 petavurte & penn [12 13] o311 eo g258 8 NC = NOCONNECT a oa 3.2.4 Microcircuit Technology Group. This microcircuit is covered by Technology Group (81). REV. A cs RD HBEN NC CLK OUT CLKIN bos ANALOG-TO-DIGITAL CONVERTERS 6-87 ANALOG-TO-DIGITAL CONVERTERS aAD7572 4.2.1 Life Test Burn-In Circuit. Steady state life test is per MIL-STD-883 Method 1005. Burn-in is per MIL-STD-883 Method 1015 test condition (B). AD7572 TOP VIEW {Not to Scale) AD7572 TOP VIEW {Not to Scale} ov GND AIN CLK tS-AD -15V Ves +5V Vop TEST POINTS ov GND AIN CLK cS-RD TEST POINTS ~15V Vis +8V Vop NOTE BOARDS BUILT BEFORE 1989 HAVE FOLLOWING DIFFERENCES: RESISTOR ON Vor LINE IS 100R. AIN CONNECTS DIRECTLY TO GND. THEY ARE NOT USABLE FOR DYNAMIC BURN-IN, AD7572 Edge Connections a n JU 12 CYCLES @ 35kHz Static Burn-in Initialization 6-88 ANALOG-TO-DIGITAL CONVERTERS REV. AAD7972 AD7572 TIMING' Design Limit Test Symbol | Device | Ty, to Ty, | Units CS to RD Setup Time ty -1,2,3 | 0 ns min RD to BUSY Propagation Delay & 1,2,3 | 270 ns max Data Access Time after RD, C,=20 pF t;? ~1,2,3 | 120 ns max Data Access Time after RD, C, =100 pF 170 ns max RD Pulse Width t& -1,2,3 | ts ns min CS to RD Hold Time ts -1,2,3 | 0 ns min Data Setup Time after BUSY te ~1,2,3 | 100 ns max Bus Relinquish Time t,? -1,2,3 | 20 ns min 90 ms max HBEN to RD Setup Time ts -1,2,3 | 0 ns min HBEN to RD Hold Time ty -1,2,3 | 0 ns min Delay Between Successive Read Operations | t,o -1,2,3 | 200 ns min NOTES All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. *t; and t, are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V. 3t, is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2. Specifications subject to change without notice. 5V 5V 3ka2 3ka2 DBN DEN DBN DBN 3kQ Cc Cy 1, 10pF DGND L Loe DGND L DGND a. High-Z to Voy (ts) b. High-Z to Vo, (ts) a. Vo, to High-Z b. Vo, to High-Z and Vo, to Von (ts) and Voy, to Vo, te) Figure 1. Load Circuits for Access Time Figure 2. Load Circuits for Output Float Delay 6.0 Converter Details. Conversion start is controlled by the CS, RD and HBEN inputs. At the start of conversion the successive approximation register (SAR) is reset and the three-state data outputs are enabled. Once a conversion cycle has begun it cannot be restarted. During conversion, the internal 12-bit voltage mode DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 3, the AIN input con- nects to the comparator input via 2.5 kN. The DAC which has a similar 2.5 kQ output impedance con- nects to the same comparator input. Bit decisions are made by the comparator (zero crossing detector) which checks the addition of each successive weighted bit from the DAC output. The MSB decision is made 80 ns (typically) after the second falling edge of CLK IN following a conversion start. Similarly, the succeeding bit decisions are made approximately 80 ns after a CLK IN edge until conversion is fin- ished. At the end of conversion, the DAC output current balances the AIN input current. The SAR con- tents (12-bit data word) which represent the AIN input signal is loaded into a 12-bit latch. REV. A ANALOG-TO-DIGITAL CONVERTERS 6-89 ANALOG-TO-DIGITAL CONVERTERS aAD7572 AIN sam \ [ | 7. [J fo ac. COMPARATOR 54 | 1 t [ rT T | 2.5kQ " BUSY \ < / | i, 80ns TYP CLK IN j \ j t j \ j \ j \ j \ tt AD7572 | { | { 4 2 12-BIT D611 0810 OBI OBO LATCH (MsB) (LSB) Figure 3. AD7572 AIN Input Figure 4. Operating Waveforms Using an External Clock Source for CLK IN 6.1 Driving the Analog Input. During conversion, the AIN input current is modulated by the DAC output current at a rate equal to the CLK IN frequency (i.e., 2.5 MHz when CLK IN = 2.5 MHz). The analog input voltage must remain fixed during this period and as a result must be driven from an op amp or sample hold with a low output impedance. The output impedance of an op amp is equal to the open loop output impedance divided by the loop gain at the frequency of interest. Suitable devices capable of driving the AD7572 AIN input are the AD OP-27 and AD711 op amps or the AD585 sample hold. 6.2 Control Inputs Synchronization. In applications where the RD control input is not synchronized with the ADC clock then conversion time can vary from 12 to 13 CLK IN periods. This is because the ADC waits for the first falling CLK IN edge after conversion start before the conversion procedure begins. Without synchronization, this delay can vary from zero to an entire clock period. If a constant conversion time is required, then the following approach ensures a fixed 5 s conversion time for the AD7572XX 05 and 12.5 ws for the AD7572XX12: when initiating a conversion, RD must go low on either the rising edge of CLK IN or the falling edge of CLK OUT. 6.3 Unipolar Offset and Full-Scale Error Adjustment. In applications where absolute accuracy is important, then offset and full-scale error can be adjusted to zero. Offset error must be adjusted before full-scale error. Figure 5 shows the extra components required for full-scale error adjustment. Zero offset is achieved by adjusting the offset of the op amp driving AIN (i.e., Al in Figure 5.). For zero offset error apply 0.61 mV (i.e., 1/2 LSB) at Vy, and adjust the op amp offset voltage until the ADC output code flickers between 0000 0000 0000 and 0000 0000 0001. For zero full-scale error apply an analog input of 4.99817 V (i.e., FS 3/2 LSBs or last code transition) at Vin and adjust R1 until the ADC output code flickers between 1111 1111 1110 and 1111 1111 1111. 6-90 ANALOG-TO-DIGITAL CONVERTERS REV. AAD7572 AD OP-27 0-5V ADS5e5 ANALOG O INPUT Vin * ADDITIONAL PINS OMITTED FOR CLARITY AIN AD7572* 200 R2 20k AGND Figure &. Unipolar 0 to +5 V Operation with Gain Error Adjust 6.4 Bipolar Operation. Figures 6 and 7 show how bipolar operation can be achieved with the AD7572. Both circuits use an op amp to offset the analog signal (V;) by 2.5 V. Alternatively, the op amp (Al) can be replaced by a sam- ple hold as shown in Figure 24. The op amp transfer functions are given below: Figure 10: AIN = (Vyy + 2.5) volts Figure 12: AIN = (Vyy + 2.5) volts Both circuits have an analog input range of +2.5 V and an LSB size of 1.22 mV. The output codes are offset binary for Figure 6 and complimentary offset binary for Figure 7. ANALOG INPUT Vv 'N AD OP-27 AD711 R3 6.19k AD7572* *ADDITIONAL PINS OMITTED FOR CLARITY *ADDITIONAL PINS OMITTED FOR CLARITY Figure 6. AD7572 Bipolar Operation Output Code Figure 7. AD7572 Bipolar Operation Output Code is Offset Binary is Complementary Offset Binary Signal ranges other than +2.5 V are easily accommodated using different values of R3 and R4 for Figure 6, and a different R2 value for Figure 7. These resistors should be chosen such that the voltage range at AIN covers the full dynamic range (i.e., 0 V to 5 V) of the ADC. All resistors should be the same type and from the same manufacturer so that their temperature coefficients match. In measurement applications where absolute accuracy is required, offset and full-scale error can be adjusted to zero as in Figure 8. 6.5 Bipolar Offset and Full-Scale Error Adjustment. The bipolar circuit of Figure 6 can be adjusted for offset and full-scale errors, by including two potenti- ometers R5 and R6, as shown in Figure 8. Offset must be adjusted before full-scale error. This is achieved by applying an analog input of 0.61 mV (1/2 LSB) at Vy, and adjusting R5 until the ADC out- put code flickers between 1000 0000 0000 and 1000 0000 0001. REV. A ANALOG-TO-DIGITAL CONVERTERS 6-91 ANALOG-TO-DIGITAL CONVERTERS aAD7572 For full-scale error adjustment, the analog input must be at 2.49817 volts (i.e., FS/2 -3/2 LSBs or last transition point). Then R6 is adjusted until the ADC output code flickers between 1111 1111 1110 and 1111 1111 1121. A similar offset and full-scale error adjustment procedure may be employed for Figure 7 by making Rl and R2 variable. Offset must again be adjusted before full scale error. This is achieved by applying an analog input of 0.61 mV at V,,, and adjusting R1 until the ADC output code flickers between O111 1111 1110 and 0111 1111 1111. For full-scale error adjust, apply a signal source of 2.49817 V at Vj, and adjust R2 until the ADC out- put code flickers between 0000 0000 0000 and 0000 0000 0001. ANALOG INPUT o Vin & RB > 6.19k > S ADOP-27 ao711 RES ADsas 500$ Rag R2 13k 6.19k AD7572* *ADDITIONAL PINS OMITTED FOR CLAAITY Figure 8. AD7572 Bipolar Operation with Offset and Gain Error Adjust 6.6 Internal Reference. The AD7572 has an on-chip, buffered, temperature-compensated, buried Zener reference, which is fac- tory trimmed to 5.25 V + 1%. It is internally connected to the DAC and is also available at Pin 2 to provide up to 550 A current to an external load. For minimum code transition noise the reference output should be decoupled with a capacitor to filter out wideband noise from the reference diode (10 wF of tantalum in parallel with 100 nF ceramic). How- ever, large values of decoupling capacitor can affect the dynamic response and stability of the reference amplifier. A 10 resistor in series with the decoupling capacitors will eliminate this problem without adversely affecting the filtering effect of the capacitors. A simplified schematic of the reference with its recommended decoupling components is shown in Figure 9. AD7572 TEMPERATURE i COMPENSATION * To | Pp pac [| -5,.25V -15V AGND Veer Ly Ley O.1pF 40 + 10pF Figure 9. AD7572 Internal 5.25 V Reference 6-92 ANALOG-TO-DIGITAL CONVERTERS REV. A