TECHNICAL NOTE
System Power Supply LSIs for use in automotive electronics
Power Supply for system
With built-in for system
Communication functions
BD9401FM/BD9403FV
zDescription
The BD9401FM/BD9403FV can be combined with the BD9400BFP to create application-specific, system power supplies.
The BD9401FM features 3 built-in channels: a 1 A LDO channel, a switching regulator controller channel, and a 500 mA
high-side switch channel. The BD9403FV features one built-in switching regulator controller channel. The combination of a
switching regulator with an LDO enables the IC to deliver reduced voltage consumption.
zFeatures
1. The IC can be combined with the BD9400BFP, providing design flexibility.
2. Broad input voltage range: 7 V to 36 V
3. Built-in 1 A variable LDO (BD9401FM)
4. Output voltage accuracy of ± 2% (BD9401FM LDO)
5. Built-in 500 mA high-side switch (BD9401FM)
6. Built-in open collector type PWM controller channel for design flexibility
7. Maximum frequency: 500 kHz
8. Built-in short protection circuit (SCP)
9. Built-in thermal shutdown circuit
10. HSOP-M28/SSOP-B14 package
zApplications
Car audio, satellite navigation systems, etc.
zAbsolute maximum ratings (Ta = 25°C)
Parameter Symbol Limit Unit
Power supply voltage 1 VCC 36*1 V
Power supply voltage 2 VLDOVcc 12*1 V
Power supply voltage 3 VREG, VREF 7 V
PWM output current IoMAX 100 mA
Power dissipation 1 (HSOPM28) P01 1.8*2 W
Power dissipation 2 (HSOPM28) P02 2.2*3 W
Power dissipation 3 (SSOPB14) P03 0.35*4 W
Power dissipation 4 (SSOPB14) P04 0.4*5 W
Operating temperature range TOPR -40 to +85 °C
Storage temperature range TSTG +150 °C
Maximum junction temperature TJMAX +150 °C
*1 Not to exceed Pd.
*2 Reduced by 14.4 mW/°C over 25°C during IC without heat sink operation.
*3 Reduced by 17.6 mW/°C over 25°C, when mounted on a glass epoxy board (70 mm × 70 mm × 1.6 mm).
*4 Reduced by 2.8 mW/°C over 25°C during IC without heat sink operation.
*5 Reduced by 3.2 mW/°C over 25°C, when mounted on a glass epoxy board (70 mm × 70 mm × 1.6 mm).
Ver.B Oct.2005
2/16
zRecommended operating ranges (Ta = 25°C) (Not to exceed Pd.)
Parameter Symbol Min. Max. Unit
Power supply voltage 1 VCC 8 26 V
Power supply voltage 2 VLDOVcc 3 11 V
Oscillating frequency FOSC 30 500 KHz
zElectrical characteristics 1:BD9401FM (Unless otherwise specified, Ta = 25°C; VCC = 13.5 V; VREF = 3.0 V; VREG = 5.0 V)
Limit
Parameter Symbol
Min. Typ. Max.
Unit Conditions
[Total supply current]
Total supply current VCC ICC — 200 400 µA PWMCTL = HSDCTL = 2 V, Io = 0 mA
Total supply current VREG IVREG — 0.68 — mA VREG = 5.0 V
Total supply current VREF IVREF — 0.96 — mA VREF = 3.0 V
Total supply current during
standby operation ISTBY — 1 10 µA VREF = VREG = PWMCTL = HSDCTL = 0 V
[Variable LDO regulator: 1 A]
Output voltage — 3.3 — V Io = 10 mA
NF voltage VNF 1.225 1.250 1.275 V
Output maximum current IPEAK 1.0 — — A
Line regulation ∆VOLI — 10 20 mV VLDOVcc = 5 V to 11 V
Load regulation ∆VOLO — 50 100 mV Io = 0 mA to 800 mA
Minimum I/O voltage
difference
∆VOLDO — 0.5 1.0 V Io = 800 mA
Ripple rejection R.R. 50 60 — dB Io = 10 mA, VIN = 0.1 Vp.p
[High-side switch: 500 mA]
Dropout voltage VDH — 0.5 1.0 V Io = 500 mA
Output maximum current IPEAKH 0.5 — — A
[High-side switch control pin]
Off voltage input range VHSDOFF 0 — 1.0 V
On voltage input range VHSDON 2.0 — VREF V
[Error amp]
INV pin threshold voltage VINV 1.225 1.250 1.275 V VFB = 3.0 V
INV pin input current IBIAS -1 — 1 uA VINV = 0 V
DC voltage gain AV — 60 — dB
Max. output voltage VFBM 2.0 2.4 2.8 V VINV = 2.0 V
Min. output voltage VFBL — — 0.1 V VINV = 2.0 V
Output sinking current IFBSI 1 2.5 4 mA VFB = 3 V, VINV = 0 V
Output source current IFBSO 50 100 200 uA VFB = 0 V, VINV = 2 V
[PWM comparator]
0% duty cycle VTH0D 0.90 1.00 1.10 V FB voltage, OSCIN = 1.0 V
100% duty cycle VTH100D 1.80 2.00 2.20 V FB voltage, OSCIN = 2.0 V
[Short protection circuit (SCP)]
INV pin short detection
voltage
VSINV 0.8 0.9 1.0 V
INV voltage
Voltage when SCP is off VSSCP — 50 100 mV SCP voltage
Threshold voltage 1 VT1SCP 0.85 1.05 1.2 V SCP voltage, SCD, OUT: HIGH
Threshold voltage 2 VT2SCP 1.80 2.00 2.2 V SCP voltage, PWM: OFF
SCP pin source current ISCP 1.5 2.5 4.0 µA VSCP = 0 V
[Undervoltage protection circuit (UVLO)]
Threshold voltage VUVLO — 5.70 — V Vcc = 13.5 V→5 V
Hysteresis voltage VHYS — 0.07 — V Vcc = 5 V→13.5 V ∆VUVLO
3/16
zElectrical Characteristics 2:BD9401FM (Unless otherwise specified, Ta = 25°C, Vcc = 13.5 V, STDY = 3.3 V, VREF = 3.0 V,
VREG = 5.0 V)
Limit
Parameter Symbol
Min. Typ. Max.
Unit Conditions
[PWM driver output block]
Output saturation voltage VSAT — 0.8 1.4 V Io = 75 mA, VFB = 3.0 V
Output current when DWM is off VDOFF — — 10 uA VPWMOUT = 30 V, VPNMCTL = 0 V
[Switching regulator control pin]
Off voltage input range VPNMOFF 0 — 1.0 V
On voltage input range VPWMON 2.0 — VREF V
[SCD (short protection detection) signal output pin]
SCD low output voltage VSCPL 0.0 — 1.0 V VSCP = 0 V
SCD high output voltage VSCOH 2.0 — VREF V VSCP = 2 V
zElectrical Characteristics 3:BD9403FV (Unless otherwise specified, Ta = 25°C, Vcc = 13.5 V, STDY = 3.3 V, VREF = 3.0 V,
VREG = 5.0 V)
Limit
Parameter Symbol
Min. Typ. Max.
Unit Conditions
[Total supply current]
Total supply current VCC ICC — 200 400 µA Io = 10 mA
Total supply current VREG IVREG — 0.68 — mA VREG = 5.0 V
Total supply current VREF IVREF — 0.96 — ｍA VREF = 3.0 V
Total supply current during
standby operation ISTBY — 1 10 µA VREF = VREG = PWMCTL = 0 V
[Error amp]
INV pin threshold voltage VINV 1.225 1.250 1.275 V VFB = 3.0 V
INV pin input current IBIAS -1 — 1 uA VINV = 0 V
DC voltage gain AV — 60 — dB
Maximum output voltage VFBM 2.0 2.4 2.8 V VINV = 2.0 V
Minimum output voltage VFBL — — 0.1 V VINV = 2.0 V
Output sinking current IFBSI 1 2.5 4 mA VFB = 3 V, VINV = 0 V
Output source current IFBSO 50 100 200 uA VFB = 0 V, VINV = 2 V
[PWM comparator]
0% duty cycle VTH0D 0.90 1.00 1.10 V FB voltage, OSCIN = 1.0 V
100% duty cycle VTH100D 1.80 2.00 2.20 V FB voltage, OSCIN = 2.0 V
[Short protection circuit (SCP)]
INV pin short detection voltage VSINV 0.8 0.9 1.0 V INV voltage
Voltage when SCP is off VSSCP — 50 100 mV SCP voltage
Threshold voltage 1 VT1SCP 0.85 1.05 1.2 V
SCP voltage, SCD,
OUT: HIGH
Threshold voltage 2 VT2SCP 1.80 2.00 2.2 V SCP voltage, PWM OFF
SCP pin source current ISCP 1.5 2.5 4.0 µA VSCP = 0 V
[Undervoltage protection circuit (UVLO)]
Threshold voltage VUVLO — 5.70 — V Vcc = 13.5 V→5 V
Hysteresis voltage VHYS — 0.07 — V Vcc = 5 V→13.5 V ∆VdVLO
[PWM driver output block]
Output saturation voltage VSAT — 1.0 2.0 V Io = 75 mA
Output current when DWM is off VOFF — — 20 uA VPWMOUT = 30 V, VPWMCTL = 0 V
[Switching regulator control pin]
Off voltage input range VPWMOFF 0 — 1.0 V
On voltage input range VPWMON 2.0 — VREF V
[CD (short protection detection) signal output pin]
SCD low output voltage VSCDL 0.0 — 1.0 V VSCP = 0 V
SCD high output voltage VSCDH 2.0 — VREF V VSCP = 2 V
4/16
zReference Data (Unless otherwise specified, Ta = 25°C, Vcc = 13.5 V, VLDOVCC = 5 V, VREF = 3.0 V, VREG = 5.0 V)
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0 0.2 0.4 0.6 0.8 1 1.2
OUTPUT CURRENT ： ILDO [A]
DROPOUT VOLTAGE
： VLDROPOUT[V]
0
1
2
3
4
5
024681012
INPUT VOLTAGE ： VLDOVCC [V]
OUTPUT VOLTAGE
： VLDOO [V]
0
0.2
0.4
0.6
0.8
1
0 5 10 15 20 25 30 35 40
INPUT VOLTAGE ： VCC [V]
INPUT CURRENT ： ICC[mA]
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
01234
OUTPUT VOLTAGE:Vref [V]
OUTPUT:CURRENT:IREF[mA]
0
0.5
1
1.5
2
2.5
0 5 10 15 20 25 30 35
INPUT VOLTAGE：VCC [V]
INPUT CURRENT ： ICC [mA]
0
100
200
300
400
500
024681012
INPUT VOLTAGE：VLDOVCC [V]
INPUT CURRENT ： ILDOVCC[µA]
0
100
200
300
400
500
600
0 5 10 15 20 25 30 35 40
INPUT VOLTAGE ： VCC [V]
INPUT CURRENT ： ISTBY[µA]
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
01234
INPUT VOLTAGE ： VREF [V]
INPUT CURRENT ： I_VREF [mA
]
0
0.2
0.4
0.6
0.8
1
1.2
012 3456
INPUT VOLTAGE ： VREG [V]
INPUT CURRENT ： I_VREG[mA
]
0
1
2
3
4
5
024 681012
INPUT VOLTAGE ： VLDOVCC [V]
OUTPUT VOLTAGE
： VLDOO[V]
0
1
2
3
4
00.5 11.5 22.5
OUTPUT CURRENT ： ILDOvcc [A]
OUTPUT VOLTAGE
： VLDO[V]
Fig.1 VCC Total Supply Current
(BD9401FM)
Fig.6 VCC Total Supply Current
(BD9403FV)
Fig.5 Total Supply Current
When CTL Is Off
(BD9401FM)
Fig.4 VREG Total Supply Current
(BD9401FM)
Fig.7 VREF Total Supply Current
(BD9403FV)
Fig.8 VREG Total Supply Current
(BD9403FV) Fig.9 LDO Input Stability (1)
(Io = 0 mA)
Fig.10 LDO Input Stability (2)
(When VOUT setting = 3.3 V;
Io = 200 mA)
Fig.11 LDO Load Stability
(When VOUT setting = 3.3 V) Fig.12 LDO I/O Voltage Differential
Fig.3 VREF Total Supply Current
(BD9401FM)
0
0.2
0.4
0.6
0.8
1
1.2
0123456
INPUT VOLTAGE ： VREG [V]
INPUT CURRENT ： I_VREG[mA
]
Fig.2 VLDOVcc Total Supply Current
（BD9401FM）
5/16
Fig.13 LDO Output Voltage
vs Temperature
Fig.14 LDO Ripple Rejection Fig.15 High-Side Switch
Output When Off
Fig.16 High-Side Switch I/O
(Output Load: ∞)
Fig.17 High-Side Switch I/O
(Output Load: 50 Ω)
Fig.18 High-Side Switch Load Current
Fig.19 ERRAMP Frequency Fig.20 Error Amp I/O
(VINV vs VFB)
Fig.21 PWM Output Current
Fig.22 Leak When PWM
Output Is Off
Fig.23 PWM Output FB vs Duty Fig.24 Short Protection Timer
-20
-10
0
10
20
30
40
50
60
70
80
90
10 100 1000 10000 100000
Fr eq uency:f[Hz]
RIPPLE REJECTION:RR[dB
]
0
5
10
15
20
25
0 5 10 15 20 25
INPUT VOLTAGE:VCC [V]
OUTPUT VOLTAGE:VHSDSW[V
VCC [V]
0
2
4
6
8
10
12
14
16
0 0.2 0.4 0.6 0.8 1 1.2 1.4
OUTPUT CURRENT:IHSDSW [A]
OUTPUT VOLTAGE:VHSDSW[V
0
0.5
1
1.5
2
2.5
3
00.511.522.5
INPUT VOLTAGE:VINV [V]
OUTPUT VOLTAGE:VFB[V
]
0
100
200
300
400
500
0 0.5 1 1.5 2 2.5 3
OUTPUT VOLTAGE:VPWMOUT [V]
OUTPT CURRENT:IPWMOUT[mA]
0
1
2
3
4
5
0 5 10 15 20 25 30 35
INPUT VOLTAGE:VCC [V]
OUTPUT CURRENT:I_PWMLeak[µA
]
0
20
40
60
80
100
1 1.2 1.4 1.6 1.8 2
INPUT VOLTAGE:VFB [V]
DUTY:DUTY[%]
012345678
Time:t[msec]
3.1
3.2
3.3
3.4
3.5
-40-30-20-10 0 1020304050607080
TEMPERATURE:Ta [℃]
OUTPUT VOLTAGE:VLDOUT [V
]
0
0.5
1
1.5
2
0 5 10 15 20 25 30 35
INPUT VOLTAGE:VCC [V]
OUTPUT VOLTAGE:VHSDSW[V
]
-20
-10
0
10
20
30
40
50
60
70
80
90
10 100 1000 10000 100000
Fr eq uency：f [Hz]
Gain
：G[dB]
0
5
10
15
20
25
0 5 10 15 20 25
INPUT VOLTAGE:VCC [V]
OUTPUTVOLTAGE:VHSDSW[V
]
VOUT
SCP
SCPOUT
6/16
zBlock Diagram (BD9401FM) zPin function descriptions (BD9401FM)
zPin Descriptions (BD9401FM)
Pin No. Pin name Function
1 OSCIN Triangular waveform input pin
2 SCDOUT Output short detection signal output pin (to BD9400BFP)
3 SCP Output short detection delay time setting capacitor connection pin
4 VREF Reference input VREF (3.0 V) input pin
5 VREG Reference input VREF (5.0 V) input pin
6 VCC Power supply input pin
7 GND Ground pin
8 HSDVCC High-side switch power supply input pin
9 HSDSW High-side switch output pin
10 N.C. NC pin
11 HSDCTL High-side switch On/off control pin
12 N.C. NC pin
13 N.C. NC pin
14 N.C. NC pin
15 LDOOUT LDO regulator output pin
16 N.C. NC pin
17 N.C. NC pin
18 VTGATE LDO regulator output PMOS gate pin
19 RICTL LDO regulator overcurrent protection adjustment resistance connection pin (connect to GND when not using)
20 NF LDO regulator output voltage setting resistance connection pin (reset input)
21 LDOVCC LDO regulator power supply input pin
22 N.C. NC pin
23 PWMGND PWM ground
24 PWMOUT PWM output pin
25 DTC Dead time control pin
26 FB Error amp output pin
27 INV Error amp inverted input pin
28 PWMCTL DC/DC control On/off switching pin
FIN FIN Heat dissipation fin; connect to ground.
PWMCTL
HSDCTL
HIGH-SIDE
SWITCH CTL
THD
VCC
GROUND
HSD SW
VREF
FB
LDOOUT
Err AMP.
PWM
COMP.
PNP DRIVER
SCP
OSCIN
VTGATE
NF
LDOVCC
PMWOUT
PWMGND
INV
DTC
SCD_OUT
VREG
UVLO
RICTL
PWMCTL
INV
FB
DTC
PWMOUT
PWMGND
NF
RICTL
VTGATE
LDOOUT
LDOVCC
N.C
OSCIN
SCDOUT
SCP
VREF
VREG
VCC
HSDVCC
HSDSW
HSDCTL
GND
N.C
N.C
N.C
N.C
N.C
N.C
Fig.25 BD9401FM Block Diagram
Fig.26 BD9401FM Pin Function Descriptions
HSD VCC
7/16
zBlock Diagram (BD9403FV)
zPin assignment diagram (BD9403FV)
zPin function descriptions (BD9403FV)
Pin No. Pin name Function
1 PWMGND PWM ground
2 PWMOUT PMW output pin
3 DTC Dead time control pin
4 FB Error amp output pin
5 INV Error amp inverted input pin
6 OSCIN Triangular waveform input pin
7 SCDOUT Output short detection signal output pin (to BD9400BFP)
8 SCP Output short detection delay time setting capacitor connection pin
9 VREF Reference input VREF (3.0 V) input pin
10 VREG Reference input VREF (5.0 V) input pin
11 PWMCTL DC/DC control On/off switching pin
12 VCC Power supply input pin
13 N.C NC pin
14 GND Ground pin
THD
Err AMP.
PWM
PNP
OFF
1.25V
0
1.0V
2.0V
DISCHARGE
UVLO
PWMCTL
VCC
GROUND
SCP
OSCIN
SCD_OUT
VREF
FB
PMWOUT
PWMGND
INV
DTC
VREG
SCP
VREF
VREG
VCC
PWMCTL
GND
N.C
OSCIN
SCDOUT
INV
FB
DTC
PWMOUT
PWMGND
Fig.27 BD9403FV Block Diagram
Fig.28 BD9403FV Pin Assignment Diagram
8/16
zApplication example
Fig.29 Application Example
56kΩ
0.1μF
10μF
100
p
F
GROUND
BD9400BFP
（MASTER）
SDA
SCL
VCC
SYNC+
SYNC-
HSD CTL1
SCP1
DC/DC CTL2
HSD CTL2
SCP2
3.3V 250mA
RESET
HSD_1
DC/DC CTL3
HSD CTL3
SCP3
LDO1
BD9401FM
SLAVE
DC/DC1
CT
RT
DELAY
DC/DC
VREF
VREG
LDO2
HSD_2
BD9401FM
SLAVE
LDO3
HSD_3
BD9401FM
SLAVE
DC/DC2
DC/DC3
VOUT
DGND
SYB
Y
STATUS_FLAG
1μF
0.033μF
100kΩ
100kΩ
10
μF
10μF
100Ω
220ｐF
0.033μF
50Ω
200Ω
33μH
1μF10kΩ
20kΩ
220
μF
25kΩ
75kΩ
30kΩ
30kΩ
10μF
100Ω
220ｐF
0.033μF
50
Ω
200Ω
33μH
1μF10kΩ
20kΩ
220
μF
25kΩ
75kΩ
30kΩ
30kΩ
10μF
100Ω
220ｐF
0.033μF
50
Ω
200Ω
33μH
1μF10kΩ
20kΩ
220
μF
25kΩ
35kΩ
30kΩ
50kΩ
10μF
10μF
0.1μF
10μF
0.1μF
VCC
GND
SCP
SCDOUT
HSDCTL
PWMCTL
OSCIN
HSDVCC
VREF
VREG
DTC
INV
FB
PWMOUT
LDOVcc
RICTL
LDOOUT
NF
HSDSW
9/16
zBlock operation descriptions
•LDO block
The LDO block consists of an output-stage PMOS 1 A LDO with variable output voltage.
The feedback voltage pin carries 1.25 V at a precision of ± 2%. The input LDO voltage range is 3 V to 11 V. This range is
independent of Vcc and assumes the connection of DC/DC output.
•High-side switch block
The high-side switch block consists of a high-side switch with a current capacity of 500 mA.
The HSD CTL pin provides on/off control.
The block incorporates a built-in overcurrent protection circuit.
•Error amp block
The error amp block connects the output feedback voltage to the INV pin. The reference voltage is connected internally to
the inverted input pin. The switching duty is controlled with output feedback to control the output voltage. Phase
compensation can be performed by connecting a capacitor or resistor between the INV and FB pins.
•PNM comparator
The triangular waveform from the BD9400BFP is input to the OSCIN pin. This triangular waveform and the FB voltage are
used to output a switching pulse to create the duty. A capacitor can be connected to the DTC pin to set the Soft-start.
•PNP driver
The duty output by the PWM comparator drives the output NPN open collector. The PNP base current can be set by
connecting a resistor to the PWM output.
•SCP block
The SCP block detects DC/DC converter output shorts and latches all output off after the set delay time elapses. The circuit
is cleared by setting DC/DC CTL from low to high. Detection is performed using the INV pin, and the timer starts when the
pin reaches 0.9 V. BD9401FM/BD9403FV short detection consists of 2 mode settings, with the short detection signal being
output to SCD-OUT after 1/2 the timer latch delay time. The timer time can be set with the capacitor connected to the SCP
pin.
•UVLO block
The IC incorporates a built-in UVLO (undervoltage lockout) circuit to prevent J output malfunctions, during periods of low
Vcc input. When Vcc falls to 5.7 V or lower, this circuit operates and turns off PWM output. When Vcc rises above the 5.7 V
hysteresis voltage (0.70 mA TYP), output is reset.
zTiming chart (DC/DC controller)
1) At startup
Fig.30 Timing Chart At Startup Time
VIN
DCDC CTL
FB
OSCIN
DTC
PWMOUT
10/16
2) During short protection
Fig.31 Timing Chart During Short Protection
zSelecting application components
Block name Setting procedure Calculation example
LDO
output voltage
VOUT = ((R1 + R2)/R2) × VNF
(VNF = 1.25 V)
Use a ceramic capacitor with a
capacitance of 1 µF or higher for
the output capacitor.
An electrolytic capacitor may also be
used. Use a capacitance value of
1,000 µF or lower.
VOUT = 1.8 V
(R1 + R2)/R2 = = 1.439 V
R1 = 0.439 × R2
R2 = 20 kΩ
R1 = 8.70 kΩ
DC/DC
output voltage
VOUT = ((R1 + R2)/R2) × VINV
(VINV = 1.25 V)
VOUT = 3.3 V
(R1 + R2)/R2 = =2.64 V
R1 = 1.64 × R2
R2 = 10 kΩ
R1 = 16.4 kΩ
VNF
VOUT
VINV
VOUT
R1
R2
VOUT
NF
LDOOUT
R2
R1
VINV
VOUT
VINV
SCP
SCD OUT
PWMOUT
PMWCTL
DTC
0.9 V
1.0 V
2.0 V
11/16
zSelecting application components
Block name Setting procedure Calculation example
MAX DUTY (DTC) VDTC = (R2/ (R1 + R2)) × VREF
Max DUTY =
(VDTC - VDD)/(VD100 - VDO) × 100 [%]
(VREF = 3.0 V, VD0 = 1.0 V,
VD100 = 2.0 V) (typ.)
R2 = 20 kΩ, R1 = 10 kΩ
VOTL = 2.0 V
Max DUTY =
(1.0/1.1) × 100 = 90.9%
Soft start
(DTC)
VFB =
(VOUT/VIN) × (VD100 - VDD) + VDO
VDTC = VREF × (1 - exp (- ))
VFB = VDTC
t = -C × R × IN (1 - VFB/VREF)
(VREF = 3.0 V, VD100 = 2.1 V,
VD0 = 1.0 V)
C = 10 µF1 R1 = 10 kΩ
VOUT = 3.3 V, Vcc= 13.5 V
t = 55 ms
Short protection
circuit
(SLP)
T1 = (CSCP × VSCP1) /ISCP
(ISCP = 2.5 µA, VSCP1 = 1 V,
VSCP2 = 2 V)
t1 = 50 ms
t2 = 100 ms
CCSCP = 0.125 µF
zSetting phase compensation
1. Application stability conditions
The following conditions are required in order to ensure the stability of the negative feedback circuit.
Because DC/DC converter applications use a switching frequency, the overall gain (BW) should be set to 1/10th the
switching frequency or lower. The target application characteristics can be summarized as follows:
•Phase lag should not exceed 150° at gain 1 (0 dB). (A minimum phase margin of 30°)
•BW (frequency with gain of 0 dB) should not exceed 1/10th the switching frequency.
Because the response is determined by the GBW limitation, it is necessary to use higher switching frequencies for quick
response.
One way to maintain stability through phase compensation involves canceling the secondary phase lag (-180°) caused by
LC resonance with a secondary phase advance (by inserting 2 phase advances).
Because the GMB is determined by the phase compensation capacitor, attached between the error amp output and INV
input, capacitance must be increased in order to lower the GBW.
CR
t
VFB
VDTC
t
VOUT
VSCP2
VSCP1
VSCP
SCPOUT
( to I2CBUS)
VOUT t1
t2
R1
C
VDTC
VREF
R1
12/16
(1) Standard integrator (low-pass filter) (2) Integrator's open loop characteristics
At point (a), fa = (Hz)
At point (b), fbGWB = (Hz)
The error amp performs phase compensation of types (1) and (2), making it act as a low-pass filter.
For DC/DC converter applications, R refers to feedback resistors connected in parallel.
2. When the output capacitor is an electrolytic capacitor or other capacitor with a large ESR
When the output capacitor's ESR is large (> 1 Ω), phase compensation is reasonably simple. Because LC resonant circuits
always exist in the output of DC/DC converter applications, the phase lag for those circuits is -180°. However, when an ESR
component is present, a +90° phase advance occurs, reducing the phase lag to -90°. This is an extremely effective way of
keeping the phase lag to within 150°C. However, it has the disadvantage of increasing the ripple component of the output
voltage.
(1) LC resonant circuit (2) With ESR
Fig. 34
One phase advance should be inserted due to variations in phase characteristics caused by ESR. This phase advance can
be accomplished by either of the following methods:
(3) Insert C1 into the feedback resistors (4) Insert R3 into the integrator
Fig. 36 Fig. 37
Phase advance fz = (Hz) Phase advance fz = (Hz)
To cancel LC resonance, set the phase advance frequency to the LC resonant frequency. This setting has been obtained in a
simple fashion and does not reflect a rigorous calculation, so adjustment may be required for the actual implementation.
These characteristics vary with board layout, load conditions, and other factors. They should be confirmed in the actual
implementation during the mass production design process.
+
-
R
Feedback
FB
A
C
-180
-90
0
0
A
-90°C
-180°C
(a)
GBW (b)
-20 dB/decade
Phase margin
Gain
[dB]
Phase
[ ]
1
1
2πRC
1
L
C
Vo
Vcc
L
C
Vo
Vcc
RESR
Resonance point and phase lag of -180° at
fr = LC2 π
1
[Hz]
Resonance point at fr = LC2 π
1
(Hz)
Phase advance at Fesr = CR2 πESR
1
(Hz)
Phase lag = -90°
2ππC1R
1
2ππC2R
1
Fig. 32 Fig. 33
Fig. 35
A
FB
INV
R2
R1
Vo
A
FB
INV
R2
R1 R3 C2
Vo
2πRCA
1
13/16
zI/O Equivalent circuits
Fig.38 I/O Equivalent Circuits
VREG
VCC
VREF Vcc
Vcc HSDVcc HSDVcc Vcc
SCP
Vcc VREF
VREF
VCC
VREG
VCC
10k
LDOOG
LDOVcc LDOVcc
LDOVCC
LDOVcc
VREG VCC
VCC VREG VCC VREG VREF
Vcc VREF
1k
1. OSCIN 2. SCDOUT 3. SCP
9. HSDSW 11. 28. HSDCTL
PWMCTL
15. LDOOUT
18. VTGATE
19. RICTL 20. NF
24. PWMOUT 25. DTC
26. FB
27. INV
14/16
zOperation Notes
1. Absolute maximum ratings
Use of the IC in excess of absolute maximum ratings, such as the applied voltage or operating temperature range
(Topr), may result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open
mode) when such damage is suffered. A physical safety measure, such as a fuse, should be implemented when using
the IC at times where the absolute maximum ratings may be exceeded.
2. GND potential
Ensure a minimum GND pin potential in all operating conditions. Make sure that no pins are at a voltage below the
GND at any time, regardless of whether it is a transient signal or not.
3. Thermal design
Perform thermal design, in which there are adequate margins, by taking into account the permissible dissipation (Pd)
in actual states of use.
4. Short circuit between terminals and erroneous mounting
Pay attention to the assembly direction of the ICs. Wrong mounting direction or shorts between terminals, GND, or other
components on the circuits, can damage the IC.
5. Operation in strong electromagnetic field
Using the ICs in a strong electromagnetic field can cause operation malfunction.
6. Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to
stress. Always discharge capacitors after each process or step. Always turn the IC's power supply off before
connecting it to, or removing it from a jig or fixture, during the inspection process. Ground the IC during assembly
steps as an antistatic measure. Use similar precaution when transporting and storing the IC.
7. Regarding input pin of the IC (Fig. 40)
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements to keep them isolated.
P–N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic
diode or transistor. For example, the relation between each potential is as follows:
When GND > Pin A and GND > Pin B, the P–N junction operates as a parasitic diode.
When Pin B > GND > Pin A, the P–N junction operates as a parasitic transistor.
Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes
operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be
used.
8. Ground wiring patterns
The power supply and ground lines must be as short and thick as possible to reduce line impedance. Fluctuating
voltage on the power ground line may damage the device.
9. Thermal Shutdown Circuit (TSD)
The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is
designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee
its operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the
operation of this circuit is assumed.
10. Over current protection circuit
The IC incorporates a built-in overcurrent protection circuit that operates according to the output current capacity. This
circuit serves to protect the IC from damage when the load is shorted. The protection circuit is designed to limit
current flow by not latching in the event of a large and instantaneous current flow originating from a large capacitor or
other component. These protection circuits are effective in preventing damage due to sudden and unexpected
accidents. However, the IC should not be used in applications characterized by the continuous operation or
transitioning of the protection circuits. At the time of thermal designing, keep in mind that the current capability has
negative characteristics to temperatures.
15/16
11. When the Vcc pin is opposite in voltage to each pin in the application, the internal circuit or element may be damaged.
For example, such damage might occur when VCC is shorted with the GND pin while an external capacitor is charged.
Use the output pin capacity with a maximum capacitance of 1000 µF. It is recommended to insert a diode in order to
prevent back current flow in series with VCC or bypass diodes between VCC and each pin.
Fig. 39 Bypass diode Fig. 40 Example of Simple Bipolar IC Architecture
025 75 100
0
125 150
50
0.2
0.1
0
[°C ]
0.4
0.5
0.3
[W]
Ambient Temperature [Ta]
0.4 W (1)
(1) 70 mm × 70 mm × 1.6 mm PCB
(Glass epoxy resin)
(2) Without heat sink
θJ-A = 36.76°C/W
0.35 W (2)
0 25 75 100
0
125 150
50
1.0
0.5
0
[°C ]
2.0
2.5
1.5
[W]
Ambient Temperature [Ta]
2.2 W (1)
1.8 W (2)
(1) 70 mm
×
70 mm × 1.6 mm PCB
(Glass epoxy resin)
(2) Without heat sink
θJ-A = 36.76°C/W
～
～
GND
P基板
N
P
N N
P＋
P＋
（端子 A）
抵抗
～
～
GND
Ｎ
Ｐ
N Ｎ
P＋ P＋
（端子 B）
トランジスタ
(
NPN
)
B
N
E
C
GND
P基板
寄生素子
Transistor (NPN)
（Pin A） （Pin B）
P substrate
N
P
N
Parasitic elements
Resistor
(Pin A)
GND
Parasitic elements
～
～
GND
(Pin B)
B
C
E
Parasitic elements or
Transistor
～
～
VCC
Output pin
Diode for preventing back current flow
Bypass diode
Catalog No.05T388Be '05.10 ROHM C 1000 TSU
zSelecting a model name when ordering
ROHM
model name Packaging specifications
E2: Emboss taping
(BD9403FV)
No: T ube container
(BD9401FM)
B D
Packaging
FM: HSOP-M28
(BD9401FN)
FV: SSOP-B14
(BD9403FV)
F M E 2
Part number
9 4 0 1
（Unit:mm)
SSOP-B14
<Dimension>
8
7
14
1
0.1 6.4 ± 0.3
4.4
±
0.2
5.0 ± 0.2
0.22 ± 0.1
1.15 ± 0.1
0.65
0.15 ± 0.1
0.3Min.
0.1
<Tape and Reel information>
Ta
p
e
Quantit
y
Direction
of feed
Embossed carrier ta
p
e
2500
p
cs
E2
(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand)
Reel Direction of feed
1pin
1234
1234
1234
1234
1234
1234
1234
1234
※When you order , please order in times the amount of package quantity.
HSOP-M28
(Unit:mm)
<Dimension>
18.5 ± 0.2
7.5 ± 0.2
9.9 ± 0.3
28 15
114
2.2 ± 0.1
0.35 ± 0.1
5.15 ± 0.1
0.5 ± 0.2
0.8
0.25 ± 0.1
16.0 ± 0.2
0.11
0.1 S
0.08
M
Tape
Quantity
Direction
of feed
Embossed carrier tape
1500pcs
(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand)
<Tape and Reel information>
E2
Reel 1Pin
1234
1234
1234
1234
1234
1234
1234
Direction of feed
※When you order , please order in times the amount of package quantity.
Notes
No technical content pages of this document may be reproduced in any form or transmitted by any
means without prior permission of ROHM CO.,LTD.
The contents described herein are subject to change without notice. The specifications for the
product described in this document are for reference only. Upon actual use, therefore, please request
that specifications to be separately delivered.
Application circuit diagrams and circuit constants contained herein are shown as examples of standard
use and operation. Please pay careful attention to the peripheral conditions when designing circuits
and deciding upon circuit constants in the set.
Any data, including, but not limited to application circuit diagrams information, described herein
are intended only as illustrations of such devices and not as the specifications for such devices. ROHM
CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any
third party's intellectual property rights or other proprietary rights, and further, assumes no liability of
whatsoever nature in the event of any such infringement, or arising from or connected with or related
to the use of such devices.
Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or
otherwise dispose of the same, no express or implied right or license to practice or commercially
exploit any intellectual property rights or other proprietary rights owned or controlled by
ROHM CO., LTD. is granted to any such buyer.
Products listed in this document are no antiradiation design.
Appendix1-Rev2.0
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact your nearest sales office.
ROHM Customer Support System THE AMERICAS / EUROPE / ASIA / JAPAN
Contact us : webmaster@ rohm.co.jp
www.rohm.com
Copyright © 2008 ROHM CO.,LTD.
The products listed in this document are designed to be used with ordinary electronic equipment or devices
(such as audio visual equipment, office-automation equipment, communications devices, electrical
appliances and electronic toys).
Should you intend to use these products with equipment or devices which require an extremely high level
of reliability and the malfunction of which would directly endanger human life (such as medical
instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers
and other safety devices), please be sure to consult with our sales representative in advance.
It is our top priority to supply products with the utmost quality and reliability. However, there is always a chance
of failure due to unexpected factors. Therefore, please take into account the derating characteristics and allow
for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in
order to prevent possible accidents that may result in bodily harm or fire caused by component failure. ROHM
cannot be held responsible for any damages arising from the use of the products under conditions out of the
range of the specifications or due to non-compliance with the NOTES specified in this catalog.
21 Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan TEL : +81-75-311-2121
FAX : +81-75-315-0172
Appendix
