September 2013 Doc ID 16782 Rev 3 1/27
1
VN750PS-E
High-side driver
Features
■
ECOPACK
®
: lead free and RoHS compliant
■
Automotive Grade: compliance with AEC
guidelines
■
CMOS compatible input
■
On-state open-load detection
■
Off-state open-load detection
■
Shorted load protection
■
Undervoltage and overvoltage shutdown
■
Protection against loss of ground
■
Very low standby current
■
Reverse battery protection
Description
The VN750PS-E is a monolithic device designed
in STMicroelectronics™ VIPower™ M0 -3
Technology intended for driving any kind of load
with one side connected to ground.
Active V
CC
pin voltage clamp protects the device
against low energy spikes (see ISO7637 transient
compatibility table). Active current limitation
combined with thermal shutdown and automatic
restart help protect the device against overload.
The device detects open load condition in on and
off-state. Output shorted to V
CC
is detected in the
off-state. Device automatically turns off in case of
ground pin disconnection.
Type R
DS(on)
I
OUT
V
CC
VN750PS-E 60 mΩ6A 36V
Table 1. Device summary
Package Order codes
Tube Tape and reel
SO-8 VN750PS-E VN750PSTR-E
SO-8
www.st.com
Contents VN750PS-E
2/27 Doc ID 16782 Rev 3
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Electrical characteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5 GND protect ion network against reverse battery . . . . . . . . . . . . . . . . . . . 16
2.6 Load dump pr otection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.7 Microcontroller I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.8 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.9 SO-8 maximum demagnetization energy (V
CC
= 13.5 V) . . . . . . . . . . . . 19
3 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1 SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1 SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2 SO-8 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
VN750PS-E List of tables
Doc ID 16782 Rev 3 3/27
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 7. Electrical transient requirements on V
CC
pin (part 1/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 8. Electrical transient requirements on V
CC
pin (part 2/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 9. Electrical transient requirements on V
CC
pin (part 3/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 10. Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 11. SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
List of figures VN750PS-E
4/27 Doc ID 16782 Rev 3
List of figures
Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Switching time waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. High level input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 13. On-state resistance vs T
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 14. On-state resistance vs V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 15. Open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 16. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 17. Input low level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 18. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 19. Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 20. Open-load off-state voltage detection threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 21. Turn-on voltage slope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 22. Turn-off voltage slope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 23. I
lim
vs T
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 24. Application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 25. Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 26. SO-8 maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 27. PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 28. Rthj-amb vs PCB copper area in open box free air condition. . . . . . . . . . . . . . . . . . . . . . . 20
Figure 29. SO-8 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 30. Thermal fitting model of a single channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 31. SO-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 32. SO-8 tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 33. SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
VN750PS-E Block diagram and pin description
Doc ID 16782 Rev 3 5/27
1 Block diagram and pin description
Figure 1. Block diagram
Figure 2. Conf iguration diagram (top view)
Table 2. Suggested connections for unused and not connected pins
Connection/pin Status N.C. Output Input
Floating X X X X
To ground X Through 10 KΩ resistor
UNDERVOLTAGE
OVER TEMPERA TURE
V
CC
GND
INPUT OUTPUT
OVERVOLTAGE
CURRENT
LIMITER
LOGIC
DRIVER
Power
CLAMP
STATUS
V
CC
CLAMP
ON
-
STATE
OPEN-LOAD
OFF-STATE
OPEN-LOAD
AND
OUTPUT
SHORTED
TO
V
CC
DETECTION
DETECTION
DETECTION
DETECTION
DETECTION
SO-8
V
CC
V
CC
OUTPUT
OUTPUT
N.C.
GND
STATUS
INPUT
1
4
5
8
Electrical specifications VN750PS-E
6/27 Doc ID 16782 Rev 3
2 Electrical specifications
Figure 3. Current and voltage conventions
2.1 Absolute maximum ratings
Stress values that exceed those listed in the “Absolute maximum ratings” table can cause
permanent damage to the device. These are stress ratings only and operation of the device
at these or any other conditions greater than those indicated in the operating sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. Refer also to the STMicroelectronics sure program and
other relev ant qua li ty doc ume nts.
INPUT
I
S
I
IN
V
IN
V
CC
STATUS
I
STAT
V
STAT
GND
VCC
I
OUT
V
OUT
I
GND
OUTPUT
V
F
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
V
CC
DC supply voltage 41 V
-V
CC
Reverse DC supply voltage - 0.3 V
-I
gnd
DC reverse ground pin current - 200 mA
I
OUT
DC output current Internally limited A
-I
OUT
Reverse DC output current - 6 A
I
IN
DC input current +/-10 mA
I
STAT
DC stat us current +/- 10 mA
V
ESD
Electrostatic discharge
(human body model: R = 1.5 KΩ; C=100pF)
- Input
- St atus
- Output
- V
CC
4000
4000
5000
5000
V
V
V
V
VN750PS-E Electrical specifications
Doc ID 16782 Rev 3 7/27
2.2 Thermal data
E
MAX
Maximu m swi tch i ng ene rgy
(L = 1.8 mH; R
L
=0Ω; V
bat
= 13.5 V;
T
jstart
=150°C; I
L
=9A) 100 mJ
P
tot
Power di ss ipa tio n T
C
=25°C 4.2 W
T
j
Junction operating temperature Internally limited °C
T
c
Case operating temperature - 40 to 150 °C
T
stg
Storage temperature - 55 to 150 °C
Table 3. Absolute maximum ratings (continued)
Symbol Parameter Value Unit
Table 4. Thermal data
Symbol Parameter Max. value Unit
R
thj-lead
Thermal resi stanc e j unction-l ead 30 °C/W
R
thj-amb
Thermal resistance junction-ambient 93
(1)
1. When mounted on a standard single-sided FR-4 board with 0.5 cm
2
of Cu (at least 35 µm thick) connected
to all V
CC
pins. Horizontal mounting and no artificial air flow.
°C/W
82
(2)
2. When mounted on a standard single-sided FR-4 board with 2 cm
2
of Cu (at least 35 µm thick) connected to
all V
CC
pins. Horizontal mounting and no artificial air flow.
°C/W
Electrical specifications VN750PS-E
8/27 Doc ID 16782 Rev 3
2.3 Electrical characteristics
Values specified in this section are for 8 V < V
CC
<36V;
-40 °C < T
j
< 150 °C, unless
otherwise stated.
Table 5. Electrical characteristics
Symbol Parameter Test conditions Min. Typ. Max. Unit
Power
V
CC
Operating supply voltage 5.5 13 36 V
V
USD
Undervoltage shutdown 3 4 5.5 V
V
USDhyst
Undervoltage shutdown
hysteresis 0.5 V
V
OV
Overvoltage shutdown 36 V
R
ON
On-state resistance I
OUT
= 2 A; T
j
=25°C;
V
CC
>8V 60 mΩ
I
OUT
= 2 A; V
CC
>8 V 120 mΩ
I
S
Supply current
Off-state; V
CC
=13V;
V
IN
=V
OUT
=0V 10 25 µA
Off-state; V
CC
=13V;
V
IN
=V
OUT
=0V; T
j
=
25
°C 10 20 µA
On-state; V
CC
=13V;
V
IN
=5V; I
OUT
=0A 23.5mA
I
L(off1)
Off-state output current V
IN
=V
OUT
=0V 0 50 µA
I
L(off2)
Off-state output current V
IN
=0V; V
OUT
=3.5V -75 0 µA
I
L(off3)
Off-state output current V
IN
=V
OUT
=0V; V
CC
=13V;
T
j
=125°C 5µA
I
L(off4)
Off-state output current V
IN
=V
OUT
=0V; V
CC
=13V;
T
j
=25°C 3µA
Switching (V
CC
=13V)
t
d(on)
Turn-on delay time R
L
=6.5Ω from V
IN
rising
edge to V
OUT
=1.3V 40 µs
t
d(off)
Turn-off delay time R
L
=6.5Ω from V
IN
falling
edge to V
OUT
=11.7V 30 µs
dV
OUT
/dt
(on)
Turn-on voltage sl ope R
L
=6.5Ω from V
OUT
=1.3V
to V
OUT
= 10.4 V See Figure 21 V/µs
dV
OUT
/dt
(off)
Turn-off voltage slope R
L
=6.5Ω from V
OUT
=11.7V
to V
OUT
=1.3V See Figure 22 V/µs
Input pin
V
IL
Input low level 1.25 V
I
IL
Low level input current V
IN
=1.25V 1 µA
V
IH
Input high leve l 3.25 V
VN750PS-E Electrical specifications
Doc ID 16782 Rev 3 9/27
I
IH
High level input current V
IN
=3.25V 10 µA
V
hyst
Input hysteresis vo lt age 0.5 V
V
ICL
Input clamp voltage I
IN
=1mA 6 6.8 8 V
I
IN
=-1mA -0.7 V
V
CC
output diode
V
F
Forward on voltage -I
OUT
= 1.3 A; T
j
= 150 °C 0.6 V
Status pin
V
STAT
Status low output voltage I
STAT
=1.6mA 0.5 V
I
LSTAT
Status leakage current Normal operation; V
STAT
=5V 10 µA
C
STAT
Status pin input capacitance Normal operation; V
STAT
= 5 V 100 pF
V
SCL
Status clamp v oltage I
STAT
=1mA 6 6.8 8 V
I
STAT
=-1mA -0.7 V
Protections
(1)
T
TSD
Shutdown temperature 150 175 200 °C
T
R
Reset temperature 135 °C
T
hyst
Thermal hysteresis 7 15 °C
t
SDL
Status del ay in ove rload
condition T
j
>T
jsh
20 ms
I
lim
Current limitation 9V<V
CC
<36 V 6 9 15 A
5V<V
CC
<36 V 15 A
V
demag
Turn-off output clamp
voltage I
OUT
= 2 A; V
IN
=0V;
L=6mH V
CC
-41 V
CC
-48 V
CC
-55 V
Open-load detection
I
OL
Open-load on-state
detection threshold V
IN
= 5 V 50 200 mA
t
DOL(on)
Open-load on-state
detection delay I
OUT
= 0 A 200 µs
V
OL
Open-load off-state voltage
detection threshold V
IN
=0V 1.5 3.5 V
t
DOL(off)
Open-load detection delay at
turn-off 1000 µs
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals
must be used together with a proper software strategy. If the device operates under abnormal conditions this software must
limit the duration and number of activation cycles.
Table 5. Electrical characteristics (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Electrical specifications VN750PS-E
10/27 Doc ID 16782 Rev 3
Figure 4. Status timings
Figure 5. Switching time waveforms
Table 6. Truth table
Conditions Input Output Status
Norm al op er at i on L
HL
HH
H
Current limitation L
H
H
L
X
X
H
(T
j
< T
TSD
) H
(T
j
> T
TSD
) L
Over temperature L
HL
LH
L
Undervoltage L
HL
LX
X
Overvoltage L
HL
LH
H
V
IN
V
STAT
t
DOL(off)
OPEN-LOAD STATUS TIMING
(with extern al pull-up) OVERTEMP STATUS TIMING
I
OUT
< I
OL
V
OUT
> V
OL
t
DOL(on)
T
j
> T
jsh
V
IN
V
STAT
t
SDL
t
SDL
Figure 1: Test Conditions for High Side switching times measurement.
t
t
V
OUT
V
IN
80%
10%
dV
OUT
/dt
(on)
t
d(off)
90%
dV
OUT
/dt
(off)
t
d(on)
VN750PS-E Electrical specifications
Doc ID 16782 Rev 3 11/27
Output voltage > V
OL
L
HH
HL
H
Out put current < I
OL
L
HL
HH
L
Table 7. Electrical transient requirements on V
CC
pin (part 1/3)
ISO T/R 7637/1
test pulse
Test levels
I II III IV Delays and
impedance
1 -25 V -50 V -75 V -100 V 2 ms 10 Ω
2 +25 V +50 V +75 V +100 V 0.2 ms 10 Ω
3a -25 V -50 V -100 V -150 V 0.1 µs 50 Ω
3b +25 V +50 V +75 V +100 V 0.1 µs 50 Ω
4 -4 V -5 V -6 V -7 V 100 ms, 0.01
Ω
5 +26.5 V +46.5 V +66.5 V +86.5 V 400 ms, 2
Ω
Table 8. Electrical transient requirements on V
CC
pin (part 2/3)
ISO T/R 7637/1
test pulse
Test levels results
I II III IV
1CCCC
2CCCC
3aCCCC
3bCCCC
4CCCC
5CEEE
Table 9. Electrical transient requirements on V
CC
pin (part 3/3)
Class Contents
C All functions of the device are performed as designed after exposure to disturbance.
EOne or more functions of the device is not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
Table 6. Truth table (continued)
Conditions Input Output Status
Electrical specifications VN750PS-E
12/27 Doc ID 16782 Rev 3
Figure 6. Waveforms
OPEN LOAD wi thout external pull-u p
STATUS
INPUT NORMAL OPERATION
UNDERVOLTAGE
V
CC
V
USD
V
USDhyst
INPUT
OVERVOLTAGE
V
CC
V
CC
>V
OV
STATUS
INPUT
STATUS
STATUS
INPUT
STATUS
INPUT
OPEN LOAD with external pull-up
undefined
LOAD VOLTAGE
V
CC
<V
OV
LOAD VOLTAGE
LOAD VOLTAGE
LOAD VOLTAGE
LOAD VOLTAGE
OVER TEMPERATURE
INPUT
STATUS
T
TSD
T
R
T
j
LOAD CURRENT
V
OUT
>V
OL
V
OL
VN750PS-E Electrical specifications
Doc ID 16782 Rev 3 13/27
2.4 Electrical characteristics curves
Figure 7. Off-state output current Figure 8. High level input current
Figure 9. Input clamp voltage Figure 10. Status leakage current
Figure 11. Status low output voltage Figure 12. Status clamp voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
-1
-0.5
0
0.5
1
1.5
2
2.5
3
IL(off1) (uA)
Off state
Vcc=36V
Vin=Vout=0V
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
0
1
2
3
4
5
6
7
Iih (uA)
Vin=3.25V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
6
6.2
6.4
6.6
6.8
7
7.2
7.4
7.6
7.8
8
Vicl (V)
Iin=1mA
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.01
0.02
0.03
0.04
0.05
Ilstat (uA)
Vstat=5V
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
0
0.1
0.2
0.3
0.4
0.5
0.6
Vstat (V)
Istat=1.6mA
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
6
6.2
6.4
6.6
6.8
7
7.2
7.4
7.6
7.8
8
Vscl (V)
Istat=1mA
Electrical specifications VN750PS-E
14/27 Doc ID 16782 Rev 3
Figure 13. On-state resistance vs T
case
Figure 14. On-state resistance vs V
CC
Figure 15. Open-load on-state detection
threshold Figure 16. Input high level
Figure 17. Input low level Figure 18. Input hysteresis voltage
510152025303540
Vcc (V)
20
30
40
50
60
70
80
90
100
110
120
Ron (mOhm)
Iout=2A
Tc= - 40°C
Tc= 25° C
Tc= 125°C
Tc= 150°C
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
0
20
40
60
80
100
120
140
160
180
200
220
Iol (mA)
Vcc=13V
Vin=5V
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Vih (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
Vhyst (V)
VN750PS-E Electrical specifications
Doc ID 16782 Rev 3 15/27
Figure 19. Overvoltage shutdown Figure 20. Open-load off-state vo ltage
detection threshold
Figure 21. Turn-on voltage slope Figure 22. Turn-off voltage slope
Figure 23. I
lim
vs T
case
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
1
1.5
2
2.5
3
3.5
4
4.5
5
Vol (V)
Vin=0V
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
0
100
200
300
400
500
600
700
800
900
1000
dVout/dt/(on) (V/ms)
Vcc=13V
Rl=6.5Ohm
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
0
50
100
150
200
250
300
350
400
450
500
dVout/dt(off) (V/ms)
Vcc=13V
Rl=6.5Ohm
Electrical specifications VN750PS-E
16/27 Doc ID 16782 Rev 3
Figure 24. Application schematic
2.5 GND protection network against reverse battery
Solution 1: resistor in the ground line (R
GND
only). This can be used with any type of load.
The following is an indication on how to dimension the R
GND
resistor.
1. R
GND
≤ 600 mV / (I
S(on)max
).
2. R
GND
≥ (−V
CC
) / (−I
GND
)
where -I
GND
is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power dissipation in R
GND
(when V
CC
< 0: during reverse battery situations) is:
P
D
= (−V
CC
)
2
/R
GND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
S(on)max
becomes the sum of the
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
R
GND
produces a shift (I
S(on)max
* R
GND
) in the input thresholds and the status output
values. This shift varies depending on how many devices are on in the case of several high
side drivers sharing the same R
GND
.
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize solution 2 (see below).
Solution 2: diode (D
GND
) in the ground line A resistor (R
GND
=1 kΩ) should be inserted in
parallel to D
GND
if the device drives an inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈600 mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
V
CC
GND
OUTPUT
D
GND
R
GND
D
ld
μ
C
+5V
R
prot
V
GND
STATUS
INPUT
+5V
R
prot
VN750PS-E Electrical specifications
Doc ID 16782 Rev 3 17/27
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
Series resistor in input and status lines are also required to prevent that, during battery
voltage transient, the current exceeds the absolute maximum rating.
Safest configuration for unused input and status pin is to leave them unconnected.
2.6 Load dump protection
D
ld
is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
V
CC
max DC rating. The same applies if the device is subject to transients on the V
CC
line
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
2.7 Microcontroller I/Os protection
If a ground protection network is used and negative transient are present on the V
CC
line,
the control pins will be pulled negative. ST suggests to insert a resistor (R
prot
) in line to
prevent the microcontroller I/O pins to latch-up.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os.
-V
CCpeak
/I
latchup
≤ R
prot
≤ (V
OH
µ
C
-V
IH
-V
GND
) / I
IHmax
Calculation example:
For V
CCpeak
= - 100 V and I
latchup
≥ 20 mA; V
OH
µ
C
≥ 4.5 V
5kΩ ≤ R
prot
≤ 65 kΩ.
Recommended values: R
prot
=10kΩ.
2.8 Open-load detection in off-state
Off-state open-load detection requires an external pull-up resistor (R
PU
) connected between
output pin and a positive supply voltage (V
PU
) like the +5V line used to supply the
microprocessor.
The external resistor has to be selected according to the following requirements:
1. no false open-load indication when load is connected: in this case we have to avoid
V
OUT
to be higher than V
Olmin
; this results in the following condition
V
OUT
=(V
PU
/(R
L
+R
PU
))R
L
<V
Olmin
.
2. no misdetection when load is disconnected: in this case the V
OUT
has to be higher than
V
OLmax
; this results in the following condition R
PU
<(V
PU
–V
OLmax
)/I
L(off2)
.
Because I
s(OFF)
may significantly increase if V
out
is pulled high (up to several mA), the pull-
up resistor R
PU
should be connected to a supply that is switched off when the module is in
standby.
The values of V
OLmin
, V
OLmax
and I
L(off2)
are available in the electrical characteristics
section.
Electrical specifications VN750PS-E
18/27 Doc ID 16782 Rev 3
Figure 25. Open-load detection in off-state
V
OL
V batt. V
PU
R
PU
R
L
R
DRIVER
+
LOGIC
+
-
INPUT
STATUS
V
CC
OUT
GROUND
I
L(off2)
VN750PS-E Electrical specifications
Doc ID 16782 Rev 3 19/27
2.9 SO-8 maximum demagnetization energy (V
CC
= 13.5 V)
Figure 26. SO-8 maximum turn-off current versus inductance
C: T
jstart
= 125 °C repetitive pulse
A: T
jstart
= 150 °C single pulse
B: T
jstart
= 100 °C repetitive pulse
Demagnetization Demagnetization Demagnetization
t
V
IN
, I
L
1
10
100
0.1 1 10 100
L(mH)
I
LMAX (A)
A
B
C
Note:
Values are generated with R
L
=0
Ω
.In case of repetitive pulses, T
jstart
(at beginning of each demagnetization) of every pulse
must not exceed the temperature specified above for curves A and B.
Package and PCB thermal data VN750PS-E
20/27 Doc ID 16782 Rev 3
3 Package and PCB thermal data
3.1 SO-8 thermal data
Figure 27. PC board
Figure 28. R
thj-amb
vs PCB copper area in open box free air condition
.
Note:
Layout condition of R
th
and Z
th
measurements (PCB FR4 area = 58 mm x 58 mm, PCB thickness = 2 mm, Cu
thickness=35 µm, Copper areas: 0.14 cm
2
, 0.8 cm
2
, 2 cm
2
).
70
75
80
85
90
95
100
105
110
00.511.522.5
PCB Cu heatsink a rea (cm^2)
RTHj_am b (ºC/W)
SO-8 at 2 pi ns connected to TAB
VN750PS-E Package and PCB thermal data
Doc ID 16782 Rev 3 21/27
Figure 29. SO-8 thermal impedance junction ambient single pulse
Equation 1: pulse calculation formula
where δ = t
P
/T
Figure 30. Thermal fitting model of a single channel
0.01
0.1
1
10
100
1000
0.0001 0.001 0.01 0.1 1 10 100 1000
Time (s)
ZTH (°C/W)
0.5 cm
2
2 cm
2
ZTHδRTH δZTHtp 1δ–()+⋅=
Package and PCB thermal data VN750PS-E
22/27 Doc ID 16782 Rev 3
Table 10. Thermal parameter
Area/island (cm
2
)0.52
R1 (°C/W) 0.05
R2 (°C/W) 0.8
R3 (°C/W) 3.5
R4 (°C/W) 21
R5 (°C/W) 16
R6 (°C/W) 58 28
C1 (W·s/°C) 0.006
C2 (W·s/°C) 0.0026
C3 (W·s/°C) 0.0075
C4 (W·s/°C) 0.045
C5 (W·s/°C) 0.35
C6 (W·s/°C) 1.05 2
VN750PS-E Package and packing information
Doc ID 16782 Rev 3 23/27
4 Package and packing information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.
4.1 SO-8
package infor mation
Figure 31. SO-8 package dimensions
001602 3 D
Package and packing information VN750PS-E
24/27 Doc ID 16782 Rev 3
Table 11. SO-8 mechanical data
Dim. mm
Min. Typ. Max.
A1.75
A1 0.10 0.25
A2 1.25
b 0.28 0.48
c 0.17 0.23
D
(1)
1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15 mm in total (both side).
4.80 4.90 5.00
E 5.80 6.00 6.20
E1
(2)
2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25 mm per side.
3.80 3.90 4.00
e 1.27
h 0.25 0.50
L 0.40 1.27
L1 1.04
k 0° 8°
ccc 0.10
VN750PS-E Package and packing information
Doc ID 16782 Rev 3 25/27
4.2 SO-8 packing information
The devices can be packed in tube or tape and reel shipments (see the Device summary on
page 1).
Figure 32. SO-8 tube shipment (no suffix)
Figure 33. SO-8 tape and reel shipment (suffix “TR”)
All dimensions are in mm.
Base Q.ty 100
Bulk Q.ty 2000
Tube length (± 0 .5 ) 532
A3.2
B6
C (± 0.1) 0.6
C
B
A
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
All dimensions are in mm.
Tape width W 12
Tape Hole Spacing P0 (± 0.1) 4
Component Spaci n g P 8
Hole Diameter D (+0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.05) 5.5
Compartment Depth K (max) 4.5
Hole Spacing P1 (± 0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500mm min
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
Reel dimensions
All dimensio ns are in mm.
Base Q.ty 2500
Bulk Q.ty 2500
A (max) 330
B (min) 1.5
C (± 0.2) 13
F20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4
Revision history VN750PS-E
26/27 Doc ID 16782 Rev 3
5 Revision history
Table 12. Document revision history
Date Revision Changes
23-Nov-2009 1 Initial release.
15-Oct-2010 2
Updated Table 4: Thermal data
Updated following figure titles:
–Figure 21: Turn-on voltage slope
–Figure 22: Turn-off voltage slope
19-Sep-20 13 3 Upda ted Disc la im er.
VN750PS-E
Doc ID 16782 Rev 3 27/27
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