AAT4712
DATA SHEET
Power Path with Input Current Limit and Capacitor Charger
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General Description
The AAT4712 is a programmed, current limited P-channel
MOSFET power switch designed for high-side load-switch-
ing applications for SSD memory buffer saving solutions.
With the programmed current limit, the AAT4712 ensures
that the power ratings of the host are not exceeded and
balances the system load and supercap charging current
automatically to provide enough system load current in
top-priority. The integrated discharge path control assures
that the system load can still be supported in the short
term when the input power has not fully charged the
supercap. The current limit is programmed by an external
resistor allowing ±10% accuracy at room temperature.
The AAT4712 integrates discharge path for SYS (to
system load) from VCC input or OUT input (connect to
supercap). The low RDS(ON) from OUT to SYS prolongs the
supercap backup time when VCC drops below a threshold
voltage which is programmed by an external resistor
from ADJ to ground.
The AAT4712 incorporates a POK function which can
indicate system input power good. An ADJ pin is pro-
vided with the addition of an external resistor for setting
the input power good detect threshold. The AAT4712
also incorporates a supercap charge ready (RDY) indicate
function. The quiescent supply current is typically a low
70A from the discharge path of VCC to SYS.
The AAT4712 is available in a 16-pin TDFN34 package
and is specified over a -40 to 85°C temperature range.
Features
V
CC Range: 2.5V – 5.5V
Input Current Limits:
150mA - 2400mA
±10% Current Accuracy at 2A Input Current Limit
Setting
Low Quiescent Current:
70A Typical (VCC Input)
12A Typical (OUT Input)
Under-Voltage Lockout
Integrated Discharge Path for SYS (to System Load)
from VCC Input or OUT Input (Connect to Supercap)
Maximum 100m RDS(ON) from OUT to SYS at 5V VCC
Reverse Blocking Protection
Power Loop Current Reduction
Over-Temperature Protection
SYS Short Circuit Protection
Input Power Good Detect Threshold Setting (ADJ)
Input Power Good Indicate (POK)
Supercap Charge Ready (RDY) Output
Temperature Range: -40 to 85°C
16-Pin TDFN34 Package
Applications
SSD
Typical Application
VCC
2.5V - 5.5V
CIN
10µF
CSYS
10µF
VCC
GND
OUT
SYS
ISET
ADJ RDY
POK
RADJ
RSET
VSYS
VIO
Super
Capacitor
POK
RDY
AAT4712
AAT4712
DATA SHEET
Power Path with Input Current Limit and Capacitor Charger
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Pin Descriptions
Pin # Symbol Function
1 RDY Supercap charge ready output, initiated when the capacitor is 98% charged. Open drain, active high.
2 ISET Input current-limit set input. A resistor from ISET to ground is necessary and sets the maximum cur-
rent limit for the switch. The current limit can be programmed from 150mA to 2000mA.
3 N/C No connect.
4, 5, 6, 7, 8 SYS System power output supplied from the VCC input or OUT input.
9, 10, 11 OUT Connect to super capacitor from OUT to GND.
12, 13 VCC Input pins to the P-channel MOSFET source. Connect a 10F capacitor from VCC to GND.
14 ADJ Input power good detect threshold. An internal 50k resistor is integrated between ADJ and VCC.
15 GND Device ground connection.
16 POK Input power good indicator. Push pull, active high.
Pin Configuration
TDFN34-16
(Top View)
N/C
SYS
SYS
RDY
ISET
3
SYS
SYS
SYS
ADJ
VCC
VCC
POK
GND
OUT
OUT
OUT
4
5
1
2
6
7
8
14
13
12
16
15
11
10
9
AAT4712
DATA SHEET
Power Path with Input Current Limit and Capacitor Charger
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1. Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation at conditions other than the operating conditions
specified is not implied. Only one Absolute Maximum Rating should be applied at any one time.
2. Mounted on a FR4 board.
3. Derate 50mW/°C above 25°C.
Absolute Maximum Ratings1
Symbol Description Value Units
VPVCC, OUT to GND -0.3 to 6 V
VRDY, VPOK , VADJ RDY, POK, ADJ to GND -0.3 to VP + 0.3 V
VISET
, VSYS ISET, SYS to GND -0.3 to VP + 0.3 V
IMAX Maximum Continuous Switch Current 2.5 A
TJOperating Junction Temperature Range -40 to 150 °C
TSTG Storage Temperature -40 to 150 °C
TLEAD Maximum Soldering Temperature (at Leads) 300 °C
Thermal Characteristics2
Symbol Description Value Units
JA Maximum Thermal Resistance350 °C/W
PDMaximum Power Dissipation3 2W
AAT4712
DATA SHEET
Power Path with Input Current Limit and Capacitor Charger
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1. The AAT4712 is guaranteed to meet performance specifications over the -40°C to 85°C operating temperature range and is assured by design, characterization and correlation
with statistical process controls.
Electrical Characteristics1
VCC = 2.5V to 5.5V, TA = -40°C to 85°C unless otherwise noted. Typical values are at TA = 25°C
Symbol Description Conditions Min Typ Max Units
VCC Normal Operation Voltage 2.5 5.5 V
IQVCC Quiescent Current IOUT = 0, No Load at SYS Pin 70 120 A
IOUT_OP OUT Operating Current VOUT = 5V, VCC = GND, No Load at SYS Pin 12 30 A
VUVLO_VCC VCC Under-Voltage Lockout Falling Edge 2.1 2.4 V
Hysteresis 150 mV
VUVLO_OUT OUT Under-Voltage Lockout Falling Edge 1.8 2 V
Hysteresis 250 mV
RDS(ON)_SWA VCC to SYS On-Resistance VCC = 5V, RSET = 1.24M, ILOAD = 600mA 50 100 m
VCC = 3.3V, RSET = 1.24M, ILOAD = 600mA 65 120
RDS(ON)_SWB VCC to OUT On-Resistance VCC = 5V, RSET = 1.24M, ILOAD = 600mA 140 300 m
VCC = 3.3V, RSET = 1.24M, ILOAD = 600mA 160 320
RDS(ON)_SWC OUT to SYS On-Resistance VOUT = 3V ~ 5V 100 m
ILIMHACC Input High Current Limit Accuracy RSET = 1.24M, TA = 25°C 1800 2000 2200 mA
ILIM(MIN) Minimum Input Current Limit 150 mA
TRESP Current Limit Response Time VCC = 5V, RSET = 1.24M2s
TDEL(OFF) Turn-Off Delay Time VCC = 5V 0.4 10 s
TSW OUT to SYS Switch Turn On Response Time VCC Voltage Step-Down Signal from 5V to
4.5V 6s
VADJ ADJ Pin Voltage with Trigger Comparator 1.2 V
TDETECT ADJ Pin Detect Delay Time ADJ Voltage Step Down Signal from 1.3V
to 1.1V 2s
VPOK(L) Output Low Voltage ADJ 1.2V 0.4 V
VPOK(H) Output High Voltage ADJ > 1.2V 0.8
VCC
V
VRDY Supercap Charge Ready Trip Threshold VOUT Rising, TA = 25°C 98 % of
VCC
VRDYSYS Supercap Charge Ready Hysteresis 200 mV
VRDY(L) RDY Output Low Voltage RDY Pin Sinks 1mA 0.4 V
OTMP Shutdown Temperature 150 °C
THYS Over-Temperature Shutdown Hysteresis 15 °C
AAT4712
DATA SHEET
Power Path with Input Current Limit and Capacitor Charger
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Typical Characteristics
VCC Quiescent Current vs. Temperature
Temperature (°C)
IQ (µA)
-40 -15 10 35 60 85
40
50
60
70
80
90
VCC = 5.5V
VCC = 5.0V
VCC = 3.0V
VCC = 2.5V
VOUT Quiescent Current vs. Temperature
Temperature (°C)
IQ (µA)
-40 -15 10 35 60 85
0
5
10
15
20
25
VOUT = 5.5V
VOUT = 5.0V
VOUT = 3.0V
VOUT = 2.5V
VUVLO_VCC vs. Temperature
Temperature (°C)
VUVLO_VCC (V)
-40 -15 10 35 60 85
1.98
2.02
2.06
2.10
2.14
2.18
2.22
2.26
2.30
VCC Rising
VCC Falling
VUVLO_OUT vs. Temperature
Temperature (°C)
VUVLO_OUT (V)
-40 -15 10 35 60 85
1.64
1.70
1.76
1.82
1.88
1.94
2.00
2.06
2.12
2.18
VOUT Rising
VOUT Falling
RDS(ON)_SWA vs. Temperature
(Load Current = 600mA, RSET = 1.24MΩ)
Temperature (°C)
RDS(ON)_SWA (mΩ)
-40 -15 10 35 60 85
20
36
52
68
84
100
VCC = 3.3V
VCC = 5.0V
RDS(ON)_SWC vs. Temperature
(Load Current = 600mA, RSET = 1.24MΩ)
Temperature (°C)
RDS(ON)_SWC (mΩ)
-40 -15 10 35 60 85
20
40
60
80
100
120
VOUT = 3.3V
VOUT = 5.0V
AAT4712
DATA SHEET
Power Path with Input Current Limit and Capacitor Charger
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Typical Characteristics
RDS(ON) vs. Input Voltage
(Load Current = 600mA, RSET = 1.24MΩ)
Input Voltage (V)
RDS(ON) (mΩ)
2.5 3 3.5 4 4.5 5 5.5
40
45
50
55
60
65
70
75
80
RDS(ON)_SWA
RDS(ON)_SWC
Current Limit Error vs. Temperature
(VCC = 5.0V, RSET = 1.24MΩ)
Temperature (°C)
Current Limit Error (%)
-40 -15 10 35 60 85
-6
-4
-2
0
2
4
Current Limit vs. SYS Voltage
(RADJ = 18.2kΩ, RSET = 1.24MΩ, CIN = CSYS = 10μF)
VSYS (V)
Current Limit (A)
5 4.5 4 3.5 3 2.5 2 1.5 1
0.00
0.50
1.00
1.50
2.00
2.50
Current Limit vs. RSET
(VCC = 5.0V)
RSET (kΩ)
Current Limit (A)
0 400 800200 600 160012001000 1400
0.00
0.50
1.00
1.50
2.00
2.50
ADJ Detect Delay Time
(VCC = 5.0V, RSET = 1.24MΩ)
Time (0.8µs/div)
VPOK
(2V/div)
VADJ
(0.2V/div)
POK Delay Time
(RADJ = 18.2kΩ)
Time (100µs/div)
VPOK
(2V/div)
VCC
(1V/div)
AAT4712
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Power Path with Input Current Limit and Capacitor Charger
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Typical Characteristics
RDY Delay Time From High to Low
(VCC = 5.0V, RSET = 1.24MΩ)
Time (2µs/div)
VRDY
(2V/div)
VOUT
(1V/div)4.5
0
RDY Delay Time From Low to High
(VCC = 5.0V, RSET = 1.24MΩ)
Time (100µs/div)
VRDY
(2V/div)
VOUT
(1V/div)
0
4.5
Current Limit Response
(VCC = 5.0V, RSET = 1.24MΩ, RLOAD = 5Ω to 1Ω)
Time (20µs/div)
VCC
(0.2V/div)
VSYS
(2V/div)
ISYS
(2A/div)
5
0
0
Load Transient
(VCC = 5.0V, VOUT = 2.0V,
RSET = 1.24MΩ, ISYS = 1A to 2A)
Time (10ms/div)
ICC
(1A/div)
VSYS
(1V/div)
IOUT
(2A/div)
ISYS
(2A/div)
2
1
4.5
0
Discharge Path Switching
(VOUT = 5.0V, RSET = 1.24MΩ, RADJ = 18.2kΩ,
VCC = 5V to 4V, 1A Load)
Time (100ms/div)
ICC
(1A/div)
VCC
(1V/div)
IOUT
(1A/div)
ISYS
(1A/div)
0
1
4
0
AAT4712
DATA SHEET
Power Path with Input Current Limit and Capacitor Charger
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Functional Block Diagram
Reverse
Blocking
Over-Temp
Protection
GND ISET
VCC SYS
OUT
Under -
Voltage
Lockout
Current Limit
Control
1.2V
Reference
Power
Loop
Control
System
Voltage
Detector
POK
ADJ RDY
Functional Description
The AAT4712 is an integrated P-channel MOSFET load
switch with adjustable current limits, integrated discharge
path, over temperature protection, a power loop and a
super capacitor charger. The input current limit control is
combined with an over-temperature thermal limit and
power loop circuit to provide a comprehensive system to
protect the load switch and its supply from load condi-
tions exceeding the supply specifications. The AAT4712
integrates the discharge path for SYS (to system load)
from the VCC input or OUT input (connected to supercap)
determined by whether VCC is higher than the programmed
threshold setting by ADJ through an external resistor.
The input current is limited and is programmed by an
external resistor for both system load and supercapaci-
tor charging; system load always has higher priority.
The device decreases supercapacitor charging current to
provide more current to system load when the system
load increases and keeps the host power rating from
exceeding the input current limit.
The integrated over-temperature circuits act indepen-
dently of the input current limit. The device input cur-
rent limit is activated when the output load current
exceeds an internal threshold level. The input current
limit threshold in each case is determined by external
resistors connected between the ISET pin and ground.
The minimum input current limit threshold is specified
by ILIM(MIN). If the load condition maintains the device in
current limit and the chip temperature reaches a critical
point, then an internal power loop will reduce the cur-
rent to a safe level.
VCC pin under-voltage lockout circuitry ensures that the
VCC supply is high enough for correct operation of the IC.
OUT pin under-voltage lockout circuitry ensures that the
VOUT supply is high enough for correct operation of the
IC when no VCC input power or VCC below UVLO voltage.
An integrated POK function is adopted to indicate the
system input power good.
AAT4712
DATA SHEET
Power Path with Input Current Limit and Capacitor Charger
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RSET Range (Ω)I
ISET (μA) ILIM/VISET (A/V) Current Limit Range (A) Current Limit
1.5M - 750k 0.8 2 2.4-1.2 RSET*0.8*2
750k - 375k 1.6 1 1.2-0.6 RSET*1.6*1
375k - 187.5k 3.2 0.5 0.6-0.3 RSET*3.2*0.5
187.5k - 93.75k 6.4 0.25 0.3-0.15 RSET*6.4*0.25
Table 1: RSET Values for Setting the Input Current.
Time (20ms/div)
ICC
(100mA/div)
0A
Increase Ambient Temperature
Drop to 1/32 of
1A Current Limit
Time (20ms/div)
ICC
(100mA/div)
0A
Figure 1: AAT4712 Power Loop Function at 1A Figure 2: AAT4712 Power Loop Function at 1A
Current Limit with Ambient Temperature Increasing. Current Limit with Ambient Temperature Decreasing.
Setting the Input Current Limit
The AAT4712 current limit is set via the ISET resistor.
The ISET node operates within a window of 0.6V to 1.2V
for resistor values ranging from 93.75k to 1.5M.
Resistor values outside this range are not recommended.
The ISET source current varies with the resistor value as
shown in Table 1.
VISET = RSET · IISET = 0.6V to 1.2V
If the set pin is open circuit or allowed to exceed 2V, all
power devices are disabled and the input is disconnected
from the output.
SYS Load and Capacitor Charge
The input current limit is equal to the SYS current plus
the OUT charging current. If the SYS current increases/
decreases, the OUT charging current will automatically
decrease/increase accordingly by the device control
loop. For example, if the input current limit is pro-
grammed to 1A and the SYS load current is 0.5A, then
the OUT charging current is 0.5A; if the SYS load current
increases to 0.8A, the OUT current decreases to 0.2A
accordingly; if the SYS load current decreases to 0.2A,
the OUT current increases to 0.8A dynamically.
Discharge Path Control
When the input voltage drops below the power good
detect threshold programmed by the external resistor
from ADJ pin to GND and the OUT pin voltage is greater
than the VUVLO_OUT and SYS pin voltage, the AAT4712
turns on the OUT to SYS switch discharge path after 6s
(TSW) response time, then turns off the path of VCC to
the SYS P-channel load switch. The OUT to SYS switch
remains continuously on until the OUT pin voltage falls
below VUVLO_OUT
.
Power Loop
The AAT4712's power loop limits the load current if
device power dissipation becomes excessive. The power
loop decreases the load current gradually to 1/32 of the
current limit set point when the die temperature exceeds
130°C. The load current then increases in increments of
1/32 of the current limit set point until the set current
limit point is reached or the die temperature exceeds
130°C. Figures 1 and 2 show the the power loop function
as the device temperature increases and decreases at a
1A current limit setting.
AAT4712
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Power Path with Input Current Limit and Capacitor Charger
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The delay time between die temperature measurements
varies depending on the load current limit set point. The
delay ranges from 0.5ms for a 150mA current limit set
point to 4ms for a 2.4A current limit set point.
Over-Temperature Protection
If the die temperature rises quickly enough to exceed
the power loop regulated temperature, over-temperature
shutdown disables the device. The over-temperature
threshold is 150°C. After over-temperature shutdown,
soft start is initiated once the die temperature drops to
135°C.
Power OK Indicator (POK)
On initial power-up, if VCC is higher than the power good
detect threshold programmed by the external resistor
from the ADJ pin to GND, the POK signal switches from
low to high after 2s delay time (TDETECT) to indicate input
power good.
If VCC drops below the power good detect point, the POK
signal switches from high to low after 2s delay time
(TDETECT).
Capacitor Charge Ready Indicator (RDY)
The internal comparator senses the OUT voltage and
delivers a high level as ready signal to the external
microcontroller when the OUT voltage reaches 98% of
the VCC voltage with fixed 200mV hysteresis.
The capacitor charge ready pin (RDY) is an open drain
output. A external pull up resistor with a typical value of
100k is required.
Application Information
Input Current Limit Setting
The input current limit is programmed by RSET from ISET
to ground in the range from 150mA to 2.4A. The current
limit limits the maximum current of both VCC to SYS and
VCC to OUT. The RSET can be calculated by:
RSET = ILIM
1.6 (Current in A, resistance in k)
Table 2 lists some 1% standard metal film resistor values
for current limit settings from 150mA to 2.4A.
RSET (kΩ) Current Limit (A)
1500 2.4
1240 2
1000 1.6
750 1.2
620 1
499 0.8
374 0.6
249 0.4
187 0.3
93.1 0.15
Table 2: Recommended Current Limit RSET Values.
Power Good Detect Threshold Setting
The power good detect threshold (VPOK_TH) determines the
point at which the discharge path changes from VCC –
SYS to OUT – SYS if the OUT pin voltage is above VUVLO_OUT
and the SYS pin voltage. The power good detect thresh-
old is programmed by the external resistor RADJ connected
from the ADJ pin to GND. The RADJ value can be calcu-
lated by:
RADJ = 60
VPOK_TH - 1.2 (Voltage in V, resistance in k)
AAT4712
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Table 3 summarizes some 1% standard metal film resis-
tor values for various VPOK_TH settings.
RADJ (kΩ)V
POK_TH (V)
15.8 5.0
18.2 4.5
20.5 4.0
26.1 3.5
33.2 3.0
47 2.5
Table 3: Recommended Resistor Values
for VPOK_TH Settings.
Discharge Path Control
As the AAT4712 powers the system load, the device
automatically selects VCC or OUT as the power source.
OUT is designed to connect a supercapacitor as a backup
source. Figure 3 shows the discharge path control opera-
tion at 1A current limit setting. When VCC is powered on
from zero to 5V, the SYS voltage also rises to 5V and
500mA current is passed through from VCC to SYS as
system load. With the 1A current limit, the additional
500mA is used to charge the supercapacitor via IOUT as
shown. After 3.5 seconds, the 550mF supercapacitor is
fully charged; the charging current decreases to zero,
and ICC current decreases to 500mA. When VCC drops
from 5V to zero, the backup power source VOUT pro-
vides the 500mA load current to SYS until the superca-
pacitor voltage is discharged to below the UVLO voltage
threshold (typ. 1.8V).
Time (2s/div)
ISYS
(1A/div)
VSYS
(5V/div)
ICC
(1A/div)
IOUT
(1A/div)
VOUT
(5V/div)
VCC
(5V/div)
Figure 3: Discharge Path Control with 550mF
Supercapacitor at 1A Current Limit Setting and
500mA System Load.
Reverse Blocking
The internal reverse blocking comparator disconnects
the VCC to SYS path by turning off the power PMOSFETs
when SYS is higher than VCC minus 18mV, preventing
any reverse current from the system load to the input.
With 22mV hysteresis, the VCC to SYS path will be
reconnected by turning on the power PMOSFETs when
the SYS voltage drops to VIN minus 40mV. The reverse
blocking comparator has a typical 5s delay time, which
may lead to output voltage ripple on the SYS output at
light load. Increasing the SYS output capacitor value can
improve the output voltage ripple when the application
has special SYS voltage ripple requirements.
Input Capacitor
A 10F capacitor is typically recommended for CIN. CIN
should be located as close to the device VCC pin as prac-
tically possible. Ceramic, tantalum, or aluminum electro-
lytic capacitors may be selected for CIN. There is no spe-
cific capacitor equivalent series resistance (ESR) require-
ment for CIN. However, for higher current operation,
ceramic capacitors are recommended for CIN due to their
inherent capability over tantalum capacitors to withstand
input current surges from low impedance sources.
System Output Capacitor
A small output capacitance of approximately 10F is
required at the system output. The output capacitor
helps to filter the SYS voltage when the device works
between reverse blocking and normal operation. For
higher output voltage ripple requirements at light load
(below 1/3 current limit), a greater output capacitor
value is required.
OUT Supercapacitor
The AAT4712's OUT pin is designed to connect a super-
capacitor to ground to give the system a backup when
VCC experiences short power interrupts. A supercapaci-
tor offers high capacitance in a small package; it adopts
special electrodes and some electrolyte. Three types of
electrode materials are suitable for the supercapacitor:
high surface area activated carbons, metal oxide, and
conducting polymers. The first option is the lowest cost
to manufacture; the electrolyte usually is aqueous or
organic. An aqueous electrolyte offers low internal resis-
AAT4712
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Manufacturer Part Number Capacitance (mF) Rated Voltage (V)
ESR
(mΩ) Size LxWxH (mm)
Cap-xx
HS 203F 250 5.5 70 39x17x2.15
HS 211F 370 5.5 55 39x17x2.9
HS 206F 600 5.5 70 39x17x2.4
HW 207F 450 5.5 100 28.5x17x2.9
TDK EDLC152344-551-2F-30 550 5.5 30 44x23x1.5
EDLC262020-501-2F-50 500 5.5 50 20x20x2.6
Table 4: Recommended Supercapacitors
tance but limits the voltage to 1V; the organic allows
2.5V of charge but has higher internal resistance. For
higher voltage applications, supercapacitors are con-
nected in series. To prevent any cell from charging over-
voltage, a balance resistor is required on a string of
more than three cells.
Three parameters should be considered when selecting a
supercapacitor. These parameters are capacitance, rated
voltage, and ESR. Table 4 shows some recommended
supercapacitors. Other parameters such as temperature
range, RMS current, leakage current, etc. should also be
considered during the system design.
SYS Short Circuit Protection
The series pass power MOSFET from VCC to SYS limits
the current to a low level after the SYS output shorts to
ground to protect the device and downstream compo-
nents. During the fault condition, the power loop is still
active to monitor the die temperature and reduce the
current when the die temperature exceeds 130°C. Once
the short-circuit fault is removed, the SYS voltage recov-
ers to the normal value automatically.
The AAT4712 also includes short-circuit protection cir-
cuitry for the discharge path from OUT to SYS to avoid
large current discharging through the device over a long
term and avoid damage to the device.
PCB Layout Recommendations
For proper thermal management and to take advantage
of the low RDS(ON) of the AAT4712, certain circuit board
layout rules should be followed:
1. VCC, VOUT
, and VSYS should be routed using wide trac-
es.
2. GND should be connected to a ground plane. The
ground plane area connected to the ground pins
should be made as large as possible.
3. For best performance, CIN and CSYS should be placed
close to the VCC and SYS pins.
4. For maximum power dissipation of the AAT4712
TDFN package, the exposed pad should be soldered
to the board ground plane to further increase local
heat dissipation. A ground pad below the exposed
pad is strongly recommended.
AAT4712
DATA SHEET
Power Path with Input Current Limit and Capacitor Charger
13
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
201912A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • May 2, 2012
Evaluation Board Schematic
ADJ
14
ISET
2
GND
15
SYS
4
OUT 9
VCC 12
VCC 13
POK 16
1
RDY
3
SYS
5
SYS
6
SYS
7
SYS
8
OUT 10
OUT 11
U1 AAT4712
RSET 1.24M
C1
10µF
C3
22µF
C2
10µF
RADJ 18.2k
R1 1.74k
R2 1.74k
VCC
RDY
GND
POK
SYS
LED
D2
LEDD1
N/C
OUT
RB1
RB2
Super
Cap
Figure 4: AAT4712 Evaluation Board Schematic.
Evaluation Board Layout
a: Top Side b: Bottom Side
Figure 5: AAT4712 Evaluation Board Layout.
Component Part Number Description Manufacturer
U1 AAT4712 Current Limited Switch with Capacitor Charger Skyworks
R1,R2 RC0603FR-071K74L Res 1.74K 1/10W 1% 0603 SMD
YageoRSET RC0603FR-071M24L Res 1.24M 1/10W 1% 0603 SMD
RADJ RC0603FR-0718K2L Res 18.2K 1/10W 1% 0603 SMD
C1, C2 GRM21BR61C106K Cap Ceramic 10F 0805 X5R 16V 10% Murata
C3 GRM21BR60J226M Cap Ceramic 22F 0805 X5R 6.3V 20%
D1, D2 0805KRCT Red LED 0805 HB
SUPERCAP, RB1, RB2 Not populated
Table 5: AAT4712 Evaluation Board Bill of Materials.
AAT4712
DATA SHEET
Power Path with Input Current Limit and Capacitor Charger
14 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
201912A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • May 2, 2012
Copyright © 2012 Skyworks Solutions, Inc. All Rights Reserved.
Information in this document is provided in connection with Skyworks Solutions, Inc. (“Skyworks”) products or services. These materials, including the information contained herein, are provided by Skyworks as a
service to its customers and may be used for informational purposes only by the customer. Skyworks assumes no responsibility for errors or omissions in these materials or the information contained herein. Sky-
works may change its documentation, products, services, speci cations or product descriptions at any time, without notice. Skyworks makes no commitment to update the materials or information and shall have no
responsibility whatsoever for con icts, incompatibilities, or other dif culties arising from any future changes.
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THE MATERIALS, PRODUCTS AND INFORMATION ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, INCLUDING FITNESS FOR A PARTICULAR
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CLUDING BUT NOT LIMITED TO ANY SPECIAL, INDIRECT, INCIDENTAL, STATUTORY, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS THAT MAY RESULT FROM
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Customers are responsible for their products and applications using Skyworks products, which may deviate from published speci cations as a result of design defects, errors, or operation of products outside of pub-
lished parameters or design speci cations. Customers should include design and operating safeguards to minimize these and other risks. Skyworks assumes no liability for applications assistance, customer product
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Skyworks, the Skyworks symbol, and “Breakthrough Simplicity” are trademarks or registered trademarks of Skyworks Solutions, Inc., in the United States and other countries. Third-party brands and names are for
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1. XYY = assembly and date code.
2. Sample stock is generally held on part numbers listed in BOLD.
3. The leadless package family, which includes QFN, TQFN, DFN, TDFN and STDFN, has exposed copper (unplated) at the end of the lead terminals due to the manufacturing
process. A solder fillet at the exposed copper edge cannot be guaranteed and is not required to ensure a proper bottom solder connection.
Ordering Information
Package Marking1Part Number (Tape and Reel)2
TDFN34-16 G9XYY AAT4712IRN-T1
Skyworks Green™ products are compliant with
all applicable legislation and are halogen-free.
For additional information, refer to Skyworks
Definition of Green™, document number
SQ04-0074.
Package Information3
TDFN34-16
3.000
±
0.050 1.600
±
0.050
0.000
+
0.100
-0.000 0.203 REF
0.750
±
0.050
4.000
±
0.050
3.300
±
0.050
Index Area
Detail "A"
Top View Bottom View
Side View
0.450
±
0.050
0.230
±
0.0500.450
±
0.050
Detail "A"
All dimensions in millimeters.