Enpirion(R) Power Datasheet EY1501DI-ADJ High Performance 1A LDO EY1501DI-ADJ Datasheet The EY1501DI-ADJ is a low voltage, high current, single output LDO specified at 1A output current. This LDO operates from input voltages from 2.2V to 6V, and is capable of providing output voltages from 0.8V to 5V. The EY1501DI-ADJ features an adjustable output. Features A sub-micron BiCMOS process is utilized to deliver the best in class analog performance and overall value. This CMOS LDO will consume significantly lower quiescent current as a function of load compared to bipolar LDOs, which translates into higher efficiency and packages with smaller footprints. State of the art internal compensation achieves a very fast load transient response. An external capacitor on the soft-start pin provides an adjustable soft-starting ramp. The EN feature allows the part to be placed into a low quiescent current shutdown mode. A Power OK logic output signals a fault condition. * Very Low 130mV Dropout Voltage at VOUT = 2.5V * 0.2% initial VOUT Accuracy * 1.8% VOUT Accuracy Guaranteed Over Line, Load and TJ = -40C to +125C * Very Fast Transient Response * Programmable Soft-starting * Power OK Output * Excellent 58dB PSRR at 1kHz * Current Limit Protection * Thermal Shutdown Function * Available in a 10 Ld DFN Package * Pb-Free (RoHS Compliant) Applications Table 1 shows the EY1501DI-ADJ features. TABLE 1. EY1501DI-ADJ Features * DSP, FPGA and P Core Power Supplies PART NUMBER PROGRAMMABLE ILIMIT ILIMIT (DEFAULT) VOUT EY1501DI-ADJ No 1.75A ADJ * Noise-Sensitive Instrumentation Systems * Post Regulation of Switched Mode Power Supplies * Industrial Systems * Medical Equipment * Telecommunications and Networking Equipment * Servers * Hard Disk Drives (HD/HDD) 10 10F CIN VIN VOUT 9 V IN VOUT 1 2 82pF CPB 10k R3 VFB 3 1.00k R1 EY1501DI-ADJ 7 6 0.01F CSS EN POK 2.61k R2 1.8V 140 10F COUT 120 100k RPOK 4 DROPOUT VOLTAGE (mV) 2.5V 10% 100 80 60 40 20 VOUT = 2.5V SS GND 0 5 0 0.2 0.4 0.6 0.8 1.0 OUTPUT CURRENT (A) FIGURE 2. DROPOUT vs LOAD CURRENT FIGURE 1. TYPICAL APPLICATION CIRCUIT 101 Innovation Drive San Jose, CA 95134 www.altera.com May 2014 (c) 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9001:2008 Registered Altera Corporation Subscribe 10039 May 28, 2014 Rev A Page 2 Ordering Information PART NUMBER (Note 3) EY1501DI-ADJ (Note 1) PART MARKING 1501 VOUT VOLTAGE (Note 2) TEMP RANGE (C) ADJ -40 to +125 PACKAGE (Pb-Free) 10 Ld 3x3 DFN PKG DWG. # L10.3x3 NOTES: 1. Please refer to Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html 2. For other output voltages, contact Altera Enpirion Marketing. 3. These Altera Enpirion Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Altera Enpirion Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Enpirion Power Datasheet EY1501DI-ADJ High Performance 1A LDO 10039 May 28, 2014 May 2014 Altera Corporation Rev A Page 3 Pin Configuration EY1501DI-ADJ (10 LD 3x3 DFN) TOP VIEW VOUT 1 VOUT 2 VFB 3 POK GND 10 VIN 9 VIN 8 NC 4 7 EN 5 6 SS EPAD Pin Descriptions PIN NUMBER PIN NAME 1, 2 VOUT Regulated output voltage. A minimum 10F X5R/X7R output capacitor is required for stability. See "External Capacitor Requirements" on page 9 for more details. 3 VFB This pin is connected to the feedback resistor divider and provides voltage feedback signals for the LDO to set the output voltage. In addition, the Power OK circuit uses this input to monitor the output voltage status. 4 POK This is an open drain logic output used to indicate the status of the output voltage. Logic low indicates VOUT is not in regulation. Must be grounded if not used. 5 GND Ground. 6 SS External capacitor on this pin adjusts startup ramp and controls inrush current. 7 EN VIN independent chip EN. TTL and CMOS compatible. 8 NC No connection. Leave floating. 9, 10 VIN Input supply. A minimum of 10F X5R/X7R input capacitor is required for proper operation. See "External Capacitor Requirements" on page 9 for more details. - EPAD May 2014 10039 DESCRIPTION EPAD at ground potential. It is recommended to solder the EPAD to the ground plane. Altera Corporation Enpirion Power Datasheet EY1501DI-ADJ High Performance 1A LDO May 28, 2014 Rev A Page 4 Absolute Maximum Ratings Thermal Information VIN Relative to GND (Note 4). . . . . . . . . . . . . . . . -0.3V to +6.5V VOUT Relative to GND (Note 4) . . . . . . . . . . . . . . -0.3V to +6.5V POK, EN, VFB, SS Relative to GND (Note 4) . . . . . . . . . . . . . . . . . -0.3V to +6.5V ESD Rating Human Body Model (Tested per JESD22 A114F) . . . . . 2.5kV Machine Model (Tested per JESD22 A115C) . . . . . . . . . 250V Latch Up (Tested per JESD78C, Class 2, Level A)100mA at +85C Thermal Resistance (Typical) JA (C/W) JC (C/W) 10 Ld DFN Package (Notes 5, 6). 48 7 Storage Temperature Range . . . . . . . . . . . . . . . .-65C to +150C Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150C Recommended Operating Conditions (Notes 7, 8) Junction Temperature Range (TJ) (Note 7) . . . . -40C to +125C VIN Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2V to 6V VOUT Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mV to 5V POK, EN, VFB, SS relative to GND . . . . . . . . . . . . . . . 0V to 6V POK Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <10mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. ABS max voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%. 5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. 6. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 7. Extended operation at these conditions may compromise reliability. Exceeding these limits will result in damage. Recommended operating conditions define limits where specifications are guaranteed. 8. Electromigration specification defined as lifetime average junction temperature of +110C where max rated DC current = lifetime average current. Electrical Specifications Unless otherwise noted, VIN = VOUT + 0.4V, VOUT = 1.8V, CIN = COUT = 2.2F, TJ = +25C. Applications must follow thermal guidelines of the package to determine worst case junction temperature. Please refer to "Applications Information" on page 8. Boldface limits apply over the operating temperature range, -40C to +125C. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 9) TYP MAX (Note 9) UNITS 491 500 509 mV 1 % DC CHARACTERISTICS Feedback Pin (VFB Option Only) VVFB 2.2V VIN 6V, 0A < ILOAD < 1A DC Input Line Regulation VOUT/ VIN VOUT + 0.5V < VIN < 5V DC Output Load Regulation VOUT/ IOUT 0A < ILOAD < 1A, All voltage options Feedback Input Current Ground Pin Current VVFB = 0.5V IQ -1 % 0.01 1 A ILOAD = 0A, 2.2V < VIN < 6V 3 5 mA ILOAD = 1A, 2.2V < VIN < 6V 5 7 mA Ground Pin Current in Shutdown ISHDN EN Pin = 0.2V, VIN = 6V 0.2 12 A Dropout Voltage (Note 10) VDO ILOAD = 1A, VOUT = 2.5V 130 212 mV Output Short Circuit Current OCP VOUT = 0V, 2.2V < VIN < 6V 1.75 A Thermal Shutdown Temperature TSD 2.2V < VIN < 6V 160 C Thermal Shutdown Hysteresis (Rising Threshold) TSDn 2.2V < VIN < 6V 30 C PSRR f = 1kHz, ILOAD = 1A; VIN = 2.2V 58 dB f = 120Hz, ILOAD = 1A; VIN = 2.2V 72 dB ILOAD = 1A, BW = 10Hz < f < 100kHz 63 VRMS AC CHARACTERISTICS Input Supply Ripple Rejection Output Noise Voltage Enpirion Power Datasheet EY1501DI-ADJ High Performance 1A LDO 10039 May 28, 2014 May 2014 Altera Corporation Rev A Page 5 Electrical Specifications Unless otherwise noted, VIN = VOUT + 0.4V, VOUT = 1.8V, CIN = COUT = 2.2F, TJ = +25C. Applications must follow thermal guidelines of the package to determine worst case junction temperature. Please refer to "Applications Information" on page 8. Boldface limits apply over the operating temperature range, -40C to +125C. (Continued) PARAMETER MIN (Note 9) TYP MAX (Note 9) UNITS 2.2V < VIN < 6V 0.3 0.8 1 V 10 80 200 mV SYMBOL TEST CONDITIONS EN PIN CHARACTERISTICS Turn-on Threshold Hysteresis (Rising Threshold) 2.2V < VOUT + 0.4V < 6V EN Pin Turn-on Delay COUT = 10F, ILOAD = 1A EN Pin Leakage Current VIN = 6V, EN = 3V 100 s 1 A SOFT-START CHARACTERISTICS SS Pin Currents (Note 11) IPD VIN = 3.5V, EN = 0V, SS = 1V ICHG 0.5 1 1.3 mA -3.3 -2 -0.8 A 75 85 92 %VOUT 100 mV 1 A POK PIN CHARACTERISTICS VOUT POK Flag Threshold VOUT POK Flag Hysteresis 4 POK Flag Low Voltage VIN = 2.5V, ISINK = 500A POK Flag Leakage Current VIN = 6V, POK = 6V % NOTES: 9. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 10. Dropout is defined as the difference in supply VIN and VOUT when the supply produces a 2% drop in VOUT from its nominal voltage. 11. IPD is the internal pull down current that discharges the external SS capacitor on disable. ICHG is the current from the SS pin that charges the external SS capacitor during start-up. May 2014 10039 Altera Corporation Enpirion Power Datasheet EY1501DI-ADJ High Performance 1A LDO May 28, 2014 Rev A Page 6 Typical Operating Performance Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10F, TJ = +25C, IL = 0A. 200 1.8 VOUT = 2.5V 180 1.2 140 IOUT = 1.0A 0.6 120 100 DVOUT (%) DROPOUT VOLTAGE (mV) 160 IOUT = 0.5A 80 0 -0.6 60 IOUT = 0.1A 40 -1.2 20 0 -40 -25 -10 5 20 35 50 65 80 95 -1.8 -50 110 125 -25 0 25 50 75 100 125 150 JUNCTION TEMPERATURE (C) TEMPERATURE (C) FIGURE 3. DROPOUT vs TEMPERATURE FIGURE 4. VOUT vs TEMPERATURE 1.8 2.0 1.8 1.2 1.4 0.6 1.2 DVOUT (%) OUTPUT VOLTAGE (V) 1.6 +125C 1.0 0.8 -40C +25C +25C 0 -0.6 0.6 0.4 -40C +125C -1.2 0.2 0 0 2 1 4 3 5 -1.8 6 0 0.25 SUPPLY VOLTAGE (V) FIGURE 5. OUTPUT VOLTAGE vs SUPPLY VOLTAGE 0.50 OUTPUT CURRENT (A) 0.75 1.00 FIGURE 6. OUTPUT VOLTAGE vs OUTPUT CURRENT 3.5 5 3.0 GROUND CURRENT (mA) GROUND CURRENT (mA) 4 2.5 2.0 1.5 +25C +125C -40C 1.0 0.5 0 0 0.2 0.4 0.6 0.8 1.0 2 1 0 2 3 4 5 6 INPUT VOLTAGE (V) LOAD CURRENT (A) FIGURE 7. GROUND CURRENT vs LOAD CURRENT FIGURE 8. GROUND CURRENT vs SUPPLY VOLTAGE Enpirion Power Datasheet EY1501DI-ADJ High Performance 1A LDO 10039 3 May 28, 2014 May 2014 Altera Corporation Rev A Page 7 Typical Operating Performance Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10F, TJ = +25C, IL = 0A. (Continued) 3.5 2.5 2.0 CURRENT (A) VOLTAGE RAILS AT 50mV/DIV VIN = 3.7V, VOUT = 3.3V, COUT = 10F, CPB = 100pF 6V 2.2V 1.5 1.0 0.5 VIN = 2.9V, VOUT = 2.5V, COUT = 10F, CPB = 82pF 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 JUNCTION TEMPERATURE (C) FIGURE 10. CURRENT LIMIT vs TEMPERATURE (VOUT = 0V) VIN = 2.5V, VOUT = 1.8V, COUT = 10F, CPB = 82pF VIN = 2.5V, VOUT = 1.5V, COUT = 22F, CPB = 150pF EN (2V/DIV) VIN = 2.5V, VOUT = 1.2V, COUT = 47F, CPB = 270pF VOUT (1V/DIV) VIN = 2.5V, VOUT = 1.0V, COUT = 47F, CPB = 220pF SS (1V/DIV) 1A 1mA di/dt = 4A/s FIGURE 9. LOAD TRANSIENT RESPONSE FIGURE 11. EN START-UP (Css = 2.2nF) 90 90 80 80 500mA 70 COUT = 10F, Cpb = 82pF COUT = 100F 70 1A 60 60 50 PSRR (dB) PSRR (dB) (500s/DIV) POK (1V/DIV) TIME (20s/DIV) 0mA 100mA 40 50 40 30 30 20 20 10 10 Cpb = 82pF 0 100 1k 10k FREQUENCY (Hz) 100k 1M FIGURE 12. PSRR vs FREQUENCY AND LOAD CURRENT May 2014 10039 0 100 1k 10k FREQUENCY (Hz) 100k 1M FIGURE 13. PSRR VS FREQUENCY AND OUTPUT CAPACITANCE (IOUT = 100MA) Altera Corporation Enpirion Power Datasheet EY1501DI-ADJ High Performance 1A LDO May 28, 2014 Rev A Page 8 Typical Operating Performance Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10F, TJ = +25C, IL = 0A. (Continued) 10 VIN = 3.8V 1 VIN (2V/DIV) NOISE (V/Hz) VIN = 2.25V 0.1 VIN = 2.2V 0.01 VOUT = 1.8V COUT = 10F IL = 1A VOUT (5mV/DIV) 0.001 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) TIME (200s/DIV) FIGURE 15. OUTPUT NOISE SPECTRAL DENSITY FIGURE 14. LINE TRANSIENT RESPONSE Block Diagram VIN EN CONTROL LOGIC EA POK THERMAL SENSOR REFERENCE + SOFT-START + FET DRIVER WITH CURRENT LIMIT VOUT SS VFB + POK - GND Applications Information Input Voltage Requirements EY1501DI-ADJ is capable of delivering output voltages from 0.8V to 5.0V. Due to the nature of an LDO, VIN must be some margin higher than VOUT plus dropout at the maximum rated current of the application if active filtering (PSRR) is expected from VIN to VOUT. The very low dropout specification allows applications to design for a level of efficiency that can accommodate profiles smaller than the TO220/263. EN Operation The EN turn-on threshold is typically 800mV with 80mV of hysteresis. This pin must not be left floating, and should be tied to VIN if not used. A 1k to 10k pull-up resistor is required for applications that use open collector or open drain outputs to control the EN pin. An internal pull-up or pull-down resistor to change these values is available upon request. The EN pin may be connected directly to VIN for applications with outputs that are always on. Enpirion Power Datasheet EY1501DI-ADJ High Performance 1A LDO 10039 May 28, 2014 May 2014 Altera Corporation Rev A Page 9 Power OK Operation POK is a logic output that indicates the status of VOUT. The POK flag is an open-drain NMOS that can sink up to 10mA. It requires an external pull-up resistor typically connected to the VOUT pin. The POK pin should not be pulled up to a voltage source greater than VIN. POK goes low when the output voltage drops below 84% of the nominal output voltage or if the part is disabled. The POK comparator functions during current limit and thermal shutdown. For applications not using this feature, connect this pin to ground. Soft-Start Operation The soft-start circuit controls the rate at which the output voltage rises up to regulation at power-up or LDO enable. This start-up ramp time can be set by adding an external capacitor from the SS pin to ground. An internal 2A current source charges up this CSS and the feedback reference voltage is clamped to the voltage across it. The start-up time is set by Equation 1. C SS x0.5 T start = -------------------2A (EQ. 1) Equation 2 determines the CSS required for a specific start-up in-rush current, where VOUT is the output voltage, COUT is the total capacitance on the output and IINRUSH is the desired in-rush current. V OUT xC OUT x2A C SS = -------------------------------------------I INRUSH x0.5V (EQ. 2) The external capacitor is always discharged to ground at the beginning of start-up or enabling. Output Voltage Selection An external resistor divider, R1 and R2 as referenced in Figure 1 on page 1, is used to scale the output voltage relative to the internal reference voltage. The output voltage can be programmed to any level between 0.8V and 5V. The recommended value for R2 is 500 to 5k. R1 is then chosen to satisfy Equation 3. R2 V OUT = 0.5V x ------ + 1 R1 (EQ. 3) External Capacitor Requirements External capacitors are required for proper operation. Careful attention must be paid to the layout guidelines and selection of capacitor type and value to ensure optimal performance. OUTPUT CAPACITOR The EY1501DI-ADJ applies state-of-the-art internal compensation to keep the selection of the output capacitor simple for the customer. Stable operation over full temperature, VIN range, VOUT range and load extremes are guaranteed for all capacitor types and values assuming the minimum recommended ceramic capacitor is used for local bypass on VOUT. There is a growing trend to use very-low ESR multilayer ceramic capacitors (MLCC) because they can support fast load transients and also bypass very high frequency noise from other sources. However, the effective capacitance of MLCCs drops with applied voltage, age, and temperature. X7R and X5R dieletric ceramic capacitors are strongly recommended as they typically maintain a capacitance range within 20% of nominal voltage over full operating ratings of temperature and voltage. This output capacitor must be connected to the VOUT and GND pins of the LDO with PCB traces no longer than 0.5cm. Additional capacitors of any value in ceramic, POSCAP, alum/tantalum electrolytic types may be placed in parallel to improve PSRR at higher frequencies and/or load transient AC output voltage tolerances. The use of Cpb (see following section) is recommended when only the minimum recommended ceramic capacitor is used on the output. Please refer to Table 2 for these minimum conditions for various output voltages. May 2014 10039 Altera Corporation Enpirion Power Datasheet EY1501DI-ADJ High Performance 1A LDO May 28, 2014 Rev A Page 10 Phase Boost Capacitor A small phase boost capacitor, Cpb, can be placed across the top resistor, R2, in the feedback resistor divider network in order to place a zero at: 1 F z = -----------------------------2xR 2 xC PB (EQ. 4) This zero increases the crossover frequency of the LDO and provides additional phase resulting in faster load transient response. It is important to note that LDO stability and load transient performance are affected by the type of output capacitor used. For optimal result, empirical tuning of CPB is suggested for each specific application. It is recommended to not use CPB when high ESR capacitors such as Aluminum Electrolytic or Tantalum are used on the output. Table 2 shows the recommended minimum ceramic COUT and corresponding CPB, R2 and R1 for different output voltages. TABLE 2. RECOMMENDED CPB FOR DIFFERENT VOUT AND COUT VOUT (V) R2 (k) R1 (k) COUT (F) CPB (pF) 5.0 2.61 0.287 10 100 3.3 2.61 0.464 10 100 2.5 2.61 0.649 10 82 1.8 2.61 1.0 10 82 1.5 2.61 1.3 10 68 1.5 2.61 1.3 22 150 1.2 2.61 1.87 22 120 1.2 2.61 1.87 47 270 1.0 2.61 2.61 47 220 0.8 2.61 4.32 47 220 INPUT CAPACITOR For proper operation, a minimum capacitance of 10F X5R/X7R is required at the input. This ceramic input capacitor must be connected to the VIN and GND pins of the LDO with PCB traces no longer than 0.5cm. Power Dissipation and Thermals The junction temperature must not exceed the range specified in the "Recommended Operating Conditions (Notes 7, 8)" on page 4. The power dissipation can be calculated by using Equation 5: (EQ. 5) P D = ( V IN - V OUT ) x I OUT + V IN x I GND The maximum allowable junction temperature, TJ(MAX) and the maximum expected ambient temperature, TA(MAX) determine the maximum allowable power dissipation, as shown in Equation 6: (EQ. 6) P D ( MAX ) = ( T J ( MAX ) - T A ) JA JA is the junction-to-ambient thermal resistance. For safe operation, enure that the power dissipation PD, calculated from Equation 5, is less than the maximum allowable power dissipation PD(MAX). Enpirion Power Datasheet EY1501DI-ADJ High Performance 1A LDO 10039 May 28, 2014 May 2014 Altera Corporation Rev A Page 11 The DFN package uses the copper area on the PCB as a heat-sink. The EPAD of this package must be soldered to the copper plane (GND plane) for effective heat dissipation. Figure 16 shows a curve for the JA of the DFN package for different copper area sizes. 49 47 JA C/W 45 43 41 39 37 2 4 6 8 10 12 14 16 18 20 22 24 EPAD-MOUNT COPPER LAND AREA ON PCB, mm2 FIGURE 16. 3MMX3MM-10 PIN DFN ON 4-LAYER PCB WITH THERMAL VIAS JA VS EPAD-MOUNT COPPER LAND AREA ON PCB Thermal Fault Protection The power level and the thermal impedance of the package (+45C/W for DFN) determine when the junction temperature exceeds the thermal shutdown temperature. In the event that the die temperature exceeds around +160C, the output of the LDO will shut down until the die temperature cools down to about +130C. Current Limit Protection The EY1501DI-ADJ LDO incorporates protection against overcurrent due to any short or overload condition applied to the output pin. The LDO performs as a constant current source when the output current exceeds the current limit threshold noted in the "Electrical Specifications" table on page 4. If the short or overload condition is removed from VOUT, then the output returns to normal voltage regulation mode. In the event of an overload condition, the LDO may begin to cycle on and off due to the die temperature exceeding thermal fault condition and subsequently cooling down after the power device is turned off. May 2014 10039 Altera Corporation Enpirion Power Datasheet EY1501DI-ADJ High Performance 1A LDO May 28, 2014 Rev A Page 12 Revision History The table lists the revision history for this document. DATE REVISION May, 2014 1.0 CHANGE Initial Release. Enpirion Power Datasheet EY1501DI-ADJ High Performance 1A LDO 10039 May 28, 2014 May 2014 Altera Corporation Rev A Page 13 Package Outline Drawing L10.3x3 10 LEAD DUAL FLAT PACKAGE (DFN) 3.00 6 PIN #1 INDEX AREA A B 1 6 PIN 1 INDEX AREA (4X) 3.00 2.00 8x 0.50 2 10 x 0.23 4 0.10 1.60 TOP VIEW 10x 0.35 BOTTOM VIEW 4 (4X) 0.10 M C A B 0.415 PACKAGE OUTLINE 0.200 0.23 0.35 (10 x 0.55) SEE DETAIL "X" (10x 0.23) 1.00 MAX 0.10 C 0.20 2.00 C BASE PLANE SEATING PLANE 0.08 C SIDE VIEW (8x 0.50) C 0.20 REF 5 1.60 0.05 TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Lead width applies to the metallized terminal and is measured between 0.18mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. May 2014 10039 Altera Corporation Enpirion Power Datasheet EY1501DI-ADJ High Performance 1A LDO May 28, 2014 Rev A