v3.0 TM ProASICPLUS Flash Family FPGAs Fe a t ur es an d B e ne f i ts * 100% Routability and Utilization High C apaci t y I/O * 75,000 to 1 million System Gates * 27k to 198kbits of Two-Port SRAM * 66 to 712 User I/Os Rep ro gra m m able Fl as h T ech nol ogy * * * * 0.22 4LM Flash-based CMOS Process Live at Power-Up, Single-Chip Solution No Configuration Device Required Retains Programmed Design during Power-Down/ Power-Up Cycles * Schmitt-Trigger Option on Every Input * Mixed 2.5V/3.3V Support with Individually-Selectable Voltage and Slew Rate * Bidirectional Global I/Os * Compliance with PCI Specification Revision 2.2 * Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant * Pin Compatible Packages across ProASICPLUS Family Uni que Cl ock Con dit io ning C ir cui tr y * PLL with Flexible Phase, Multiply/Divide and Delay Capabilities * Internal and/or External Dynamic PLL Configuration * Two LVPECL Differential Pairs for Clock or Data Inputs P erf orm a nce * 3.3V, 32-bit PCI (up to 50 MHz) * Two Integrated PLLs * External System Performance up to 150 MHz S ta ndar d FP GA and AS IC De si gn F low S ecur e Pr og ram m i ng * The Industry's Most Effective Security Key (FlashLock) Prevents Read Back of Programming Bitstream Low P ower * Low Impedance Flash Switches * Segmented Hierarchical Routing Structure * Small, Efficient, Configurable (Combinatorial or Sequential) Logic Cells * Flexibility with Choice of Industry-Standard Frontend Tools * Efficient Design through Frontend Timing and Gate Optimization IS P S uppo rt * In-System Programming (ISP) via JTAG Port S RA Ms and FIFO s Hig h P er f o r m ance R out ing H i era rc hy * Ultra-Fast Local and Long-Line Network * High Speed Very Long-Line Network * High Performance, Low Skew, Splittable Global Network * ACTgen Netlist Generation Ensures Optimal Usage of Embedded Memory Blocks * 24 SRAM and FIFO Configurations with Synchronous and Asynchronous Operation up to 150 MHz (typical) Pr oA S I C PL U S P r o du ct Pr o f i l e Device APA075 Maximum System Gates 75,000 Maximum Tiles (Registers) 3,072 Embedded RAM Bits (k=1,024 bits) 27k Embedded RAM Blocks (256x9) 12 LVPECL 2 PLL 2 Global Networks 4 Maximum Clocks 24 Maximum User I/Os 158 JTAG ISP Yes PCI Yes Package (by pin count) TQFP 100, 144 PQFP 208 PBGA 144 FBGA M a y 20 0 3 (c) 2003 Actel Corporation APA150 APA300 APA450 APA600 APA750 APA1000 150,000 6,144 36k 16 2 2 4 32 242 Yes Yes 300,000 8,192 72k 32 2 2 4 32 290 Yes Yes 450,000 12,288 108k 48 2 2 4 48 344 Yes Yes 600,000 21,504 126k 56 2 2 4 56 454 Yes Yes 750,000 32,768 144k 64 2 2 4 64 562 Yes Yes 1,000,000 56,320 198k 88 2 2 4 88 712 Yes Yes 100 208 456 144, 256 208 456 144, 256 208 456 676, 896 208 456 896, 1152 208 208 456 456 144, 256, 484 256, 484, 676 1 *See Actel's website for the latest version of the datasheet. Pr o A S I C P L U S F la s h F a m il y F P GA s G en er al D e sc r i p t i on The ProASICPLUS family of devices, Actel's second generation Flash FPGAs, offers enhanced performance over Actel's ProASIC family. It combines the advantages of ASICs with the benefits of programmable devices through nonvolatile Flash technology. This enables engineers to create high-density systems using existing ASIC or FPGA design flows and tools. In addition, the ProASICPLUS family offers a unique clock conditioning circuit based on two on-board phase-locked loops (PLLs). The family offers up to 1 million system gates, supported with up to 198kbits of 2-port SRAM and up to 712 user I/Os, all providing 50 MHz PCI performance. Advantages to the designer extend beyond performance. Unlike SRAM-based FPGAs, four levels of routing hierarchy simplify routing, while the use of Flash technology allows all functionality to be live at power-up. No external Boot PROM is required to support device programming. While on-board security mechanisms prevent all access to the program information, reprogramming can be performed in-system to support future design iterations and field upgrades. The device's architecture mitigates the complexity of ASIC migration at higher user volume. This makes ProASICPLUS a cost-effective solution for applications in the networking, communications, computing, and avionics markets. The ProASICPLUS family achieves its nonvolatility and reprogrammability through an advanced Flash-based 0.22m LVCMOS process with four-layers of metal. Standard CMOS design techniques are used to implement logic and control functions, including the PLLs and LVPECL inputs. This results in predictable performance fully compatible with gate arrays. The ProASICPLUS architecture provides granularity comparable to gate arrays. The device core consists of a Sea-of-Tiles. Each tile can be configured as a flip-flop, latch, or 3-input/1-output logic function by programming the appropriate Flash switches. The combination of fine 2 granularity, flexible routing resources, and abundant Flash switches allow 100% utilization and over 95% routability for highly congested designs. Tiles and larger functions are interconnected through a 4-level routing hierarchy. Embedded 2-port SRAM blocks with built-in FIFO/RAM control logic can have user-defined depth and width. Users can also select programming for synchronous or asynchronous operation, as well as parity generations or checking. The unique clock conditioning circuitry in each device includes two clock conditioning blocks. Each block provides a PLL core, delay lines, phase shifts (0, 90, 180, 270), and clock multipliers/dividers, as well as the circuitry needed to provide bidirectional access to the PLL. The PLL block contains four programmable frequency dividers, which allow the incoming clock signal to be divided by a wide range of factors from 1 to 64. The clock conditioning circuit also delays or advances the incoming reference clock up to 8 ns (in increments of 0.25 ns). The PLL can be configured internally or externally during operation without redesigning or reprogramming the part. In addition to the PLL, there are two LVPECL differential input pairs to accommodate high speed clock and data inputs. To support customer needs for more comprehensive, lower cost board-level testing, Actel's ProASICPLUS devices are fully compatible with IEEE Standard 1149.1 for test access port and boundary-scan test architecture. For more information concerning the Flash FPGA implementation, please refer to the "Boundary Scan (JTAG)" section on page 13. ProASICPLUS devices are available in a variety of high-performance plastic packages. Those packages and the performance features discussed above are described in more detail in the following sections. v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s O r d e r i n g I nf o r m a t i o n APA1000 _ F FG 1152 I Application (Ambient Temperature Range) Blank = Commercial (0 to +70 C) I = Industrial (-40 to +85 C) PP = Pre-production ES = Engineering Silicon (Room Temperature Only) Package Lead Count Package Type TQ = Thin Quad Flat Pack (1.4mm pitch) PQ = Plastic Quad Flat Pack (0.5mm pitch) FG = Fine Pitch Ball Grid Array (1.0mm pitch) BG = Plastic Ball Grid Array (1.27mm pitch) Speed Grade Blank = Standard Speed F = 20% Slower than Standard Part Number APA075 APA150 APA300 APA450 APA600 APA750 APA1000 = = = = = = = 75,000 Equivalent System Gates 150,000 Equivalent System Gates 300,000 Equivalent System Gates 450,000 Equivalent System Gates 600,000 Equivalent System Gates 750,000 Equivalent System Gates 1,000,000 Equivalent System Gates Pl a s t i c D e vi c e Re so u r ce s User I/Os* Device TQFP 100-Pin TQFP 144-Pin PQFP 208-Pin APA075 66 107 158 APA150 66 PBGA 456-Pin FBGA 144-Pin FBGA 256-Pin FBGA 484-Pin FBGA 676-Pin FBGA 896-Pin FBGA 1152-Pin 100 158 242 100 186 APA300 158 290 100 186 APA450 158 344 100 186 344 APA600 158 356 186 370 APA750 158 356 APA1000 158 356 454 454 562 642 712 Package Definitions TQFP = Thin Quad Flat Pack, PQFP = Plastic Quad Flat Pack, PBGA = Plastic Ball Grid Array, FBGA = Fine Pitch Ball Grid Array *Each pair of PECL I/Os were counted as one user I/O. v3.0 3 Pr o A S I C P L U S F la s h F a m il y F P GA s Pr od uc t A va i l a bi l i t y Speed Grade Std. Application -F* C I APA075 Device 100-Pin Thin Quad Flat Pack (TQFP) PP PP PP PP 208-Pin Plastic Quad Flat Pack (PQFP) 144-Pin Fine Pitch Ball Grid Array (FBGA) 100-Pin Thin Quad Flat Pack (TQFP) 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Plastic Ball Grid Array (PBGA) 144-Pin Fine Pitch Ball Grid Array (FBGA) 256-Pin Fine Pitch Ball Grid Array (FBGA) 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Plastic Ball Grid Array (PBGA) 144-Pin Fine Pitch Ball Grid Array (FBGA) 256-Pin Fine Pitch Ball Grid Array (FBGA) 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Plastic Ball Grid Array (PBGA) 144-Pin Fine Pitch Ball Grid Array (FBGA) 256-Pin Fine Pitch Ball Grid Array (FBGA) 484-Pin Fine Pitch Ball Grid Array (FBGA) 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Plastic Ball Grid Array (PBGA) 256-Pin Fine Pitch Ball Grid Array (FBGA) 484-Pin Fine Pitch Ball Grid Array (FBGA) 676-Pin Fine Pitch Ball Grid Array (FBGA) 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Plastic Ball Grid Array (PBGA) 676-Pin Fine Pitch Ball Grid Array (FBGA) 896-Pin Plastic Ball Grid Array (FBGA) 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Plastic Ball Grid Array (PBGA) 896-Pin Fine Pitch Ball Grid Array (FBGA) 144-Pin Thin Quad Flat Pack (TQFP) APA150 Device APA300 Device APA450 Device APA600 Device APA750 Device APA1000 Device 1152-Pin Fine Pitch Ball Grid Array (FBGA) Note: *-F parts are only available as commercial temperature devices. Applications: 4 C = Commercial I = Industrial Availability: = Available PP = Product Planned v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Pr oA S I C PL U S A r c hi t e c t u r e The proprietary ProASICPLUS architecture granularity comparable to gate arrays. provides The ProASICPLUS device core consists of a Sea-of-TilesTM (Figure 1). Each tile can be configured as a 3-input logic function (e.g., NAND gate, D-Flip-Flop, etc.) by programming the appropriate Flash switch interconnections (Figure 2 on page 6 and Figure 3 on page 6). Tiles and larger functions are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Flash switches are programmed to connect signal lines to the appropriate logic cell inputs and outputs. Dedicated high-performance lines are connected as needed for fast, low-skew global signal distribution throughout the core. Maximum core utilization is possible for virtually any design. ProASICPLUS devices also contain embedded two-port SRAM blocks with built-in FIFO/RAM control logic. Programming options include synchronous or asynchronous operation, two-port RAM configurations, user defined depth and width, and parity generation or checking. Please see the "Embedded Memory Configurations" section on page 21 for more information. Fla sh S wit ch Unlike SRAM FPGAs, ProASICPLUS uses a live on power-up ISP Flash switch as its programming element. In the ProASICPLUS Flash switch, two transistors share the floating gate, which stores the programming information. One is the sensing transistor, which is only used for writing and verification of the floating gate voltage. The other is the switching transistor. It can be used in the architecture to connect/separate routing nets or to configure logic. It is also used to erase the floating gate (Figure 2 on page 6). Logi c Ti le The logic tile cell (Figure 3 on page 6) has three inputs (any or all of which can be inverted) and one output (which can connect to both ultra-fast local and efficient long-line routing resources). Any three-input, one-output logic function (except a three-input XOR) can be configured as one tile. The tile can be configured as a latch with clear or set or as a flip-flop with clear or set. Thus, the tiles can flexibly map logic and sequential gates of a design. RAM Block 256x9 Two-Port SRAM or FIFO Block I/Os Logic Tile RAM Block 256x9 Two Port SRAM or FIFO Block Figure 1 * The ProASICPLUS Device Architecture v3.0 5 Pr o A S I C P L U S F la s h F a m il y F P GA s Floating Gate Sensing Switch In Switching Word Switch Out Figure 2 * Flash Switch Local Routing In 1 Efficient Long-Line Routing In 2 (CLK) In 3 (Reset) Figure 3 * Core Logic Tile Rou ti ng Res our ces The routing structure of ProASICPLUS devices is designed to provide high performance through a flexible four-level hierarchy of routing resources: ultra-fast local resources, efficient long-line resources, high speed very long-line resources, and high performance global networks. The ultra-fast local resources are dedicated lines that allow the output of each tile to connect directly to every input of the eight surrounding tiles (Figure 4 on page 7). The efficient long-line resources provide routing for longer distances and higher fanout connections. These resources vary in length (spanning 1, 2, or 4 tiles), run both vertically and horizontally, and cover the entire ProASICPLUS device (Figure 5 on page 7). Each tile can drive signals onto the efficient long-line resources, which can in turn, access every input of every tile. Active buffers are inserted automatically by routing software to limit the loading effects due to distance and fanout. 6 The high-speed very long-line resources, which span the entire device with minimal delay, are used to route very long or very high fanout nets. (Figure 6 on page 8). The high-performance global networks are low skew, high fanout nets that are accessible from external pins or from internal logic (Figure 7 on page 9). These nets are typically used to distribute clocks, resets, and other high fanout nets requiring a minimum skew. The global networks are implemented as clock trees, and signals can be introduced at any junction. These can be employed hierarchically with signals accessing every input on all tiles. v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s L Inputs L L L Ultra-Fast Local Lines (connects a tile to the adjacent tile, I/O buffer, or memory block) Output L L L L L Figure 4 * Ultra-Fast Local Resources Spans 4 Tiles Spans 1 Tile Spans 2 Tiles Logic Tile L L L L L L L L L L L L L L L L L L L L L L L L Spans 1 Tile Spans 2 Tiles Spans 4 Tiles Logic Cell L L L L L L Figure 5 * Efficient Long-Line Resources v3.0 7 Pr o A S I C P L U S F la s h F a m il y F P GA s High Speed Very Long-Line Resouces PAD RING I/O RING I/O RING PAD RING SRAM SRAM PAD RING Figure 6 * High Speed Very Long-Line Resources 8 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Cl ock Res our ce s PLUS based on a network of spines and ribs that reach all the tiles in their regions (Figure 7). This flexible clock tree architecture allows users to map up to 88 different internal/external clocks in an APA1000 device. Details on the clock spines and various numbers of the family are given in Table 1 on page 10. The ProASIC family offers powerful and flexible control of circuit timing through the use of analog circuitry. Each chip has two clock conditioning blocks containing a phase-locked loop (PLL) core, delay lines, phase shifter (0, 90, 180, 270), clock multiplier/dividers and all the circuitry needed for the selection and interconnection of inputs to the global network (thus providing bidirectional access to the PLL). This permits the PLL block to drive inputs and/or outputs via the two global lines on each side of the chip (four total lines). This circuitry is discussed in more detail in the "ProASICPLUS Clock Management System" section on page 15. The flexible use of the ProASICPLUS clock spine allows the designer to cope with several design requirements. Users implementing clock resource intensive applications can easily route external or gated internal clocks using global routing spines. Users can also drastically reduce delay penalties and save buffering resources by mapping critical high-fanout nets to spines. For design hints on using these features, refer to Actel's Efficient Use of ProASIC Clock Trees application note. Cl ock T ree s One of the main architectural benefits of ProASICPLUS is the set of power and delay friendly global networks. ProASICPLUS offers four global trees. Each of these trees is High Performace Global Network I/O RING PAD RING PAD RING Top Spine Global Networks Global Pads Global Pads Global Spine Bottom Spine I/O RING Global Ribs Scope of Spine (Shaded area plus local RAMs and I/Os) PAD RING Note: This figure shows routing for only one global path. Figure 7 * High Performance Global Network v3.0 9 Pr o A S I C P L U S F la s h F a m il y F P GA s Table 1 * Clock Spines APA075 APA150 APA300 APA450 APA600 APA750 APA1000 4 6 24 16 512 3,072 4 8 32 24 768 6,144 4 8 32 32 1,024 8,192 4 12 48 32 1,024 12,288 4 14 56 48 1,536 21,504 4 16 64 64 2,048 32,768 4 22 88 80 2,560 56,320 Global Clock Networks (Trees) Clock Spines/Tree Total Spines Top or Bottom Spine Height (Tiles) Tiles in Each Top or Bottom Spine Total Tiles Ar r ay Co ord ina tes one-to-one correspondence between I/O cells and core cells. In addition, the I/O coordinate system changes depending on the die/package combination. During many place-and-route operations in Actel's Designer software tool, it is possible to set constraints that require array coordinates. Core cell coordinates start at the lower left corner (1,1) or (1,5) if memories are present at the bottom. Memory coordinates use the same system and are indicated in Table 2. The memory coordinates for an APA1000 are illustrated in Figure 8. For more information on how to use constraints, see the Designer User's Guide for ProASICPLUS software tools. Table 2 is provided as a reference. The array coordinates are measured from the lower left (0,0). They can be used in region constraints for specific groups, designated by a wildcard, and containing core cells, I/Os, and memories. I/O and cell coordinates are used for placement constraints. Two coordinate systems are needed because there is not a Table 2 * Array Coordinates Logic Tile Min. Memory Rows Max. Device x y APA075 1 APA150 1 Bottom Top All x y y y Min. Max. 1 96 32 - (33,33) or (33, 35) 0,0 97, 37 1 128 48 - (49,49) or (49, 51) 0,0 129, 53 APA300 1 5 128 68 (1,3) or (1,5) (69,69) or (69, 71) 0,0 129, 73 APA450 1 5 192 68 (1,3) or (1,5) (69,69) or (69, 71) 0,0 193, 73 APA600 1 5 224 100 (1,3) or (1,5) (101,101) or (101, 103) 0,0 225, 105 APA750 1 5 256 132 (1,3) or (1,5) (133,133) or (133, 135) 0,0 257, 137 APA1000 1 5 352 164 (1,3) or (1,5) (165,165) or (165, 167) 0,0 353, 169 Memory Blocks (1,169) (353,169) (1,167) (352,167) (1,165) (352,165) (1,164) (352,165) Core (1,5) (352,5) (1,3) (352,3) (1,1) (352,1) (353,0) (0,0) Memory Blocks Figure 8 * Core Cell Coordinates for the APA1000 10 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Inpu t/ Out put Blo cks Six or seven standard I/O pads are grouped with a GND pad and either a VDD (core power) or VDDP (I/O power) pad. Two reference bias signals circle the chip. One protects the cascaded output drivers while the other creates a virtual VDD supply for the I/O ring. To meet complex system demands, the ProASICPLUS family offers devices with a large number of user I/O pins, up to 712 on the APA1000. If the I/O pad power supply (VDDP) is 3.3V, each I/O can be selectively configured at the 2.5V and 3.3V threshold levels. Table 3 shows the available supply voltage configurations (the PLL block uses an independent 2.5V supply on the AVDD and AGND pins). All I/Os include ESD protection circuits. Each I/O has been tested to 2000V to the human body model (per JESD22 (HMB)). I/O pads are fully configurable to provide the maximum flexibility and speed. Each pad can be configured as an input, an output, a tristate driver, or a bidirectional buffer (Figure 9 and Table 4). Table 3 * ProASICPLUS I/O Power Supply Voltages 3.3V/2.5V Signal Control VDDP 2.5V 3.3V Input Compatibility 2.5V 3.3V, 2.5V Output Drive 2.5V 3.3V, 2.5V Note: Y Pull-up Control EN A VDD is always 2.5V. Pad 3.3V/2.5V Signal Control Drive Strength and Slew-Rate Control Figure 9 * I/O Block Schematic Representation Table 4 * I/O Features Function Description I/O pads configured as inputs * Individually selectable 2.5V or 3.3V threshold levels * Optional pull-up resistor * Optionally configurable as Schmitt trigger input. The Schmitt trigger input option can be configured as an input only, not a bidirectional buffer. This input type may be slower than a standard input under certain conditions and has a typical hysteresis of 0.35V. I/O macros with an "S" in the standard I/O library have added Schmitt capabilities I/O pads configured as outputs * 3.3V PCI Compliant * Individually selectable 2.5V or 3.3V compliant output signals - 2.5V - JEDEC JESD 8-5 - 3.3V - JEDEC JESD 8-A (LVTTL and LVCMOS) * 3.3V PCI compliant * Ability to drive LVTTL and LVCMOS levels * Selectable drive strengths * Selectable slew rates I/O pads configured as bidirectional buffers * Tristate * Individually selectable 2.5V or 3.3V compliant output signals - 2.5V - JEDEC JESD 8-5 - 3.3V - JEDEC JESD 8-A (LVTTL and LVCMOS) * 3.3V PCI compliant * Optional pull-up resistor * Selectable drive strengths * Selectable slew rates * Tristate v3.0 11 Pr o A S I C P L U S F la s h F a m il y F P GA s P ower -u p S eq uenci ng PLUS PPECL (I/P) (PECLN) and NPECL (PECLREF). The LVPECL input pad cell differs from the standard I/O cell in that it is operated from VDD only. While ProASIC devices are live at power-up, the order of VDD and VDDP power-up is important during system start-up. VDD should be powered up before (or coincident with) VDDP on ProASICPLUS devices. Failure to follow these guidelines may result in undesirable pin behavior during system start-up. For more information, refer Actel's ProASICPLUS Family Devices Power-Up Behavior application note. Since it is exclusively an input, it requires no output signal, output enable signal, or output configuration bits. As a special high-speed differential input, it also does not require pull ups. Recommended termination for LVPECL inputs is shown in Figure 10. The LVPECL pad cell compares voltages, as illustrated in Figure 11, on the PPECL (I/P) pad and the NPECL pad and sends the results to the global MUX (Figure 14 on page 16). This high speed, low skew output essentially controls the clock conditioning circuit. LVP E C L Inp ut P ads In addition to standard I/O pads and power pads, ProASICPLUS devices have a single LVPECL input pad on both the east and west sides of the device, along with AVDD and AGND pins to power the PLL block. The LVPECL pad cell consists of an input buffer (containing a low voltage differential amplifier) and a signal and its complement, LVPECLs are designed to meet LVPECL JEDEC receiver standard levels (Table 5). Z 0 = 50 PPECL + From LVPECL Driver R = 100 Z 0 = 50 Data _ NPECL Figure 10 * Recommended Termination for LVPECL Inputs Voltage 2.72 2.125 1.49 0.86 Figure 11 * LVPECL High and Low Threshold Values Table 5 * LVPECL Receiver Specifications Symbol Parameter Min. Max Units VIH Input High Voltage 1.49 2.72 V VIL Input Low Voltage 0.86 2.125 V VID Differential Input Voltage 0.3 VDD V 12 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Boundary Scan (JTAG) ProASICPLUS devices are compatible with IEEE Standard 1149.1, which defines a set of hardware architecture and mechanisms for cost-effective board-level testing. The basic ProASICPLUS boundary-scan logic circuit is composed of the TAP (test access port), TAP controller, test data registers, and instruction register (Figure 12). This circuit supports all mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/PRELOAD and BYPASS) and the optional IDCODE instruction (Table 6). boundary-scan test usage. Actel recommends that a nominal 20k pull-up resistor is added to TDO and TCK pins. The TAP controller is a four-bit state machine (16 states) that operates as shown in Figure 13 on page 14. The `1's and `0's represent the values that must be present at TMS at a rising edge of TCK for the given state transition to occur. IR and DR indicate that the instruction register or the data register is operating in that state. ProASICPLUS devices have to be programmed at least once for complete boundary-scan functionality to be available. If boundary-scan functionality is required prior to partial programming, refer to online technical support on the Actel website and search for ProASICPLUS BSDL. Each test section is accessed through the TAP, which has five associated pins: TCK (test clock input), TDI and TDO (test data input and output), TMS (test mode selector) and TRST (test reset input). TMS, TDI and TRST are equipped with pull-up resistors to ensure proper operation when no input data is supplied to them. These pins are dedicated for I/O I/O I/O I/O I/O TDI Test Data Registers Instruction Register TAP Controller Device Logic TDO I/O TRST I/O TMS I/O TCK I/O Bypass Register I/O I/O I/O I/O I/O Figure 12 * ProASICPLUS JTAG Boundary Scan Test Logic Circuit Table 6 * Boundary-Scan Opcodes Hex Opcode EXTEST 00 SAMPLE/PRELOAD 01 IDCODE 0F CLAMP 05 BYPASS FF v3.0 13 Pr o A S I C P L U S F la s h F a m il y F P GA s The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals for the rest of the test logic architecture. On power-up, the TAP controller enters the Test-Logic-Reset state. To guarantee a reset of the controller from any of the possible states, TMS must remain high for five TCK cycles. The TRST pin may also be used to asynchronously place the TAP controller in the Test-Logic-Reset state. ProASICPLUS devices support three types of test data registers: bypass, device identification, and boundary scan. The bypass register is selected when no other register needs to be accessed in a device. This speeds up test data transfer to other devices in a test data path. The 32-bit device 1 Test-Logic Reset 0 0 Run-Test/ Idle 1 identification register is a shift register with four fields (lowest significant byte (LSB), ID number, part number and version). The boundary-scan register observes and controls the state of each I/O pin. Each I/O cell has three boundary-scan register cells, each with a serial-in, serial-out, parallel-in, and parallel-out pin. The serial pins are used to serially connect all the boundary-scan register cells in a device into a boundary-scan register chain, which starts at the TDI pin and ends at the TDO pin. The parallel ports are connected to the internal core logic tile and the input, output, and control ports of an I/O buffer to capture and load data into the register to control or observe the logic state of each I/O. 1 Select-DRScan 0 Scan 0 Capture-DR 1 Capture-IR 1 0 0 0 Shift-DR 0 0 1 1 0 0 Pause-IR 1 1 Exit2-DR 0 Exit2-IR 1 Update-DR 0 1 Figure 13 * TAP Controller State Diagram 14 v3.0 1 Exit-IR Pause-DR 0 0 Shift-IR 1 Exit-DR 1 Select-IR- 1 Update-IR 1 0 Pr o A SI C P L U S F la s h F a m il y F P GA s Ti m i ng C on t r o l an d Ch a r ac t e r i s t i cs P roA S I C P L U S Cl ock Man agem en t S ys te m Global B Introduction * Output from Global MUX B ProASICPLUS devices provide designers with very flexible clock conditioning capabilities. Each member of the ProASICPLUS family contains two phase-locked loop (PLL) blocks which perform the following functions: * Delayed or advanced version of fOUT * Clock Phase Adjustment via Programmable Delay (250 ps steps from -8 ns to +8 ns) * Clock Skew Minimization * Clock Frequency Synthesis Each PLL has the following key features: * Input Frequency Range (fIN) = 1.5 to 180 MHz * Feedback Frequency Range (fVCO) = 1.5 to 180 MHz * Output Frequency Range (fOUT) = 6 to 180 MHz * Output Phase Shift = 0 , 90 , 180 , and 270 * Output Duty Cycle = 50% * Low Output Jitter (max at 25 C) - fVCO <10 MHz. Jitter 1% or better - 10 MHz < fVCO < 60 MHz. Jitter 2% or better - fVCO > 60 MHz. Jitter 1% or better * Maximum Acquisition Time = 80s * Low Power Consumption - 6.9 mW (max - analog supply) + 7.0W/MHz (max - digital supply) * Divided version of either of the above * Further delayed version of either of the above (0.25 ns, 0.50 ns, or 4.00 ns delay)1 Func ti onal D es cr ipt io n Each PLL block contains four programmable dividers as shown in Figure 14 on page 16. These allow frequency scaling of the input clock signal as follows: * The n divider divides the input clock by integer factors from 1 to 32. * The m divider in the feedback path allows multiplication of the input clock by integer factors ranging from 1 to 64. * The two dividers together can implement any combination of multiplication and division resulting in a clock frequency between 24 and 180 MHz exiting the PLL core. This clock has a fixed 50% duty cycle. * The output frequency of the PLL core is given by the following formula (fREF is the reference clock frequency): fOUT = fREF * m/n * The third and fourth dividers (u and v) permit the signals applied to the global network to each be further divided by integer factors ranging from 1 to 4. The implementations: P hys ic al Im ple m ent at ion Each side of the chip contains a clock conditioning circuit based upon a 180 MHz PLL block (Figure 14 on page 16). Two global multiplexed lines extend along each side of the chip to provide bidirectional access to the PLL on that side (neither MUX can be connected to the opposite side's PLL). Each global line has optional LVPECL input pads (described below). The global lines may be driven by either the LVPECL global input pad or the outputs from the PLL block or both. Each global line can be driven by a different output from the PLL. Unused global pins can be configured as regular I/Os or left unconnected. They default to an input with pull-up. The two signals available to drive the global networks are as follows (Figure 15 on page 17): Global A (secondary clock) * Output from Global MUX A * Conditioned version of PLL output (fOUT) - delayed or advanced fGLB = m/(n*u) fGLA = m/(n*v) enable the user to define a wide range of frequency multipliers and divisors. The clock conditioning circuit can advance or delay the clock up to 8 ns (in increments of 0.25 ns) relative to the positive edge of the incoming reference clock. The system also allows for the selection of output frequency clock phases of 0, 90, 180, and 270. Prior to the application of signals to the rib drivers, they pass through programmable delay units, one per global network. These units permit the delaying of global signals relative to other signals to assist in the control of input set-up times. Not all possible combinations of input and output modes can be used. The degrees of freedom available in the bidirectional global pad system and in the clock conditioning circuit have been restricted. This avoids unnecessary and unwieldy design kit and software work. * Divided version of either of the above * Further delayed version of either of the above (0.25 ns, 0.50 ns, or 4.00 ns delay)1 1. This mode is available through the delay feature of the Global MUX driver. v3.0 15 Pr o A S I C P L U S F la s h F a m il y F P GA s Lock Signal each PLL and then latched into the PLL block. The JTAG ports can be used along with a built-in user JTAG interface hardware to load the configuration shift register externally. Another option is internal dynamic configuration via userdesigned hardware. Refer to Actel's ProASICPLUS PLL Dynamic Reconfiguration Using JTAG application note for more information. A Lock signal (Active High) is provided (using the ACTgen PLL development tool) to indicate that the PLL has locked to the incoming clock signal. Users can employ the Lock signal as a soft reset of the logic driven by GLB and/or GLA. P LL C onfi gur at io n Op ti ons The PLL can be configured during design (via Flash-configuration bits set in the programming bitstream) or dynamically during device operation, thus eliminating the need for complete reprogramming. The dynamic configuration bits are loaded into a serial-in/parallel-out shift register provided in the clock conditioning circuit of For information on the clock conditioning circuit, refer to the, Actel's Using ProASICPLUS Clock Conditioning Circuits application note. AVDD VDD AGND GND GLA Global MUX B OUT Input Pins to the PLL See Figure 13 + 17 on page - Clock Conditioning Circuitry (Top level view) External Feedback Signal GLB 27 4 Global MUX A OUT 8 Flash Configuration Bits Dynamic Configuration Bits Clock Conditioning Circuitry Detailed Block Diagram Global MUX B OUT /n PLL Core /m FBDLY D 270 180 90 0 DLYAFB D 1 /u /v Global MUX A OUT Notes: 1. FBDLY is a programmable delay line from 0 to 4 ns in 250 ps increments. 2. DLYA, DLYB, DLYAFB is a programmable delay line with values 0, 250 ps, 500 ps, and 4 ns. Figure 14 * PLL Block - Top-Level View and Detailed PLL Block Diagram v3.0 2 GLB 2 External Feedback 16 DLYB D DLYA2 D GLA Pr o A SI C P L U S F la s h F a m il y F P GA s Package Pins GL Physical I/O Buffers Global MUX Configuration Tile Std. Pad Cell Global MUX B OUT NPECL PECL Pad Cell PPECL External Feedback GLMX Std. Pad Cell GL Std. Pad Cell Global MUX A OUT Configuration Tile CORE Legend Physical Pin DATA Signals to the Global MUX DATA Signals to the Core Control Signals to the Global MUX DATA Signals to the PLL Block Note: When a signal from an I/O tile is connected to the core, it cannot be connected to the Global MUX at the same time. Figure 15 * Input Connectors to ProASICPLUS Clock Conditioning Circuitry Sa m p l e I m pl e m e nt a t i o ns C l oc k S k ew M i n i m i z ati o n Fr eque ncy S yn th esi s Figure 20 on page 20 indicates how feedback from the clock network can be used to create minimal skew between the distributed clock network and the "input" clock. The input clock is fed to the reference clock input of the PLL. The output clock (GLA) feeds a clock network. The feedback input to the PLL uses a clock input delayed by a routing network. The PLL then adjusts the phase of the input clock to match the delayed clock, thus providing nearly zero effective skew between the two clocks. Refer to Actel's Using ProASICPLUS Clock Conditioning Circuits application note for more information. Figure 16 on page 18 illustrates an example where the PLL is used to multiply a 33 MHz external clock up to 133 MHz. Figure 17 on page 18 uses two dividers to synthesize a 50 MHz output clock from a 40 MHz input reference clock. The input frequency of 40 MHz is multiplied by 5 and divided by 4, giving an output clock (GLB) frequency of 50 MHz. When dividers are used, a given ratio can be generated in multiple ways, allowing the user to stay within the operating frequency ranges of the PLL. For example, in this case the input divider could have been 2 and the output divider also 2, giving us a division of the input frequency by 4 to go with the feedback loop division (effective multiplication) by 5. A dj u st a b l e C l o ck D el a y Figure 18 on page 19 illustrates the delay of the input clock by employing one of the adjustable delay lines. This is easily done in ProASICPLUS by bypassing the PLL core entirely and using the output delay line. Notice also that the output clock can be effectively advanced relative to the input clock by using the delay line in the feedback path. This is shown in Figure 19 on page 19. Logi c Ti le T im i ng C har act er i st ics Timing characteristics for ProASICPLUS devices fall into three categories: family dependent, device dependent, and design dependent. The input and output buffer characteristics are common to all ProASICPLUS family members. Internal routing delays are device dependent. Design dependency means that actual delays are not determined until after placement and routing of the user's design are complete. Delay values may then be determined by using the Timer utility or performing simulation with post-layout delays. v3.0 17 Pr o A S I C P L U S F la s h F a m il y F P GA s Cr it ic al Net s and T ypi cal Ne ts T im i ng Der at in g PLUS Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most timing critical paths. Critical nets are determined by net property assignment prior to placement and routing. Refer to the Actel Designer User's Guide for details on using constraints. Global MUX B OUT 33 MHz Since ProASIC devices are manufactured with a CMOS process, device performance will vary with temperature, voltage, and process. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and optimal process variations. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case process variations (within process specifications). /1 /n 270 180 90 0 PLL Core /m /4 /u GLB D /1 133 MHz /v D D D External Feedback GLA Global MUX A OUT Figure 16 * Using the PLL 33 MHz In, 133 MHz Out Global MUX B OUT 40 MHz /4 /n 270 180 90 0 PLL Core /m /5 /u /1 GLB D 50 MHz D D External Feedback /v Global MUX A OUT Figure 17 * Using the PLL 40 MHz In, 50 MHz Out 18 v3.0 D GLA Pr o A SI C P L U S F la s h F a m il y F P GA s Global MUX B OUT 133 MHz /1 /n 270 180 90 0 PLL Core /m /1 /u GLB D /1 133 MHz /v D D D External Feedback GLA Global MUX A OUT Figure 18 * Using the PLL to Delay the Input Clock Global MUX B OUT 133 MHz /1 /n 270 180 90 0 PLL Core /m /1 /u /1 GLB D 133 MHz D D External Feedback /v D GLA Global MUX A OUT Figure 19 * Using the PLL to "Advance" the Input Clock v3.0 19 Pr o A S I C P L U S F la s h F a m il y F P GA s Global MUX B OUT 133 MHz /1 /n 270 180 90 0 PLL Core /m /1 /u D GLB /1 D D External Feedback /v Global MUX A OUT Q Q SET D CLR Figure 20 * Using the PLL for Clock De-skewing 20 v3.0 133 MHz D GLA Pr o A SI C P L U S F la s h F a m il y F P GA s PL L El e c t r i c al S pe c i f i c at i o n s Parameter Value Notes Reference Frequency fIN (min.) 1.5 MHz Reference Frequency fIN (max.) 180 MHz OSC Frequency fVCO (min.) 24 MHz OSC Frequency fVCO (max.) 180 MHz Clock conditioning circuitry (min.) lowest output frequency Clock conditioning circuitry (max.) highest output frequency Lowest output frequency voltage controlled oscillator Highest output frequency voltage controlled oscillator Lowest input frequency clock conditioning circuitry Highest input frequency clock conditioning circuitry Frequency Ranges Clock Conditioning Circuitry fOUT (min.) 6 MHz Clock Conditioning Circuitry fOUT (max.) 180 MHz Long Term Jitter Peak-to-Peak Max. Temperature Frequency MHz fVCO<10 10<fVCO<60 fVCO>60 25C (or higher) 1% 2% 1% 0C 1.5% 2.5% 1% -40C 2.5% 3.5% 1% Acquisition Time from Cold Start Acquisition Time (max.) Acquisition Time (max.) Power Consumption Analog Supply Power (max*) 6.9 mW Digital Supply Current (max) Duty Cycle 7 W/MHz 50% 0.5% Note: TM 200 cycles 80 s Period of low reference clock frequencies High reference clock frequencies *High clock frequency U se r S e c u r it y PLUS ProASIC devices have FlashLock protections bits that, once programmed, block the entire programmed contents from being read externally. If locked, the user can only reprogram the device employing the user-defined security key. This protects the device from being read back and duplicated. Since programmed data is stored in nonvolatile memory cells (which are actually very small capacitors), rather than in the wiring, physical deconstruction cannot be used to compromise data. This approach is further hampered by the placement of the memory cells beneath the four metal layers (whose removal cannot be accomplished without disturbing the charge in the capacitor). This is the highest security provided in the industry. For more information, refer to Actel's Design Security in Nonvolatile Flash and Antifuse FPGAs white paper. E m bedde d M em or y Flo orp lan The embedded memory is located across the top and bottom of the device in 256x9 blocks (Figure 1 on page 5). Depending upon the device, up to 88 blocks are available to support a variety of memory configurations. Each block can be programmed as an independent memory or combined (using dedicated memory routing resources) to form larger, more complex memories. A single memory configuration cannot include blocks from both the top and bottom memory locations. E m bedde d M em or y Con f igu rat i ons The embedded memory in the ProASICPLUS family provides great configuration flexibility (Table 7 on page 22). Unlike many other programmable vendors each ProASICPLUS block is designed and optimized as a two-port memory (1 read, 1 write). This provides 198kbits of total memory for two-port and single port usage in the APA1000 device. Each memory can be configured as FIFO or SRAM, with independent selection of synchronous or asynchronous read and write ports (Table 8 on page 22). Additional characteristics include programmable flags as well as parity checking and generation. Figure 21 on page 23 and Figure 22 on page 24 show the block diagrams of the basic SRAM and FIFO blocks. Table 9 on page 23 and Table 10 on page 24 describe memory block SRAM and FIFO interface signals, respectively. A single memory is designed to operate v3.0 21 Pr o A S I C P L U S F la s h F a m il y F P GA s Figure 24 on page 25 gives an example of optimal memory usage. Ten blocks with 23,040 bits have been used to generate three memories of various widths and depths. Figure 25 on page 25 shows how memory can be used in parallel to create extra read ports. In this example, using only 10 of the 88 available blocks of the APA1000 yields an effective 6,912 bits of multiple port memories. The Actel ACTgen software facilitates building wider and deeper memories for optimal memory usage. at up to 150 MHz (standard speed grade typical conditions). Each block contains a 256 word, 9-bit wide (1 read port, 1 write port) memory. The memory blocks may be combined in parallel to form wider memories or stacked to form deeper memories (Figure 23 on page 25). This provides optimal bit widths of 9 (1 block), 18, 36, and 72, and optimal depths of 256, 512, 768, and 1,024. Refer to Actel's A Guide to ACTgen Macros for more information. Table 7 * ProASICPLUS Memory Configurations by Device Maximum Width Maximum Depth Device Bottom Top D W D W APA075 0 12 256 108 1,536 9 APA150 0 16 256 144 2,048 9 APA300 16 16 256 144 2,048 9 APA450 24 24 256 216 3,072 9 APA600 28 28 256 252 3,584 9 APA750 32 32 256 288 4,096 9 APA1000 44 44 256 396 5,632 9 Table 8 * Basic Memory Configurations Type Write Access Read Access Parity RAM Asynchronous Asynchronous Checked RAM256x9AA RAM Asynchronous Asynchronous Generated RAM256x9AAP RAM Asynchronous Synchronous Transparent Checked RAM256x9AST RAM Asynchronous Synchronous Transparent Generated RAM256x9ASTP RAM Asynchronous Synchronous Pipelined Checked RAM256x9ASR RAM Asynchronous Synchronous Pipelined Generated RAM256x9ASRP RAM Synchronous Asynchronous Checked RAM256x9SA RAM Synchronous Asynchronous Generated RAM256xSAP RAM Synchronous Synchronous Transparent Checked RAM256x9SST RAM Synchronous Synchronous Transparent Generated RAM256x9SSTP RAM Synchronous Synchronous Pipelined Checked RAM256x9SSR RAM Synchronous Synchronous Pipelined Generated RAM256x9SSRP FIFO Asynchronous Asynchronous Checked FIFO256x9AA FIFO Asynchronous Asynchronous Generated FIFO256x9AAP FIFO Asynchronous Synchronous Transparent Checked FIFO256x9AST FIFO Asynchronous Synchronous Transparent Generated FIFO256x9ASTP FIFO Asynchronous Synchronous Pipelined Checked FIFO256x9ASR FIFO Asynchronous Synchronous Pipelined Generated FIFO256x9ASRP FIFO Synchronous Asynchronous Checked FIFO256x9SA FIFO Synchronous Asynchronous Generated FIFO256x9SAP FIFO Synchronous Synchronous Transparent Checked FIFO256x9SST FIFO Synchronous Synchronous Transparent Generated FIFO256x9SSTP FIFO Synchronous Synchronous Pipelined Checked FIFO256x9SSR FIFO Synchronous Synchronous Pipelined Generated FIFO256x9SSRP 22 v3.0 Library Cell Name Pr o A SI C P L U S F la s h F a m il y F P GA s DI <0:8> WADDR <0:7> WRB WBLKB WCLKS DO <0:8> RADDR <0:7> SRAM (256 X 9) Sync Write & Sync Read Ports RDB RBLKB RCLKS WRB WBLKB PARODD DI <0:8> WADDR <0:7> WRB WBLKB WCLKS Sync Write & Async Read Ports RDB RBLKB RPE SRAM (256 X 9) Async Write & Sync Read Ports DO <0:8> RADDR <0:7> RDB RBLKB RCLKS RPE WPE PARODD Note: DI <0:8> WADDR <0:7> WRB WBLKB RDB RBLKB RPE WPE DO <0:8> RADDR <0:7> PARODD DO <0:8> RADDR <0:7> SRAM (256 X 9) SRAM (256 X 9) Async Write & Async Read Ports WPE RPE WPE DI <0:8> WADDR <0:7> PARODD To save area while using embedded memories, the memory blocks contain multiplexers (called DMUX) for each output signal. These DMUX cells do not consume any core logic tiles and connect directly to high speed routing resources between the memory blocks. They are used when memories are cascaded and are automatically inserted by the software tools. Figure 21 * Example SRAM Block Diagrams Table 9 * Memory Block SRAM Interface Signals SRAM Signal Bits In/Out WCLKS 1 IN RCLKS 1 IN RADDR<0:7> 8 IN RBLKB 1 IN RDB 1 IN WADDR<0:7> 8 IN WBLKB 1 IN DI<0:8> 9 IN WRB 1 IN DO<0:8> 9 OUT RPE 1 OUT WPE 1 OUT PARODD 1 IN Note: Not all signals shown are used in all modes. Description Write clock used on synchronization on write side Read clock used on synchronization on read side Read address Read block select (active LOW) Read pulse (active LOW) Write address Write block select (active LOW) Input data bits <0:8>, <8> can be used for parity in Write pulse (active LOW) Output data bits <0:8>, <8> can be used for parity out Read parity error Write parity error Selects odd parity generation/detect when high, even when low v3.0 23 Pr o A S I C P L U S F la s h F a m il y F P GA s DI<0:8> LEVEL<0:7> LGDEP<0:2> WRB WBLKB DI <0:8> LEVEL <0:7> LGDEP<0:2> WRB WBLKB DO <0:8> FIFO (256 X 9) Sync Write & Sync Read Ports RDB RBLKB WPE RPE FULL EMPTY RDB RBLKB EQTH PARODD FIFO (256 X 9) Sync Write & Async Read Ports RESET GEQTH RESET RDB RBLKB DI <0:8> LEVEL <0:7> LGDEP<0:2> WRB WBLKB DO <0:8> FIFO (256 X 9) Async Write & Sync Read Ports WPE RPE FULL EMPTY RDB EQTH PARODD DO <0:8> FIFO (256 X 9) Async Write & Async Read Ports RBLKB GEQTH RESET WPE RPE FULL EMPTY EQTH GEQTH PARODD RCLKS Note: FULL EMPTY WCLKS RCLKS DI <0:8> LEVEL <0:7> LGDEP<0:2> WRB WBLKB WPE RPE EQTH PARODD GEQTH WCLKS DO <0:8> RESET To save area while using embedded memories, the memory blocks contain multiplexers (called DMUX) for each output signal. These DMUX cells do not consume any core logic tiles and connect directly to high speed routing resources between the memory blocks. They are used when memories are cascaded and are automatically inserted by the software tools. Figure 22 * Basic FIFO Block Diagrams Table 10 * Memory Block FIFO Interface Signals FIFO Signal Bits In/Out Description WCLKS RCLKS LEVEL <0:7> RBLKB RDB RESET WBLKB DI<0:8> WRB FULL, EMPTY 1 1 8 1 1 1 1 9 1 2 IN IN IN IN IN IN IN IN IN OUT EQTH, GEQTH 2 OUT DO<0:8> RPE WPE LGDEP <0:2> PARODD 9 1 1 3 1 OUT OUT OUT IN IN Write clock used for synchronization on write side Read clock used for synchronization on read side Direct configuration implements static flag logic Read block select (active LOW) Read pulse (active LOW) Reset for FIFO pointers (active LOW) Write block select (active LOW) Input data bits <0:8>, <8> will be generated if PARGEN is true Write pulse (active LOW) FIFO flags. FULL prevents write and EMPTY prevents read EQTH is true when the FIFO holds the number of words specified by the LEVEL signal. GEQTH is true when the FIFO holds (LEVEL) words or more Output data bits <0:8> Read parity error Write parity error 24 Configures DEPTH of the FIFO to 2 (LGDEP+1) Parity generation/detect - Even when low, odd when high v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 9 Word Width 9 9 9 9 9 256 256 9 9 256 9 ... 256 256 256 256 256 Word Depth 256 88 blocks Figure 23 * APA1000 Memory Block Architecture Word Width Word Depth 9 9 9 256 256 256 256 256 256 9 9 256 256 256 words x 18 bits, 1 read, 1 write 512 words x 18 bits, 1 read, 1 write 256 256 1,024 words x 9 bits, 1 read, 1 write Total Memory Blocks Used = 10 Total Memory Bits = 23,040 Figure 24 * Example Showing Memories with Different Widths and Depths Word Width 9 Word Depth 99 9 9 9 Write Port 9 9 Write Port 9 256 256 256 256 256 256 Read Ports 256 256 256 256 256 words x 9 bits, 2 read, 1 write Read Ports 512 words x 9 bits, 4 read, 1 write Total Memory Blocks Used = 10 Total Memory Bits = 6,912 Figure 25 * Multiport Memory Usage v3.0 25 Pr o A S I C P L U S F la s h F a m il y F P GA s D es i gn E nv i r on m e nt The ProASICPLUS family of FPGAs is fully supported by both Actel's LiberoTM Integrated Design Environment and Actel's Designer FPGA Development Software. Actel's Designer software provides a comprehensive suite of backend development tools for FPGA development. The Designer software includes timing-driven place and route, a world-class integrated static timing analyzer and constraints editor, a design netlist schematic viewer, and SmartPower, a tool that allows the user to quickly estimate the power consumption in a design. software, Model TechnologyTM ModelSim HDL Simulator, and SynaptiCADTM WaveFormer Lite. ISP The user can generate *.bit or *.stp programming files from the Designer software and can use these files to program a device. ProASICPLUS devices can be programmed in system. For more information on ISP of ProASICPLUS devices, refer to the In-System Programming ProASICPLUS Devices and Performing Internal In-System Programming Using Actel's ProASICPLUS Devices application notes. Prior to being programmed for the first time, the ProASICPLUS device I/Os are inputs with pull-ups. Libero IDE provides an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools (Figure 26). Libero IDE includes Synplicity (R) Synplify for Actel, Mentor GraphicsTM ViewDraw for Actel, Actel's own Designer Libero TM IDE Project Manager Design Creation/Verification ACTgen Macro Builder HDL Editor User Testbench Stimulus Generation Synthesis Synthesis Libraries Functional Simulation Design Synthesis and Optimization Simulator Schematic Entry Timing Simulation Design Implementation Timer Compile SmartPower Static Timing Analyzer and Constraints Editor Optimization and DRC PinEdit Layout NetlistViewer I/O Assignments Timing Driven Place-and-Route Schematic Viewer ChipEdit and ChipViewer Placement Editor Fuse or Bitstream Power Analysis Back-Annotate Cross-Probing System Verification Programming Silicon Sculptor (Antifuse and Flash Families) Actel Device FlashPro (Flash Families) FlashPro Lite (ProASIC PLUS Family) BP Microsystems Programmers Figure 26 * Design Flow 26 v3.0 Silicon Explorer II (Antifuse and Flash Families) Pr o A SI C P L U S F la s h F a m il y F P GA s Pa c ka ge T he r m a l C ha r a ct e r i s t i c s The ProASICPLUS family is available in several package types with a range of pin counts. Actel has selected packages based on high pin count, reliability factors, and superior thermal characteristics. Thermal resistance defines the ability of a package to conduct heat away from the silicon, through the package to the surrounding air. Junction-to-ambient thermal resistance is measured in degrees Celsius/Watt and is represented as Theta ja (ja). The lower the thermal resistance, the more efficiently a package will dissipate heat. thermal resistance ja. Maximum junction temperature is the maximum allowable temperature on the active surface of the IC and is 110 C. P is defined as: TJ - TA P = ---------------- ja ja is a function of the rate (in linear feet per minute - lfpm) of airflow in contact with the package. When the estimated power consumption exceeds the maximum allowed power, other means of cooling, such as increasing the airflow rate, must be used. A package's maximum allowed power (P) is a function of maximum junction temperature (TJ), maximum ambient operating temperature (TA), and junction-to-ambient Pin Count jc ja Still Air ja 300 ft./min. Units Thin Quad Flat Pack (TQFP) 100 12 37.5 30 C/W Thin Quad Flat Pack (TQFP) 144 11 32 24 C/W Plastic Quad Flat Pack (PQFP) 208 8 30 23 C/W PQFP with Heatspreader 208 3.8 20 17 C/W Plastic Ball Grid Array (PBGA) 456 3 15.6 12 C/W Fine Pitch Ball Grid Array (FBGA) 144 3.8 38.8 26.7 C/W Fine Pitch Ball Grid Array (FBGA) Package Type 256 3.8 25 22 C/W Fine Pitch Ball Grid Array (FBGA)1 484 3.2 20 15 C/W Fine Pitch Ball Grid Array (FBGA)2 484 3.2 20.5 16.6 C/W Fine Pitch Ball Grid Array (FBGA) 676 3.2 16.4 11.5 C/W Fine Pitch Ball Grid Array (FBGA) 896 2.4 13.6 10.3 C/W Fine Pitch Ball Grid Array (FBGA) 1152 1.8 12 8.9 C/W Notes: 1. Depopulated Array 2. Full Array v3.0 27 Pr o A S I C P L U S F la s h F a m il y F P GA s C al c ul a t i n g T y pi c al Po w er D i ss i pa t i o n ProASICPLUS device power is calculated with both a static and an active component. The active component is a function of both the number of tiles utilized and the system speed. Power dissipation can be calculated using the following formula: Ptotal = Pdc + Pac where: * Pdc = 12.5 mW (Typically 2.5V x 5mA) Pdc includes the static components of: PVDDP + PVDD + PAVDD * Pac = Pclock + Pstorage + Plogic + Pinputs Pmemory + Ppll + Poutputs + Pclock, the clock component of power dissipation, is given by Pclock = (P1 + P2 * R - P7*R2) * Fs where: * P1 = 100 W/MHz is the basic power consumption of the clock tree per MHz of the clock * P2 = 1.3 W/MHz is the incremental power consumption of the clock tree per storage tile - also per MHz of the clock * P7 = 0.00003 W/MHz is a correction factor for highly loaded clock-trees * R = the number of storage tiles clocked by this clock * Fs = the clock frequency Pstorage, the storage-tile (Register) component of AC power dissipation, is given by Pstorage = P5 * ms * Fs where: * P5 = 1.1 W/MHz is the average power consumption of a storage-tile per MHz of its output toggling rate. The maximum output toggling rate is Fs/2 * ms = the number of storage tiles (Register) switching during each Fs cycle * Fs = the clock frequency Poutputs, the I/O component of AC power dissipation, is given by Poutputs = (P4 + (Cload * VDDP2)) * p * Fp where: * P4 = 326 W/MHz is the intrinsic power consumption of an output pad normalized per MHz of the output frequency. This is the total I/O current VDD + VDDP * Cload = the output load * p = the number of outputs * Fp = the average output frequency The input's component of AC power dissipation is given by Pinputs = P8 * q * Fq where: * P8 = 29 W/MHz is the intrinsic power consumption of an input pad normalized per MHz of the input frequency * q = the number of inputs * Fq = the average input frequency Ppll = P9 * Npll where: * P9 = 6.9 mW. This value has been estimated at maximum PLL clock frequency * NPll = number of PLLs used Finally, Pmemory, the memory component of AC power consumption, is given by Pmemory = P6 * Nmemory * Fmemory * Ememory where: * P6 = 175 W/MHz is the average power consumption of a memory block per MHz of the clock * Nmemory = the number of RAM/FIFO blocks (1 block = 256 words * 9 bits) * Fmemory = the clock frequency of the memory * Ememory = the average number of active blocks divided by the total number of blocks (N) of the memory. * Typical values for Ememory would be 1/4 for a 1k x 8,9,16, 32 memory and 1/16 for a 4kx8, 9, 16, and 32 memory Plogic, the logic-tile component of AC power dissipation, is given by Plogic = P3 * mc * Fs where: * P3 = 1.4 W/MHz, is the average power consumption of a logic tile per MHz of its output toggling rate. The maximum output toggling rate is Fs/2 * mc = the number of logic tiles switching during each Fs cycle * Fs = the clock frequency 28 * In addition, an application-dependent component to Ememory can be considered. For example, for a 1kx8 memory using only 1 cycle out of 3, Ememory = 1/4*1/3 = 1/12 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s The following is an APA750 example using a shift register design with 13,440 storage tiles (Register) and 0 logic tiles. This design has one clock at 10 MHz, and 24 outputs toggling at 5 MHz. We then calculate the various components as follows: Pclock * Fs = 10 MHz * R = 13,440 => Pclock = (P1 + P2 * R - P7*R2) * Fs = 124.2 mW Pstorage * ms = 13,440 (in a shift register 100% of storage-tiles are toggling at each clock cycle and Fs = 10 MHz) => Pstorage = P5 * ms * Fs = 147.8 mW Plogic * mc = 0 (no logic tile in this shift-register) => Plogic = 0 mW Poutputs * * * * Cload VDDP p Fp = = = = 40 pF 3.3 V 24 5 MHz => Poutputs = (P4 + Cload * VDDP2) * p * Fp = 87.3 mW Pinputs * q = 1 * Fq = 10 MHz => Pinputs = P8 * q * Fq = 0.3 mW Pmemory Nmemory = 0 (no RAM/FIFO in this shift-register) => Pmemory = 0 mW Pac => 360 mW Ptotal Pdc + Pac = 372 mW (Typical) v3.0 29 Pr o A S I C P L U S F la s h F a m il y F P GA s O pe r a t i ng C on d i t i on s Standard and -F parts are the same unless otherwise noted. -F parts are only available as commercial. Abs ol ut e M axim u m Ra ti ngs * Parameter Condition Minimum Maximum Units Supply Voltage Core (VDD) -0.3 3.0 V -0.3 4.0 V Supply Voltage I/O Ring (VDDP) DC Input Voltage -0.3 VDDP + 0.3 V PCI DC Input Voltage -1.0 VDDP + 1.0 V PCI DC Input Clamp Current (absolute) VIN < -1 or VIN= VDDP + 1V 10 mA LVPECL Input Voltage -0.3 VDDP + 0.5 V GND 0 0 V Note: * Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions. P rog ra m mi ng , St or age and Oper at in g L i m it s Storage Temperature Product Grade Programming Cycles Program Retention Min. Operating TJ Max Junction Temperature Max. Commercial 100 20 years -55C 110C 110C Industrial 100 20 years -55C 110C 110C Note: This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification is not implied. S uppl y Vol t ages Mode VDD VDDP Single Voltage Mixed Voltage 2.5V 2.5V 2.5V 3.3V Commercial/Industrial Parameter VPP VPN Condition Minimum Maximum Units 15.8 0 -13.8 -13.8 16.5 16.5 -13.2 0 25 10 VDD GND V V V V mA mA V V During Programming Normal Operation1 During Programming Normal Operation2 During Programming During Programming IPP IPN AVDD VDD AGND GND Notes: 1. Please refer to the "VPP Programming Supply Pin" section on page 60 for more information. 2. Please refer to the "VPN Programming Supply Pin" section on page 61 for more information. Rec om m ende d Op era ti ng Con dit io ns Limits Parameter DC Supply Voltage (2.5V I/Os) DC Supply Voltage (Mixed 2.5V, 3.3V I/Os) Operating Ambient Temperature Range Maximum Operating Junction Temperature 30 Symbol Commercial Industrial VDD & VDDP VDDP VDD TA TJ 2.5V 0.2V 3.3V 0.3V 2.5V 0.2V 0C to 70C 110C 2.5V 0.2V 3.3V 0.3V 2.5V 0.2V -40C to 85C 110C v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s DC E le ct ri cal S peci fic at ions ( V D D P = 2. 5V 0 .2V ) 1 Commercial / Industrial1 , 2 Symbol Parameter Conditions Min. Output High Voltage High Drive (OB25LPH) IOH = -6 mA IOH = -12 mA IOH = -24 mA 2.1 2.0 1.7 Low Drive (OB25LPL) IOH = -3 mA IOH = -6 mA IOH = -8 mA 2.1 1.9 1.7 VOH Output Low Voltage High Drive (OB25LPH) VOL Low Drive (OB25LPL) Typ. Max. Units V IOL = 8 mA IOL = 15 mA IOL = 24 mA 0.2 0.4 0.7 IOL = 4 mA IOL = 8 mA IOL = 15 mA 0.2 0.4 0.7 V VIH Input High Voltage 1.7 VDDP + 0.3 V VIL Input Low Voltage -0.3 0.7 V RWEAKPULLUP Weak Pull-up Resistance (OTB25LPU) VIN 1.25V 6 56 k HYST Input Hysteresis Schmitt See Table 4 on page 11 0.3 0.45 V IIN Input Current with pull up (VIN = GND) -240 - 20 A without pull up (VIN = GND or VDD) -10 10 A IDDQ Quiescent Supply Current (standby) Commercial VIN = GND3 or VDD IDDQ Quiescent Supply Current (standby) Industrial VIN = GND3 or VDD IOZ 3-State Output Leakage Current VOH = GND or VDD IOSH Output Short Circuit Current High High Drive (OB25LPH) VIN = VSS VIN = VSS Low Drive (OB25LPL) IOSL Output Short Circuit Current Low High Drive (OB25LPH) VIN = VDDP Low Drive (OB25LPL) VIN = VDDP 100 30 mA CI/O I/O Pad Capacitance 10 pF CCLK Clock Input Pad Capacitance 10 pF 0.35 Std. 5.0 15 mA -F 5.0 25 mA Std. 5.0 20 mA Std. -10 10 A -F4 -10 100 A -120 -100 mA Notes: 1. All process conditions. Junction Temperature: -40 to +110C. 2. -F parts are only available as commercial. 3. No pull-up resistor. 4. This will not exceed 2mA total per device. v3.0 31 Pr o A S I C P L U S F la s h F a m il y F P GA s DC E le ct ri cal S peci fic at ions ( V D D P = 3. 3V 0 .3V an d V D D 2 .5V 0.2 V) 1 Commercial / Industrial1,2 Symbol Parameter Output High Voltage 3.3V I/O, High Drive (OB33P) Conditions Min. IOH = -14 mA IOH = -24 mA 0.9VDDP 2.4 IOH = -6 mA IOH = -12 mA 0.9VDDP 2.4 Typ. Max. Units V 3.3V I/O, Low Drive (OB33L) VOH Output High Voltage IOH = -0.1 mA 2.5V I/O, High Drive (OB25H) IOH = -0.5 mA IOH = -3.0 mA 2.1 2.0 1.7 IOH = -0.1 mA IOH = -0.5 mA IOH = -1.0 mA 2.1 2.0 1.7 V 2.5V I/O, Low Drive (OB25L) Output Low Voltage 3.3V I/O, High Drive (OB33P) IOL = 15 mA IOL = 20 mA IOL = 28 mA 0.1VDDP 0.4 0.7 IOL = 7 mA IOL = 10 mA IOL = 15 mA 0.1VDDP 0.4 0.7 V 3.3V I/O, Low Drive (OB33L) VOL Output Low Voltage IOL = 7 mA 2.5V I/O, High Drive (OB25H) IOL = 14 mA IOL = 28 mA 0.2 0.4 0.7 IOL = 5 mA IOL = 10 mA IOL = 15 mA 0.2 0.4 0.7 V 2.5V I/O, Low Drive (OB25L) Input High Voltage 3.3V LVTTL/LVCMOS 2.5V Mode Input Low Voltage 3.3V LVTTL/LVCMOS VIL 2.5V Mode Weak Pull-up Resistance RWEAKPULLUP (IOB33U) Weak Pull-up Resistance RWEAKPULLUP (IOB25U) VIH IIN IDDQ IDDQ Input Current Quiescent Supply Current (standby) Commercial Quiescent Supply Current (standby) Industrial 2 1.7 VDDP + 0.3 VDDP + 0.3 0.3 0.3 0.8 0.7 V VIN 1.5V 7 43 k VIN 1.5V 7 43 k -300 -10 A A mA with pull up (VIN = GND) without pull up (VIN = GND or VDD) VIN = GND3 or VDD VIN = GND3 or VDD Notes: 1. All process conditions. Junction Temperature: -40 to +110C. 2. -F parts are only available as commercial. 3. No pull-up resistor. 4. This will not exceed 2mA total per device. 32 v3.0 V Std. 5.0 -40 10 15 -F 5.0 25 mA Std. 5.0 20 mA Pr o A SI C P L U S F la s h F a m il y F P GA s DC E le ct ri cal S peci fic at ions ( V D D P = 3. 3V 0 .3V an d V D D 2 .5V 0.2 V) 1 (Con ti nued ) Commercial / Industrial1,2 Symbol Parameter IOZ 3-State Output Leakage Current VOH = GND or VDD IOSH IOSL Conditions Typ. Max. Units Std. -10 10 A 4 -10 100 A -F Output Short Circuit Current High VIN = GND 3.3V High Drive (OB33P) VIN = GND 3.3V Low Drive (OB33L) -200 -100 mA VIN = GND 2.5V High Drive (OB25H) VIN = GND 2.5V Low Drive (OB25L) Output Short Circuit Current Low VIN = VDD 3.3V High Drive VIN = VDD 3.3V Low Drive 2.5V High Drive 2.5V Low Drive CI/O Min. -20 -10 200 100 mA VIN = VDD VIN = VDD 200 100 I/O Pad Capacitance CCLK Clock Input Pad Capacitance Notes: 1. All process conditions. Junction Temperature: -40 to +110C. 2. -F parts are only available as commercial. 3. No pull-up resistor. 4. This will not exceed 2mA total per device. 10 pF 10 pF DC S pec if i cat ion s (3.3 V P C I Op era ti on) 1 Commercial / Industrial2,3 Symbol Parameter VDD Condition Min. Max. Units Supply Voltage for Core 2.3 2.7 V VDDP Supply Voltage for I/O Ring 3.0 3.6 V VIH Input High Voltage 0.5VDDP VDDP + 0.5 V VIL Input Low Voltage -0.5 0.3VDDP V Voltage4 IIPU Input Pull-up 0.7VDDP IIL Input Leakage Current5 0 < VIN < VCCI VOH Output High Voltage IOUT = -500 A VOL Output Low Voltage IOUT = 1500 A CIN Input Pin Capacitance (except CLK) CCLK CLK Pin Capacitance V Std. -10 10 A -F6 -10 100 A 0.9VDDP 5 V 0.1VDDP V 10 pF 12 pF Notes: 1. For PCI operation, use OTB33PH, OB33PH, IOB33PH, IB33, or IB33S macro library cell only. 2. All process conditions. Junction Temperature: -40 to +110C. 3. -F parts are available as commercial only. 4. This specification is guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated network. Designers with applications sensitive to static power utilization should ensure that the input buffer is conducting minimum current at this input voltage. 5. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs. 6. The sum of the leakage currents for all inputs shall not exceed 2mA per device. v3.0 33 Pr o A S I C P L U S F la s h F a m il y F P GA s AC Specifications (3.3V PCI Revision 2.2 Operation) Commercial / Industrial Symbol Parameter Condition Min. 0 < VOUT 0.3VCCI* -12VCCI 0.3VCCI VOUT < Switching Current High 0.9VCCI* Units mA mA (-17.1 + (VDDP - VOUT)) IOH(AC) See equation C - page 124 of the PCI Specification document rev. 2.2 0.7VCCI < VOUT < VCCI* (Test Point) Max. VOUT = 0.7VCC* -32VCCI VCCI > VOUT 0.6VCCI* 16VDDP 0.6VCCI > VOUT > Switching Current Low 0.1VCCI 1 mA mA (26.7VOUT) IOL(AC) mA See equation D - page 124 of the PCI Specification document rev. 2.2 0.18VCCI > VOUT > 0* (Test Point) VOUT = 0.18VCC ICL Low Clamp Current -3 < VIN -1 ICH High Clamp Current VCCI + 4 > VIN VCCI + 1 25 + (VIN - VDDP - 1)/0.015 slewR Output Rise Slew Rate 0.2VCCI to 0.6VCCI load* 1 4 V/ns slewF Output Fall Slew Rate 0.6VCCI to 0.2VCCI load* 1 4 V/ns Note: 38VCCI -25 + (VIN + 1)/0.015 * Refer to the PCI Specification document rev. 2.2. Pad Loading Applicable to the Rising Edge PCI pin 1/2 in. max output buffer 10 pF 1k Pad Loading Applicable to the Falling Edge PCI pin output buffer 34 1k 10 pF v3.0 mA mA mA Pr o A SI C P L U S F la s h F a m il y F P GA s T r i s t a t e B uf f e r D e l a y s EN A PAD OTBx A 50% PAD VOL 50% VOH EN 50% 50% 50% VCC EN 50% 50% PAD 35pF PAD GND 10% VOL tDLH tDHL 50% tENZL 50% VOH 90% 50% tENZH Tr i s t a t e B uf f e r D e l a y s ( W or st -C as e C om m er cia l Cond it ion s, V D D P = 3.0 V, V D D = 2 .3V , 35 p F l oad, T J = 70 C) Max tDLH1 Max tDHL2 Max tENZH3 Max tENZL4 Macro Type Description STD -F STD -F STD -F STD -F Unit s OTB33PH OTB33PN OTB33PL OTB33LH OTB33LN OTB33LL OTB25HH OTB25HN OTB25HL OTB25LH OTB25LN OTB25LL 3.3V, PCI Output Current, High Slew Rate 3.3V, High Output Current, Nominal Slew Rate 3.3V, High Output Current, Low Slew Rate 3.3V, Low Output Current, High Slew Rate 3.3V, Low Output Current, Nominal Slew Rate 3.3V, Low Output Current, Low Slew Rate 2.5V, High Output Current, High Slew Rate 2.5V, High Output Current, Nominal Slew Rate 2.5V, High Output Current, Low Slew Rate 2.5V, Low Output Current, High Slew Rate 2.5V, Low Output Current, Nominal Slew Rate 2.5V, Low Output Current, Low Slew Rate 2.5V, Low Power, High Output Current, High Slew Rate5 2.5V, Low Power, High Output Current, Nominal Slew Rate5 2.5V, Low Power, High Output Current, Low Slew Rate5 2.5V, Low Power, Low Output Current, High Slew Rate5 2.5V, Low Power, Low Output Current, Nominal Slew Rate5 2.5V, Low Power, Low Output Current, Low Slew Rate5 2.0 2.2 2.5 2.6 2.9 3.0 3.1 3.1 3.1 4.6 4.6 4.6 2.4 2.6 3.0 3.1 3.5 3.6 3.8 3.7 3.7 5.6 5.6 5.6 2.2 2.9 3.2 4.0 4.3 5.6 1.8 2.7 3.9 2.9 3.7 5.1 2.6 3.5 3.9 4.8 5.2 6.7 2.2 3.3 4.7 3.5 4.5 6.1 2.2 2.4 2.7 2.8 3.2 3.3 2.8 2.9 2.9 4.6 4.6 4.5 2.6 2.9 3.3 3.4 3.8 3.9 3.4 3.5 3.5 5.5 5.5 5.4 2.0 2.1 2.8 3.0 4.1 5.5 1.7 2.7 3.8 2.9 3.6 4.8 2.4 2.5 3.4 3.6 4.9 6.6 2.0 3.2 4.6 3.4 4.3 5.8 ns ns ns ns ns ns ns ns ns ns ns ns 2.0 2.4 2.1 2.5 2.3 2.7 2.0 2.4 ns 2.4 2.9 3.0 3.6 2.7 3.2 2.1 2.5 ns 2.9 2.7 3.5 3.3 3.2 4.6 3.8 5.5 3.1 3.0 3.8 3.6 2.7 2.6 3.2 3.1 ns ns 3.5 4.2 4.2 5.1 3.8 4.5 3.8 4.6 ns 4.0 4.8 5.3 6.4 4.2 5.1 5.1 6.1 ns OTB25LPHH OTB25LPHN OTB25LPHL OTB25LPLH OTB25LPLN OTB25LPLL Notes: 1. tDLH=Data-to-Pad HIGH 2. tDHL=Data-to-Pad LOW 3. tENZH=Enable-to-Pad, Z to HIGH 4. tENZL = Enable-to-Pad, Z to LOW 5. Low power I/O work with VDDP=2.5V 10% only. VDDP=2.3V for delays. v3.0 35 Pr o A S I C P L U S F la s h F a m il y F P GA s O ut p u t B uf f e r D e l ay s A A PAD 50% VOH 50% PAD VOL 35pF OBx 50% 50% tDLH tDHL O ut p u t B uf f e r D e l ay s ( W or st -C as e C om m er cia l Cond it ion s, V D D P = 3.0 V, V D D = 2 .3V , 35 p F l oad, T J = 70 C) Max tDLH1 Max tDHL2 Macro Type Description STD -F STD -F Units OB33PH 3.3V, PCI Output Current, High Slew Rate 2.0 2.4 2.2 2.6 ns OB33PN 3.3V, High Output Current, Nominal Slew Rate 2.2 2.6 2.9 3.5 ns OB33PL 3.3V, High Output Current, Low Slew Rate 2.5 3.0 3.2 3.9 ns OB33LH 3.3V, Low Output Current, High Slew Rate 2.6 3.1 4.0 4.8 ns OB33LN 3.3V, Low Output Current, Nominal Slew Rate 2.9 3.5 4.3 5.2 ns OB33LL 3.3V, Low Output Current, Low Slew Rate 3.0 3.6 5.6 6.7 ns OB25HH 2.5V, High Output Current, High Slew Rate 3.1 3.8 1.8 2.2 ns OB25HN 2.5V, High Output Current, Nominal Slew Rate 3.1 3.7 2.7 3.3 ns OB25HL 2.5V, High Output Current, Low Slew Rate 3.1 3.7 3.9 4.7 ns OB25LH 2.5V, Low Output Current, High Slew Rate 4.6 5.6 2.9 3.5 ns OB25LN 2.5V, Low Output Current, Nominal Slew Rate 4.6 5.6 3.7 4.5 ns OB25LL 2.5V, Low Output Current, Low Slew Rate 4.6 5.6 5.1 6.1 ns OB25LPHH 2.5V, Low Power, High Output Current, High Slew Rate3 2.0 2.4 2.1 2.6 ns OB25LPHN 2.4 2.9 3.0 3.6 ns 2.5V, Low Power, High Output Current, Low Slew Rate3 2.9 3.5 3.2 3.8 ns OB25LPLH 2.5V, Low Power, Low Output Current, High Slew Rate3 2.7 3.3 4.6 5.5 ns OB25LPLN 2.5V, Low Power, Low Output Current, Nominal Slew Rate3 3.5 4.2 4.2 5.1 ns 4.0 4.8 4.3 6.4 ns OB25LPHL OB25LPLL 2.5V, Low Power, High Output Current, Nominal Slew Rate3 2.5V, Low Power, Low Output Current, Low Slew Rate3 Notes: 1. tDLH = Data-to-Pad HIGH 2. tDHL = Data-to-Pad LOW 3. Low power I/O work with VDDP=2.5V 10% only. VDDP=2.3V for delays. 36 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s I n pu t B uf f er D e l ay s VCC PAD Y PAD Y GND IBx 0V 50% 50% VCC 50% 50% tINYH tINYL I n pu t B uf f er D e l ay s ( W or st -C as e C om m er cia l Cond it ion s, V D D P = 3.0 V, V D D = 2 .3V , T J = 70 C Macro Type Description IB25 2.5V, CMOS Input Levels3, No Pull-up Resistor 3, Max. tINYH1 Max. tINYL2 Std. -F Std. -F Units 0.7 0.9 0.8 1.0 ns No Pull-up Resistor, Schmitt Trigger 0.7 0.9 0.8 1.0 ns 2.5V, CMOS Input Levels3, Low Power 0.9 1.1 0.6 0.8 ns IB25LPS 2.5V, CMOS Input Levels3, Low Power, Schmitt Trigger 0.7 0.9 0.9 1.1 ns IB33 3.3V, CMOS Input Levels3, No Pull-up Resistor 0.4 0.5 0.6 0.7 ns 0.6 0.7 0.8 0.9 ns IB25S IB25LP IB33S 2.5V, CMOS Input Levels 3.3V, CMOS Input Levels3, No Pull-up Resistor, Schmitt Trigger Notes: 1. tINYH = Input Pad-to-Y HIGH 2. tINYL = Input Pad-to-Y LOW 3. LVTTL delays are the same as CMOS delays. 4. For LP Macros, VDDP=2.3V for delays. G l ob al I np ut Bu f f e r D e l ay s ( W or st -C as e C om m er cia l Cond it ion s, V D D P = 3.0 V, V D D = 2 .3V , T J = 70 ) Max. tINYH1 Macro Type Description -F Std. -F No Pull-up Resistor 1.3 1.6 1.0 1.2 ns No Pull-up Resistor, Schmitt Trigger 1.3 1.6 1.0 1.2 ns 2.5V, CMOS Input 2.5V, CMOS Input Levels3, GL25LP 2.5V, CMOS Input Levels3, Low Power GL25LPS 2.5V, CMOS Input Levels3, Low Power, Schmitt Trigger GL25S Units Std. Levels3, GL25 Max. tINYL2 1.1 1.2 1.0 1.3 ns 1.3 1.6 1.0 1.1 ns 3.3V, CMOS Input Levels3, No Pull-up Resistor 1.0 1.2 1.1 1.3 ns GL33S 3.3V, CMOS Input Levels3, No Pull-up Resistor, Schmitt Trigger 1.0 1.2 1.1 1.3 ns PECL PPECL Input Levels 1.0 1.2 1.1 1.3 ns GL33 Notes: 1. tINYH = Input Pad-to-Y HIGH 2. tINYL = Input Pad-to-Y LOW 3. LVTTL delays are the same as CMOS delays. 4. For LP Macros, VDDP=2.3V for delays. v3.0 37 Pr o A S I C P L U S F la s h F a m il y F P GA s Pr ed i ct ed G l ob a l Ro u t i ng D el a y* ( W or st -C as e C om m er cia l Cond it ion s, V D D P = 3.0 V, V D D = 2 .3V , T J = 70 C ) Max. Parameter Description Std. -F Units tRCKH Input Low to High (fully loaded row) 1.1 1.3 ns tRCKL Input High to Low (fully loaded row) 1.0 1.2 ns tRCKH Input Low to High (minimally loaded row) 0.8 1.0 ns 0.8 1.0 ns tRCKL Input High to Low (minimally loaded row) Note: * The timing delay difference between tile locations is less than 15ps. G l ob al R o ut i ng S ke w ( W or st -C as e C om m er cia l Cond it ion s, V D D P = 3.0 V, V D D = 2 .3V , T J = 70 C ) Max. Parameter Description Std. -F Units tRCKSWH tRCKSHH Maximum Skew Low to High Maximum Skew High to Low 270 270 320 320 ps ps 38 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s M od u l e D e l ay s A B C A Y 50% 50% B 50% 50% C 50% 50% Y 50% 50% 50% 50% tDCLH tDBLH tDALH 50% 50% tDCHL tDBHL tDAHL Sa m p l e M a c r oc e l l Li b r a r y L i s t i ng * ( W or st -C as e C om m er cia l Cond it ion s, V D D = 2.3V , T J = 7 0 C) Standard Maximu m -F Cell Name Description NAND2 2-Input NAND 0.5 0.6 ns AND2 2-Input AND 0.4 0.5 ns NOR3 3-Input NOR 0.8 1.0 ns MUX2L 2-1 MUX with Active Low Select 0.5 0.6 ns OA21 2-Input OR into a 2-Input AND 0.8 1.0 ns XOR2 2-Input Exclusive OR 0.6 0.8 ns LH 0.9 1.1 HL 0.8 0.9 Minimum Maximu m Minimum Units Active Low Latch (LH/HL) LDL CLK-Q ns tsetup 0.7 0.8 thold 0.1 0.2 Negative Edge-Triggered D-type Flip-Flop (LH/HL) DFFL Note: CLK-Q LH 0.9 1.1 HL 0.8 1.0 ns tsetup 0.6 0.7 thold 0.0 0.0 *Intrinsic delays have a variable component, coupled to the input slope of the signal. These numbers assume an input slope typical of local interconnect. v3.0 39 Pr o A S I C P L U S F la s h F a m il y F P GA s Recommended Operating Conditions Limits Parameter Symbol Commercial/Industrial Maximum Clock Frequency* fCLOCK 180 MHz Maximum RAM Frequency* fRAM 150 MHz * Schmitt Mode tR/tF 100 ns * Non-schmitt Mode tR/tF 10 ns Maximum Rise/Fall Time on Inputs* Maximum LVPECL Frequency* 180 MHz Maximum tCK Frequency (JTAG) Note: tCK 10 MHz *-F parts will be 20% slower than standard commercial devices. Slew Rates Measured at C = 30pF, Nominal Power Supplies and 25C Trig. Level Rising Edge (nS) Slew Rate (V/ns) Falling Edge (nS) Slew Rate (V/ns) PCI Mode OB33PH 10%-90% 1.60 1.65 1.65 1.60 Yes OB33PN 10%-90% 1.57 1.68 3.32 0.80 No OB33PL 10%-90% 1.57 1.68 1.99 1.32 No OB33LH 10%-90% 3.80 0.70 4.84 0.55 No OB33LN 10%-90% 4.19 0.63 3.37 0.78 No OB33LL 10%-90% 5.49 0.48 2.98 0.89 No OB25HH 20%-60% 3.31 0.30 0.75 1.33 No OB25HN 20%-60% 3.20 0.32 0.77 1.30 No OB25HL 20%-60% 3.27 0.31 0.77 1.30 No OB25LH 20%-60% 8.41 0.12 1.38 0.72 No OB25LN 20%-60% 8.54 0.12 1.15 0.87 No OB25LL 20%-60% 8.50 0.12 1.19 0.84 No OB25LPHH 10%-90% 1.55 1.29 1.56 1.28 No OB25LPHN 10%-90% 1.70 1.18 2.08 0.96 No OB25LPHL 10%-90% 1.97 1.02 2.09 0.96 No OB25LPLH 10%-90% 3.57 0.56 3.93 0.51 No OB25LPLN 10%-90% 4.65 0.43 3.28 0.61 No OB25LPLL 10%-90% 5.52 0.36 3.44 0.58 No Type Note: 40 Standard and -F parts. v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Em b e dd ed M e m or y S pe ci f i ca t i o ns This section discusses ProASICPLUS SRAM/FIFO embedded memory and its interface signals, including timing diagrams that show the relationships of signals as they pertain to single embedded memory blocks (Table 11). Table 8 on page 22 shows basic SRAM and FIFO configurations. Simultaneous Read and Write to the same location must be done with care. On such accesses the DI bus is output to the DO bus. The difference between synchronous transparent and pipeline modes is the timing of all the output signals from the memory. In transparent mode, the outputs will change within the same clock cycle to reflect the data requested by the currently valid access to the memory. If clock cycles are short (high clock speed), the data requires most of the clock cycle to change to valid values (stable signals). Processing of this data in the same clock cycle is nearly impossible. Most designers add registers at all outputs of the memory to push the data processing into the next clock cycle. An entire clock cycle can then be used to process the data. To simplify use of this memory setup, suitable registers have been implemented as part of the memory primitive and are available to the user in the synchronous pipeline mode. In this mode, the output signals will change shortly after the second rising edge, following the initiation of the read access. Enclosed Timing Diagrams--SRAM Mode: * Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent) * Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined) * Asynchronous SRAM Write * Asynchronous SRAM Read, Address Controlled, RDB=0 * Asynchronous SRAM Read, RDB Controlled * Synchronous SRAM Write * Embedded Memory Specifications Table 11 * Memory Block SRAM Interface Signals SRAM Signal Bits In/Out WCLKS 1 IN RCLKS 1 IN RADDR<0:7> 8 IN RBLKB 1 IN RDB 1 IN WADDR<0:7> 8 IN WBLKB 1 IN DI<0:8> 9 IN WRB 1 IN DO<0:8> 9 OUT RPE 1 OUT WPE 1 OUT PARODD 1 IN Note: Not all signals shown are used in all modes. Description Write clock used on synchronization on write side Read clock used on synchronization on read side Read address True read block select (active LOW) True read pulse (active LOW) Write address Write block select (active LOW) Input data bits <0:8>, <8> can be used for parity in Negative true write pulse Output data bits <0:8>, <8> can be used for parity out Read parity error (active HIGH) Write parity error (active HIGH) Selects odd parity generation/detect when high, even when low v3.0 41 Pr o A S I C P L U S F la s h F a m il y F P GA s Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent) RCLKS Cycle Start RBD, RBLKB New Valid Address RADDR Old Data Out DO New Valid Data Out RPE tRACS tRDCS tRDCH tRACH tOCH tRPCH tCMH tCML tOCA tRPCA tCCYC Note: The plot shows the normal operation status. T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx Description Min. CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns OCA New DO access from RCLKS 7.5 ns OCH Old DO valid from RCLKS RACH RADDR hold from RCLKS 0.5 ns RACS RADDR setup to RCLKS 1.0 ns RDCH RDB hold from RCLKS 0.5 ns RDCS RDB setup to RCLKS 1.0 ns RPCA New RPE access from RCLKS 9.5 ns RPCH Note: 42 Max. 3.0 Old RPE valid from RCLKS 3.0 -F speed grade devices are 20% slower than the standard numbers. v3.0 Units ns ns Notes Pr o A SI C P L U S F la s h F a m il y F P GA s Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined) RCLKS Cycle Start RDB, RBLKB RADDR New Valid Address DO New Valid Data Out Old Data Out RPE Old RPE Out New RPE Out tOCA tRACS tRACH tRPCH tRDCH tOCH tRDCS tRPCA tCMH tCML tCCYC Note: The plot shows the normal operation status. T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx Description Min. CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns OCA New DO access from RCLKS 2.0 ns OCH Old DO valid from RCLKS RACH RADDR hold from RCLKS 0.5 ns RACS RADDR setup to RCLKS 1.0 ns RDCH RDB hold from RCLKS 0.5 ns RDCS RDB setup to RCLKS 1.0 ns RPCA New RPE access from RCLKS 4.0 ns RPCH Old RPE valid from RCLKS Note: Max. 0.75 1.0 Units Notes ns ns -F speed grade devices are 20% slower than the standard numbers. v3.0 43 Pr o A S I C P L U S F la s h F a m il y F P GA s Asynchronous SRAM Write WADDR WRB, WBLKB DI WPE tAWRS tAWRH tDWRH tWPDA tWPDH tDWRS tWRML tWRMH tWRCYC Note: The plot shows the normal operation status. T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx Description Min. AWRH WADDR hold from WB 1.0 ns AWRS WADDR setup to WB 0.5 ns DWRH DI hold from WB 1.5 ns DWRS DI setup to WB 0.5 ns PARGEN is inactive DWRS DI setup to WB 2.5 ns PARGEN is active WPDA WPE access from DI 3.0 ns WPE is invalid while WPDH WPE hold from DI ns PARGEN is active WRCYC Cycle time 7.5 ns WRMH WB high phase 3.0 ns Inactive WB low phase 3.0 ns Active WRML Note: 44 Max. 1.0 -F speed grade devices are 20% slower than the standard numbers. v3.0 Units Notes Pr o A SI C P L U S F la s h F a m il y F P GA s Asynchronous SRAM Read, Address Controlled, RDB=0 RADDR DO RPE tOAH tRPAH tOAA tRPAA tACYC The plot shows the normal operation status. Note: T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx Description ACYC Min. Max. Units Read cycle time 7.5 ns OAA New DO access from RADDR stable 7.5 ns OAH Old DO hold from RADDR stable RPAA New RPE access from RADDR stable RPAH Old RPE hold from RADDR stable Note: 3.0 10.0 Notes ns ns 3.0 ns -F speed grade devices are 20% slower than the standard numbers. v3.0 45 Pr o A S I C P L U S F la s h F a m il y F P GA s Asynchronous SRAM Read, RDB Controlled RB=(RDB+RBLKB) DO RPE tORDH tRPRDH tORDA tRPRDA tRDML tRDMH tRDCYC Note: The plot shows the normal operation status. T J = 0 C t o 1 10 C; V D D = 2 .3V t o 2.7V Symbol txxx Description Min. ORDA New DO access from RB 7.5 ORDH Old DO valid from RB RDCYC Read cycle time 7.5 ns RDMH RB high phase 3.0 ns Inactive setup to new cycle RDML RB low phase 3.0 ns Active RPRDA New RPE access from RB 9.5 ns RPRDH Old RPE valid from RB Note: 46 Max. 3.0 v3.0 Notes ns 3.0 -F speed grade devices are 20% slower than the standard numbers. Units ns ns Pr o A SI C P L U S F la s h F a m il y F P GA s Synchronous SRAM Write WCLKS Cycle Start WRB, WBLKB WADDR, DI WPE tWRCH, tWBCH tWRCS, tWBCS tDCS, tWDCS tWPCH tDCH, tWACH tWPCA tCMH tCML tCCYC Note: The plot shows the normal operation status. T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx Description Min. Max. CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns DCH DI hold from WCLKS 0.5 ns DCS DI setup to WCLKS 1.0 ns WACH WADDR hold from WCLKS 0.5 ns WDCS WADDR setup to WCLKS 1.0 ns WPCA New WPE access from WCLKS 3.0 ns WPE is invalid while WPCH Old WPE valid from WCLKS ns PARGEN is active WRCH, WBCH WRB & WBLKB hold from WCLKS 0.5 ns WRCS, WBCS WRB & WBLKB setup to WCLKS 1.0 ns 0.5 Units Notes Notes: 1. On simultaneous read and write accesses to the same location DI is output to DO. 2. -F speed grade devices are 20% slower than the standard numbers. v3.0 47 Pr o A S I C P L U S F la s h F a m il y F P GA s Synchronous Write and Read to the Same Location t CCYC t CMH t CML RCLKS DO New Data* Last Cycle Data WCLKS t WCLKRCLKH t WCLKRCLKS t OCH t OCA * New data is read if WCLKS occurs before setup time. The data stored is read if WCLKS occurs after hold time. Note: The plot shows the normal operation status. T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx Description Min. CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns WCLKRCLKS WCLKS to RCLKS setup time - 0.1 ns WCLKRCLKH WCLKS to RCLKS hold time 7.0 ns OCH Old DO valid from RCLKS 3.0 ns OCA New DO valid from RCLKS 7.5 Max. Units ns Notes OCA/OCH displayed for Access Timed Output Notes: 1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output. 2. During synchronous write and synchronous read access to the same location, the new write data will be read out if the active write clock edge occurs before or at the same time as the active read clock edge. The negative setup time insures this behavior for WCLKS and RCLKS driven by the same design signal. 3. If WCLKS changes after the hold time, the data will be read. 4. A setup or hold time violation will result in unknown output data. 5. -F speed grade devices are 20% slower than the standard numbers. 48 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Asynchronous Write and Synchronous Read to the Same Location t CMH t CML RCLKS New Data* DO Last Cycle Data WB = {WRB + WBLKB} DI t WRCKS t BRCLKH t OCH t OCA t DWRRCLKS t DWRH t CCYC * New data is read if WB occurs before setup time. The stored data is read if WB occurs after hold time. Note: The plot shows the normal operation status. T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx Description Min. Max. Units CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns WBRCLKS WB to RCLKS setup time -0.1 ns WBRCLKH WB to RCLKS hold time 7.0 ns OCH Old DO valid from RCLKS 3.0 ns OCA New DO valid from RCLKS DWRRCLKS DI to RCLKS setup time DWRH DI to WB hold time 7.5 ns 0 ns 1.5 Notes OCA/OCH displayed for Access Timed Output ns Notes: 1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output. 2. In asynchronous write and synchronous read access to the same location, the new write data will be read out if the active write signal edge occurs before or at the same time as the active read clock edge. If WB changes to low after hold time, the data will be read. 3. A setup or hold time violation will result in unknown output data. 4. -F speed grade devices are 20% slower than the standard numbers. v3.0 49 Pr o A S I C P L U S F la s h F a m il y F P GA s Asynchronous Write and Read to the Same Location RB, RADDR DO NEW OLD NEWER WB = {WRB+WBLKB} t ORDA t RAWRH t ORDH t RAWRS t OWRA t OWRH Note: The plot shows the normal operation status. T J = 0 C to 11 0C ; V D D = 2. 3V t o 2 .7V Symbol txxx Description Min. Max. ORDA New DO access from RB ORDH Old DO valid from RB OWRA New DO access from WB OWRH Old DO valid from WB RAWRS RB or RADDR from WB 5.0 ns RAWRH RB or RADDR from WB 5.0 ns 7.5 Units Notes ns 3.0 3.0 ns ns 0.5 ns Notes: 1. During an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically trigger a read operation which updates the read data. 2. Violation or RAWRS will disturb access to the OLD data. 3. Violation of RAWRH will disturb access to the NEWER data. 4. -F speed grade devices are 20% slower than the standard numbers. 50 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Synchronous Write and Asynchronous Read to the Same Location RB, RADDR DO NEW OLD NEWER WCLKS t ORDA t RAWCLKH t ORDH t OWRA t OWRH t RAWCLKS Note: The plot shows the normal operation status. T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx Description Min. Max. ORDA New DO access from RB ORDH Old DO valid from RB OWRA New DO access from WCLKS OWRH Old DO valid from WCLKS RAWCLKS RB or RADDR from WCLKS 5.0 ns RAWCLKH RB or RADDR from WCLKS 5.0 ns 7.5 Units Notes ns 3.0 3.0 ns ns 0.5 ns Notes: 1. During an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically trigger a read operation which updates the read data. 2. Violation of RAWCLKS will disturb access to OLD data. 3. Violation of RAWCLKH will disturb access to NEWER data. 4. -F speed grade devices are 20% slower than the standard numbers. v3.0 51 Pr o A S I C P L U S F la s h F a m il y F P GA s Asynchronous FIFO Full and Empty Transitions The asynchronous FIFO accepts writes and reads while not full or not empty. When the FIFO is full, all writes are inhibited. Conversely, when the FIFO is empty, all reads are inhibited. A problem is created if the FIFO is written during the transition out of full to not full or read during the transition out of empty to not empty. The exact time at which the write or read operation changes from inhibited to accepted after the read (write) signal which causes the transition from full or empty to not full or not empty is indeterminate. This indeterminate period starts 1 ns after the RB (WB) transition, which deactivates full or not empty and ends 3 ns after the RB (WB) transition for slow cycles. For fast cycles, the indeterminate period ends 3 ns (7.5 ns - RDL (WRL)) after the RB (WB) transition, whichever is later (Table 12). The timing diagram for write is shown in Figure 27 on page 53. The timing diagram for read is shown in Figure 28 on page 53. For basic SRAM configurations, see Table 9 on page 23. Enclosed Timing Diagrams - FIFO Mode: * Asynchronous FIFO Read * Asynchronous FIFO Write * Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent) * Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined) * Synchronous FIFO Write * FIFO Reset Table 12 * Memory Block FIFO Interface Signals FIFO Signal Bits In/Out Description WCLKS 1 IN Write clock used for synchronization on write side RCLKS 1 IN Read clock used for synchronization on read side LEVEL <0:7>* 8 IN Direct configuration implements static flag logic RBLKB 1 IN Read block select (active LOW) RDB 1 IN Read pulse (active LOW) RESET 1 IN Reset for FIFO pointers (active LOW) WBLKB 1 IN Write block select (active LOW) DI<0:8> 9 IN Input data bits <0:8>, <8> will be generated if PARGEN is true WRB 1 IN Write pulse (active LOW) FULL, EMPTY 2 OUT FIFO flags. FULL prevents write and EMPTY prevents read EQTH, GEQTH 2 OUT EQTH is true when the FIFO holds the number of words specified by the LEVEL signal. GEQTH is true when the FIFO holds (LEVEL) words or more DO<0:8> 9 OUT Output data bits <0:8> RPE 1 OUT Read parity error (active HIGH) WPE 1 OUT Write parity error (active HIGH) LGDEP <0:2> 3 IN Configures DEPTH of the FIFO to 2 (LGDEP+1) PARODD 1 IN Selects odd parity generation/detect when high, even when low Note: 52 *LEVEL is always eight bits (0000.0000, 0000.0001). That means for values of DEPTH greater than 256, not all values will be possible, e.g. for DEPTH=512, the LEVEL can only have the values 2, 4, . . ., 512. The LEVEL signal circuit will generate signals that indicate whether the FIFO is exactly filled to the value of LEVEL (EQTH) or filled equal or higher (GEQTH) than the specified LEVEL. Since counting starts at 0, EQTH will become true when the FIFO holds (LEVEL+1) words for 512-bit FIFOs. v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s FULL RB Write cycle Write inhibited Write accepted 1 ns 3 ns WB Note: -F speed grade devices are 20% slower than the standard numbers. Figure 27 * Write Timing Diagram EMPTY WB Read cycle Read inhibited Read accepted 1 ns 3 ns RB Note: -F speed grade devices are 20% slower than the standard numbers. Figure 28 * Read Timing Diagram v3.0 53 Pr o A S I C P L U S F la s h F a m il y F P GA s Asynchronous FIFO Read tRDL tRDH Cycle Start RB=(RDB+RBLKB) (Empty inhibits read) RDATA RPE WB EMPTY FULL EQTH, GETH tRDWRS tERDH, tFRDH tORDH tERDA, tFRDA tRPRDH tTHRDH tORDA tTHRDA tRPRDA tRDL Note: tRDH The plot shows the normal operation status. T J = 0C to 110C; V DD = 2.3V to 2.7V Symbol txxx Description ERDH, FRDH, THRDH ERDA FRDA ORDA ORDH RDCYC RDWRS Old EMPTY, FULL, EQTH, & GETH valid hold time from RB New EMPTY access from RB FULL access from RB New DO access from RB Old DO valid from RB Read cycle time WB , clearing EMPTY, setup to Min. Units 0.5 ns 3.0 ns ns ns ns ns ns ns 3.01 3.01 7.5 7.5 3.02 RB RB high phase RB low phase New RPE access from RB Old RPE valid from RB EQTH or GETH access from RB 1.0 RDH 3.0 RDL 3.0 RPRDA 9.5 RPRDH THRDA 4.5 Notes: 1. At fast cycles, ERDA and FRDA = MAX (7.5 ns - RDL), 3.0 ns. 2. At fast cycles, RDWRS (for enabling read) = MAX (7.5 ns - WRL), 3.0 ns. 3. -F speed grade devices are 20% slower than the standard numbers. 54 Max. v3.0 4.0 ns ns ns ns ns Notes Empty/full/thresh are invalid from the end of hold until the new access is complete Enabling the read operation Inhibiting the read operation Inactive Active Pr o A SI C P L U S F la s h F a m il y F P GA s Asynchronous FIFO Write Cycle Start WB=(WRB+WBLKB) WDATA (Full inhibits write) WPE RB FULL EMPTY EQTH, GETH tWRRDS tDWRH tWPDH tWPDA tDWRS tEWRH, tFWRH tEWRA, tFWRA tTHWRH tTHWRA tWRL tWRH tWRCYC Note: The plot shows the normal operation status. T J = 0C to 110C; V DD = 2.3V to 2.7V Symbol txxx Description Min. DWRH DI hold from WB 1.5 DWRS DI setup to WB 0.5 ns PARGEN is inactive DWRS DI setup to WB 2.5 ns PARGEN is active EWRH, FWRH, THWRH Old EMPTY, FULL, EQTH, & GETH valid hold time after WB ns Empty/full/thresh are invalid from the end of hold until the new access is complete EWRA EMPTY access from WB 3.01 ns FWRA New FULL access from WB 3.01 ns THWRA EQTH or GETH access from WB 4.5 ns WPDA WPE access from DI 3.0 ns WPDH WPE hold from DI WRCYC Cycle time 7.5 WRRDS RB , clearing FULL, setup to 3.02 WB high phase Units 1.0 ns 3.0 v3.0 WPE is invalid while PARGEN is active ns ns 1.0 WRL WB low phase 3.0 Notes: 1. At fast cycles, EWRA, FWRA = MAX (7.5 ns - WRL), 3.0 ns. 2. At fast cycles, WRRDS (for enabling write) = MAX (7.5 ns - RDL), 3.0 ns. 3. -F speed grade devices are 20% slower than the standard numbers. Notes ns 0.5 WB WRH Max. Enabling the write operation Inhibiting the write operation ns Inactive ns Active 55 Pr o A S I C P L U S F la s h F a m il y F P GA s Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent) RCLK Cycle Start RDB RDATA Old Data Out New Valid Data Out (Empty Inhibits Read) RPE EMPTY FULL EQTH, GETH tRDCH tECBH, tFCBH tECBA, tFCBA tRDCS tTHCBH tOCH tRPCH tHCBA tOCA tRPCA tCMH tCML tCCYC Note: The plot shows the normal operation status. T J = 0C to 110C; V DD = 2.3V to 2.7V Symbol txxx Description Min. CCYC Cycle time 7.5 CMH Clock high phase 3.0 CML Clock low phase 3.0 ECBA New EMPTY access from RCLKS 3.01 FCBA FULL access from RCLKS 3.01 ECBH, Old EMPTY, FULL, EQTH, & GETH valid FCBH, hold time from RCLKS THCBH OCA New DO access from RCLKS 7.5 OCH Old DO valid from RCLKS RDCH RDB hold from RCLKS 0.5 RDCS RDB setup to RCLKS 1.0 RPCA New RPE access from RCLKS 9.5 RPCH Old RPE valid from RCLKS HCBA EQTH or GETH access from RCLKS 4.5 Notes: 1. At fast cycles, ECBA and FCBA = MAX (7.5 ns - CMH), 3.0 ns. 2. -F speed grade devices are 20% slower than the standard numbers. 56 v3.0 Max. Units Notes ns ns ns ns ns 1.0 3.0 3.0 ns ns ns ns ns ns ns ns Empty/full/thresh are invalid from the end of hold until the new access is complete Pr o A SI C P L U S F la s h F a m il y F P GA s Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined) RCLK Cycle Start RDB RDATA Old Data Out RPE New Valid Data Out Old RPE Out New RPE Out EMPTY FULL EQTH, GETH tECBH, tFCBH tOCA tRDCH tECBA, tFCBA tTHCBH tRDCS tRPCH tOCH tHCBA tRPCA tCMH tCML tCCYC Note: The plot shows the normal operation status. T J = 0C to 110C; V DD = 2.3V to 2.7V Symbol txxx Description Min. CCYC CMH CML ECBA FCBA Cycle time Clock high phase Clock low phase New EMPTY access from RCLKS FULL access from RCLKS 7.5 3.0 3.0 3.01 3.01 ECBH, FCBH, Old EMPTY, FULL, EQTH, & GETH valid THCBH hold time from RCLKS Max. v3.0 Notes ns ns ns ns ns 1.0 OCA New DO access from RCLKS 2.0 OCH Old DO valid from RCLKS RDCH RDB hold from RCLKS 0.5 RDCS RDB setup to RCLKS 1.0 RPCA New RPE access from RCLKS 4.0 RPCH Old RPE valid from RCLKS HCBA EQTH or GETH access from RCLKS 4.5 Notes: 1. At fast cycles, ECBA and FCBA = MAX (7.5 ns - CMS), 3.0 ns. 2. -F speed grade devices are 20% slower than the standard numbers. Units 0.75 1.0 ns Empty/full/thresh are invalid from the end of hold until the new access is complete ns ns ns ns ns ns ns 57 Pr o A S I C P L U S F la s h F a m il y F P GA s Synchronous FIFO Write WCLKS Cycle Start WRB, WBLKB (Full Inhibits Write) DI WPE FULL EMPTY EQTH, GETH tWRCH, tWBCH tECBH, tFCBH tWRCS, tWBCS tECBA, tFCBA tDCS tHCBH tHCBA tWPCH tDCH tWPCA tCMH tCML tCCYC Note: The plot shows the normal operation status. T J = 0C to 110C; V DD = 2.3V to 2.7V Symbol txxx Description Min. CCYC Cycle time 7.5 CMH Clock high phase 3.0 CML Clock low phase 3.0 DCH DI hold from WCLKS 0.5 DCS DI setup to WCLKS 1.0 FCBA New FULL access from WCLKS 3.01 ECBA EMPTY access from WCLKS 3.01 ECBH, Old EMPTY, FULL, EQTH, & GETH valid FCBH, hold time from WCLKS HCBH HCBA EQTH or GETH access from WCLKS 4.5 WPCA New WPE access from WCLKS 3.0 WPCH Old WPE valid from WCLKS WRCH, WRB & WBLKB hold from WCLKS 0.5 WBCH WRCS, WRB & WBLKB setup to WCLKS 1.0 WBCS Notes: 1. At fast cycles, ECBA and FCBA = MAX (7.5 ns - CMH), 3.0 ns. 2. -F speed grade devices are 20% slower than the standard numbers. 58 v3.0 Max. Units 1.0 ns ns ns ns ns ns ns ns 0.5 ns ns ns ns ns Notes Empty/full/thresh are invalid from the end of hold until the new access is complete WPE is invalid while PARGEN is active Pr o A SI C P L U S F la s h F a m il y F P GA s FIFO Reset RESETB Cycle Start WB* WCLKS, RCLKS Cycle Start FULL EMPTY EQTH, GETH tCBRSS tERSA, tFRSA tCBRSH tTHRSA tWBRSH *WB = WRB tRSL + WBLRB tWBRSS Note: *The plot shows the normal operation status. T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx Description CBRSH WCLKS or RCLKS hold from RESETB 1.5 ns Synchronous mode only CBRSS WCLKS or RCLKS setup to RESETB 1.5 ns Synchronous mode only ERSA New EMPTY access from RESETB 3.0 ns FRSA FULL access from RESETB 3.0 ns RSL RESETB low phase 7.5 ns THRSA EQTH or GETH access from RESETB 4.5 ns WBRSH WB hold from RESETB 1.5 ns Asynchronous mode only WBRSS WB setup to RESETB 1.5 ns Asynchronous mode only Note: Min. Max. Units Notes -F speed grade devices are 20% slower than the standard numbers. v3.0 59 Pr o A S I C P L U S F la s h F a m il y F P GA s Pi n D es c r i pt i on U se r P in s I/O TDI User Input/Output The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are compatible with standard LVTTL and LVCMOS specifications. Unused I/O pins are configured as inputs with pull-up resistors. NC No Connect To maintain compatibility with other Actel ProASICPLUS products, it is recommended that this pin not be connected to the circuitry on the board. GL Global Pin Low skew input pin for clock or other global signals. This pin can be configured with an internal pull-up resistor. When it is not connected to the global network or the clock conditioning circuit, it can be configured and used as a normal I/O. GLMX Global Multiplexing Pin Low skew input pin for clock or other global signals. This pin can be used in one of two special ways: (Please see Actel's ProASICPLUS Clock Conditioning Circuits application note for details). 1. When the external feedback option is selected for the PLL block, this pin is routed as the external feedback source to the clock conditioning circuit. 2. In applications where two different signals access the same global net (but at different times) through the use of GLMXx and GLMXLx macros, this pin will be fixed as one of the source pins. This pin can be configured with an internal pull-up resistor. When it is not connected to the global network or the clock conditioning circuit, it can be configured and used as any normal I/O. If not used, a global will be configured as an input with pull-up. Ded ica ted P in s GND Ground Common ground supply voltage. V DD Logic Array Power Supply Pin 2.5V supply voltage. V DDP I/O Pad Power Supply Pin 2.5V or 3.3V supply voltage. TMS Test Mode Select The TMS pin controls the use of boundary-scan circuitry. This pin has an internal pull-up resistor. TCK TDO Test Data Out Serial output for boundary scan. Actel recommends adding a nominal 20k pull-up resistor to this pin. TRST Test Reset Input Asynchronous, active low input pin for resetting boundary-scan circuitry. This pin has an internal pull-up resistor. S pec ial Fu nct ion P in s RCK Running Clock A free running clock is needed during programming if the programmer cannot guarantee that TCK will be uninterrupted. If not used, this pin has an internal pull-up and can be left floating. NPECL User Negative Input Provides high speed clock or data signals to the PLL block. If unused, leave the pin unconnected. PPECL User Positive Input Provides high speed clock or data signals to the PLL block. If unused, leave the pin unconnected. AVDD PLL Power Supply Analog VDD should be VDD (core voltage) 2.5V (nominal) and be decoupled from GND with suitable decoupling capacitors to reduce noise. For more information, refer to Actel's Using ProASICPLUS Clock Conditioning Circuits application note. If the PLLs or clock conditioning circuitry are not used in a design, AVDD should be tied high (2.5V normal). AGND PLL Power Ground Analog GND should be 0V and be decoupled from GND with suitable decoupling capacitors to reduce noise. For more information, refer to Actel's ProASICPLUS Clock Conditioning Circuits application note. If the PLLs or clock conditioning circuitry are not used in a design, AGND should be tied to GND. VPP Programming Supply Pin This pin may be connected to any voltage between GND and 16.5V during normal operation, or it can be left unconnected.2 For information on using this pin during programming, see the Performing Internal In-System Programming Using Actel's ProASICPLUS Devices application note. Actel recommends floating the pin or connecting it to VDDP. Test Clock Clock input pin for boundary scan (maximum 10 MHz). Actel recommends adding a nominal 20k pull-up resistor to this pin. 60 Test Data In Serial input for boundary scan. A dedicated pull-up resistor is included to pull this pin high when not being driven. 2. There is a nominal 40k pull-up resistor on VPP. v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s V PN Programming Supply Pin This pin may be connected to any voltage between GND and -13.8V during normal operation, or it can be left unconnected.3 For information on using this pin during programming, see the Performing Internal In-System Programming Using Actel's ProASICPLUS Devices application note. Actel recommends floating the pin or connecting it to GND. R ec om m e n de d D e si g n Pr a c t i ce f o r V PN / V P P Bypass capacitors are required from VPP to GND and VPN to GND for all ProASICPLUS devices during programming. During the erase cycle, ProASICPLUS devices may have current surges on the VPP and VPN power supplies. The only way to maintain the integrity of the power distribution to the ProASICPLUS device during these current surges is to counteract the inductance of the finite length conductors that distribute the power to the device. This can be accomplished by providing a sufficient amount of bypass capacitance between the VPP and VPN pins and GND (using the shortest paths possible). Without sufficient bypass capacitance to counteract the inductance, the VPP and VPN pins may incur a voltage spike beyond the voltage that the device can withstand. This issue applies to all programming configurations. The power supply voltage limits are defined in the "Supply Voltages" table on page 30. The solution prevents spikes from damaging the ProASICPLUS devices. Bypass capacitors are required for the VPP and VPN pads. Use a 0.01 F to 0.1 F ceramic capacitor with a 25V or greater rating. To filter low-frequency noise (decoupling), use a 4.7 F (low ESR, <1 <, tantalum, 25V or greater rating) capacitor. The capacitors should be located as close to the device pins as possible (within 2.5cm is desirable). The smaller, high-frequency capacitor should be placed closer to the device pins than the larger low-frequency capacitor. The same dual capacitor circuit should be used on both the VPP and VPN pins (Figure 29). 3. There is a nominal 40k pull-down resistor on VPN. 2.5cm + _ V PP 0.1F or 0.01F Actel PLUS ProASIC Device 4.7F + Programming Header or Supplies _ + V PN 0.1F or 0.01F 4.7F + Figure 29 * ProASICPLUS VPP and VPN Capacitor Requirements v3.0 61 Pr o A S I C P L U S F la s h F a m il y F P GA s Pa c ka ge P i n A s si g nm e n t s 100- P in T Q FP 100 1 100-Pin TQFP 62 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 100- P in T Q FP 100- P in T Q FP Pin Number APA075 Function APA150 Function Pin Number APA075 Function APA150 Function 1 GND GND 43 I/O I/O 2 I/O I/O 44 I/O I/O 3 I/O I/O 45 I/O I/O 4 I/O I/O 46 I/O I/O 5 I/O I/O 47 TCK TCK 6 I/O I/O 48 TDI TDI 7 I/O I/O 49 TMS TMS 8 I/O I/O 50 VDDP VDDP 9 GND GND 51 GND GND 10 I/O (GLMX1) I/O (GLMX1) 52 VPP VPP 11 GL1 GL1 53 VPN VPN 12 AGND AGND 54 TDO TDO 13 NPECL1 NPECL1 55 TRST TRST 14 AVDD AVDD 56 RCK RCK 15 PPECL1 (I/P) PPECL1 (I/P) 57 I/O I/O 16 GL2 GL2 58 I/O I/O 17 VDD VDD 59 I/O I/O 18 I/O I/O 60 GL3 GL3 19 I/O I/O 61 PPECL2 (I/P) PPECL2 (I/P) 20 I/O I/O 62 AVDD AVDD 21 I/O I/O 63 NPECL2 NPECL2 22 I/O I/O 64 AGND AGND 23 I/O I/O 65 GL4 GL4 24 I/O I/O 66 I/O (GLMX2) I/O (GLMX2) 25 GND GND 67 GND GND 26 VDDP VDDP 68 VDD VDD 27 I/O I/O 69 I/O I/O 28 I/O I/O 70 I/O I/O 29 I/O I/O 71 I/O I/O 30 I/O I/O 72 I/O I/O 31 I/O I/O 73 I/O I/O 32 I/O I/O 74 I/O I/O 33 I/O I/O 75 GND GND 34 I/O I/O 76 VDDP VDDP 35 I/O I/O 77 I/O I/O 36 I/O I/O 78 I/O I/O 37 VDD VDD 79 I/O I/O 38 GND GND 80 I/O I/O 39 VDDP VDDP 81 I/O I/O 40 GND GND 82 I/O I/O 41 I/O I/O 83 I/O I/O 42 I/O I/O 84 I/O I/O v3.0 63 Pr o A S I C P L U S F la s h F a m il y F P GA s 100- P in T Q FP Pin Number 64 APA075 Function APA150 Function 85 I/O I/O 86 GND GND 87 VDDP VDDP 88 GND GND 89 VDD VDD 90 I/O I/O 91 I/O I/O 92 I/O I/O 93 I/O I/O 94 I/O I/O 95 I/O I/O 96 I/O I/O 97 I/O I/O 98 I/O I/O 99 I/O I/O 100 VDDP VDDP v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Pa c ka ge P i n A s si g nm e n t s 144-Pin TQFP 144 1 144-Pin TQFP v3.0 65 Pr o A S I C P L U S F la s h F a m il y F P GA s 144- P in T Q FP 1 44- Pi n T Q F P 14 4-P i n T Q FP 144- P in T Q FP Pin Number APA075 Function Pin Number APA075 Function Pin Number APA075 Function Pin Number APA075 Function 1 I/O 43 I/O 85 I/O 127 I/O 2 I/O 44 I/O 86 I/O 128 I/O 3 I/O 45 VDD 87 I/O 129 I/O 4 I/O 46 GND 88 I/O (GLMX) 130 I/O 5 I/O 47 VDDP 89 PPECL (I/P) 131 I/O 6 I/O 48 I/O 90 AVDD 132 I/O 7 I/O 49 I/O 91 NPECL 133 I/O 8 I/O 50 I/O 92 AGND 134 VDDP 66 9 VDD 51 I/O 93 GL 135 GND 10 GND 52 I/O 94 GL 136 VDD 11 VDDP 53 I/O 95 I/O 137 I/O 12 I/O 54 I/O 96 I/O 138 I/O 13 I/O 55 I/O 97 I/O 139 I/O 14 I/O 56 I/O 98 VDDP 140 I/O 15 GL 57 I/O 99 GND 141 I/O 16 GL 58 I/O 100 VDD 142 I/O 17 AGND 59 I/O 101 I/O 143 I/O 18 NPECL 60 I/O 102 I/O 144 I/O 19 AVDD 61 I/O 103 I/O 20 PPECL (I/P) 62 VDD 104 I/O 21 I/O (GLMX) 63 GND 105 I/O 22 I/O 64 VDDP 106 I/O 23 I/O 65 I/O 107 I/O 24 I/O 66 I/O 108 I/O 25 I/O 67 I/O 109 I/O 26 I/O 68 I/O 110 I/O 27 GND 69 TCK 111 I/O 28 VDDP 70 TDI 112 I/O 29 I/O 71 TMS 113 I/O 30 I/O 72 NC 114 I/O 31 I/O 73 VPP 115 I/O 32 I/O 74 VPN 116 I/O 33 I/O 75 TDO 117 VDDP 34 I/O 76 TRST 118 GND 35 I/O 77 RCK 119 VDD 36 I/O 78 I/O 120 I/O 37 I/O 79 I/O 121 I/O 38 I/O 80 I/O 122 I/O 39 I/O 81 VDDP 123 I/O 40 I/O 82 GND 124 I/O 41 I/O 83 I/O 125 I/O 42 I/O 84 I/O 126 I/O v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Pa c ka ge P i n A s si g nm e n t s (Continued) 208- P in P Q FP 1 208 208-Pin PQFP v3.0 67 Pr o A S I C P L U S F la s h F a m il y F P GA s 208- P in P Q FP Pin Number APA075 Function APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function 1 GND GND GND GND GND GND GND 2 I/O I/O I/O I/O I/O I/O I/O 3 I/O I/O I/O I/O I/O I/O I/O 4 I/O I/O I/O I/O I/O I/O I/O 5 I/O I/O I/O I/O I/O I/O I/O 6 I/O I/O I/O I/O I/O I/O I/O 7 I/O I/O I/O I/O I/O I/O I/O 8 I/O I/O I/O I/O I/O I/O I/O 9 I/O I/O I/O I/O I/O I/O I/O 10 I/O I/O I/O I/O I/O I/O I/O 11 I/O I/O I/O I/O I/O I/O I/O 12 I/O I/O I/O I/O I/O I/O I/O 13 I/O I/O I/O I/O I/O I/O I/O 14 I/O I/O I/O I/O I/O I/O I/O 15 I/O I/O I/O I/O I/O I/O I/O 16 VDD VDD VDD VDD VDD VDD VDD 17 GND GND GND GND GND GND GND 18 I/O I/O I/O I/O I/O I/O I/O 19 I/O I/O I/O I/O I/O I/O I/O 20 I/O I/O I/O I/O I/O I/O I/O 21 I/O I/O I/O I/O I/O I/O I/O 22 VDDP VDDP VDDP VDDP VDDP VDDP VDDP 23 I/O (GLMX1) I/O (GLMX1) I/O (GLMX1) I/O (GLMX1) I/O (GLMX1) I/O (GLMX1) I/O (GLMX1) 24 GL1 GL1 GL1 GL1 GL1 GL1 GL1 25 AGND AGND AGND AGND AGND AGND AGND 26 NPECL1 NPECL1 NPECL1 NPECL1 NPECL1 NPECL1 NPECL1 27 AVDD AVDD AVDD AVDD AVDD AVDD AVDD 28 68 PPECL1 (I/P) PPECL1 (I/P) PPECL1 (I/P) PPECL1 (I/P) PPECL1 (I/P) PPECL1 (I/P) PPECL1 (I/P) 29 GND GND GND GND GND GND GND 30 GL2 GL2 GL2 GL2 GL2 GL2 GL2 31 I/O I/O I/O I/O I/O I/O I/O 32 I/O I/O I/O I/O I/O I/O I/O 33 I/O I/O I/O I/O I/O I/O I/O 34 I/O I/O I/O I/O I/O I/O I/O 35 I/O I/O I/O I/O I/O I/O I/O 36 VDD VDD VDD VDD VDD VDD VDD 37 I/O I/O I/O I/O I/O I/O I/O 38 I/O I/O I/O I/O I/O I/O I/O 39 I/O I/O I/O I/O I/O I/O I/O 40 VDDP VDDP VDDP VDDP VDDP VDDP VDDP 41 GND GND GND GND GND GND GND 42 I/O I/O I/O I/O I/O I/O I/O v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 208- P in P Q FP (C ont inu ed) Pin Number APA075 Function APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function 43 I/O I/O I/O I/O I/O I/O I/O 44 I/O I/O I/O I/O I/O I/O I/O 45 I/O I/O I/O I/O I/O I/O I/O 46 I/O I/O I/O I/O I/O I/O I/O 47 I/O I/O I/O I/O I/O I/O I/O 48 I/O I/O I/O I/O I/O I/O I/O 49 I/O I/O I/O I/O I/O I/O I/O 50 I/O I/O I/O I/O I/O I/O I/O 51 I/O I/O I/O I/O I/O I/O I/O 52 GND GND GND GND GND GND GND 53 VDDP VDDP VDDP VDDP VDDP VDDP VDDP 54 I/O I/O I/O I/O I/O I/O I/O 55 I/O I/O I/O I/O I/O I/O I/O 56 I/O I/O I/O I/O I/O I/O I/O 57 I/O I/O I/O I/O I/O I/O I/O 58 I/O I/O I/O I/O I/O I/O I/O 59 I/O I/O I/O I/O I/O I/O I/O 60 I/O I/O I/O I/O I/O I/O I/O 61 I/O I/O I/O I/O I/O I/O I/O 62 I/O I/O I/O I/O I/O I/O I/O 63 I/O I/O I/O I/O I/O I/O I/O 64 I/O I/O I/O I/O I/O I/O I/O 65 GND GND GND GND GND GND GND 66 I/O I/O I/O I/O I/O I/O I/O 67 I/O I/O I/O I/O I/O I/O I/O 68 I/O I/O I/O I/O I/O I/O I/O 69 I/O I/O I/O I/O I/O I/O I/O 70 I/O I/O I/O I/O I/O I/O I/O 71 VDD VDD VDD VDD VDD VDD VDD 72 VDDP VDDP VDDP VDDP VDDP VDDP VDDP 73 I/O I/O I/O I/O I/O I/O I/O 74 I/O I/O I/O I/O I/O I/O I/O 75 I/O I/O I/O I/O I/O I/O I/O 76 I/O I/O I/O I/O I/O I/O I/O 77 I/O I/O I/O I/O I/O I/O I/O 78 I/O I/O I/O I/O I/O I/O I/O 79 I/O I/O I/O I/O I/O I/O I/O 80 I/O I/O I/O I/O I/O I/O I/O 81 GND GND GND GND GND GND GND 82 I/O I/O I/O I/O I/O I/O I/O 83 I/O I/O I/O I/O I/O I/O I/O 84 I/O I/O I/O I/O I/O I/O I/O v3.0 69 Pr o A S I C P L U S F la s h F a m il y F P GA s 208- P in P Q FP (C ont inu ed) 70 Pin Number APA075 Function APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function 85 I/O I/O I/O I/O I/O I/O I/O 86 I/O I/O I/O I/O I/O I/O I/O 87 I/O I/O I/O I/O I/O I/O I/O 88 VDD VDD VDD VDD VDD VDD VDD 89 VDDP VDDP VDDP VDDP VDDP VDDP VDDP 90 I/O I/O I/O I/O I/O I/O I/O 91 I/O I/O I/O I/O I/O I/O I/O 92 I/O I/O I/O I/O I/O I/O I/O 93 I/O I/O I/O I/O I/O I/O I/O 94 I/O I/O I/O I/O I/O I/O I/O 95 I/O I/O I/O I/O I/O I/O I/O 96 I/O I/O I/O I/O I/O I/O I/O 97 GND GND GND GND GND GND GND 98 I/O I/O I/O I/O I/O I/O I/O 99 I/O I/O I/O I/O I/O I/O I/O 100 I/O I/O I/O I/O I/O I/O I/O 101 TCK TCK TCK TCK TCK TCK TCK 102 TDI TDI TDI TDI TDI TDI TDI 103 TMS TMS TMS TMS TMS TMS TMS 104 VDDP VDDP VDDP VDDP VDDP VDDP VDDP 105 GND GND GND GND GND GND GND 106 VPP VPP VPP VPP VPP VPP VPP 107 VPN VPN VPN VPN VPN VPN VPN 108 TDO TDO TDO TDO TDO TDO TDO 109 TRST TRST TRST TRST TRST TRST TRST 110 RCK RCK RCK RCK RCK RCK RCK 111 I/O I/O I/O I/O I/O I/O I/O 112 I/O I/O I/O I/O I/O I/O I/O 113 I/O I/O I/O I/O I/O I/O I/O 114 I/O I/O I/O I/O I/O I/O I/O 115 I/O I/O I/O I/O I/O I/O I/O 116 I/O I/O I/O I/O I/O I/O I/O 117 I/O I/O I/O I/O I/O I/O I/O 118 I/O I/O I/O I/O I/O I/O I/O 119 I/O I/O I/O I/O I/O I/O I/O 120 I/O I/O I/O I/O I/O I/O I/O 121 I/O I/O I/O I/O I/O I/O I/O 122 GND GND GND GND GND GND GND 123 VDDP VDDP VDDP VDDP VDDP VDDP VDDP 124 I/O I/O I/O I/O I/O I/O I/O 125 I/O I/O I/O I/O I/O I/O I/O 126 VDD VDD VDD VDD VDD VDD VDD v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 208- P in P Q FP (C ont inu ed) Pin Number APA075 Function APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function 127 I/O I/O I/O I/O I/O I/O I/O 128 GL3 GL3 GL3 GL3 GL3 GL3 GL3 129 130 PPECL2 (I/P) PPECL2 (I/P) PPECL2 (I/P) PPECL2 (I/P) PPECL2 (I/P) PPECL2 (I/P) PPECL2 (I/P) GND GND GND GND GND GND GND 131 AVDD AVDD AVDD AVDD AVDD AVDD AVDD 132 NPECL2 NPECL2 NPECL2 NPECL2 NPECL2 NPECL2 NPECL2 133 AGND AGND AGND AGND AGND AGND AGND 134 GL4 GL4 GL4 GL4 GL4 GL4 GL4 135 I/O (GLMX2) I/O (GLMX2) I/O (GLMX2) I/O (GLMX2) I/O (GLMX2) I/O (GLMX2) I/O (GLMX2) 136 I/O I/O I/O I/O I/O I/O I/O 137 I/O I/O I/O I/O I/O I/O I/O 138 VDDP VDDP VDDP VDDP VDDP VDDP VDDP 139 I/O I/O I/O I/O I/O I/O I/O 140 I/O I/O I/O I/O I/O I/O I/O 141 GND GND GND GND GND GND GND 142 VDD VDD VDD VDD VDD VDD VDD 143 I/O I/O I/O I/O I/O I/O I/O 144 I/O I/O I/O I/O I/O I/O I/O 145 I/O I/O I/O I/O I/O I/O I/O 146 I/O I/O I/O I/O I/O I/O I/O 147 I/O I/O I/O I/O I/O I/O I/O 148 I/O I/O I/O I/O I/O I/O I/O 149 I/O I/O I/O I/O I/O I/O I/O 150 I/O I/O I/O I/O I/O I/O I/O 151 I/O I/O I/O I/O I/O I/O I/O 152 I/O I/O I/O I/O I/O I/O I/O 153 I/O I/O I/O I/O I/O I/O I/O 154 I/O I/O I/O I/O I/O I/O I/O 155 I/O I/O I/O I/O I/O I/O I/O 156 GND GND GND GND GND GND GND 157 VDDP VDDP VDDP VDDP VDDP VDDP VDDP 158 I/O I/O I/O I/O I/O I/O I/O 159 I/O I/O I/O I/O I/O I/O I/O 160 I/O I/O I/O I/O I/O I/O I/O 161 I/O I/O I/O I/O I/O I/O I/O 162 GND GND GND GND GND GND GND 163 I/O I/O I/O I/O I/O I/O I/O 164 I/O I/O I/O I/O I/O I/O I/O 165 I/O I/O I/O I/O I/O I/O I/O 166 I/O I/O I/O I/O I/O I/O I/O 167 I/O I/O I/O I/O I/O I/O I/O 168 I/O I/O I/O I/O I/O I/O I/O v3.0 71 Pr o A S I C P L U S F la s h F a m il y F P GA s 208- P in P Q FP (C ont inu ed) Pin Number 72 APA075 Function APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function 169 I/O I/O I/O I/O I/O I/O I/O 170 VDDP VDDP VDDP VDDP VDDP VDDP VDDP 171 VDD VDD VDD VDD VDD VDD VDD 172 I/O I/O I/O I/O I/O I/O I/O 173 I/O I/O I/O I/O I/O I/O I/O 174 I/O I/O I/O I/O I/O I/O I/O 175 I/O I/O I/O I/O I/O I/O I/O 176 I/O I/O I/O I/O I/O I/O I/O 177 I/O I/O I/O I/O I/O I/O I/O 178 GND GND GND GND GND GND GND 179 I/O I/O I/O I/O I/O I/O I/O 180 I/O I/O I/O I/O I/O I/O I/O 181 I/O I/O I/O I/O I/O I/O I/O 182 I/O I/O I/O I/O I/O I/O I/O 183 I/O I/O I/O I/O I/O I/O I/O 184 I/O I/O I/O I/O I/O I/O I/O 185 I/O I/O I/O I/O I/O I/O I/O 186 VDDP VDDP VDDP VDDP VDDP VDDP VDDP 187 VDD VDD VDD VDD VDD VDD VDD 188 I/O I/O I/O I/O I/O I/O I/O 189 I/O I/O I/O I/O I/O I/O I/O 190 I/O I/O I/O I/O I/O I/O I/O 191 I/O I/O I/O I/O I/O I/O I/O 192 I/O I/O I/O I/O I/O I/O I/O 193 I/O I/O I/O I/O I/O I/O I/O 194 I/O I/O I/O I/O I/O I/O I/O 195 GND GND GND GND GND GND GND 196 I/O I/O I/O I/O I/O I/O I/O 197 I/O I/O I/O I/O I/O I/O I/O 198 I/O I/O I/O I/O I/O I/O I/O 199 I/O I/O I/O I/O I/O I/O I/O 200 I/O I/O I/O I/O I/O I/O I/O 201 I/O I/O I/O I/O I/O I/O I/O 202 I/O I/O I/O I/O I/O I/O I/O 203 I/O I/O I/O I/O I/O I/O I/O 204 I/O I/O I/O I/O I/O I/O I/O 205 I/O I/O I/O I/O I/O I/O I/O 206 I/O I/O I/O I/O I/O I/O I/O 207 I/O I/O I/O I/O I/O I/O I/O 208 VDDP VDDP VDDP VDDP VDDP VDDP VDDP v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Pa c ka ge P i n A s si g nm e n t s (Continued) 456- P in P BGA (B ott om Vi ew) A1 Ball Pad Corner 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF v3.0 73 Pr o A S I C P L U S F la s h F a m il y F P GA s 4 5 6 - P in P BG A 74 Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function A1 VDDP VDDP VDDP VDDP VDDP VDDP A2 VDDP VDDP VDDP VDDP VDDP VDDP A3 NC NC I/O I/O I/O I/O A4 NC NC I/O I/O I/O I/O A5 NC NC I/O I/O I/O I/O A6 NC NC I/O I/O I/O I/O A7 NC NC I/O I/O I/O I/O A8 I/O I/O I/O I/O I/O I/O A9 I/O I/O I/O I/O I/O I/O A10 I/O I/O I/O I/O I/O I/O A11 I/O I/O I/O I/O I/O I/O A12 I/O I/O I/O I/O I/O I/O A13 I/O I/O I/O I/O I/O I/O A14 I/O I/O I/O I/O I/O I/O A15 I/O I/O I/O I/O I/O I/O A16 I/O I/O I/O I/O I/O I/O A17 I/O I/O I/O I/O I/O I/O A18 I/O I/O I/O I/O I/O I/O A19 I/O I/O I/O I/O I/O I/O A20 NC NC I/O I/O I/O I/O A21 NC NC I/O I/O I/O I/O A22 NC NC I/O I/O I/O I/O A23 NC NC I/O I/O I/O I/O A24 NC NC I/O I/O I/O I/O A25 VDDP VDDP VDDP VDDP VDDP VDDP A26 VDDP VDDP VDDP VDDP VDDP VDDP B1 VDDP VDDP VDDP VDDP VDDP VDDP B2 VDDP VDDP VDDP VDDP VDDP VDDP B3 NC NC NC I/O I/O I/O B4 NC NC I/O I/O I/O I/O B5 NC NC I/O I/O I/O I/O B6 NC NC I/O I/O I/O I/O B7 NC NC I/O I/O I/O I/O B8 I/O I/O I/O I/O I/O I/O B9 I/O I/O I/O I/O I/O I/O B10 I/O I/O I/O I/O I/O I/O B11 I/O I/O I/O I/O I/O I/O B12 I/O I/O I/O I/O I/O I/O B13 I/O I/O I/O I/O I/O I/O B14 I/O I/O I/O I/O I/O I/O B15 I/O I/O I/O I/O I/O I/O B16 I/O I/O I/O I/O I/O I/O v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 456- P in P BGA (C ont inu ed) Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function B17 I/O I/O I/O I/O I/O I/O B18 I/O I/O I/O I/O I/O I/O B19 I/O I/O I/O I/O I/O I/O B20 NC NC I/O I/O I/O I/O B21 NC NC I/O I/O I/O I/O B22 NC NC I/O I/O I/O I/O B23 NC NC I/O I/O I/O I/O B24 NC NC I/O I/O I/O I/O B25 VDDP VDDP VDDP VDDP VDDP VDDP B26 VDDP VDDP VDDP VDDP VDDP VDDP C1 VDDP VDDP VDDP VDDP VDDP VDDP C2 NC I/O I/O I/O I/O I/O C3 VDDP VDDP VDDP VDDP VDDP VDDP C4 NC NC NC I/O I/O I/O C5 NC NC I/O I/O I/O I/O C6 NC NC I/O I/O I/O I/O C7 I/O I/O I/O I/O I/O I/O C8 I/O I/O I/O I/O I/O I/O C9 I/O I/O I/O I/O I/O I/O C10 I/O I/O I/O I/O I/O I/O C11 I/O I/O I/O I/O I/O I/O C12 I/O I/O I/O I/O I/O I/O C13 I/O I/O I/O I/O I/O I/O C14 I/O I/O I/O I/O I/O I/O C15 I/O I/O I/O I/O I/O I/O C16 I/O I/O I/O I/O I/O I/O C17 I/O I/O I/O I/O I/O I/O C18 I/O I/O I/O I/O I/O I/O C19 I/O I/O I/O I/O I/O I/O C20 I/O I/O I/O I/O I/O I/O C21 NC NC I/O I/O I/O I/O C22 NC NC I/O I/O I/O I/O C23 NC NC I/O I/O I/O I/O C24 VDDP VDDP VDDP VDDP VDDP VDDP C25 NC NC NC I/O I/O I/O C26 NC NC NC I/O I/O I/O D1 NC NC NC I/O I/O I/O D2 NC NC NC I/O I/O I/O D3 NC I/O I/O I/O I/O I/O D4 VDDP VDDP VDDP VDDP VDDP VDDP D5 NC NC I/O I/O I/O I/O D6 NC NC I/O I/O I/O I/O v3.0 75 Pr o A S I C P L U S F la s h F a m il y F P GA s 456- P in P BGA (C ont inu ed) 76 Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function D7 I/O I/O I/O I/O I/O I/O D8 I/O I/O I/O I/O I/O I/O D9 I/O I/O I/O I/O I/O I/O D10 I/O I/O I/O I/O I/O I/O D11 I/O I/O I/O I/O I/O I/O D12 I/O I/O I/O I/O I/O I/O D13 I/O I/O I/O I/O I/O I/O D14 I/O I/O I/O I/O I/O I/O D15 I/O I/O I/O I/O I/O I/O D16 I/O I/O I/O I/O I/O I/O D17 I/O I/O I/O I/O I/O I/O D18 I/O I/O I/O I/O I/O I/O D19 I/O I/O I/O I/O I/O I/O D20 I/O I/O I/O I/O I/O I/O D21 I/O I/O I/O I/O I/O I/O D22 NC NC I/O I/O I/O I/O D23 VDDP VDDP VDDP VDDP VDDP VDDP D24 NC I/O I/O I/O I/O I/O D25 NC NC NC I/O I/O I/O D26 NC NC NC I/O I/O I/O E1 NC I/O I/O I/O I/O I/O E2 NC I/O I/O I/O I/O I/O E3 NC I/O I/O I/O I/O I/O E4 NC I/O I/O I/O I/O I/O E5 VDD VDD VDD VDD VDD VDD E6 VDD VDD VDD VDD VDD VDD E7 VDD VDD VDD VDD VDD VDD E8 VDD VDD VDD VDD VDD VDD E9 I/O I/O I/O I/O I/O I/O E10 I/O I/O I/O I/O I/O I/O E11 I/O I/O I/O I/O I/O I/O E12 I/O I/O I/O I/O I/O I/O E13 I/O I/O I/O I/O I/O I/O E14 I/O I/O I/O I/O I/O I/O E15 I/O I/O I/O I/O I/O I/O E16 I/O I/O I/O I/O I/O I/O E17 I/O I/O I/O I/O I/O I/O E18 I/O I/O I/O I/O I/O I/O E19 I/O I/O I/O I/O I/O I/O E20 VDD VDD VDD VDD VDD VDD E21 VDD VDD VDD VDD VDD VDD E22 VDD VDD VDD VDD VDD VDD v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 456- P in P BGA (C ont inu ed) Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function E23 NC I/O I/O I/O I/O I/O E24 NC I/O I/O I/O I/O I/O E25 NC I/O I/O I/O I/O I/O E26 NC I/O I/O I/O I/O I/O F1 NC I/O I/O I/O I/O I/O F2 NC I/O I/O I/O I/O I/O F3 NC I/O I/O I/O I/O I/O F4 NC I/O I/O I/O I/O I/O F5 VDD VDD VDD VDD VDD VDD F22 VDD VDD VDD VDD VDD VDD F23 NC I/O I/O I/O I/O I/O F24 NC I/O I/O I/O I/O I/O F25 NC I/O I/O I/O I/O I/O F26 NC I/O I/O I/O I/O I/O G1 I/O I/O I/O I/O I/O I/O G2 I/O I/O I/O I/O I/O I/O G3 NC I/O I/O I/O I/O I/O G4 NC I/O I/O I/O I/O I/O G5 VDD VDD VDD VDD VDD VDD G22 VDD VDD VDD VDD VDD VDD G23 NC I/O I/O I/O I/O I/O G24 NC I/O I/O I/O I/O I/O G25 NC I/O I/O I/O I/O I/O G26 I/O I/O I/O I/O I/O I/O H1 I/O I/O I/O I/O I/O I/O H2 I/O I/O I/O I/O I/O I/O H3 I/O I/O I/O I/O I/O I/O H4 I/O I/O I/O I/O I/O I/O H5 VDD VDD VDD VDD VDD VDD H22 VDD VDD VDD VDD VDD VDD H23 I/O I/O I/O I/O I/O I/O H24 I/O I/O I/O I/O I/O I/O H25 I/O I/O I/O I/O I/O I/O H26 I/O I/O I/O I/O I/O I/O J1 I/O I/O I/O I/O I/O I/O J2 I/O I/O I/O I/O I/O I/O J3 I/O I/O I/O I/O I/O I/O J4 I/O I/O I/O I/O I/O I/O J5 I/O I/O I/O I/O I/O I/O J22 I/O I/O I/O I/O I/O I/O J23 I/O I/O I/O I/O I/O I/O J24 I/O I/O I/O I/O I/O I/O v3.0 77 Pr o A S I C P L U S F la s h F a m il y F P GA s 456- P in P BGA (C ont inu ed) 78 Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function J25 I/O I/O I/O I/O I/O I/O J26 I/O I/O I/O I/O I/O I/O K1 I/O I/O I/O I/O I/O I/O K2 I/O I/O I/O I/O I/O I/O K3 I/O I/O I/O I/O I/O I/O K4 I/O I/O I/O I/O I/O I/O K5 I/O I/O I/O I/O I/O I/O K22 I/O I/O I/O I/O I/O I/O K23 I/O I/O I/O I/O I/O I/O K24 I/O I/O I/O I/O I/O I/O K25 I/O I/O I/O I/O I/O I/O K26 I/O I/O I/O I/O I/O I/O L1 I/O I/O I/O I/O I/O I/O L2 I/O I/O I/O I/O I/O I/O L3 I/O I/O I/O I/O I/O I/O L4 I/O I/O I/O I/O I/O I/O L5 I/O I/O I/O I/O I/O I/O L11 GND GND GND GND GND GND L12 GND GND GND GND GND GND L13 GND GND GND GND GND GND L14 GND GND GND GND GND GND L15 GND GND GND GND GND GND L16 GND GND GND GND GND GND L22 I/O I/O I/O I/O I/O I/O L23 I/O I/O I/O I/O I/O I/O L24 I/O I/O I/O I/O I/O I/O L25 I/O I/O I/O I/O I/O I/O L26 I/O I/O I/O I/O I/O I/O M1 GL1 GL1 GL1 GL1 GL1 GL1 M2 GL2 GL2 GL2 GL2 GL2 GL2 M3 I/O I/O I/O I/O I/O I/O M4 I/O I/O I/O I/O I/O I/O M5 I/O I/O I/O I/O I/O I/O M11 GND GND GND GND GND GND M12 GND GND GND GND GND GND M13 GND GND GND GND GND GND M14 GND GND GND GND GND GND M15 GND GND GND GND GND GND M16 GND GND GND GND GND GND M22 GL4 GL4 GL4 GL4 GL4 GL4 M23 I/O I/O I/O I/O I/O I/O M24 I/O I/O I/O I/O I/O I/O v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 456- P in P BGA (C ont inu ed) Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function M25 I/O I/O I/O I/O I/O I/O M26 I/O I/O I/O I/O I/O I/O N1 I/O I/O I/O I/O I/O I/O N2 I/O (GLMX1) I/O (GLMX)1 I/O (GLMX1) I/O (GLMX1) I/O (GLMX1) I/O (GLMX1) N3 AGND AGND AGND AGND AGND AGND N4 PPECL1 (I/P) PPECL1 (I/P) PPECL1 (I/P) PPECL1 (I/P) PPECL1 (I/P) PPECL1 (I/P) N5 AVDD AVDD AVDD AVDD AVDD AVDD N11 GND GND GND GND GND GND N12 GND GND GND GND GND GND N13 GND GND GND GND GND GND N14 GND GND GND GND GND GND N15 GND GND GND GND GND GND N16 GND GND GND GND GND GND N22 NPECL2 NPECL2 NPECL2 NPECL2 NPECL2 NPECL2 N23 GL3 GL3 GL3 GL3 GL3 GL3 N24 AVDD AVDD AVDD AVDD AVDD AVDD N25 I/O (GLMX2) I/O (GLMX) I/O (GLMX2) I/O (GLMX2) I/O (GLMX2) I/O (GLMX2) N26 AGND AGND AGND AGND AGND AGND P1 I/O I/O I/O I/O I/O I/O P2 I/O I/O I/O I/O I/O I/O P3 I/O I/O I/O I/O I/O I/O P4 I/O I/O I/O I/O I/O I/O P5 NPECL1 NPECL1 NPECL1 NPECL1 NPECL1 NPECL1 P11 GND GND GND GND GND GND P12 GND GND GND GND GND GND P13 GND GND GND GND GND GND P14 GND GND GND GND GND GND P15 GND GND GND GND GND GND P16 GND GND GND GND GND GND P22 I/O I/O I/O I/O I/O I/O P23 I/O I/O I/O I/O I/O I/O P24 I/O I/O I/O I/O I/O I/O P25 I/O I/O I/O I/O I/O I/O P26 PPECL2 (I/P) PPECL2 (I/P) PPECL2 (I/P) PPECL2 (I/P) PPECL2 (I/P) PPECL2 (I/P) R1 I/O I/O I/O I/O I/O I/O R2 I/O I/O I/O I/O I/O I/O R3 I/O I/O I/O I/O I/O I/O R4 I/O I/O I/O I/O I/O I/O R5 I/O I/O I/O I/O I/O I/O R11 GND GND GND GND GND GND R12 GND GND GND GND GND GND R13 GND GND GND GND GND GND v3.0 79 Pr o A S I C P L U S F la s h F a m il y F P GA s 456- P in P BGA (C ont inu ed) 80 Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function R14 GND GND GND GND GND GND R15 GND GND GND GND GND GND R16 GND GND GND GND GND GND R22 I/O I/O I/O I/O I/O I/O R23 I/O I/O I/O I/O I/O I/O R24 I/O I/O I/O I/O I/O I/O R25 I/O I/O I/O I/O I/O I/O R26 I/O I/O I/O I/O I/O I/O T1 I/O I/O I/O I/O I/O I/O T2 I/O I/O I/O I/O I/O I/O T3 I/O I/O I/O I/O I/O I/O T4 I/O I/O I/O I/O I/O I/O T5 I/O I/O I/O I/O I/O I/O T11 GND GND GND GND GND GND T12 GND GND GND GND GND GND T13 GND GND GND GND GND GND T14 GND GND GND GND GND GND T15 GND GND GND GND GND GND T16 GND GND GND GND GND GND T22 I/O I/O I/O I/O I/O I/O T23 I/O I/O I/O I/O I/O I/O T24 I/O I/O I/O I/O I/O I/O T25 I/O I/O I/O I/O I/O I/O T26 I/O I/O I/O I/O I/O I/O U1 I/O I/O I/O I/O I/O I/O U2 I/O I/O I/O I/O I/O I/O U3 I/O I/O I/O I/O I/O I/O U4 I/O I/O I/O I/O I/O I/O U5 I/O I/O I/O I/O I/O I/O U22 I/O I/O I/O I/O I/O I/O U23 I/O I/O I/O I/O I/O I/O U24 I/O I/O I/O I/O I/O I/O U25 I/O I/O I/O I/O I/O I/O U26 I/O I/O I/O I/O I/O I/O V1 I/O I/O I/O I/O I/O I/O V2 I/O I/O I/O I/O I/O I/O V3 I/O I/O I/O I/O I/O I/O V4 I/O I/O I/O I/O I/O I/O V5 I/O I/O I/O I/O I/O I/O V22 I/O I/O I/O I/O I/O I/O V23 I/O I/O I/O I/O I/O I/O V24 I/O I/O I/O I/O I/O I/O v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 456- P in P BGA (C ont inu ed) Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function V25 I/O I/O I/O I/O I/O I/O V26 I/O I/O I/O I/O I/O I/O W1 I/O I/O I/O I/O I/O I/O W2 I/O I/O I/O I/O I/O I/O W3 I/O I/O I/O I/O I/O I/O W4 I/O I/O I/O I/O I/O I/O W5 VDD VDD VDD VDD VDD VDD W22 VDD VDD VDD VDD VDD VDD W23 I/O I/O I/O I/O I/O I/O W24 I/O I/O I/O I/O I/O I/O W25 I/O I/O I/O I/O I/O I/O W26 I/O I/O I/O I/O I/O I/O Y1 I/O I/O I/O I/O I/O I/O Y2 I/O I/O I/O I/O I/O I/O Y3 I/O I/O I/O I/O I/O I/O Y4 NC I/O I/O I/O I/O I/O Y5 VDD VDD VDD VDD VDD VDD Y22 VDD VDD VDD VDD VDD VDD Y23 NC I/O I/O I/O I/O I/O Y24 NC I/O I/O I/O I/O I/O Y25 NC I/O I/O I/O I/O I/O Y26 NC I/O I/O I/O I/O I/O AA1 I/O I/O I/O I/O I/O I/O AA2 NC I/O I/O I/O I/O I/O AA3 NC I/O I/O I/O I/O I/O AA4 NC I/O I/O I/O I/O I/O AA5 VDD VDD VDD VDD VDD VDD AA22 VDD VDD VDD VDD VDD VDD AA23 NC I/O I/O I/O I/O I/O AA24 NC I/O I/O I/O I/O I/O AA25 NC I/O I/O I/O I/O I/O AA26 NC I/O I/O I/O I/O I/O AB1 NC I/O I/O I/O I/O I/O AB2 NC I/O I/O I/O I/O I/O AB3 NC I/O I/O I/O I/O I/O AB4 NC I/O I/O I/O I/O I/O AB5 VDD VDD VDD VDD VDD VDD AB6 VDD VDD VDD VDD VDD VDD AB7 VDD VDD VDD VDD VDD VDD AB8 I/O I/O I/O I/O I/O I/O AB9 I/O I/O I/O I/O I/O I/O AB10 I/O I/O I/O I/O I/O I/O v3.0 81 Pr o A S I C P L U S F la s h F a m il y F P GA s 456- P in P BGA (C ont inu ed) 82 Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function AB11 I/O I/O I/O I/O I/O I/O AB12 I/O I/O I/O I/O I/O I/O AB13 I/O I/O I/O I/O I/O I/O AB14 I/O I/O I/O I/O I/O I/O AB15 I/O I/O I/O I/O I/O I/O AB16 I/O I/O I/O I/O I/O I/O AB17 I/O I/O I/O I/O I/O I/O AB18 I/O I/O I/O I/O I/O I/O AB19 I/O I/O I/O I/O I/O I/O AB20 VDD VDD VDD VDD VDD VDD AB21 VDD VDD VDD VDD VDD VDD AB22 VDD VDD VDD VDD VDD VDD AB23 NC I/O I/O I/O I/O I/O AB24 NC I/O I/O I/O I/O I/O AB25 NC I/O I/O I/O I/O I/O AB26 NC NC NC I/O I/O I/O AC1 NC I/O I/O I/O I/O I/O AC2 NC I/O I/O I/O I/O I/O AC3 NC I/O I/O I/O I/O I/O AC4 VDDP VDDP VDDP VDDP VDDP VDDP AC5 NC NC I/O I/O I/O I/O AC6 I/O I/O I/O I/O I/O I/O AC7 I/O I/O I/O I/O I/O I/O AC8 I/O I/O I/O I/O I/O I/O AC9 I/O I/O I/O I/O I/O I/O AC10 I/O I/O I/O I/O I/O I/O AC11 I/O I/O I/O I/O I/O I/O AC12 I/O I/O I/O I/O I/O I/O AC13 I/O I/O I/O I/O I/O I/O AC14 I/O I/O I/O I/O I/O I/O AC15 I/O I/O I/O I/O I/O I/O AC16 I/O I/O I/O I/O I/O I/O AC17 I/O I/O I/O I/O I/O I/O AC18 I/O I/O I/O I/O I/O I/O AC19 I/O I/O I/O I/O I/O I/O AC20 I/O I/O I/O I/O I/O I/O AC21 TMS TMS TMS TMS TMS TMS AC22 TDO TDO TDO TDO TDO TDO AC23 VDDP VDDP VDDP VDDP VDDP VDDP AC24 RCK RCK RCK RCK RCK RCK AC25 NC NC I/O I/O I/O I/O AC26 NC I/O I/O I/O I/O I/O v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 456- P in P BGA (C ont inu ed) Pin Number APA150 Function APA300 Function APA450 Function AD1 NC NC NC I/O I/O I/O AD2 NC I/O I/O I/O I/O I/O AD3 VDDP VDDP VDDP VDDP VDDP VDDP AD4 NC NC I/O I/O I/O I/O AD5 NC NC I/O I/O I/O I/O AD6 NC NC I/O I/O I/O I/O AD7 I/O I/O I/O I/O I/O I/O AD8 I/O I/O I/O I/O I/O I/O APA600 Function APA750 Function APA1000 Function AD9 I/O I/O I/O I/O I/O I/O AD10 I/O I/O I/O I/O I/O I/O AD11 I/O I/O I/O I/O I/O I/O AD12 I/O I/O I/O I/O I/O I/O AD13 I/O I/O I/O I/O I/O I/O AD14 I/O I/O I/O I/O I/O I/O AD15 I/O I/O I/O I/O I/O I/O AD16 I/O I/O I/O I/O I/O I/O AD17 I/O I/O I/O I/O I/O I/O AD18 I/O I/O I/O I/O I/O I/O AD19 I/O I/O I/O I/O I/O I/O AD20 NC NC I/O I/O I/O I/O AD21 TCK TCK TCK TCK TCK TCK AD22 VPP VPP VPP VPP VPP VPP AD23 NC NC NC I/O I/O I/O AD24 VDDP VDDP VDDP VDDP VDDP VDDP AD25 NC NC I/O I/O I/O I/O AD26 NC NC I/O I/O I/O I/O AE1 VDDP VDDP VDDP VDDP VDDP VDDP AE2 VDDP VDDP VDDP VDDP VDDP VDDP AE3 NC NC I/O I/O I/O I/O AE4 NC NC I/O I/O I/O I/O AE5 NC NC I/O I/O I/O I/O AE6 NC NC I/O I/O I/O I/O AE7 NC NC I/O I/O I/O I/O AE8 I/O I/O I/O I/O I/O I/O AE9 I/O I/O I/O I/O I/O I/O AE10 I/O I/O I/O I/O I/O I/O AE11 I/O I/O I/O I/O I/O I/O AE12 I/O I/O I/O I/O I/O I/O AE13 I/O I/O I/O I/O I/O I/O AE14 I/O I/O I/O I/O I/O I/O AE15 I/O I/O I/O I/O I/O I/O AE16 I/O I/O I/O I/O I/O I/O v3.0 83 Pr o A S I C P L U S F la s h F a m il y F P GA s 456- P in P BGA (C ont inu ed) 84 Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function AE17 I/O I/O I/O I/O I/O I/O AE18 I/O I/O I/O I/O I/O I/O AE19 I/O I/O I/O I/O I/O I/O AE20 NC NC I/O I/O I/O I/O AE21 NC NC I/O I/O I/O I/O AE22 NC NC I/O I/O I/O I/O AE23 VPN VPN VPN VPN VPN VPN AE24 TRST TRST TRST TRST TRST TRST AE25 VDDP VDDP VDDP VDDP VDDP VDDP AE26 VDDP VDDP VDDP VDDP VDDP VDDP AF1 VDDP VDDP VDDP VDDP VDDP VDDP AF2 VDDP VDDP VDDP VDDP VDDP VDDP AF3 NC NC I/O I/O I/O I/O AF4 NC NC I/O I/O I/O I/O AF5 NC NC I/O I/O I/O I/O AF6 NC NC I/O I/O I/O I/O AF7 NC NC I/O I/O I/O I/O AF8 NC NC NC I/O I/O I/O AF9 I/O I/O I/O I/O I/O I/O AF10 I/O I/O I/O I/O I/O I/O AF11 I/O I/O I/O I/O I/O I/O AF12 I/O I/O I/O I/O I/O I/O AF13 I/O I/O I/O I/O I/O I/O AF14 I/O I/O I/O I/O I/O I/O AF15 I/O I/O I/O I/O I/O I/O AF16 I/O I/O I/O I/O I/O I/O AF17 I/O I/O I/O I/O I/O I/O AF18 NC NC I/O I/O I/O I/O AF19 NC NC I/O I/O I/O I/O AF20 NC NC I/O I/O I/O I/O AF21 NC NC I/O I/O I/O I/O AF22 NC NC I/O I/O I/O I/O AF23 TDI TDI TDI TDI TDI TDI AF24 NC NC I/O I/O I/O I/O AF25 VDDP VDDP VDDP VDDP VDDP VDDP AF26 VDDP VDDP VDDP VDDP VDDP VDDP v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Pa c ka ge A ss i gn m e nt s (Continued) 144- FB GA (Bot t om V iew ) A1 Ball Pad Corner 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M v3.0 85 Pr o A S I C P L U S F la s h F a m il y F P GA s 144- FB GA P i n Pin APA075 Number Function 86 14 4-FB GA P in (Co nti nue d) APA150 Function APA300 Function APA450 Function Pin APA075 Number Function APA150 Function APA300 Function APA450 Function A1 I/O I/O I/O I/O D7 I/O I/O I/O I/O A2 I/O I/O I/O I/O D8 I/O I/O I/O I/O A3 I/O I/O I/O I/O D9 I/O I/O I/O I/O A4 I/O I/O I/O I/O D10 I/O I/O I/O I/O D11 I/O I/O I/O I/O D12 I/O (GLMX2) I/O (GLMX2) I/O (GLMX2) I/O (GLMX2) A5 I/O I/O I/O I/O A6 GND GND GND GND A7 I/O I/O I/O I/O A8 VDD VDD VDD VDD E1 VDD VDD VDD VDD A9 I/O I/O I/O I/O E2 I/O I/O I/O I/O I/O I/O I/O I/O A10 I/O I/O I/O I/O E3 A11 I/O I/O I/O I/O E4 VDDP VDDP VDDP VDDP A12 I/O I/O I/O I/O E5 I/O I/O I/O I/O B1 I/O I/O I/O I/O E6 VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP B2 GND GND GND GND E7 B3 I/O I/O I/O I/O E8 AVDD AVDD AVDD AVDD B4 I/O I/O I/O I/O E9 VDDP VDDP VDDP VDDP B5 I/O I/O I/O I/O E10 VDD VDD VDD VDD NPECL2 NPECL2 NPECL2 NPECL2 B6 I/O I/O I/O I/O E11 B7 I/O I/O I/O I/O E12 AGND AGND AGND AGND B8 I/O I/O I/O I/O F1 GL1 GL1 GL1 GL1 B9 I/O I/O I/O I/O F2 AGND AGND AGND AGND F3 I/O (GLMX1) I/O (GLMX1) I/O (GLMX1) I/O (GLMX1) F4 I/O I/O I/O I/O F5 GND GND GND GND F6 GND GND GND GND F7 GND GND GND GND F8 I/O I/O I/O I/O B10 I/O I/O I/O I/O B11 GND GND GND GND B12 I/O I/O I/O I/O C1 I/O I/O I/O I/O C2 GL2 GL2 GL2 GL2 C3 I/O I/O I/O I/O C4 VDD VDD VDD VDD C5 I/O I/O I/O I/O C6 I/O I/O I/O I/O C7 I/O I/O I/O C8 I/O I/O C9 I/O C10 F9 GL4 GL4 GL4 GL4 F10 GND GND GND GND I/O F11 PPECL2 (I/P) PPECL2 (I/P) PPECL2 (I/P) PPECL2 (I/P) I/O I/O F12 GL3 GL3 GL3 GL3 I/O I/O I/O I/O I/O I/O I/O G1 PPECL1 (I/P) PPECL1 (I/P) PPECL1 (I/P) PPECL1 (I/P) C11 I/O I/O I/O I/O G2 GND GND GND GND C12 I/O I/O I/O I/O G3 AVDD AVDD AVDD AVDD NPECL1 NPECL1 NPECL1 NPECL1 D1 I/O I/O I/O I/O G4 D2 I/O I/O I/O I/O G5 GND GND GND GND D3 I/O I/O I/O I/O G6 GND GND GND GND D4 I/O I/O I/O I/O G7 GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O D5 I/O I/O I/O I/O G8 D6 I/O I/O I/O I/O G9 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 144- FB GA Pi n ( Cont i nued) Pin APA075 Number Function 144- FB GA Pi n ( Cont i nued) APA150 Function APA300 Function APA450 Function Pin APA075 Number Function APA150 Function APA300 Function APA450 Function G10 I/O I/O I/O I/O L4 I/O I/O I/O I/O G11 I/O I/O I/O I/O L5 VDDP VDDP VDDP VDDP G12 I/O I/O I/O I/O L6 I/O I/O I/O I/O H1 VDD VDD VDD VDD L7 I/O I/O I/O I/O H2 I/O I/O I/O I/O L8 I/O I/O I/O I/O H3 I/O I/O I/O I/O L9 TMS TMS TMS TMS H4 I/O I/O I/O I/O L10 RCK RCK RCK RCK H5 VDD VDD VDD VDD L11 I/O I/O I/O I/O H6 I/O I/O I/O I/O L12 TRST TRST TRST TRST H7 I/O I/O I/O I/O M1 I/O I/O I/O I/O H8 I/O I/O I/O I/O M2 I/O I/O I/O I/O H9 I/O I/O I/O I/O M3 I/O I/O I/O I/O H10 VDDP VDDP VDDP VDDP M4 I/O I/O I/O I/O H11 I/O I/O I/O I/O M5 I/O I/O I/O I/O H12 VDD VDD VDD VDD M6 I/O I/O I/O I/O J1 I/O I/O I/O I/O M7 I/O I/O I/O I/O J2 I/O I/O I/O I/O M8 I/O I/O I/O I/O J3 VDDP VDDP VDDP VDDP M9 TDI TDI TDI TDI J4 I/O I/O I/O I/O M10 VDDP VDDP VDDP VDDP J5 I/O I/O I/O I/O M11 VPP VPP VPP VPP M12 VPN VPN VPN VPN J6 I/O I/O I/O I/O J7 VDD VDD VDD VDD J8 TCK TCK TCK TCK J9 I/O I/O I/O I/O J10 TDO TDO TDO TDO J11 I/O I/O I/O I/O J12 I/O I/O I/O I/O K1 I/O I/O I/O I/O K2 I/O I/O I/O I/O K3 I/O I/O I/O I/O K4 I/O I/O I/O I/O K5 I/O I/O I/O I/O K6 I/O I/O I/O I/O K7 GND GND GND GND K8 I/O I/O I/O I/O K9 I/O I/O I/O I/O K10 GND GND GND GND K11 I/O I/O I/O I/O K12 I/O I/O I/O I/O L1 GND GND GND GND L2 I/O I/O I/O I/O L3 I/O I/O I/O I/O v3.0 87 Pr o A S I C P L U S F la s h F a m il y F P GA s Pa c ka ge A ss i gn m e nt s (Continued) 256- FB GA ( Bot t om V iew ) A1 Ball Pad Corner 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T 88 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 256- P in FBG A Pin Number APA150 Function APA300 Function APA450 Function APA600 Function A1 GND GND GND GND A2 I/O I/O I/O I/O A3 I/O I/O I/O I/O A4 I/O I/O I/O I/O A5 I/O I/O I/O I/O A6 I/O I/O I/O I/O A7 I/O I/O I/O I/O A8 I/O I/O I/O I/O A9 I/O I/O I/O I/O A10 I/O I/O I/O I/O A11 I/O I/O I/O I/O A12 I/O I/O I/O I/O A13 I/O I/O I/O I/O A14 I/O I/O I/O I/O A15 I/O I/O I/O I/O A16 GND GND GND GND B1 I/O I/O I/O I/O B2 I/O I/O I/O I/O B3 I/O I/O I/O I/O B4 I/O I/O I/O I/O B5 I/O I/O I/O I/O B6 I/O I/O I/O I/O B7 I/O I/O I/O I/O B8 I/O I/O I/O I/O B9 I/O I/O I/O I/O B10 I/O I/O I/O I/O B11 I/O I/O I/O I/O B12 I/O I/O I/O I/O B13 I/O I/O I/O I/O B14 I/O I/O I/O I/O B15 I/O I/O I/O I/O B16 I/O I/O I/O I/O C1 I/O I/O I/O I/O C2 I/O I/O I/O I/O C3 I/O I/O I/O I/O C4 I/O I/O I/O I/O C5 I/O I/O I/O I/O C6 I/O I/O I/O I/O C7 I/O I/O I/O I/O C8 I/O I/O I/O I/O C9 I/O I/O I/O I/O C10 I/O I/O I/O I/O C11 I/O I/O I/O I/O C12 I/O I/O I/O I/O C13 I/O I/O I/O I/O v3.0 89 Pr o A S I C P L U S F la s h F a m il y F P GA s 256- P in FBG A ( Cont i nued) 90 Pin Number APA150 Function APA300 Function APA450 Function APA600 Function C14 I/O I/O I/O I/O C15 I/O I/O I/O I/O C16 I/O I/O I/O I/O D1 I/O I/O I/O I/O D2 I/O I/O I/O I/O D3 I/O I/O I/O I/O D4 I/O I/O I/O I/O D5 I/O I/O I/O I/O D6 I/O I/O I/O I/O D7 I/O I/O I/O I/O D8 I/O I/O I/O I/O D9 I/O I/O I/O I/O D10 I/O I/O I/O I/O D11 I/O I/O I/O I/O D12 I/O I/O I/O I/O D13 I/O I/O I/O I/O D14 I/O I/O I/O I/O D15 I/O I/O I/O I/O D16 I/O I/O I/O I/O E1 I/O I/O I/O I/O E2 I/O I/O I/O I/O E3 I/O I/O I/O I/O E4 I/O I/O I/O I/O E5 I/O I/O I/O I/O E6 VDDP VDDP VDDP VDDP E7 VDDP VDDP VDDP VDDP E8 I/O I/O I/O I/O E9 I/O I/O I/O I/O E10 VDDP VDDP VDDP VDDP E11 VDDP VDDP VDDP VDDP E12 I/O I/O I/O I/O E13 I/O I/O I/O I/O E14 I/O I/O I/O I/O E15 I/O I/O I/O I/O E16 I/O I/O I/O I/O F1 I/O I/O I/O I/O F2 I/O I/O I/O I/O F3 I/O I/O I/O I/O F4 I/O I/O I/O I/O F5 VDDP VDDP VDDP VDDP F6 GND GND GND GND F7 VDD VDD VDD VDD F8 VDD VDD VDD VDD F9 VDD VDD VDD VDD F10 VDD VDD VDD VDD v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 256- P in FBG A ( Cont i nued) Pin Number APA150 Function APA300 Function APA450 Function APA600 Function F11 GND GND GND GND F12 VDDP VDDP VDDP VDDP F13 I/O I/O I/O I/O F14 I/O I/O I/O I/O F15 I/O I/O I/O I/O F16 I/O I/O I/O I/O G1 I/O I/O I/O I/O G2 I/O I/O I/O I/O G3 I/O I/O I/O I/O G4 I/O I/O I/O I/O G5 VDDP VDDP VDDP VDDP G6 VDD VDD VDD VDD G7 GND GND GND GND G8 GND GND GND GND G9 GND GND GND GND G10 GND GND GND GND G11 VDD VDD VDD VDD G12 VDDP VDDP VDDP VDDP G13 I/O I/O I/O I/O G14 I/O I/O I/O I/O G15 I/O I/O I/O I/O G16 I/O I/O I/O I/O H1 GL1 GL1 GL1 GL1 H2 NPECL1 NPECL1 NPECL1 NPECL1 H3 I/O (GLMX1) I/O (GLMX1) I/O (GLMX1) I/O (GLMX1) H4 AGND AGND AGND AGND H5 I/O I/O I/O I/O H6 VDD VDD VDD VDD H7 GND GND GND GND H8 GND GND GND GND H9 GND GND GND GND H10 GND GND GND GND H11 VDD VDD VDD VDD H12 I/O I/O I/O I/O H13 I/O (GLMX2) I/O (GLMX2) I/O (GLMX2) I/O (GLMX2) H14 NPECL2 NPECL2 NPECL2 NPECL2 H15 AGND AGND AGND AGND H16 GL4 GL4 GL4 GL4 J1 GL2 GL2 GL2 GL2 J2 PPECL1 (I/P) PPECL1 (I/P) PPECL1 (I/P) PPECL1 (I/P) J3 AVDD AVDD AVDD AVDD J4 I/O I/O I/O I/O J5 I/O I/O I/O I/O J6 VDD VDD VDD VDD J7 GND GND GND GND v3.0 91 Pr o A S I C P L U S F la s h F a m il y F P GA s 256- P in FBG A ( Cont i nued) 92 Pin Number APA150 Function APA300 Function APA450 Function APA600 Function J8 GND GND GND GND J9 GND GND GND GND J10 GND GND GND GND J11 VDD VDD VDD VDD J12 I/O I/O I/O I/O J13 PPECL2 (I/P) PPECL2 (I/P) PPECL2 (I/P) PPECL2 (I/P) J14 I/O I/O I/O I/O J15 AVDD AVDD AVDD AVDD J16 GL3 GL3 GL3 GL3 K1 I/O I/O I/O I/O K2 I/O I/O I/O I/O K3 I/O I/O I/O I/O K4 I/O I/O I/O I/O K5 VDDP VDDP VDDP VDDP K6 VDD VDD VDD VDD K7 GND GND GND GND K8 GND GND GND GND K9 GND GND GND GND K10 GND GND GND GND K11 VDD VDD VDD VDD K12 VDDP VDDP VDDP VDDP K13 I/O I/O I/O I/O K14 I/O I/O I/O I/O K15 I/O I/O I/O I/O K16 I/O I/O I/O I/O L1 I/O I/O I/O I/O L2 I/O I/O I/O I/O L3 I/O I/O I/O I/O L4 I/O I/O I/O I/O L5 VDDP VDDP VDDP VDDP L6 GND GND GND GND L7 VDD VDD VDD VDD L8 VDD VDD VDD VDD L9 VDD VDD VDD VDD L10 VDD VDD VDD VDD L11 GND GND GND GND L12 VDDP VDDP VDDP VDDP L13 I/O I/O I/O I/O L14 I/O I/O I/O I/O L15 I/O I/O I/O I/O L16 I/O I/O I/O I/O M1 I/O I/O I/O I/O M2 I/O I/O I/O I/O M3 I/O I/O I/O I/O M4 I/O I/O I/O I/O v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 256- P in FBG A ( Cont i nued) Pin Number APA150 Function APA300 Function APA450 Function APA600 Function M5 I/O I/O I/O I/O M6 VDDP VDDP VDDP VDDP M7 VDDP VDDP VDDP VDDP M8 I/O I/O I/O I/O M9 I/O I/O I/O I/O M10 VDDP VDDP VDDP VDDP M11 VDDP VDDP VDDP VDDP M12 I/O I/O I/O I/O M13 I/O I/O I/O I/O M14 I/O I/O I/O I/O M15 I/O I/O I/O I/O M16 I/O I/O I/O I/O N1 I/O I/O I/O I/O N2 I/O I/O I/O I/O N3 I/O I/O I/O I/O N4 I/O I/O I/O I/O N5 I/O I/O I/O I/O N6 I/O I/O I/O I/O N7 I/O I/O I/O I/O N8 I/O I/O I/O I/O N9 I/O I/O I/O I/O N10 I/O I/O I/O I/O N11 I/O I/O I/O I/O N12 I/O I/O I/O I/O N13 I/O I/O I/O I/O N14 RCK RCK RCK RCK N15 I/O I/O I/O I/O N16 I/O I/O I/O I/O P1 I/O I/O I/O I/O P2 I/O I/O I/O I/O P3 I/O I/O I/O I/O P4 I/O I/O I/O I/O P5 I/O I/O I/O I/O P6 I/O I/O I/O I/O P7 I/O I/O I/O I/O P8 I/O I/O I/O I/O P9 I/O I/O I/O I/O P10 I/O I/O I/O I/O P11 I/O I/O I/O I/O P12 I/O I/O I/O I/O P13 TCK TCK TCK TCK P14 VPP VPP VPP VPP P15 TRST TRST TRST TRST P16 I/O I/O I/O I/O R1 I/O I/O I/O I/O v3.0 93 Pr o A S I C P L U S F la s h F a m il y F P GA s 256- P in FBG A ( Cont i nued) 94 Pin Number APA150 Function APA300 Function APA450 Function APA600 Function R2 I/O I/O I/O I/O R3 I/O I/O I/O I/O R4 I/O I/O I/O I/O R5 I/O I/O I/O I/O R6 I/O I/O I/O I/O R7 I/O I/O I/O I/O R8 I/O I/O I/O I/O R9 I/O I/O I/O I/O R10 I/O I/O I/O I/O R11 I/O I/O I/O I/O R12 I/O I/O I/O I/O R13 I/O I/O I/O I/O R14 TDI TDI TDI TDI R15 VPN VPN VPN VPN R16 TDO TDO TDO TDO T1 GND GND GND GND T2 I/O I/O I/O I/O T3 I/O I/O I/O I/O T4 I/O I/O I/O I/O T5 I/O I/O I/O I/O T6 I/O I/O I/O I/O T7 I/O I/O I/O I/O T8 I/O I/O I/O I/O T9 I/O I/O I/O I/O T10 I/O I/O I/O I/O T11 I/O I/O I/O I/O T12 I/O I/O I/O I/O T13 I/O I/O I/O I/O T14 I/O I/O I/O I/O T15 TMS TMS TMS TMS T16 GND GND GND GND v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Pa c ka ge A ss i gn m e nt s (Continued) 484-Pin FBGA (Bottom View) A1 Ball Pad Corner 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB v3.0 95 Pr o A S I C P L U S F la s h F a m il y F P GA s 484- P in FBG A 96 48 4-P i n FB GA (Co nti nue d) Pin Number APA450 Function APA600 Function Pin Number APA450 Function APA600 Function A1 GND GND B21 VDDP VDDP A2 GND GND B22 GND GND A3 VDDP VDDP C1 VDDP VDDP A4 I/O I/O C2 NC I/O A5 I/O I/O C3 I/O I/O A6 I/O I/O C4 I/O I/O A7 I/O I/O C5 GND GND A8 I/O I/O C6 I/O I/O A9 I/O I/O C7 I/O I/O A10 I/O I/O C8 VDD VDD A11 I/O I/O C9 VDD VDD A12 I/O I/O C10 I/O I/O A13 I/O I/O C11 I/O I/O A14 I/O I/O C12 NC I/O A15 I/O I/O C13 NC I/O A16 I/O I/O C14 VDD VDD A17 I/O I/O C15 VDD VDD A18 I/O I/O C16 NC I/O A19 I/O I/O C17 I/O I/O A20 VDDP VDDP C18 GND GND A21 GND GND C19 I/O I/O A22 GND GND C20 I/O I/O B1 GND GND C21 I/O I/O B2 VDDP VDDP C22 VDDP VDDP B3 I/O I/O D1 I/O I/O B4 I/O I/O D2 I/O I/O B5 I/O I/O D3 NC I/O B6 I/O I/O D4 GND GND B7 I/O I/O D5 I/O I/O B8 I/O I/O D6 I/O I/O B9 I/O I/O D7 I/O I/O B10 I/O I/O D8 I/O I/O B11 I/O I/O D9 I/O I/O B12 I/O I/O D10 I/O I/O B13 I/O I/O D11 I/O I/O B14 I/O I/O D12 I/O I/O B15 I/O I/O D13 I/O I/O B16 I/O I/O D14 I/O I/O B17 I/O I/O D15 I/O I/O B18 I/O I/O D16 I/O I/O B19 I/O I/O D17 I/O I/O B20 I/O I/O D18 I/O I/O v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 484- P in FBG A ( Cont i nued) 484- P in FB GA ( Cont i nued) Pin Number APA450 Function APA600 Function Pin Number APA450 Function APA600 Function D19 GND GND F17 I/O I/O D20 I/O I/O F18 I/O I/O D21 I/O I/O F19 I/O I/O D22 I/O I/O F20 I/O I/O E1 I/O I/O F21 I/O I/O E2 NC I/O F22 NC I/O E3 GND GND G1 I/O I/O E4 I/O I/O G2 I/O I/O E5 I/O I/O G3 NC I/O E6 I/O I/O G4 I/O I/O E7 I/O I/O G5 I/O I/O E8 I/O I/O G6 I/O I/O E9 I/O I/O G7 I/O I/O E10 I/O I/O G8 I/O I/O E11 I/O I/O G9 I/O I/O E12 I/O I/O G10 I/O I/O E13 I/O I/O G11 I/O I/O E14 I/O I/O G12 I/O I/O E15 I/O I/O G13 I/O I/O E16 I/O I/O G14 I/O I/O E17 I/O I/O G15 I/O I/O E18 I/O I/O G16 I/O I/O E19 I/O I/O G17 I/O I/O E20 GND GND G18 I/O I/O E21 I/O I/O G19 I/O I/O E22 I/O I/O G20 I/O I/O F1 I/O I/O G21 I/O I/O F2 I/O I/O G22 I/O I/O F3 I/O I/O H1 I/O I/O F4 I/O I/O H2 I/O I/O F5 I/O I/O H3 VDD VDD F6 I/O I/O H4 I/O I/O F7 I/O I/O H5 I/O I/O F8 I/O I/O H6 I/O I/O F9 I/O I/O H7 I/O I/O F10 I/O I/O H8 I/O I/O F11 I/O I/O H9 VDDP VDDP F12 I/O I/O H10 VDDP VDDP F13 I/O I/O H11 I/O I/O F14 I/O I/O H12 I/O I/O F15 I/O I/O H13 VDDP VDDP F16 I/O I/O H14 VDDP VDDP v3.0 97 Pr o A S I C P L U S F la s h F a m il y F P GA s 484- P in FBG A ( Cont i nued) 98 48 4-P i n FB GA (Co nti nue d) Pin Number APA450 Function APA600 Function Pin Number APA450 Function APA600 Function H15 I/O I/O K13 GND GND H16 I/O I/O K14 VDD VDD H17 I/O I/O K15 VDDP VDDP H18 I/O I/O K16 I/O I/O H19 I/O I/O K17 I/O I/O H20 VDD VDD K18 I/O I/O H21 I/O I/O K19 I/O I/O H22 I/O I/O K20 I/O I/O J1 I/O I/O K21 I/O I/O J2 I/O I/O K22 I/O I/O J3 NC I/O L1 NC I/O J4 I/O I/O L2 I/O I/O J5 I/O I/O L3 I/O I/O J6 I/O I/O L4 GL1 GL1 J7 I/O I/O L5 NPECL1 NPECL1 J8 VDDP VDDP L6 I/O (GLMX1) I/O (GLMX1) J9 GND GND L7 AGND AGND J10 VDD VDD L8 I/O I/O J11 VDD VDD L9 VDD VDD J12 VDD VDD L10 GND GND J13 VDD VDD L11 GND GND J14 GND GND L12 GND GND J15 VDDP VDDP L13 GND GND J16 I/O I/O L14 VDD VDD J17 I/O I/O L15 I/O I/O J18 I/O I/O L16 I/O (GLMX2) I/O (GLMX2) J19 I/O I/O L17 NPECL2 NPECL2 J20 NC I/O L18 AGND AGND J21 I/O I/O L19 GL4 GL4 J22 I/O I/O L20 I/O I/O K1 I/O I/O L21 I/O I/O K2 I/O I/O L22 I/O I/O K3 NC I/O M1 I/O I/O K4 I/O I/O M2 I/O I/O K5 I/O I/O M3 I/O I/O K6 I/O I/O M4 GL2 GL2 K7 I/O I/O M5 PPECL1 (I/P) PPECL1 (I/P) K8 VDDP VDDP M6 AVDD AVDD K9 VDD VDD M7 I/O I/O K10 GND GND M8 I/O I/O K11 GND GND M9 VDD VDD K12 GND GND M10 GND GND v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 484- P in FBG A ( Cont i nued) 484- P in FB GA ( Cont i nued) Pin Number APA450 Function APA600 Function Pin Number APA450 Function APA600 Function M11 GND GND P9 GND GND M12 GND GND P10 VDD VDD M13 GND GND P11 VDD VDD M14 VDD VDD P12 VDD VDD M15 I/O I/O P13 VDD VDD M16 PPECL2 (I/P) PPECL2 (I/P) P14 GND GND M17 I/O I/O P15 VDDP VDDP M18 AVDD AVDD P16 I/O I/O M19 GL3 GL3 P17 I/O I/O M20 I/O I/O P18 I/O I/O M21 I/O I/O P19 I/O I/O M22 I/O I/O P20 NC I/O N1 I/O I/O P21 I/O I/O N2 I/O I/O P22 I/O I/O N3 NC I/O R1 I/O I/O N4 I/O I/O R2 I/O I/O N5 I/O I/O R3 VDD VDD N6 I/O I/O R4 I/O I/O N7 I/O I/O R5 I/O I/O N8 VDDP VDDP R6 I/O I/O N9 VDD VDD R7 I/O I/O N10 GND GND R8 I/O I/O N11 GND GND R9 VDDP VDDP N12 GND GND R10 VDDP VDDP N13 GND GND R11 I/O I/O N14 VDD VDD R12 I/O I/O N15 VDDP VDDP R13 VDDP VDDP N16 I/O I/O R14 VDDP VDDP N17 I/O I/O R15 I/O I/O N18 I/O I/O R16 I/O I/O N19 I/O I/O R17 I/O I/O N20 NC I/O R18 I/O I/O N21 I/O I/O R19 I/O I/O N22 I/O I/O R20 VDD VDD P1 I/O I/O R21 I/O I/O P2 I/O I/O R22 I/O I/O P3 I/O I/O T1 I/O I/O P4 I/O I/O T2 I/O I/O P5 I/O I/O T3 NC I/O P6 I/O I/O T4 I/O I/O P7 I/O I/O T5 I/O I/O P8 VDDP VDDP T6 I/O I/O v3.0 99 Pr o A S I C P L U S F la s h F a m il y F P GA s 484- P in FBG A ( Cont i nued) 100 48 4-P i n FB GA (Co nti nue d) Pin Number APA450 Function APA600 Function Pin Number APA450 Function APA600 Function T7 I/O I/O V5 I/O I/O T8 I/O I/O V6 I/O I/O T9 I/O I/O V7 I/O I/O T10 I/O I/O V8 I/O I/O T11 I/O I/O V9 I/O I/O T12 I/O I/O V10 I/O I/O T13 I/O I/O V11 I/O I/O T14 I/O I/O V12 I/O I/O T15 I/O I/O V13 I/O I/O T16 I/O I/O V14 I/O I/O T17 RCK RCK V15 I/O I/O T18 I/O I/O V16 I/O I/O T19 I/O I/O V17 TDI TDI T20 NC I/O V18 VPN VPN T21 I/O I/O V19 TDO TDO T22 I/O I/O V20 GND GND U1 I/O I/O V21 NC I/O U2 I/O I/O V22 I/O I/O U3 I/O I/O W1 NC I/O U4 I/O I/O W2 I/O I/O U5 I/O I/O W3 I/O I/O U6 I/O I/O W4 GND GND U7 I/O I/O W5 I/O I/O U8 I/O I/O W6 I/O I/O U9 I/O I/O W7 I/O I/O U10 I/O I/O W8 I/O I/O U11 I/O I/O W9 I/O I/O U12 I/O I/O W10 I/O I/O U13 I/O I/O W11 I/O I/O U14 I/O I/O W12 I/O I/O U15 I/O I/O W13 I/O I/O U16 TCK TCK W14 I/O I/O U17 VPP VPP W15 I/O I/O U18 TRST TRST W16 I/O I/O U19 I/O I/O W17 I/O I/O U20 NC I/O W18 TMS TMS U21 I/O I/O W19 GND GND U22 I/O I/O W20 NC I/O V1 I/O I/O W21 NC I/O V2 I/O I/O W22 I/O I/O V3 GND GND Y1 VDDP VDDP V4 I/O I/O Y2 I/O I/O v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 484- P in FBG A ( Cont i nued) 484- P in FB GA ( Cont i nued) Pin Number APA450 Function APA600 Function Pin Number APA450 Function APA600 Function Y3 I/O I/O AB1 GND GND Y4 I/O I/O AB2 GND GND Y5 GND GND AB3 VDDP VDDP Y6 I/O I/O AB4 I/O I/O Y7 I/O I/O AB5 I/O I/O Y8 VDD VDD AB6 I/O I/O Y9 VDD VDD AB7 I/O I/O Y10 I/O I/O AB8 I/O I/O Y11 I/O I/O AB9 I/O I/O Y12 I/O I/O AB10 I/O I/O Y13 I/O I/O AB11 I/O I/O Y14 VDD VDD AB12 I/O I/O Y15 VDD VDD AB13 I/O I/O Y16 I/O I/O AB14 I/O I/O Y17 I/O I/O AB15 I/O I/O Y18 GND GND AB16 I/O I/O Y19 I/O I/O AB17 I/O I/O Y20 I/O I/O AB18 NC I/O Y21 NC I/O AB19 I/O I/O Y22 VDDP VDDP AB20 VDDP VDDP AA1 GND GND AB21 GND GND AA2 VDDP VDDP AB22 GND GND AA3 I/O I/O AA4 I/O I/O AA5 I/O I/O AA6 I/O I/O AA7 I/O I/O AA8 I/O I/O AA9 I/O I/O AA10 I/O I/O AA11 I/O I/O AA12 I/O I/O AA13 I/O I/O AA14 I/O I/O AA15 I/O I/O AA16 I/O I/O AA17 I/O I/O AA18 NC I/O AA19 NC I/O AA20 I/O I/O AA21 VDDP VDDP AA22 GND GND v3.0 101 Pr o A S I C P L U S F la s h F a m il y F P GA s Pa c ka ge P i n A s si g nm e n t s (Continued) 676- P in FBG A ( Bot t om V iew ) A1 Ball Pad Corner 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 102 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 676- FB GA Pi n 676- FB GA Pi n ( Cont i nued) Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function A1 GND GND B18 I/O I/O A2 GND GND B19 I/O I/O A3 I/O I/O B20 I/O I/O A4 I/O I/O B21 I/O I/O A5 I/O I/O B22 I/O I/O A6 I/O I/O B23 I/O I/O A7 I/O I/O B24 I/O I/O A8 I/O I/O B25 GND GND A9 I/O I/O B26 GND GND A10 I/O I/O C1 GND GND A11 I/O I/O C2 GND GND A12 I/O I/O C3 GND GND A13 I/O I/O C4 GND GND A14 I/O I/O C5 I/O I/O A15 I/O I/O C6 I/O I/O A16 I/O I/O C7 I/O I/O A17 I/O I/O C8 I/O I/O A18 I/O I/O C9 I/O I/O A19 I/O I/O C10 I/O I/O A20 I/O I/O C11 I/O I/O A21 I/O I/O C12 I/O I/O A22 I/O I/O C13 I/O I/O A23 I/O I/O C14 I/O I/O A24 I/O I/O C15 I/O I/O A25 GND GND C16 I/O I/O A26 GND GND C17 I/O I/O B1 GND GND C18 I/O I/O B2 GND GND C19 I/O I/O B3 GND GND C20 I/O I/O B4 GND GND C21 I/O I/O B5 I/O I/O C22 I/O I/O B6 I/O I/O C23 I/O I/O B7 I/O I/O C24 I/O I/O B8 I/O I/O C25 I/O I/O B9 I/O I/O C26 I/O I/O B10 I/O I/O D1 I/O I/O B11 I/O I/O D2 I/O I/O B12 I/O I/O D3 GND GND B13 I/O I/O D4 I/O I/O B14 I/O I/O D5 I/O I/O B15 I/O I/O D6 I/O I/O B16 I/O I/O D7 I/O I/O B17 I/O I/O D8 I/O I/O v3.0 103 Pr o A S I C P L U S F la s h F a m il y F P GA s 676- FB GA P i n ( Cont i nued) 104 67 6-FB GA P in (Co nti nue d) Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function D9 I/O I/O E26 I/O I/O D10 I/O I/O F1 I/O I/O D11 I/O I/O F2 I/O I/O D12 I/O I/O F3 I/O I/O D13 I/O I/O F4 I/O I/O D14 I/O I/O F5 GND GND D15 I/O I/O F6 I/O I/O D16 I/O I/O F7 NC NC D17 I/O I/O F8 I/O I/O D18 I/O I/O F9 I/O I/O D19 I/O I/O F10 I/O I/O D20 I/O I/O F11 I/O I/O D21 I/O I/O F12 I/O I/O D22 I/O I/O F13 I/O I/O D23 I/O I/O F14 I/O I/O D24 I/O I/O F15 I/O I/O D25 I/O I/O F16 I/O I/O D26 I/O I/O F17 I/O I/O E1 I/O I/O F18 I/O I/O E2 I/O I/O F19 I/O I/O E3 I/O I/O F20 I/O I/O E4 I/O I/O F21 I/O I/O E5 I/O I/O F22 I/O I/O E6 I/O I/O F23 I/O I/O E7 I/O I/O F24 I/O I/O E8 I/O I/O F25 I/O I/O E9 I/O I/O F26 I/O I/O E10 I/O I/O G1 I/O I/O E11 I/O I/O G2 I/O I/O E12 I/O I/O G3 I/O I/O E13 I/O I/O G4 I/O I/O E14 I/O I/O G5 I/O I/O E15 I/O I/O G6 I/O I/O E16 I/O I/O G7 I/O I/O E17 I/O I/O G8 VDD VDD E18 I/O I/O G9 NC NC E19 I/O I/O G10 I/O I/O E20 I/O I/O G11 NC NC E21 I/O I/O G12 I/O I/O E22 I/O I/O G13 NC NC E23 I/O I/O G14 I/O I/O E24 I/O I/O G15 NC NC E25 I/O I/O G16 I/O I/O v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 676- FB GA Pi n ( Cont i nued) 676- FB GA Pi n ( Cont i nued) Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function G17 NC NC J8 VDDP VDDP G18 I/O I/O J9 VDD VDD G19 VDDP VDDP J10 VDD VDD G20 NC NC J11 VDD VDD G21 I/O I/O J12 VDD VDD G22 I/O I/O J13 VDD VDD G23 I/O I/O J14 VDD VDD G24 I/O I/O J15 VDD VDD G25 I/O I/O J16 VDD VDD G26 I/O I/O J17 VDD VDD H1 I/O I/O J18 VDD VDD H2 I/O I/O J19 VDDP VDDP H3 I/O I/O J20 NC NC H4 I/O I/O J21 I/O I/O H5 I/O I/O J22 I/O I/O H6 I/O I/O J23 I/O I/O H7 VDDP VDDP J24 I/O I/O H8 VDD VDD J25 I/O I/O H9 VDDP VDDP J26 I/O I/O H10 VDDP VDDP K1 I/O I/O H11 VDDP VDDP K2 I/O I/O H12 VDDP VDDP K3 I/O I/O H13 VDDP VDDP K4 I/O I/O H14 VDDP VDDP K5 I/O I/O H15 VDDP VDDP K6 I/O I/O H16 VDDP VDDP K7 I/O I/O H17 VDDP VDDP K8 VDDP VDDP H18 VDDP VDDP K9 VDD VDD H19 VDD VDD K10 GND GND H20 VDD VDD K11 GND GND H21 I/O I/O K12 GND GND H22 I/O I/O K13 GND GND H23 I/O I/O K14 GND GND H24 I/O I/O K15 GND GND H25 I/O I/O K16 GND GND H26 I/O I/O K17 GND GND J1 I/O I/O K18 VDD VDD J2 I/O I/O K19 VDDP VDDP J3 I/O I/O K20 I/O I/O J4 I/O I/O K21 I/O I/O J5 I/O I/O K22 I/O I/O J6 I/O I/O K23 I/O I/O J7 NC NC K24 I/O I/O v3.0 105 Pr o A S I C P L U S F la s h F a m il y F P GA s 676- FB GA P i n ( Cont i nued) 106 67 6-FB GA P in (Co nti nue d) Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function K25 I/O I/O M16 GND GND K26 I/O I/O M17 GND GND L1 I/O I/O M18 VDD VDD L2 I/O I/O M19 VDDP VDDP L3 I/O I/O M20 I/O I/O L4 I/O I/O M21 I/O I/O L5 I/O I/O M22 I/O I/O L6 I/O I/O M23 I/O I/O L7 NC NC M24 I/O I/O L8 VDDP VDDP M25 I/O I/O L9 VDD VDD M26 I/O I/O L10 GND GND N1 GL1 GL1 L11 GND GND N2 AGND AGND L12 GND GND N3 I/O (GLMX1) I/O (GLMX1) L13 GND GND N4 I/O I/O L14 GND GND N5 NPECL1 NPECL1 L15 GND GND N6 I/O I/O L16 GND GND N7 NC NC L17 GND GND N8 VDDP VDDP L18 VDD VDD N9 VDD VDD L19 VDDP VDDP N10 GND GND L20 NC NC N11 GND GND L21 I/O I/O N12 GND GND L22 I/O I/O N13 GND GND L23 I/O I/O N14 GND GND L24 I/O I/O N15 GND GND L25 I/O I/O N16 GND GND L26 I/O I/O N17 GND GND M1 I/O I/O N18 VDD VDD M2 I/O I/O N19 VDDP VDDP M3 I/O I/O N20 NC NC M4 I/O I/O N21 I/O I/O M5 I/O I/O N22 GL3 GL3 M6 I/O I/O N23 I/O I/O M7 I/O I/O N24 NPECL2 NPECL2 M8 VDDP VDDP N25 GL4 GL4 M9 VDD VDD N26 I/O I/O M10 GND GND P1 GL2 GL2 M11 GND GND P2 AVDD AVDD M12 GND GND P3 I/O I/O M13 GND GND P4 I/O I/O M14 GND GND P5 PPECL1 (I/P) PPECL1 (I/P) M15 GND GND P6 I/O I/O v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 676- FB GA Pi n ( Cont i nued) 676- FB GA Pi n ( Cont i nued) Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function P7 I/O I/O R24 I/O I/O P8 VDDP VDDP R25 I/O I/O P9 VDD VDD R26 I/O I/O P10 GND GND T1 I/O I/O P11 GND GND T2 I/O I/O P12 GND GND T3 I/O I/O P13 GND GND T4 I/O I/O P14 GND GND T5 I/O I/O P15 GND GND T6 I/O I/O P16 GND GND T7 I/O I/O P17 GND GND T8 VDDP VDDP P18 VDD VDD T9 VDD VDD P19 VDDP VDDP T10 GND GND P20 I/O I/O T11 GND GND P21 I/O I/O T12 GND GND P22 I/O (GLMX2) I/O (GLMX2) T13 GND GND P23 I/O I/O T14 GND GND P24 PPECL2 (I/P) PPECL2 (I/P) T15 GND GND P25 AVDD AVDD T16 GND GND P26 AGND AGND T17 GND GND R1 I/O I/O T18 VDD VDD R2 I/O I/O T19 VDDP VDDP R3 I/O I/O T20 I/O I/O R4 I/O I/O T21 I/O I/O R5 I/O I/O T22 I/O I/O R6 I/O I/O T23 I/O I/O R7 NC NC T24 I/O I/O R8 VDDP VDDP T25 I/O I/O R9 VDD VDD T26 I/O I/O R10 GND GND U1 I/O I/O R11 GND GND U2 I/O I/O R12 GND GND U3 I/O I/O R13 GND GND U4 I/O I/O R14 GND GND U5 I/O I/O R15 GND GND U6 I/O I/O R16 GND GND U7 NC NC R17 GND GND U8 VDDP VDDP R18 VDD VDD U9 VDD VDD R19 VDDP VDDP U10 GND GND R20 NC NC U11 GND GND R21 I/O I/O U12 GND GND R22 I/O I/O U13 GND GND R23 I/O I/O U14 GND GND v3.0 107 Pr o A S I C P L U S F la s h F a m il y F P GA s 676- FB GA P i n ( Cont i nued) 108 67 6-FB GA P in (Co nti nue d) Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function U15 GND GND W6 I/O I/O U16 GND GND W7 VDD VDD U17 GND GND W8 VDD VDD U18 VDD VDD W9 VDDP VDDP U19 VDDP VDDP W10 VDDP VDDP U20 NC NC W11 VDDP VDDP U21 I/O I/O W12 VDDP VDDP U22 I/O I/O W13 VDDP VDDP U23 I/O I/O W14 VDDP VDDP U24 I/O I/O W15 VDDP VDDP U25 I/O I/O W16 VDDP VDDP U26 I/O I/O W17 VDDP VDDP V1 I/O I/O W18 VDDP VDDP V2 I/O I/O W19 VDD VDD V3 I/O I/O W20 VDDP VDDP V4 I/O I/O W21 I/O I/O V5 I/O I/O W22 I/O I/O V6 I/O I/O W23 I/O I/O V7 I/O I/O W24 I/O I/O V8 VDDP VDDP W25 I/O I/O V9 VDD VDD W26 I/O I/O V10 VDD VDD Y1 I/O I/O V11 VDD VDD Y2 I/O I/O V12 VDD VDD Y3 I/O I/O V13 VDD VDD Y4 I/O I/O V14 VDD VDD Y5 I/O I/O V15 VDD VDD Y6 I/O I/O V16 VDD VDD Y7 I/O I/O V17 VDD VDD Y8 VDDP VDDP V18 VDD VDD Y9 NC NC V19 VDDP VDDP Y10 I/O I/O V20 I/O I/O Y11 NC NC V21 I/O I/O Y12 I/O I/O V22 I/O I/O Y13 NC NC V23 I/O I/O Y14 I/O I/O V24 I/O I/O Y15 NC NC V25 I/O I/O Y16 I/O I/O V26 I/O I/O Y17 NC NC W1 I/O I/O Y18 I/O I/O W2 I/O I/O Y19 VDD VDD W3 I/O I/O Y20 VPP VPP W4 I/O I/O Y21 I/O I/O W5 I/O I/O Y22 I/O I/O v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 676- FB GA Pi n ( Cont i nued) 676- FB GA Pi n ( Cont i nued) Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function Y23 I/O I/O AB14 I/O I/O Y24 I/O I/O AB15 I/O I/O Y25 I/O I/O AB16 I/O I/O Y26 I/O I/O AB17 I/O I/O AA1 I/O I/O AB18 I/O I/O AA2 I/O I/O AB19 I/O I/O AA3 I/O I/O AB20 I/O I/O AA4 I/O I/O AB21 TCK TCK AA5 I/O I/O AB22 TRST TRST AA6 GND GND AB23 I/O I/O AA7 I/O I/O AB24 I/O I/O AA8 I/O I/O AB25 I/O I/O AA9 I/O I/O AB26 I/O I/O AA10 I/O I/O AC1 I/O I/O AA11 I/O I/O AC2 I/O I/O AA12 I/O I/O AC3 I/O I/O AA13 I/O I/O AC4 I/O I/O AA14 I/O I/O AC5 GND GND AA15 I/O I/O AC6 I/O I/O AA16 I/O I/O AC7 I/O I/O AA17 I/O I/O AC8 I/O I/O AA18 I/O I/O AC9 GND GND AA19 I/O I/O AC10 I/O I/O AA20 I/O I/O AC11 I/O I/O AA21 TDO TDO AC12 I/O I/O AA22 GND GND AC13 I/O I/O AA23 GND GND AC14 I/O I/O AA24 I/O I/O AC15 I/O I/O AA25 I/O I/O AC16 I/O I/O AA26 I/O I/O AC17 I/O I/O AB1 I/O I/O AC18 I/O I/O AB2 I/O I/O AC19 I/O I/O AB3 I/O I/O AC20 I/O I/O AB4 I/O I/O AC21 I/O I/O AB5 I/O I/O AC22 TMS TMS AB6 GND GND AC23 RCK RCK AB7 GND GND AC24 I/O I/O AB8 I/O I/O AC25 I/O I/O AB9 I/O I/O AC26 I/O I/O AB10 I/O I/O AD1 I/O I/O AB11 I/O I/O AD2 I/O I/O AB12 I/O I/O AD3 I/O I/O AB13 I/O I/O AD4 I/O I/O v3.0 109 Pr o A S I C P L U S F la s h F a m il y F P GA s 676- FB GA P i n ( Cont i nued) 110 67 6-FB GA P in (Co nti nue d) Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function AD5 I/O I/O AE22 I/O I/O AD6 I/O I/O AE23 I/O I/O AD7 I/O I/O AE24 I/O I/O AD8 I/O I/O AE25 GND GND AD9 I/O I/O AE26 GND GND AD10 I/O I/O AF1 GND GND AD11 I/O I/O AF2 GND GND AD12 I/O I/O AF3 GND GND AD13 I/O I/O AF4 GND GND AD14 I/O I/O AF5 I/O I/O AD15 I/O I/O AF6 I/O I/O AD16 I/O I/O AF7 I/O I/O AD17 I/O I/O AF8 I/O I/O AD18 I/O I/O AF9 I/O I/O AD19 I/O I/O AF10 I/O I/O AD20 I/O I/O AF11 I/O I/O AD21 I/O I/O AF12 I/O I/O AD22 I/O I/O AF13 I/O I/O AD23 TDI TDI AF14 I/O I/O AD24 VPN VPN AF15 I/O I/O AD25 I/O I/O AF16 I/O I/O AD26 I/O I/O AF17 I/O I/O AE1 GND GND AF18 I/O I/O AE2 GND GND AF19 I/O I/O AE3 GND GND AF20 I/O I/O AE4 I/O I/O AF21 I/O I/O AE5 I/O I/O AF22 I/O I/O AE6 I/O I/O AF23 I/O I/O AE7 I/O I/O AF24 I/O I/O AE8 I/O I/O AF25 GND GND AE9 I/O I/O AF26 GND GND AE10 I/O I/O AE11 I/O I/O AE12 I/O I/O AE13 I/O I/O AE14 I/O I/O AE15 I/O I/O AE16 I/O I/O AE17 I/O I/O AE18 I/O I/O AE19 I/O I/O AE20 I/O I/O AE21 I/O I/O v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Pa c ka ge P i n A s si g nm e n t s (Continued) 896- P in FBG A ( Bot t om V iew ) A1 Ball Pad Corner 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK v3.0 111 Pr o A S I C P L U S F la s h F a m il y F P GA s 896 FB GA P i n 112 89 6 FB GA P in (Co nti nue d) Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function A2 GND GND B15 I/O I/O A3 GND GND B16 I/O I/O A4 I/O I/O B17 I/O I/O A5 GND GND B18 I/O I/O A6 I/O I/O B19 I/O I/O A7 GND GND B20 I/O I/O A8 I/O I/O B21 I/O I/O A9 I/O I/O B22 I/O I/O A10 I/O I/O B23 I/O I/O A11 I/O I/O B24 I/O I/O A12 I/O I/O B25 VDD VDD A13 I/O I/O B26 I/O I/O A14 I/O I/O B27 VDD VDD A15 I/O I/O B28 I/O I/O A16 I/O I/O B29 GND GND A17 I/O I/O B30 GND GND A18 I/O I/O C1 GND GND A19 I/O I/O C2 I/O I/O A20 I/O I/O C3 VDD VDD A21 I/O I/O C4 I/O I/O A22 I/O I/O C5 VDDP VDDP A23 I/O I/O C6 I/O I/O A24 GND GND C7 I/O I/O A25 I/O I/O C8 I/O I/O A26 GND GND C9 I/O I/O A27 I/O I/O C10 I/O I/O A28 GND GND C11 I/O I/O A29 GND GND C12 I/O I/O B1 GND GND C13 I/O I/O B2 GND GND C14 I/O I/O B3 I/O I/O C15 I/O I/O B4 VDD VDD C16 I/O I/O B5 I/O I/O C17 I/O I/O B6 VDD VDD C18 I/O I/O B7 I/O I/O C19 I/O I/O B8 I/O I/O C20 I/O I/O B9 I/O I/O C21 I/O I/O B10 I/O I/O C22 I/O I/O B11 I/O I/O C23 I/O I/O B12 I/O I/O C24 I/O I/O B13 I/O I/O C25 I/O I/O B14 I/O I/O C26 VDDP VDDP v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 896 FB GA Pi n ( Cont i nued) Pin Number APA750 Function 896 FB GA Pi n ( Cont i nued) APA1000 Function Pin Number APA750 Function APA1000 Function C27 I/O I/O E9 I/O I/O C28 VDD VDD E10 I/O I/O C29 NC I/O E11 I/O I/O C30 GND GND E12 I/O I/O D1 I/O I/O E13 I/O I/O D2 VDD VDD E14 I/O I/O D3 I/O I/O E15 I/O I/O D4 GND GND E16 I/O I/O D5 I/O I/O E17 I/O I/O D6 I/O I/O E18 I/O I/O D7 I/O I/O E19 I/O I/O D8 I/O I/O E20 I/O I/O D9 I/O I/O E21 I/O I/O D10 I/O I/O E22 I/O I/O D11 I/O I/O E23 I/O I/O D12 I/O I/O E24 VDDP VDDP D13 I/O I/O E25 I/O I/O D14 I/O I/O E26 VDD VDD D15 I/O I/O E27 I/O I/O D16 I/O I/O E28 VDDP VDDP D17 I/O I/O E29 I/O I/O D18 I/O I/O E30 GND GND D19 I/O I/O F1 I/O I/O D20 I/O I/O F2 VDD VDD D21 I/O I/O F3 I/O I/O D22 I/O I/O F4 I/O I/O D23 I/O I/O F5 I/O I/O D24 I/O I/O F6 GND GND D25 I/O I/O F7 I/O I/O D26 I/O I/O F8 I/O I/O D27 GND GND F9 I/O I/O D28 I/O I/O F10 I/O I/O D29 VDD VDD F11 I/O I/O D30 I/O I/O F12 I/O I/O E1 GND GND F13 I/O I/O E2 I/O I/O F14 I/O I/O E3 VDDP VDDP F15 I/O I/O E4 I/O I/O F16 I/O I/O E5 VDD VDD F17 I/O I/O E6 I/O I/O F18 I/O I/O E7 VDDP VDDP F19 I/O I/O E8 I/O I/O F20 I/O I/O v3.0 113 Pr o A S I C P L U S F la s h F a m il y F P GA s 896 FB GA P i n ( Cont i nued) 114 89 6 FB GA P in (Co nti nue d) Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function F21 I/O I/O H3 I/O I/O F22 I/O I/O H4 I/O I/O F23 I/O I/O H5 I/O I/O F24 I/O I/O H6 I/O I/O F25 GND GND H7 I/O I/O F26 I/O I/O H8 GND GND F27 I/O I/O H9 NC I/O F28 I/O I/O H10 NC I/O F29 VDD VDD H11 NC I/O F30 I/O I/O H12 NC I/O G1 GND GND H13 NC I/O G2 I/O I/O H14 NC I/O G3 I/O I/O H15 NC I/O G4 I/O I/O H16 NC I/O G5 VDDP VDDP H17 NC I/O G6 I/O I/O H18 NC I/O G7 VDD VDD H19 NC I/O G8 I/O I/O H20 NC I/O G9 VDDP VDDP H21 NC I/O G10 I/O I/O H22 NC I/O G11 I/O I/O H23 GND GND G12 I/O I/O H24 I/O I/O G13 I/O I/O H25 I/O I/O G14 I/O I/O H26 I/O I/O G15 I/O I/O H27 I/O I/O G16 I/O I/O H28 I/O I/O G17 I/O I/O H29 I/O I/O G18 I/O I/O H30 I/O I/O G19 I/O I/O J1 I/O I/O G20 I/O I/O J2 I/O I/O G21 I/O I/O J3 I/O I/O G22 VDDP VDDP J4 I/O I/O G23 I/O I/O J5 I/O I/O G24 VDD VDD J6 I/O I/O G25 I/O I/O J7 VDDP VDDP G26 VDDP VDDP J8 I/O I/O G27 I/O I/O J9 VDD VDD G28 I/O I/O J10 NC I/O G29 I/O I/O J11 NC I/O G30 GND GND J12 NC I/O H1 I/O I/O J13 NC I/O H2 I/O I/O J14 NC I/O v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 896 FB GA Pi n ( Cont i nued) 896 FB GA Pi n ( Cont i nued) Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function J15 NC I/O K27 I/O I/O J16 NC I/O K28 I/O I/O J17 NC I/O K29 I/O I/O J18 NC I/O K30 I/O I/O J19 NC I/O L1 I/O I/O J20 NC I/O L2 I/O I/O J21 NC I/O L3 I/O I/O J22 VDD VDD L4 I/O I/O J23 I/O I/O L5 I/O I/O J24 VDDP VDDP L6 I/O I/O J25 I/O I/O L7 I/O I/O J26 I/O I/O L8 I/O I/O J27 I/O I/O L9 NC I/O J28 I/O I/O L10 NC I/O J29 I/O I/O L11 VDD VDD J30 I/O I/O L12 VDD VDD K1 I/O I/O L13 VDD VDD K2 I/O I/O L14 VDD VDD K3 I/O I/O L15 VDD VDD K4 I/O I/O L16 VDD VDD K5 I/O I/O L17 VDD VDD K6 I/O I/O L18 VDD VDD K7 I/O I/O L19 VDD VDD K8 I/O I/O L20 VDD VDD K9 NC I/O L21 NC I/O K10 VDD VDD L22 NC I/O K11 NC I/O L23 I/O I/O K12 VDDP VDDP L24 I/O I/O K13 VDDP VDDP L25 I/O I/O K14 VDDP VDDP L26 I/O I/O K15 VDDP VDDP L27 I/O I/O K16 VDDP VDDP L28 I/O I/O K17 VDDP VDDP L29 I/O I/O K18 VDDP VDDP L30 I/O I/O K19 VDDP VDDP M1 I/O I/O K20 NC I/O M2 I/O I/O K21 VDD VDD M3 I/O I/O K22 NC I/O M4 I/O I/O K23 I/O I/O M5 I/O I/O K24 I/O I/O M6 I/O I/O K25 I/O I/O M7 I/O I/O K26 I/O I/O M8 I/O I/O v3.0 115 Pr o A S I C P L U S F la s h F a m il y F P GA s 896 FB GA P i n ( Cont i nued) Pin Number 116 APA750 Function 89 6 FB GA P in (Co nti nue d) APA1000 Function Pin Number APA750 Function APA1000 Function M9 NC I/O N21 VDDP VDDP M10 VDDP VDDP N22 NC I/O M11 VDD VDD N23 I/O I/O M12 GND GND N24 I/O I/O M13 GND GND N25 I/O I/O M14 GND GND N26 I/O I/O M15 GND GND N27 I/O I/O M16 GND GND N28 I/O I/O M17 GND GND N29 I/O I/O M18 GND GND N30 I/O I/O M19 GND GND P1 I/O I/O M20 VDD VDD P2 I/O I/O M21 VDDP VDDP P3 I/O I/O M22 NC I/O P4 I/O I/O M23 I/O I/O P5 I/O I/O M24 I/O I/O P6 I/O I/O M25 I/O I/O P7 I/O I/O M26 I/O I/O P8 I/O I/O M27 I/O I/O P9 I/O I/O M28 I/O I/O P10 VDDP VDDP M29 I/O I/O P11 VDD VDD M30 I/O I/O P12 GND GND N1 I/O I/O P13 GND GND N2 I/O I/O P14 GND GND N3 I/O I/O P15 GND GND N4 I/O I/O P16 GND GND N5 I/O I/O P17 GND GND N6 I/O I/O P18 GND GND N7 I/O I/O P19 GND GND N8 I/O I/O P20 VDD VDD N9 NC I/O P21 VDDP VDDP N10 VDDP VDDP P22 I/O I/O N11 VDD VDD P23 I/O I/O N12 GND GND P24 I/O I/O N13 GND GND P25 I/O I/O N14 GND GND P26 I/O I/O N15 GND GND P27 I/O I/O N16 GND GND P28 I/O I/O N17 GND GND P29 I/O I/O N18 GND GND P30 I/O I/O N19 GND GND R1 I/O I/O N20 VDD VDD R2 I/O (GLMX1) I/O (GLMX1) v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 896 FB GA Pi n ( Cont i nued) Pin Number APA750 Function 896 FB GA Pi n ( Cont i nued) APA1000 Function Pin Number APA750 Function APA1000 Function R3 AGND AGND T15 GND GND R4 NPECL1 NPECL1 T16 GND GND R5 GL1 GL1 T17 GND GND R6 I/O I/O T18 GND GND R7 I/O I/O T19 GND GND R8 I/O I/O T20 VDD VDD R9 NC I/O T21 VDDP VDDP R10 VDDP VDDP T22 I/O I/O R11 VDD VDD T23 I/O I/O R12 GND GND T24 I/O I/O R13 GND GND T25 I/O I/O R14 GND GND T26 PPECL2 (I/P) PPECL2 (I/P) R15 GND GND T27 GL4 GL4 R16 GND GND T28 GL3 GL3 R17 GND GND T29 AVDD AVDD R18 GND GND T30 I/O I/O R19 GND GND U1 I/O I/O R20 VDD VDD U2 I/O I/O R21 VDDP VDDP U3 I/O I/O R22 I/O I/O U4 I/O I/O R23 I/O I/O U5 I/O I/O R24 I/O I/O U6 I/O I/O R25 I/O I/O U7 I/O I/O R26 I/O I/O U8 I/O I/O R27 NPECL2 NPECL2 U9 NC I/O R28 AGND AGND U10 VDDP VDDP R29 I/O (GLMX2) I/O (GLMX2) U11 VDD VDD R30 I/O I/O U12 GND GND T1 I/O I/O U13 GND GND T2 AVDD AVDD U14 GND GND T3 GL2 GL2 U15 GND GND T4 PPECL1 (I/P) PPECL1 (I/P) U16 GND GND T5 I/O I/O U17 GND GND T6 I/O I/O U18 GND GND T7 I/O I/O U19 GND GND T8 I/O I/O U20 VDD VDD T9 I/O I/O U21 VDDP VDDP T10 VDDP VDDP U22 NC I/O T11 VDD VDD U23 I/O I/O T12 GND GND U24 I/O I/O T13 GND GND U25 I/O I/O T14 GND GND U26 I/O I/O v3.0 117 Pr o A S I C P L U S F la s h F a m il y F P GA s 896 FB GA P i n ( Cont i nued) 118 89 6 FB GA P in (Co nti nue d) Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function U27 I/O I/O W9 NC I/O U28 I/O I/O W10 VDDP VDDP U29 I/O I/O W11 VDD VDD U30 I/O I/O W12 GND GND V1 I/O I/O W13 GND GND V2 I/O I/O W14 GND GND V3 I/O I/O W15 GND GND V4 I/O I/O W16 GND GND V5 I/O I/O W17 GND GND V6 I/O I/O W18 GND GND V7 I/O I/O W19 GND GND V8 I/O I/O W20 VDD VDD V9 NC I/O W21 VDDP VDDP V10 VDDP VDDP W22 NC I/O V11 VDD VDD W23 I/O I/O V12 GND GND W24 I/O I/O V13 GND GND W25 I/O I/O V14 GND GND W26 I/O I/O V15 GND GND W27 I/O I/O V16 GND GND W28 I/O I/O V17 GND GND W29 I/O I/O V18 GND GND W30 I/O I/O V19 GND GND Y1 I/O I/O V20 VDD VDD Y2 I/O I/O V21 VDDP VDDP Y3 I/O I/O V22 NC I/O Y4 I/O I/O V23 I/O I/O Y5 I/O I/O V24 I/O I/O Y6 I/O I/O V25 I/O I/O Y7 I/O I/O V26 I/O I/O Y8 I/O I/O V27 I/O I/O Y9 NC I/O V28 I/O I/O Y10 NC I/O V29 I/O I/O Y11 VDD VDD V30 I/O I/O Y12 VDD VDD W1 I/O I/O Y13 VDD VDD W2 I/O I/O Y14 VDD VDD W3 I/O I/O Y15 VDD VDD W4 I/O I/O Y16 VDD VDD W5 I/O I/O Y17 VDD VDD W6 I/O I/O Y18 VDD VDD W7 I/O I/O Y19 VDD VDD W8 I/O I/O Y20 VDD VDD v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 896 FB GA Pi n ( Cont i nued) 896 FB GA Pi n ( Cont i nued) Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function Y21 NC I/O AB3 I/O I/O Y22 NC I/O AB4 I/O I/O Y23 I/O I/O AB5 I/O I/O Y24 I/O I/O AB6 I/O I/O Y25 I/O I/O AB7 VDDP VDDP Y26 I/O I/O AB8 I/O I/O Y27 I/O I/O AB9 VDD VDD Y28 I/O I/O AB10 NC I/O Y29 I/O I/O AB11 NC I/O Y30 I/O I/O AB12 NC I/O AA1 I/O I/O AB13 NC I/O AA2 I/O I/O AB14 NC I/O AA3 I/O I/O AB15 NC I/O AA4 I/O I/O AB16 NC I/O AA5 I/O I/O AB17 NC I/O AA6 I/O I/O AB18 NC I/O AA7 I/O I/O AB19 NC I/O AA8 I/O I/O AB20 NC I/O AA9 NC I/O AB21 NC I/O AA10 VDD VDD AB22 VDD VDD AA11 NC I/O AB23 I/O I/O AA12 VDDP VDDP AB24 VDDP VDDP AA13 VDDP VDDP AB25 I/O I/O AA14 VDDP VDDP AB26 I/O I/O AA15 VDDP VDDP AB27 I/O I/O AA16 VDDP VDDP AB28 I/O I/O AA17 VDDP VDDP AB29 I/O I/O AA18 VDDP VDDP AB30 I/O I/O AA19 VDDP VDDP AC1 I/O I/O AA20 NC I/O AC2 I/O I/O AA21 VDD VDD AC3 I/O I/O AA22 NC I/O AC4 I/O I/O AA23 I/O I/O AC5 I/O I/O AA24 I/O I/O AC6 I/O I/O AA25 I/O I/O AC7 I/O I/O AA26 I/O I/O AC8 GND GND AA27 I/O I/O AC9 NC I/O AA28 I/O I/O AC10 NC I/O AA29 I/O I/O AC11 NC I/O AA30 I/O I/O AC12 NC I/O AB1 I/O I/O AC13 NC I/O AB2 I/O I/O AC14 NC I/O v3.0 119 Pr o A S I C P L U S F la s h F a m il y F P GA s 896 FB GA P i n ( Cont i nued) 120 89 6 FB GA P in (Co nti nue d) Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function AC15 NC I/O AD27 I/O I/O AC16 NC I/O AD28 I/O I/O AC17 NC I/O AD29 I/O I/O AC18 NC I/O AD30 GND GND AC19 NC I/O AE1 I/O I/O AC20 NC I/O AE2 VDD VDD AC21 NC I/O AE3 I/O I/O AC22 NC I/O AE4 I/O I/O AC23 GND GND AE5 I/O I/O AC24 I/O I/O AE6 GND GND AC25 I/O I/O AE7 I/O I/O AC26 I/O I/O AE8 I/O I/O AC27 I/O I/O AE9 I/O I/O AC28 I/O I/O AE10 I/O I/O AC29 I/O I/O AE11 I/O I/O AC30 I/O I/O AE12 I/O I/O AD1 GND GND AE13 I/O I/O AD2 I/O I/O AE14 I/O I/O AD3 I/O I/O AE15 I/O I/O AD4 I/O I/O AE16 I/O I/O AD5 VDDP VDDP AE17 I/O I/O AD6 I/O I/O AE18 I/O I/O AD7 VDD VDD AE19 I/O I/O AD8 I/O I/O AE20 I/O I/O AD9 VDDP VDDP AE21 I/O I/O AD10 I/O I/O AE22 I/O I/O AD11 I/O I/O AE23 I/O I/O AD12 I/O I/O AE24 I/O I/O AD13 I/O I/O AE25 GND GND AD14 I/O I/O AE26 I/O I/O AD15 I/O I/O AE27 I/O I/O AD16 I/O I/O AE28 I/O I/O AD17 I/O I/O AE29 VDD VDD AD18 I/O I/O AE30 I/O I/O AD19 I/O I/O AF1 GND GND AD20 I/O I/O AF2 I/O I/O AD21 I/O I/O AF3 VDDP VDDP AD22 VDDP VDDP AF4 I/O I/O AD23 TCK TCK AF5 VDD VDD AD24 VDD VDD AF6 I/O I/O AD25 TRST TRST AF7 VDDP VDDP AD26 VDDP VDDP AF8 I/O I/O v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 896 FB GA Pi n ( Cont i nued) 896 FB GA Pi n ( Cont i nued) Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function AF9 I/O I/O AG21 I/O I/O AF10 I/O I/O AG22 I/O I/O AF11 I/O I/O AG23 I/O I/O AF12 I/O I/O AG24 I/O I/O AF13 I/O I/O AG25 I/O I/O AF14 I/O I/O AG26 I/O I/O AF15 I/O I/O AG27 GND GND AF16 I/O I/O AG28 RCK RCK AF17 I/O I/O AG29 VDD VDD AF18 I/O I/O AG30 I/O I/O AF19 I/O I/O AH1 GND GND AF20 I/O I/O AH2 I/O I/O AF21 I/O I/O AH3 VDD VDD AF22 I/O I/O AH4 I/O I/O AF23 I/O I/O AH5 VDDP VDDP AF24 VDDP VDDP AH6 I/O I/O AF25 I/O I/O AH7 I/O I/O AF26 VDD VDD AH8 I/O I/O AF27 TDO TDO AH9 I/O I/O AF28 VDDP VDDP AH10 I/O I/O AF29 VPN VPN AH11 I/O I/O AF30 GND GND AH12 I/O I/O AG1 I/O I/O AH13 I/O I/O AG2 VDD VDD AH14 I/O I/O AG3 I/O I/O AH15 I/O I/O AG4 GND GND AH16 I/O I/O AG5 I/O I/O AH17 I/O I/O AG6 I/O I/O AH18 I/O I/O AG7 I/O I/O AH19 I/O I/O AG8 I/O I/O AH20 I/O I/O AG9 I/O I/O AH21 I/O I/O AG10 I/O I/O AH22 I/O I/O AG11 I/O I/O AH23 I/O I/O AG12 I/O I/O AH24 I/O I/O AG13 I/O I/O AH25 I/O I/O AG14 I/O I/O AH26 VDDP VDDP AG15 I/O I/O AH27 TDI TDI AG16 I/O I/O AH28 VDD VDD AG17 I/O I/O AH29 VPP VPP AG18 I/O I/O AH30 GND GND AG19 I/O I/O AJ1 GND GND AG20 I/O I/O AJ2 GND GND v3.0 121 Pr o A S I C P L U S F la s h F a m il y F P GA s 896 FB GA P i n ( Cont i nued) Pin Number 122 APA750 Function 89 6 FB GA P in (Co nti nue d) APA1000 Function Pin Number APA750 Function APA1000 Function AJ3 I/O I/O AK16 I/O I/O AJ4 VDD VDD AK17 I/O I/O AJ5 I/O I/O AK18 I/O I/O AJ6 VDD VDD AK19 I/O I/O AJ7 I/O I/O AK20 I/O I/O AJ8 I/O I/O AK21 I/O I/O AJ9 I/O I/O AK22 I/O I/O AJ10 I/O I/O AK23 I/O I/O AJ11 I/O I/O AK24 GND GND AJ12 I/O I/O AK25 I/O I/O AJ13 I/O I/O AK26 GND GND AJ14 I/O I/O AK27 I/O I/O AJ15 I/O I/O AK28 GND GND AJ16 I/O I/O AK29 GND GND AJ17 I/O I/O AJ18 I/O I/O AJ19 I/O I/O AJ20 I/O I/O AJ21 I/O I/O AJ22 I/O I/O AJ23 I/O I/O AJ24 I/O I/O AJ25 VDD VDD AJ26 I/O I/O AJ27 VDD VDD AJ28 TMS TMS AJ29 GND GND AJ30 GND GND AK2 GND GND AK3 GND GND AK4 I/O I/O AK5 GND GND AK6 I/O I/O AK7 GND GND AK8 I/O I/O AK9 I/O I/O AK10 I/O I/O AK11 I/O I/O AK12 I/O I/O AK13 I/O I/O AK14 I/O I/O AK15 I/O I/O v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Pa c ka ge P i n A s si g nm e n t s (Continued) 1152-Pin FBGA (Bottom View) A1 Ball Pad Corner 34 33 32 31 30 2928 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AO AP v3.0 123 Pr o A S I C P L U S F la s h F a m il y F P GA s 1152 FB GA P in 1 152 FBG A P i n 1 1 5 2 F BG A P in 1152 FB GA P in Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function A2 NC B14 VDDP C25 I/O E2 GND A3 GND B15 VDDP C26 GND E3 GND A4 GND B16 I/O C27 I/O E4 I/O A5 GND B17 GND C28 GND E5 VDD A6 I/O B18 GND C29 I/O E6 I/O 124 A7 VDD B19 I/O C30 GND E7 VDDP A8 VDD B20 VDDP C31 GND E8 I/O A9 VDD B21 VDDP C32 NC E9 I/O A10 VDD B22 I/O C33 GND E10 I/O A11 I/O B23 GND C34 GND E11 I/O A12 GND B24 I/O D1 GND E12 I/O A13 I/O B25 NC D2 GND E13 I/O A14 VDDP B26 I/O D3 GND E14 I/O A15 VDDP B27 NC D4 GND E15 I/O A16 I/O B28 I/O D5 I/O E16 I/O A17 GND B29 NC D6 VDD E17 I/O A18 GND B30 GND D7 I/O E18 I/O A19 I/O B31 GND D8 VDD E19 I/O A20 VDDP B32 GND D9 I/O E20 I/O A21 VDDP B33 NC D10 I/O E21 I/O A22 I/O B34 NC D11 I/O E22 I/O A23 GND C1 GND D12 I/O E23 I/O A24 I/O C2 GND D13 I/O E24 I/O A25 VDD C3 NC D14 I/O E25 I/O A26 VDD C4 GND D15 I/O E26 I/O A27 VDD C5 GND D16 I/O E27 I/O A28 VDD C6 I/O D17 I/O E28 VDDP A29 I/O C7 GND D18 I/O E29 I/O A30 GND C8 I/O D19 I/O E30 VDD A31 GND C9 GND D20 I/O E31 I/O A32 GND C10 I/O D21 I/O E32 GND A33 NC C11 I/O D22 I/O E33 GND B1 NC C12 I/O D23 I/O E34 GND B2 NC C13 I/O D24 I/O F1 I/O B3 GND C14 I/O D25 I/O F2 NC B4 GND C15 I/O D26 I/O F3 I/O B5 GND C16 I/O D27 VDD F4 VDD B6 NC C17 I/O D28 I/O F5 I/O B7 I/O C18 I/O D29 VDD F6 GND B8 NC C19 I/O D30 I/O F7 I/O B9 I/O C20 I/O D31 GND F8 I/O B10 NC C21 I/O D32 GND F9 I/O B11 I/O C22 I/O D33 GND F10 I/O B12 GND C23 I/O D34 GND F11 I/O B13 I/O C24 I/O E1 GND F12 I/O v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 1152 FB GA P in 1152 FB GA P in 1152 FB GA P in 115 2 FB GA P in Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function F13 I/O G24 I/O J1 VDD K12 I/O F14 I/O G25 I/O J2 I/O K13 I/O F15 I/O G26 VDDP J3 GND K14 I/O F16 I/O G27 I/O J4 I/O K15 I/O F17 I/O G28 VDD J5 I/O K16 I/O F18 I/O G29 I/O J6 I/O K17 I/O F19 I/O G30 VDDP J7 VDDP K18 I/O F20 I/O G31 I/O J8 I/O K19 I/O F21 I/O G32 GND J9 VDD K20 I/O F22 I/O G33 I/O J10 I/O K21 I/O F23 I/O G34 VDD J11 VDDP K22 I/O F24 I/O H1 VDD J12 I/O K23 I/O F25 I/O H2 NC J13 I/O K24 I/O F26 I/O H3 I/O J14 I/O K25 GND F27 I/O H4 VDD J15 I/O K26 I/O F28 I/O H5 I/O J16 I/O K27 I/O F29 GND H6 I/O J17 I/O K28 I/O F30 I/O H7 I/O J18 I/O K29 I/O F31 VDD H8 GND J19 I/O K30 I/O F32 I/O H9 I/O J20 I/O K31 I/O F33 NC H10 I/O J21 I/O K32 I/O F34 NC H11 I/O J22 I/O K33 NC G1 VDD H12 I/O J23 I/O K34 VDD G2 I/O H13 I/O J24 VDDP L1 I/O G3 GND H14 I/O J25 I/O L2 I/O G4 I/O H15 I/O J26 VDD L3 I/O G5 VDDP H16 I/O J27 I/O L4 I/O G6 I/O H17 I/O J28 VDDP L5 I/O G7 VDD H18 I/O J29 I/O L6 I/O G8 I/O H19 I/O J30 I/O L7 I/O G9 VDDP H20 I/O J31 I/O L8 I/O G10 I/O H21 I/O J32 GND L9 VDDP G11 I/O H22 I/O J33 I/O L10 I/O G12 I/O H23 I/O J34 VDD L11 VDD G13 I/O H24 I/O K1 VDD L12 I/O G14 I/O H25 I/O K2 NC L13 I/O G15 I/O H26 I/O K3 I/O L14 I/O G16 I/O H27 GND K4 I/O L15 I/O G17 I/O H28 I/O K5 I/O L16 I/O G18 I/O H29 I/O K6 I/O L17 I/O G19 I/O H30 I/O K7 I/O L18 I/O G20 I/O H31 VDD K8 I/O L19 I/O G21 I/O H32 I/O K9 I/O L20 I/O G22 I/O H33 NC K10 GND L21 I/O G23 I/O H34 VDD K11 I/O L22 I/O v3.0 125 Pr o A S I C P L U S F la s h F a m il y F P GA s 1152 FB GA P in 1 152 FBG A P i n 1 1 5 2 F BG A P in 1152 FB GA P in Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function L23 I/O M34 GND P11 I/O R22 VDD L24 VDD N1 I/O P12 VDDP R23 VDDP L25 I/O N2 I/O P13 VDD R24 I/O L26 VDDP N3 I/O P14 GND R25 I/O L27 I/O N4 I/O P15 GND R26 I/O L28 I/O N5 I/O P16 GND R27 I/O L29 I/O N6 I/O P17 GND R28 I/O L30 I/O N7 I/O P18 GND R29 I/O L31 I/O N8 I/O P19 GND R30 I/O L32 I/O N9 I/O P20 GND R31 I/O L33 I/O N10 I/O P21 GND R32 I/O 126 L34 I/O N11 I/O P22 VDD R33 VDDP M1 GND N12 I/O P23 VDDP R34 VDDP M2 GND N13 VDD P24 I/O T1 I/O M3 I/O N14 VDD P25 I/O T2 I/O M4 I/O N15 VDD P26 I/O T3 I/O M5 I/O N16 VDD P27 I/O T4 I/O M6 I/O N17 VDD P28 I/O T5 I/O M7 I/O N18 VDD P29 I/O T6 I/O M8 I/O N19 VDD P30 I/O T7 I/O M9 I/O N20 VDD P31 I/O T8 I/O M10 I/O N21 VDD P32 I/O T9 I/O M11 I/O N22 VDD P33 VDDP T10 I/O M12 VDD N23 I/O P34 VDDP T11 I/O M13 I/O N24 I/O R1 VDDP T12 VDDP M14 VDDP N25 I/O R2 VDDP T13 VDD M15 VDDP N26 I/O R3 I/O T14 GND M16 VDDP N27 I/O R4 I/O T15 GND M17 VDDP N28 I/O R5 I/O T16 GND M18 VDDP N29 I/O R6 I/O T17 GND M19 VDDP N30 I/O R7 I/O T18 GND M20 VDDP N31 I/O R8 I/O T19 GND M21 VDDP N32 I/O R9 I/O T20 GND M22 I/O N33 I/O R10 I/O T21 GND M23 VDD N34 I/O R11 I/O T22 VDD M24 I/O P1 VDDP R12 VDDP T23 VDDP M25 I/O P2 VDDP R13 VDD T24 I/O M26 I/O P3 I/O R14 GND T25 I/O M27 I/O P4 I/O R15 GND T26 I/O M28 I/O P5 I/O R16 GND T27 I/O M29 I/O P6 I/O R17 GND T28 I/O M30 I/O P7 I/O R18 GND T29 I/O M31 I/O P8 I/O R19 GND T30 I/O M32 I/O P9 I/O R20 GND T31 I/O M33 GND P10 I/O R21 GND T32 I/O v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 1152 FB GA P in 1152 FB GA P in 1152 FB GA P in 115 2 FB GA P in Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function T33 I/O V7 I/O W17 GND Y28 I/O T34 I/O V8 I/O W18 GND Y29 I/O U1 GND V9 I/O W19 GND Y30 I/O U2 GND V10 I/O W20 GND Y31 I/O U3 I/O V11 I/O W21 GND Y32 I/O U4 I/O (GLMX1) V12 VDDP W22 VDD Y33 VDDP V13 VDD W23 VDDP Y34 VDDP U5 AGND V14 GND W24 I/O AA1 VDDP U6 NPECL1 V15 GND W25 I/O AA2 VDDP U7 GL1 V16 GND W26 I/O AA3 I/O U8 I/O V17 GND W27 I/O AA4 I/O U9 I/O V18 GND W28 I/O AA5 I/O U10 I/O V19 GND W29 I/O AA6 I/O U11 I/O V20 GND W30 I/O AA7 I/O U12 VDDP V21 GND W31 I/O AA8 I/O U13 VDD V22 VDD W32 I/O AA9 I/O U14 GND V23 VDDP W33 I/O AA10 I/O U15 GND V24 I/O W34 I/O AA11 I/O U16 GND V25 I/O Y1 VDDP AA12 VDDP U17 GND V26 I/O Y2 VDDP AA13 VDD U18 GND V27 I/O Y3 I/O AA14 GND U19 GND PPECL2 (I/P) I/O AA15 GND GND V28 Y4 U20 Y5 I/O AA16 GND U21 GND V29 GL4 Y6 I/O AA17 GND U22 VDD V30 GL3 Y7 I/O AA18 GND U23 VDDP V31 AVDD Y8 I/O AA19 GND U24 I/O V32 I/O Y9 I/O AA20 GND U25 I/O V33 GND Y10 I/O AA21 GND U26 I/O V34 GND Y11 I/O AA22 VDD U27 I/O W1 I/O Y12 VDDP AA23 VDDP U28 I/O W2 I/O Y13 VDD AA24 I/O U29 NPECL2 W3 I/O Y14 GND AA25 I/O U30 AGND W4 I/O Y15 GND AA26 I/O U31 I/O (GLMX2) W5 I/O Y16 GND AA27 I/O W6 I/O U32 I/O Y17 GND AA28 I/O W7 I/O U33 GND Y18 GND AA29 I/O W8 I/O U34 GND Y19 GND AA30 I/O W9 I/O V1 GND Y20 GND AA31 I/O W10 I/O V2 GND Y21 GND AA32 I/O W11 I/O V3 I/O Y22 VDD AA33 VDDP W12 VDDP V4 AVDD Y23 VDDP AA34 VDDP W13 VDD V5 GL2 Y24 I/O AB1 I/O W14 GND I/O AB2 I/O V6 PPECL1 (I/P) Y25 W15 GND Y26 I/O AB3 I/O W16 GND Y27 I/O AB4 I/O v3.0 127 Pr o A S I C P L U S F la s h F a m il y F P GA s 1152 FB GA P in 1 152 FBG A P i n 1 1 5 2 F BG A P in 1152 FB GA P in Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function AB5 I/O AC16 VDDP AD27 I/O AF4 I/O AB6 I/O AC17 VDDP AD28 I/O AF5 I/O AB7 I/O AC18 VDDP AD29 I/O AF6 I/O AB8 I/O AC19 VDDP AD30 I/O AF7 VDDP AB9 I/O AC20 VDDP AD31 I/O AF8 I/O AB10 I/O AC21 VDDP AD32 I/O AF9 VDD AB11 I/O AC22 I/O AD33 I/O AF10 I/O AB12 I/O AC23 VDD AD34 I/O AF11 VDDP AB13 VDD AC24 I/O AE1 VDD AF12 I/O AB14 VDD AC25 I/O AE2 NC AF13 I/O AB15 VDD AC26 I/O AE3 I/O AF14 I/O AB16 VDD AC27 I/O AE4 I/O AF15 I/O AB17 VDD AC28 I/O AE5 I/O AF16 I/O AB18 VDD AC29 I/O AE6 I/O AF17 I/O AB19 VDD AC30 I/O AE7 I/O AF18 I/O AB20 VDD AC31 I/O AE8 I/O AF19 I/O AB21 VDD AC32 I/O AE9 I/O AF20 I/O AB22 VDD AC33 GND AE10 GND AF21 I/O AB23 I/O AC34 GND AE11 I/O AF22 I/O AB24 I/O AD1 I/O AE12 I/O AF23 I/O AB25 I/O AD2 I/O AE13 I/O AF24 VDDP AB26 I/O AD3 I/O AE14 I/O AF25 TCK AB27 I/O AD4 I/O AE15 I/O AF26 VDD AB28 I/O AD5 I/O AE16 I/O AF27 TRST AB29 I/O AD6 I/O AE17 I/O AF28 VDDP AB30 I/O AD7 I/O AE18 I/O AF29 I/O AB31 I/O AD8 I/O AE19 I/O AF30 I/O AB32 I/O AD9 VDDP AE20 I/O AF31 I/O AB33 I/O AD10 I/O AE21 I/O AF32 GND 128 AB34 I/O AD11 VDD AE22 I/O AF33 I/O AC1 GND AD12 I/O AE23 I/O AF34 VDD AC2 GND AD13 I/O AE24 I/O AG1 VDD AC3 I/O AD14 I/O AE25 GND AG2 NC AC4 I/O AD15 I/O AE26 I/O AG3 I/O AC5 I/O AD16 I/O AE27 I/O AG4 VDD AC6 I/O AD17 I/O AE28 I/O AG5 I/O AC7 I/O AD18 I/O AE29 I/O AG6 I/O AC8 I/O AD19 I/O AE30 I/O AG7 I/O AC9 I/O AD20 I/O AE31 I/O AG8 GND AC10 I/O AD21 I/O AE32 I/O AG9 I/O AC11 I/O AD22 I/O AE33 NC AG10 I/O AC12 VDD AD23 I/O AE34 VDD AG11 I/O AC13 I/O AD24 VDD AF1 VDD AG12 I/O AC14 VDDP AD25 I/O AF2 I/O AG13 I/O AC15 VDDP AD26 VDDP AF3 GND AG14 I/O v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 1152 FB GA P in 1152 FB GA P in 1152 FB GA P in 115 2 FB GA P in Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function AG15 I/O AH26 VDDP AK3 GND AL14 I/O AG16 I/O AH27 I/O AK4 I/O AL15 I/O AG17 I/O AH28 VDD AK5 VDD AL16 I/O AG18 I/O AH29 TDO AK6 I/O AL17 I/O AG19 I/O AH30 VDDP AK7 VDDP AL18 I/O AG20 I/O AH31 VPN AK8 I/O AL19 I/O AG21 I/O AH32 GND AK9 I/O AL20 I/O AG22 I/O AH33 I/O AK10 I/O AL21 I/O AG23 I/O AH34 VDD AK11 I/O AL22 I/O AG24 I/O AJ1 I/O AK12 I/O AL23 I/O AG25 I/O AJ2 NC AK13 I/O AL24 I/O AG26 I/O AJ3 I/O AK14 I/O AL25 I/O AG27 GND AJ4 VDD AK15 I/O AL26 I/O AG28 I/O AJ5 I/O AK16 I/O AL27 VDD AG29 I/O AJ6 GND AK17 I/O AL28 I/O AG30 I/O AJ7 I/O AK18 I/O AL29 VDD AG31 VDD AJ8 I/O AK19 I/O AL30 TMS AG32 I/O AJ9 I/O AK20 I/O AL31 GND AG33 NC AJ10 I/O AK21 I/O AL32 GND AG34 VDD AJ11 I/O AK22 I/O AL33 GND AH1 VDD AJ12 I/O AK23 I/O AL34 GND AH2 I/O AJ13 I/O AK24 I/O AM1 GND AH3 GND AJ14 I/O AK25 I/O AM2 GND AH4 I/O AJ15 I/O AK26 I/O AM3 NC AH5 VDDP AJ16 I/O AK27 I/O AM4 GND AH6 I/O AJ17 I/O AK28 VDDP AM5 GND AH7 VDD AJ18 I/O AK29 TDI AM6 I/O AH8 I/O AJ19 I/O AK30 VDD AM7 GND AH9 VDDP AJ20 I/O AK31 VPP AM8 I/O AH10 I/O AJ21 I/O AK32 GND AM9 GND AH11 I/O AJ22 I/O AK33 GND AM10 I/O AH12 I/O AJ23 I/O AK34 GND AM11 I/O AH13 I/O AJ24 I/O AL1 GND AM12 I/O AH14 I/O AJ25 I/O AL2 GND AM13 I/O AH15 I/O AJ26 I/O AL3 GND AM14 I/O AH16 I/O AJ27 I/O AL4 GND AM15 I/O AH17 I/O AJ28 I/O AL5 I/O AM16 I/O AH18 I/O AJ29 GND AL6 VDD AM17 I/O AH19 I/O AJ30 RCK AL7 I/O AM18 I/O AH20 I/O AJ31 VDD AL8 VDD AM19 I/O AH21 I/O AJ32 I/O AL9 I/O AM20 I/O AH22 I/O AJ33 NC AL10 I/O AM21 I/O AH23 I/O AJ34 NC AL11 I/O AM22 I/O AH24 I/O AK1 GND AL12 I/O AM23 I/O AH25 I/O AK2 GND AL13 I/O AM24 I/O v3.0 129 Pr o A S I C P L U S F la s h F a m il y F P GA s 1152 FB GA P in 1 152 FBG A P i n Pin Number APA1000 Function Pin Number APA1000 Function AM25 I/O AP3 GND AM26 GND AP4 GND AM27 I/O AP5 GND AM28 GND AP6 I/O AM29 I/O AP7 VDD AM30 GND AP8 VDD AM31 GND AP9 VDD AM32 NC AP10 VDD AM33 GND AP11 I/O AM34 GND AP12 GND AN1 NC AP13 I/O AN2 NC AP14 VDDP AN3 GND AP15 VDDP AN4 GND AP16 I/O AN5 GND AP17 GND AN6 NC AP18 GND AN7 I/O AP19 I/O AN8 NC AP20 VDDP AN9 I/O AP21 VDDP AN10 NC AP22 I/O AN11 I/O AP23 GND AN12 GND AP24 I/O AN13 I/O AP25 VDD AN14 VDDP AP26 VDD AN15 VDDP AP27 VDD AN16 I/O AP28 VDD AN17 GND AP29 I/O AN18 GND AP30 GND AN19 I/O AP31 GND AN20 VDDP AP32 GND AN21 VDDP AP33 NC 130 AN22 I/O AN23 GND AN24 I/O AN25 NC AN26 I/O AN27 NC AN28 I/O AN29 NC AN30 GND AN31 GND AN32 GND AN33 NC AN34 NC AP2 NC v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Li s t o f C ha ng e s The following table lists critical changes that were made in the current version of the document. Previous version v2.0 Changes in current version (Advanced v3.0) The "ProASICPLUS Product Profile" table on page 1 was updated. The "Ordering Information" section on page 3 was updated. The "Plastic Device Resources" table on page 3 was updated. The "Product Availability" table on page 4 was updated. Table 2 on page 10 was updated. Figure 8 on page 10 is new. Figure 11 on page 12 is new. The Introduction in the "ProASICPLUS Clock Management System" section on page 15 was updated. The "Physical Implementation" section on page 15 was updated. The "Functional Description" section on page 15 was updated. Figure 14 on page 16 through Figure 20 on page 20 were updated. The "PLL Electrical Specifications" table on page 21 was updated. Figure 25 on page 25 was updated. The "Calculating Typical Power Dissipation" section on page 28 was updated. The "Supply Voltages" table on page 30 was updated. The "DC Electrical Specifications (VDDP = 3.3V 0.3V and VDD 2.5V 0.2V)1" table on page 32 was updated. The "Tristate Buffer Delays" table on page 35 was updated. The "Output Buffer Delays" section on page 36 was updated. The"Input Buffer Delays" section on page 37 was updated. "Global Routing Skew" table on page 38 was updated. The"Sample Macrocell Library Listing*" table on page 39 was updated. The "Pin Description" section on page 60 was updated. The following pins have been changed in the "100-Pin TQFP" table on page 63: Pin Number Function Pin Number Function 10 I/O (GLMX1) 60 GL3 11 GL1 61 PPECL2 (I/P) 13 NPECL1 63 NPECL2 15 PPECL1 (I/P) 65 GL4 16 GL2 66 I/O (GLMX2) "144-Pin TQFP" table on page 65 is new. The following pins have been changed in the "208-Pin PQFP" table on page 68: Pin Number Function Pin Number Function 23 I/O (GLMX1) 128 GL3 24 GL1 129 PPECL2 (I/P) 26 NPECL1 132 NPECL2 28 PPECL1 (I/P) 134 GL4 30 GL2 135 I/O (GLMX2) The following pins have been changed in the "456-Pin PBGA" table on page 74: Pin Number Function Pin Number Function M1 GL1 N22 NPECL2 M2 GL2 N23 GL3 M22 GL4 N25 I/O (GLMX2) N2 I/O (GLMX1) P5 NPECL1 N4 PPECL1 (I/P) P26 PPECL2 (I/P) v3.0 Page page 1 page 3 page 3 page 4 page 10 page 10 page 12 page 15 page 15 page 15 page 16 to page 20 page 21 page 25 page 28 page 30 page 32 page 35 page 36 page 37 page 38 page 39 page 60 page 63 page 65 page 68 page 74 131 Pr o A S I C P L U S F la s h F a m il y F P GA s Previous version v2.0 (continued) 132 Changes in current version (Advanced v3.0) The following pins have been changed in the "144-FBGA Pin" table on page 86: Pin Number Function Pin Number Function C2 GL2 F9 GL4 D12 I/O (GLMX2 )F11 PPECL2 (I/P E11 NPECL2 F12 GL3 F1 GL1 G1 PPECL1 (I/P) F3 I/O (GLMX1) G4 NPECL1 The following pins have been changed in the "256-Pin FBGA" table on page 89: Pin Number Function Pin Number Function H1 GL1 H16 GL4 H2 NPECL1 J1 GL2 H3 I/O (GLMX1) J2 PPECL1 (I/P) H13 I/O (GLMX2) J13 PPECL2 (I/P) H14 NPECL2 J16 GL3 The following pins have been changed in the"484-Pin FBGA" table on page 96: Pin Number Function Pin Number Function L4 GL1 L19 GL4 L5 NPECL1 M4 GL2 L6 I/O (GLMX1) M5 PPECL1 (I/P) L16 I/O (GLMX2) M16 PPECL2 (I/P) L17 NPECL2 M19 GL3 The following pins have been changed in the "676-FBGA Pin" table on page 103: Pin Number Function Pin Number Function N1 GL1 N25 GL4 N3 I/O (GLMX1) P1 GL2 N5 NPECL1 P5 PPECL1 (I/P) N22 GL3 P22 I/O (GLMX2) N24 NPECL2 P24 PPECL2 (I/P) The following pins have been changed in the "896 FBGA Pin" table on page 112: Pin Number Function Pin Number Function R2 I/O (GLMX1) T3 GL2 R4 NPECL1 T4 PPECL1 (I/P) R5 GL1 T26 PPECL2 (I/P) R27 NPECL2 T27 GL4 R29 I/O (GLMX2) T28 GL3 The following pins have been changed in the "1152 FBGA Pin" table on page 124: Pin Number Function Pin Number Function U4 I/O (GLMX1) U29 NPECL2 U6 NPECL1 U31 I/O (GLMX2) U7 GL1 V28 PPECL2 (I/P) V5 GL2 V29 GL4 V6 PPECL1 (I/P) V30 GL3 v3.0 Page page 86 page 89 page 96 page 103 page 112 page 124 Pr o A SI C P L U S F la s h F a m il y F P GA s Previous version Advanced v0.7 (Advanced v0.6) Advanced v0.5 Changes in current version (Advanced v3.0) The "Product Availability" table on page 4 was updated. The "Array Coordinates" section on page 10 and Table 2 are new. The "Power-up Sequencing" section on page 12 is new. Table 4 on page 11 was updated. The "Timing Control and Characteristics" section on page 15 was updated. Physical Implementation, Functional Description, Lock Signal, and PLL Configuration Options are new. Figure 14 on page 17 was updated. Figure 15 on page 18 was updated. Sample Implementations, Adjustable Clock Delay, and the "Clock Skew Minimization" section on page 16 are new. Figure 16, Figure 17, Figure 18, Figure 19, and Figure 20 are new. The "PLL Electrical Specifications" table on page 22 is new. The "Design Environment" section on page 27 was updated. Figure 26 on page 27 was updated. The "Calculating Typical Power Dissipation" section on page 29 was updated. The "DC Electrical Specifications (VDDP = 2.5V 0.2V)1" table on page 32 was updated. The "DC Electrical Specifications (VDDP = 3.3V 0.3V and VDD 2.5V 0.2V)1" table on page 33 was updated. The "DC Specifications (3.3V PCI Operation)1" table on page 34 was updated. The "Tristate Buffer Delays" section on page 36 (the figure and table) have been updated. The "Output Buffer Delays" section on page 37 (the figure and table) have been updated. The "Input Buffer Delays" table on page 38 was updated. The "Global Input Buffer Delays" table on page 38 was updated. The "Predicted Global Routing Delay*" table on page 39 was updated. The "Global Routing Skew" table on page 39 was updated. The "Sample Macrocell Library Listing*" table on page 40 was updated. The "Pin Description" section on page 61 was updated. GLMX is new. The "Recommended Design Practice for VPN/VPP" section on page 62 was updated. Pin AK31 of FG1152 for the APA1000 changed to VPP. The "Features and Benefits" section on page 1 were updated. The "ProASICPLUS Product Profile" table on page 1 was updated. The "Ordering Information" section on page 3 was updated. The "Plastic Device Resources" table on page 3 was updated. The "Product Plan" table on page 4 was updated. Table 1 on page 10 was updated. Figure 12 on page 15 was updated. The "Design Environment" section on page 23 was updated. The "Package Thermal Characteristics" table on page 24 was updated. The "Calculating Power Dissipation" section on page 25 was updated. The "Absolute Maximum Ratings*" table on page 26 was updated. The "Programming and Storage and Operating Temperature Limits" table on page 26 was updated. The "Supply Voltages" table on page 26 was updated. The "Recommended Operating Conditions" table on page 26 was updated. The "DC Electrical Specifications (VDDP = 2.5V 0.2V)1" table on page 27 was updated. The "DC Electrical Specifications (VDDP = 3.3V 0.3V and VDD 2.5V 0.2V)1" table on page 28 was updated. The "Synchronous Write and Read to the Same Location" figure on page 44 was updated. The "Asynchronous Write and Synchronous Read to the Same Location" figure on page 45 was updated. The "Asynchronous FIFO Read" figure on page 50 was updated. The "Pin Description" section on page 57 has been updated. The "Recommended Design Practice for VPN/VPP" section on page 57 is new. The "100-Pin TQFP" figure on page 62 is new. The "484-Pin FBGA" figure on page 96 is new. The description for the VPN pin has changed. v3.0 Page page 4 page 10 page 12 page 11 page 15 to page 16 page 17 page 18 page 16 page 19 to page 21 page 22 page 27 page 27 page 29 page 32 page 33 page 34 page 36 page 37 page 38 page 38 page 39 page 39 page 40 page 61 page 62 page 128 page 1 page 1 page 3 page 3 page 4 page 10 page 15 page 23 page 24 page 25 page 26 page 26 page 26 page 26 page 27 page 28 page 44 page 45 page 50 page 57 page 57 page 62 page 96 page 57 133 P r o A S IC P L U S F l a sh F a m ily F P GA Previous version Advanced v0.4 Changes in current version (Advanced v3.0) Page The "Plastic Device Resources" table on page 3 has been updated. Figure 12 and Figure 13 on page 15 have been updated. The "Tristate Buffer Delays" table on page 31 has been updated. The "Output Buffer Delays" table on page 32 has been updated. The "Input Buffer Delays" table on page 33 has been updated. The "Global Input Buffer Delays" table on page 34 has been updated. The "456-Pin PBGA" table on page 74 has been updated. The "676-FBGA Pin" table on page 103 has been updated. The "ProASICPLUS Product Profile" figure on page 1 has been changed. The "Plastic Device Resources" figure on page 3 has been updated. The Supply Voltages table on page 10 has been updated. WDATA has ben changed to DI, and RDATA has been changed to DO to make them consistent with the signal names found in the Macro Library Guide. page 3 page 15 page 31 page 32 page 33 page 34 page 74 page 103 page 1 page 3 page 10 page 19 and page 20 The "Design Environment" figure on page 23 and Figure 18 on page 23 have been page 23 updated. and page 23 The table in the "Package Thermal Characteristics" section on page 24 has been updated. page 24 The "Calculating Power Dissipation" section on page 25 is new. page 25 The "Programming and Storage and Operating Temperature Limits" section on page 26 is page 26 new. The "Supply Voltages" section on page 26 has been updated. page 26 The "DC Electrical Specifications (VDDP = 2.5V 0.2V)1" table on page 27 was updated. page 27 The "DC Electrical Specifications (VDDP = 3.3V 0.3V and VDD 2.5V 0.2V)1" table on page 28 page 28 was updated. The "AC Specifications (3.3V PCI Revision 2.2 Operation)" table on page 30 was updated. page 30 The "Clock Conditioning Circuit" section on page 14 was updated. page 14 Figure 12 on page 15 was updated. page 15 Figure 13 on page 15 is new. page 15 Tables 5, 6, and 7 from Advanced v0.3 were removed. The "Memory Block SRAM Interface Signals" figure on page 19 was updated. page 19 The "Memory Block FIFO Interface Signals" figure on page 48 was updated. page 48 All pinout tables have been updated, and several packages are new: 208-Pin PQFP - APA150, APA300, APA450, APA600 456-Pin PBGA - APA150, APA300, APA450, APA600 144-Pin FBGA - APA150, APA300, APA450 256-Pin FBGA - APA150, APA300, APA450, APA600 676-Pin FBGA - APA600 Figure 15 on page 21 has been updated page 21 Figure 13 on page 19 and Figure 14 on page 20 have been updated. Advanced v0.3 Advanced v0.1 D at a s h e et C a t e g o r i e s In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production." The definition of these categories are as follows: P rod uct B ri ef The product brief is a modified version of an advanced datasheet containing general product information. This brief summarizes specific device and family information for unreleased products. Adv anc ed This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. Unm ar ked (pr odu ct ion) This datasheet version contains information that is considered to be final. 134 v3.0 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. http://www.actel.com Actel Corporation Actel Europe Ltd. Actel Japan Actel Hong Kong 955 East Arques Avenue Sunnyvale, California 94086 USA Tel: (408) 739-1010 Fax: (408) 739-1540 Dunlop House, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Tel: +44 (0)1276 401450 Fax: +44 (0)1276 401490 EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Tel: +81 03-3445-7671 Fax: +81 03-3445-7668 39th Floor One Pacific Place 88 Queensway Admiralty, Hong Kong Tel: 852-22735712 5172161-8/5.03