APA1000 - Actel Corporation

May 2003 1

v3.0

ProASICPLUS Flash Family FPGAs TM

Features and Benefits

High Capacity

• 75,000 to 1 million System Gates

• 27k to 198kbits of Two-Port SRAM

• 66 to 712 User I/Os

Reprogrammable Flash Technology

•0.22µ 4LM Fl a sh-b a s ed CMO S Proc e ss

• Live at Power-Up, Single-Chip Solution

• No Configuration Device Required

• Retains Programmed Design duri ng Power-Down/

Power-Up Cyc les

Performance

• 3.3V, 32-bit PC I (up to 50 MHz)

• Two Integrated PLLs

• External System Performance up to 150 MHz

Secure Programming

• The Industry’s Most Effective Security Key (FlashLock)

Prevents Read Back o f Programming Bitstream

Low Power

• Low Impeda nce Flash Switches

• Segmented H ierarchical Routing Structure

• Small, Efficient, Configurable (Combinatorial or

Sequential) Logic Cells

High Performance Routing Hierarchy

• Ul tra-Fast Local and Long-Line N e twork

• High Speed Very Long-Line Network

• High Performance, Low Skew, Splittable Global Network

• 100% Routability and Utilization

I/O

• Schmitt-Trigger Option on Every Input

• Mixed 2.5V/3.3V Support with Individually-Selectable

Voltage and Slew Rate

• Bidirectional Global I/Os

• Compliance with PCI Specification Revision 2.2

• Bound ar y-Sca n Te st IEEE Std. 114 9.1 (JTA G) Compli a nt

• Pin Compatible Packages across ProASICPLUS Fa mi ly

Unique Clock Conditioning Circuitry

• PLL with Fl ex ib le Pha se , M ul tip ly / Div id e and De l ay

Capabilitie s

• Internal and/or External Dynamic PLL Configuration

• Two LVPECL Differential Pairs for Clock or Data Inputs

Standard FPGA and ASIC Design Flow

• Flexibility with Choice of Industry-Standard Frontend

Tools

• Effi c ient De s ign th rou gh Fr o nt end Tim in g and Gate

Optimization

ISP Support

• In-System Programming (ISP) via JTAG Port

SRAMs and FIFOs

• ACTgen Netlist G eneration Ensures Optimal Usage of

Embedded Memory B locks

• 24 SRAM and FIFO Configurations with Synchronous and

Asynchronous Operation up to 150MHz (typical)

ProASICPLUS Product Profile

Device APA075 APA150 APA300 APA450 APA600 APA750 APA1000

Maximum System Gates 75,000 150,000 300,000 450,000 600,000 750,000 1,000,000

Maximum Tiles (Registers) 3,072 6,144 8,192 12,288 21,504 32,768 56,320

Embedd ed RAM Bits (k=1,024 bits) 27k 36k 72k 108k 126k 144k 198k

Embedd ed RAM Blocks (256x9) 12 16 32 48 56 64 88

LVPECL 222 2 2 22

PLL 222 2 2 22

Global N e twork s 444 4 4 44

Maximum Clo cks 24 32 32 48 56 64 88

Maximum User I/Os 158 242 290 344 454 562 712

JTAG ISP Yes Yes Yes Yes Yes Yes Yes

PCI Yes Yes Yes Yes Yes Yes Yes

Package (by pin count)

TQFP

PQFP

PBGA

FBGA

100, 144

208

144

100

208

456

144, 256

208

456

144, 256

208

456

144, 256, 484

208

456

256, 484, 676

208

456

676, 896

208

456

896, 1152

ProASICPLUS Flash Family FPGAs

2v3.0

General Description

The ProASICPLUS family of devices, Actel’s second

generation Flash FPGAs, offers enhanced performance over

Actel’s ProASIC family. It combines the advantages of ASICs

with the benefits of programmable devices through

nonvolatile Flash technology. This enables engineers to

create high-density systems using existing ASIC or FPGA

design flows and tools. In addition, the ProASICPLUS family

offers a unique clock conditioning circuit based on two

on-board phase-locked loops (PLLs). The family offers up to

1 million system gates, supported with up to 198kbits of

2-port SRAM and up to 712 user I/Os, all providing 50 MHz

PCI performance.

Advantages to the designer extend beyond performance.

Unlike SRAM-based FPGAs, four levels of routing hierarchy

simplify routing, while the use of Flash technology allows all

fu nc t i onal i ty t o be l i v e at p ow e r - up . No ex t e rn a l Bo o t P RO M

is required to support device programming. While on-board

security mechanisms prevent all access to the program

information, reprogramming can be performed in-system to

support future design iterations and field upgrades. The

device’s architecture mitigates the complexity of ASIC

migration at higher user volume. This makes ProASICPLUS a

cost-effective solution for applications in the networking,

communications, computing, and avionics markets.

The ProASICPLUS family achieves its nonvolatility and

reprogrammability through an advanced Flash-based

0.22µm LVCMOS process with four-layers of metal. Standard

CMOS design techniques are used to implement logic and

control functions, including the PLLs and LVPECL inputs.

This results in predictable performance fully compatible

with gate arrays.

The ProASICPLUS architecture provides granularity

comparable to gate arrays. The device core consists of a

Sea-of-Tiles. Each tile can be configured as a flip-flop,

latch, or 3-input/1-output logic function by programming the

appropriate Flash switches. The combination of fine

granularity, flexible routing resources, and abundant Flash

switches allow 100% utilization and over 95% routability for

highly congested designs. Tiles and larger functions are

interconnected through a 4-level routing hierarchy.

Embedded 2-port SRAM blocks with built-in FIFO/RAM

control logic can have user-defined depth and width. Users

can also select programming for synchronous or

asynchronous operation, as well as parity generations or

checking.

The unique clock conditioning circuitry in each device

includes two clock conditioning blocks. Each block provides

a PLL core, delay lines, phase shifts (0°, 90°, 180°, 270°),

and clock multipliers/dividers, as well as the circuitry

needed to provide bidirectional access to the PLL. The PLL

block contains four programmable frequency dividers,

which allow the incoming clock signal to be divided by a

wide range of factors from 1 to 64. The clock conditioning

circuit also delays or advances the incoming reference clock

up to 8 ns (in increments of 0.25 ns). The PLL can be

configured inter nally or externally during operation wit hout

redesigning or reprogramming the part. In addition to the

PLL, there are two LVPECL differential input pairs to

accommodate high speed clock and data inputs.

To support customer needs for more comprehensive, lower

cost board-level testing, Actel’s ProASICPLUS devices are

fully compatible with IEEE Standard 1149.1 for test access

port and boundary-scan test architecture. For more

information concerning the Flash FPGA implementation,

please refer to the “Boundary Scan (JTAG)” section on

page13.

ProASICPLUS devices are available in a variety of

high-performance plastic packages. Those packages and the

performance features discussed above are described in

more detail in the following sections.

v3.0 3

ProASICPLUS Flash Family FPGAs

Ordering Information

Plastic Device Resources

APA1000 FG

Part Number

Speed Grade

Blank =Standard Speed

= 20% Slower than Standard

P ackage Type

PQ =Plastic Quad Flat Pack (0.5mm pitch)

TQ =Thin Quad Flat Pack (1.4mm pitch)

FG =Fine Pitch Ball Grid Array (1.0mm pitch)

BG =Plastic Ball Grid Array (1.27mm pitch)

1152 I

Package Lead Count

Application (Ambient Temperature Range)

Blank = Commercial (0 to +70˚ C)

I = Industrial (-40 to +85˚ C)

PP = Pre-production

ES = Engineering Silicon (Room Temperature Only)

150,000 Equivalent System Gates

APA150 =

75,000 Equivalent System Gates

APA075 =

APA450

APA600

APA750

APA1000

450,000 Equivalent System Gates

600,000 Equivalent System Gates

750,000 Equivalent System Gates

1,000,000 Equivalent S

stem Gates

APA300

300,000 Equivalent System Gates

User I/Os*

Device TQFP

100-Pin TQFP

144-Pin PQFP

208-Pin PBGA

456-Pin FBGA

144-Pin FBGA

256-Pin FBGA

484-Pin FBGA

676-Pin FBGA

896-Pin FBGA

1152-Pin

APA075 66 107 158 100

APA150 66 158 242 100 186

APA300 158 290 100 186

APA450 158 344 100 186 344

APA600 158 356 186 370 454

APA750 158 356 454 562

APA1000 158 356 642 712

Package De fin ition s

TQFP = Thin Quad Flat Pack, PQFP = Plastic Quad Flat Pack, PBGA = Plastic Ball Grid Array, FBGA = Fine Pit ch Ball Grid Array

*Each pair of PECL I/Os w ere counted as one user I/O.

ProASICPLUS Flash Family FPGAs

4v3.0

Product Availability

Speed Grade Application

Std. –F* C I

APA075 Device

100-Pin Thin Quad Flat Pack (TQF P) ✔✔ ✔ ✔

144-Pin Thin Quad Flat Pack (TQFP) PP PP PP PP

208-Pin Plastic Quad Flat Pack (PQFP) ✔✔ ✔ ✔

144-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔ ✔ ✔

APA150 Device

100-Pin Thin Quad Flat Pack (TQF P) ✔✔ ✔ ✔

208-Pin Plastic Quad Flat Pack (PQFP) ✔✔ ✔ ✔

456-Pin Plastic Ball Grid Array (PBGA) ✔✔ ✔ ✔

144-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔ ✔ ✔

256-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔ ✔ ✔

APA300 Device

208-Pin Plastic Quad Flat Pack (PQFP) ✔✔ ✔ ✔

456-Pin Plastic Ball Grid Array (PBGA) ✔✔ ✔ ✔

144-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔ ✔ ✔

256-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔ ✔ ✔

APA450 Device

208-Pin Plastic Quad Flat Pack (PQFP) ✔✔ ✔ ✔

456-Pin Plastic Ball Grid Array (PBGA) ✔✔ ✔ ✔

144-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔ ✔ ✔

256-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔ ✔ ✔

484-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔ ✔ ✔

APA600 Device

208-Pin Plastic Quad Flat Pack (PQFP) ✔✔ ✔ ✔

456-Pin Plastic Ball Grid Array (PBGA) ✔✔ ✔ ✔

256-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔ ✔ ✔

484-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔ ✔ ✔

676-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔ ✔ ✔

APA750 Device

208-Pin Plastic Quad Flat Pack (PQFP) ✔✔ ✔ ✔

456-Pin Plastic Ball Grid Array (PBGA) ✔✔ ✔ ✔

676-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔ ✔ ✔

896-Pin Plastic Ball Grid Array (FBGA) ✔✔ ✔ ✔

APA1000 Device

208-Pin Plastic Quad Flat Pack (PQFP) ✔✔ ✔ ✔

456-Pin Plastic Ball Grid Array (PBGA) ✔✔ ✔ ✔

896-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔ ✔ ✔

1152- Pin Fine Pitch Ball Grid Array (FBGA) ✔✔ ✔ ✔

Note: *–F part s are only available as com mercial temperature devices.

Applications: C = Commercial Availability: ✔=Available

I = Industrial PP= Product Planned

v3.0 5

ProASICPLUS Flash Family FPGAs

ProASICPLUS Architecture

The proprietary ProASICPLUS architecture provides

granularity comparable to gate arrays.

The ProASICPLUS device core consists of a Sea-of-Tiles™

(Figure 1). Each tile can be configured as a 3-input logic

function (e.g., NAND gate, D-Flip-Flop, etc.) by

programming the appropriate Flash switch

interconnections (Figure2 on page 6 and Figure 3 on

page6). Tiles and larger functions are connected with any

of the four levels of routing hierarchy. Flash switches are

distributed throughout the device to provide nonvolatile,

reconfigurable interconnect programming. Flash switches

are programmed to connect signal lines to the appropriate

logic cell inputs and outputs. Dedicated high-performance

lines are connected as needed for fast, low-skew global

signal distribution throughout the core. Maximum core

utilizati on is possible for virtually any design.

ProASICPLUS devices also contain embedded two-port

SRAM blocks with built-in FIFO/RAM control logic.

Programming options include synchronous or asynchronous

operation, two-port RAM configurations, user defined depth

and width, and parity generation or checking. Please see

the “Embedded Memory Configurat ions” section on page21

for more informatio n.

Flash Switch

Unlike SRAM FPGAs, ProASICPLUS uses a live on power-up

ISP Flash switch as its programming element.

In the ProASICPLUS Flash switch , two transistors share the

floating gate, which stores the programming information.

On e is the sensing transistor, which is only used for writing

and verification of the floating gate voltage. The other is the

switching transistor. It can be used in the architecture to

connect/separat e routing nets or to configure logic. It is also

used to erase the floating gate (Figure2 on page 6).

Logic Tile

The logic tile cell (Figure 3 on page 6) has three inputs (any

or all of which can be inverted) and one output (which can

connect to both ultra-fast local and efficient long-line

routing resources). Any three-input, one-output logic

function (except a three-input XOR) can be configured as

one tile. The tile can be configured as a latch with clear or

set or as a flip-flop with clear or set. Thus, the tiles can

flexibly map logic and sequential gates of a design.

Figure 1 • The ProASICPLUS Device Arch itecture

256x9 Two-Port SRAM

or FIFO Block

Logic Tile

256x9 Two Port SRAM

or FIFO Block

RAM Block

I/Os

ProASICPLUS Flash Family FPGAs

6v3.0

Routing Resources

The routing structure of ProASICPLUS devices is designed to

provide high performance through a flexible four-level

hierarchy of routing resources: ultra-fast local resources,

efficient long-line resources, high speed very long-line

resources, and high performance global networks.

The ultra-fast local resources are dedicated lines that allow

the output of each tile to connect directly to every input of

the eight surrounding tiles (Figure 4 on page 7).

The efficient long-line resources provide routing for longer

distances and higher fanout connections. These resources

vary in length (spanning 1, 2, or 4 tiles), run both vertically

and horizontally, and cover the entire ProASICPLUS device

(Figure 5 on page7). Each tile can drive signals onto the

efficient long-line resources, which can in turn, access every

input of every tile. Active buffers are inserted automatically

by routing software to limit the loading effects due to

distance and fanout.

The high-speed very long-line resources, which span the

entire device with minimal delay , are used to route very long

or very high fanout nets. (Figure 6 on page 8).

The high-performance global networks are low skew, high

fanout nets that are accessible from external pins or from

internal logic (Figure 7 on page 9). These nets are typically

used to distribute clocks, resets, and other high fanout nets

requiring a minimum skew. The global networks are

implemented as clock trees, and signals can be introduced

at any junction. These can be employed hierarchically with

signals accessing every input on all tiles.

Figure 2 • Flash Switch

Figure 3 • Core Logic Tile

Switch In

Switch Out

Word

Floating Gate

Sensing Switching

Local Routing

In 1

In 2 (CLK)

In 3 (Reset)

Efficient Long-Line Routing

v3.0 7

ProASICPLUS Flash Family FPGAs

Figure 4 • Ultra-Fast Local Resources

Figure 5 • Efficie nt Long-Line Resources

Inputs

Output

Ultra-Fast

Local Lines

(connects a tile to the

adjacent tile, I/O buffer,

or memory block)

LL L

LLLLLL

LL LLLL

LLLLLL

Logic Cell

Spans 1 Tile

Spans 2 Tiles

Spans 4 Tiles

Spans 1 Tile

Spans 2 Tiles

Spans 4 Tiles

Logic Tile

ProASICPLUS Flash Family FPGAs

8v3.0

Figure 6 • High Speed Very Long-Line Resources

PAD RING

I/O RING

High Speed Very Long-Line Resouces

SRAM

v3.0 9

ProASICPLUS Flash Family FPGAs

Clock Resources

The ProASICPLUS family offers powerful and flex ible control

of circuit timing through the use of analog circuitry. Each

chip has two clock conditioning blocks containing a

phase-locked loop (PL L) core , delay lines, phase shifter (0°,

90°, 180°, 270°), clock multiplier/dividers and all the

circuitry needed for the selection and interconnection of

inputs to the global network (thus providing bidirectional

access to the PLL). This permits the PLL block to drive

inputs and/or outputs via the two global lines on each side

of the chip (four total lines). This circuitry is discussed in

more detail in the “ProASICPLUS Clock Management

System” section on page 15.

Clock Trees

One of the main architectural benefits of ProASICPLUS is

the set of power and delay friendly global networks.

ProASICPLUS offers four global trees. Each of these trees is

based on a network of spines and ribs that reach all the tiles

in their regions (Figure 7). This flexible clock tree

architecture allows users to map up to 88 different

internal/external clocks in an APA1000 device. Details on

the clock spines and various numbers o f the family are g iven

in Table 1 on page 10.

The flexible use of the ProASICPLUS clock spine allows the

designer to cope with several design requirements. Users

implementing clock resource intensive applications can

easily route external or gated internal clocks using global

routing spines. Users can also drastically reduce delay

penalties and save buffering resources by mapping critical

high-fanout nets to spines. For design hints on using these

features, refer to Actel’s Efficient Use of ProASIC Clock

Trees application note.

Note: This figure shows routing for only one global path.

Figure 7 • High Performance Global Network

PAD RING

I/O RING

Global

Pads Global

Pads

High Performace

Global Network

Global Networks

Global Spine

Global Ribs

Scope of Spine

(Shaded area

plus local RAMs

and I/Os)

Top Spine

Bottom Spine

ProASICPLUS Flash Family FPGAs

10 v3.0

Array Coordinates

During many place-and-route operations in Actel’s Designer

software tool, it is possible to set constraints that require

array coordinates.

Table 2 is provided as a re ference. The array coordinates are

measured from the lower left (0,0). They can be used in

region constraints for specific groups, designated by a

wildcard, and containing core cells, I/Os, and memories.

I/O and cell coordinates are used for placement constraints.

Two coordinate systems are needed because there is not a

one-to-one correspondence between I/O cells and core cells.

In addition, the I/O coordinate system changes depending

on the die/package combination.

Core cell coordinates start at the lower left corner (1,1) or

(1,5) if memories are present at the bottom. Memory

coordinates use the same system and are indicated in

Table 2. The memory coordinates for an APA1000 are

illustrated in Figure 8. For more information on how to use

constraints, see the Desi gner Use r’s Gu ide for ProASICPLUS

software tools.

Table 1 • Clock Spines

APA075 APA150 APA300 APA450 APA600 APA750 APA1000

Global Clock Networks (Trees) 4444444

Clock Spines/Tree 6 8 8 12 14 16 22

Total Spines 24 32 32 48 56 64 88

Top or Bottom Spin e Hei ght ( Tiles ) 16 24 32 32 48 64 80

Tiles in Each Top or Bottom Spine 512 768 1,024 1,02 4 1,536 2,048 2,560

Total Tiles 3,072 6,144 8,192 12,288 21,504 32,768 56,320

Table 2 • Array Coordinates

Device

Logic Tile Memory Rows

AllMin. Max. Bottom Top

x y x y y y Min. Max.

APA075 1 1 96 32 – (33,33) or (33, 35) 0,0 97, 37

APA150 1 1 128 48 – (49,49) or (49, 51) 0,0 129, 53

APA300 1 5 128 68 (1,3) or (1,5) (69,69) or (69, 71) 0,0 129, 73

APA450 1 5 192 68 (1,3) or (1,5) (69,69) or (69, 71) 0,0 193, 73

APA600 1 5 224 100 (1,3) or (1,5) (101,101) or (101, 103) 0,0 225, 105

APA750 1 5 256 132 (1,3) or (1,5) (133,133) or (133, 135) 0,0 257, 137

APA1000 1 5 352 164 (1,3) or (1,5) (165,165) or (165, 167) 0,0 353, 169

Figure 8 • Core Cell Coordinates for the APA1000

(1,5)

(1,1)

Core

(1,164)

(1,165)

(1,3)

(1,167)

Memory

Blocks

Memory

Blocks

(1,169)

(0,0)

(353,169)

(352,167)

(352,165)

(352,5)

(352,3)

(353,0)

(352,1)

v3.0 11

ProASICPLUS Flash Family FPGAs

Input/Output Blocks

To meet complex system demands, the ProASICPLUS family

offers devices with a large number of user I/O pins, up to

712 on the APA1000. If the I/O pad power supply (VDDP) i s

3.3V, each I/O can be selectively configured at the 2.5V and

3.3V threshold levels. Table 3 shows the available supply

voltage configurations (the PLL block uses an independent

2.5V supply on the AVDD and AGND pins). All I/Os include

ESD protection circuits. Each I/O has been tested to 2000V

to the human body model (per JESD22 (HMB)).

Six or seven standard I/O pads are grouped with a GND pad

and either a VDD (cor e power) or VDDP (I/O power) pad. Two

reference bias signals circle the chip. One protects the

cascaded output drivers while the other creates a virtual

VDD su pply f o r the I/O ring.

I/O pads are fully configurable to provide the maximum

flexibility and speed. Each pad can be configured as an

input, an output, a tristate driver, or a bidirectional buffer

(Figure 9 and Table 4).

Table 3 • ProASICPLUS I/O Power Supply Voltages

VDDP

2.5V 3.3V

Input Compatibility 2.5V 3.3V, 2.5V

Output Drive 2.5V 3.3V, 2.5V

Note: VDD is always 2.5V.

Figure 9 • I/O Block Schematic Representation

3.3V/2.5V

Signal Control

Pull-up

Control

Pad

3.3V/2.5V Signal Control Drive

Strength and Slew-Rate Control

Table 4 • I/O Features

Function Description

I/O pads configured as inputs • Individually selectable 2.5V or 3.3V threshold levels

• Optional pull-up resistor

• Optionally con figurabl e as Schmitt tr igger i nput. The Schmitt tr igger input option can

be configured as an input only, not a bidirectional buffer. This input type may be

slower tha n a stand ard i nput under certain conditions an d has a typical hystere sis of

0.35V. I/O macros with an “S” in the standard I/O library have added Schmitt

capabilities

• 3.3V PCI Compliant

I/O pads configured as outputs • Individually selectable 2.5V or 3.3V compliant output signals

– 2.5V – JEDEC JESD 8-5

– 3.3V – JEDEC JESD 8-A (LVTTL and LVCMOS)

• 3.3V PCI compliant

• Ability to drive LVTTL and LVCMOS levels

• Selectable drive strengths

• Selectable slew rates

• Tristate

I/O pads configured as bidirectional

buffers • Individually selectable 2.5V or 3.3V compliant output signals

– 2.5V – JEDEC JESD 8-5

– 3.3V – JEDEC JESD 8-A (LVTTL and LVCMOS)

• 3.3V PCI compliant

• Optional pull-up resistor

• Selectable drive strengths

• Selectable slew rates

• Tristate

ProASICPLUS Flash Family FPGAs

12 v3.0

Power-up Sequencing

While ProASICPLUS devices ar e live at power-up, the or der of

VDD and VDDP power-up is important during system start-up.

VDD should be powere d up before (or coincident with) VDDP

on ProASICPLUS devices. Failure to follow these guidelines

may result in undesirable pin behavior during system

start-up. For more information, refer Actel’s ProASICPLUS

Family Devices Power-Up Behavior application note.

LVPECL Input Pads

In addition to standard I/O pads and power pads,

ProASICPLUS devices have a single LVPECL input pad on

both the east and west sides of th e device, along with AVDD

and AGND pins to power the PLL block. The LVPECL pad

cell consists of an input buffer (containing a low voltage

differential amplifier) and a signal and its complement,

PPECL (I/P) (PECLN) and NPECL (PECLREF). The

LVPECL input pad cell differs from the standard I/O cell in

that it is operated from VDD only.

Since it is exclusively an input, it requires no output signal,

output enable signal, or output configuration bits. As a

special high-speed differential input, it a lso does not require

pull ups. Recommended termination for LVPECL inputs is

shown in Figure 10. The LVPECL pad cell compares

voltages, as illustrated in Figure 11, on the PPECL (I/P) pad

and the NPECL pad and sends the results to the global MUX

(Figure14 on page 16). This high speed, low skew output

essentially cont rols the clock conditioning circuit.

LVPECLs are designed to meet LVPECL JEDEC receiver

standard levels (Table 5).

Figur e 10 • Recommended Terminati on for LVPECL Inputs

Figur e 11 • LVPECL High and Low Threshold Values

Table 5 • LVPECL Receiver Specifications

Symbol Parameter Min. Max Units

VIH Input High Voltage 1.49 2.72 V

VIL Input Low Voltage 0.86 2.125 V

VID Differential Input Voltage 0.3 VDD V

PPECL

NPECL

From LVPECL Driver Data

Z = 50Ω

R = 100Ω

Voltage

2.72

2.125

1.49

0.86

v3.0 13

ProASICPLUS Flash Family FPGAs

Boundary Scan (JTAG)

ProASICPLUS devices are compatible with IEEE Standard

1149.1, which defines a set of hardware architecture and

mechanisms for cost-effective board-level testing. The basic

ProASICPLUS boundary-scan logic circuit is composed of the

TAP (test access port), TAP controller, test data registers,

and instruction register (Figure 12). This circuit supports

all mandatory IEEE 1149.1 instructions (EXTEST,

SAMPLE/PRELOAD and BYPASS) and the o ptional IDCODE

instruction (Table 6).

Each test section is accessed through the TAP, which has

five associated pins: TCK (test clock input), TDI and TDO

(test data input and output), T MS (test mode selector) and

TRST (test reset input). TMS, TDI and TRST are equipped

with pull-up resistors to ensure proper operation when no

input data is supplied to them. These pins are dedicated for

boundary-scan test usage. Actel recommends that a nominal

20kΩ pull-up resistor is added to TDO and T CK pins.

The TAP controller is a four-bit state machine (16 states)

that operates as shown in Figure 13 on page 14. The ‘1’s and

‘0’s represent the values that must be present at TMS at a

rising edge of TCK for the given state transition to occur. IR

and DR indicate that the instruction register or the data

ProASICPLUS devices have to be programmed at least once

for complete boundary-scan functionality to be available. If

boundary-scan functionality is required prior to partial

programming, refer to online t e ch nical support on the Actel

website and search for ProASICPLUS BSDL.

Figur e 12 • ProASICPLUS JTAG Boundary Scan Test Logic Cir cuit

Device

Logic

TDI

TCK

TMS

TRST

TDO

I/OI/OI/O I/OI/O

I/O

Bypass Register

Instruction

TAP

Controller

Test Data

Registers

Table 6 • Boundary-Scan Opcodes

Hex Opcode

EXTEST 00

SAMPLE/PRELOAD 01

IDCODE 0F

CLAMP 05

BYPASS FF

ProASICPLUS Flash Family FPGAs

14 v3.0

The TAP controller receives two control inputs (TMS and

TCK) and generates control and clock signals f or the rest of

the test logic architecture. On power-up, the TAP cont roller

enters the Test-Logic-Reset state. To guarantee a reset of

the controller from any of the possible states, TMS must

remain high for five TCK cycles. The TRST pin may also be

used to asynchronously place the TAP controller in the

Test-Logic-Reset state.

ProASICPLUS devices support three types of test data

registers: bypass, device identification, and boundary scan.

The bypass register is selected when no other register needs

to be accessed in a device. This speeds up test data transfer

to other devices in a test data path. The 32-bit device

identification register is a shift register with four fields

(lowest significant byte (LSB), ID number, part number and

version). The boundary-scan register observes and controls

the state of each I/O pin.

Each I/O cell has three boundary-scan register cells, each

with a serial-in, serial-out, parallel-in, and parallel-out pin.

The serial pins are used to serially connect all the

boundary-scan register cells in a device into a

boundary-scan register chain, which starts at the TDI pin

and ends at the TDO pin. The parallel ports are connect ed to

the internal core logic tile and the input, output, and control

ports of an I/O buffer to capture and load data into the

Figur e 13 • TAP Controller State Diagram

Test-Logic

Reset

Run-Test/

Idle Select-DR-

Scan

Capture-DR

Shift-DR

Exit-DR

Pause-DR

Exit2-DR

Update-DR

Select-IR-

Scan

Capture-IR

Shift-IR

Exit-IR

Pause-IR

Exit2-IR

Update-IR

11 00

110

v3.0 15

ProASICPLUS Flash Family FPGAs

Timing Control and Characteristics

ProASICPLUS Clock Management System

Introduction

ProASICPLUS devices provide designers with very flexible

clock conditioning capabilities. Each member of the

ProASICPLUS family contains two phase-locked loop (PLL)

blocks which perform the following functions:

• Clock Phase Adjustment via Programmable Delay (250 ps

steps from –8 ns to +8 ns)

• Clock Skew Minimization

• Clock Fre qu enc y Synth esi s

Each PLL has the following key features:

• Input Fre q ue nc y Ran ge (fIN) = 1.5 to 180 MHz

• Feedback Frequency Range (fVCO) = 1.5 to 180 MHz

• Outp ut F req ue nc y R an g e ( f OUT) = 6 to 18 0 M Hz

• Output Phase Shift = 0 °, 90 °, 180 °, and 270 °

• Output Duty Cycle = 50%

• Low Output Jitter (max at 25° C)

–f

VCO <10 MHz. Jitter ±1% or better

– 10 MHz < fVCO < 60 MHz. Jitter ±2% or better

–f

VCO > 60 MHz. Jitter ±1% or better

• Maximum Acquisition Time = 80µ s

• Low Power Consumption – 6.9 mW (max – analog supply)

+ 7.0µW/ MHz (m ax – d ig it a l su pp ly)

Physical Implementation

Each side of the chip contains a clock conditioning circuit

based upon a 180 MHz PLL block (Figure 14 on page16).

Two global multiplexed lines extend along each side of the

chip to provide b idirectional access to the PLL on that side

(neither MUX can be connected to the opposite side's PLL).

Each global line has optional LVPECL input pads

(described below). The global lines may be driven by eit her

the LVPECL global input pad or the outputs from the PLL

block or both. E ach global line can be driven by a different

output from the PLL. Unused global pi ns can be configured

as regular I/Os or left unconnected. They default to an input

with pull-up. The two signals available to drive the global

networks are as follows (Figure 15 on page 17):

Global A (secondary clock)

• Output from Global MUX A

• Condition ed ve r s i on of PLL outp ut ( f OUT) – delayed or

advanced

• Divided version of either of the above

• Further delayed version of either of the above (0.25 ns,

0.50 ns, or 4.00 ns delay)1

Global B

• Output from G lobal MUX B

• Delayed or advanced version of fOUT

• Divided version of either of the above

• Further delayed version of either of the above (0.25 ns,

0.50 ns, or 4.00 ns delay)1

Functional Description

Each PLL block contains four programmable dividers as

shown in Figure 14 on page 16. These allow frequency

scaling of the input clock signal as follows:

• The n divider divides the input clock by integer factors

fro m 1 t o 32 .

• The m divider in the feedback path allows multiplication

of th e input clo c k by in te ge r factor s rang ing from 1 t o 6 4 .

• The t wo di vide rs t oge ther c an impl emen t any com bina tion

of mul t ip li c ati o n an d di v ision resu lt ing in a cl o ck

frequency between 24 and 180 MHz exiting the PLL core.

This clock has a fixed 50% duty cycle.

• The output freq uenc y of the PLL core is gi ven by the

following formula (fREF is the reference clock frequency):

fOUT = fREF * m/n

• The third and fourth dividers (u and v) permit the signals

appl ied to th e gl oba l n etw ork to eac h be fu rth er div ided b y

in teger factors ranging from 1 to 4.

The implementations:

fGLB = m/(n*u)

fGLA = m/(n*v)

enable the user to define a wide range of frequency

multipliers and divisors. The clock conditioning cir cuit can

advance or delay the clock up to 8 ns (in increments of

0.25ns) relative to the positive edge of the incoming

reference clock. The syst em also allow s for the selection of

output frequency clock phases of 0°, 90°, 180°, and 270°.

Prior to the application of signals to the rib drivers, they

pass through programmable delay units, one per global

network. These units permit the delaying of global signals

relative to other signals to assist in the control of input

set-up times. Not all possible combinations of input and

output modes can be used. The degrees of fre edom available

in the bidirectional global pad system and in the clock

conditioning circuit have been restricted. This avoids

unnecessary and unwieldy design kit and software work.

1. This mode is available through the delay feature of the Global MUX driver.

ProASICPLUS Flash Family FPGAs

16 v3.0

Lock Signal

A Lock signal (Active High) is provided (using the ACTgen

PLL development tool) to indicate that the PLL has locked

to the incoming clock signal. Users can employ the Lock

signal as a soft reset of the logic driven by GLB and/or GLA.

PLL Configuration Options

The PLL can be configured during design (via

Flash-configuration bits set in the programming bitstream)

or dynamically during device operation, thus eliminating the

need for complete reprogramming. The dynamic

configuration bits are loaded into a serial-in/parallel-out

shift register provided in the clock conditioning circuit of

each PLL and then latched into the PLL block. The JTAG

ports can be used along with a built-in user JTAG interface

hardware to load the configuration shift register externally.

Another option is internal dynamic configuration via user-

designed hardware. Refer to Actel’s ProASICPLUS PLL

Dynam ic R eco nfig uratio n U si ng JTA G application note for

more information.

For information on the clock conditioning circuit, refer to

the, Actel’s Using ProASICPLUS Clock Conditioning

Circuits application note.

Notes:

1. FBDLY is a programmable delay line from 0 to 4 ns in 250 ps increments.

2. DLYA, DLYB, DLYAFB is a programmable delay line with values 0, 250 ps, 500 ps, and 4 ns.

Figur e 14 • PLL Block – Top-Level View and Detailed PLL Block D iagr am

Clock Conditioning Circuitry Detailed Block Diagram

÷n

÷m÷u

÷v

PLL Core

External Feedback

Global MUX B OUT

Global MUX A OUT

GLB

GLA

0˚

90˚

180˚

270˚

External Feedback Signal

AVDD AGND GND

GLA

GLB

Dynamic

Configuration Bits

Flash

Configuration Bits

Clock Conditioning

Circuitry

(Top level view)

-Global MUX A OUT

Global MUX B OUT

VDD

See Figure 13

on page 17

Input Pins to the PLL

FBDLY DLYAFB

DLYB

DLYA

v3.0 17

ProASICPLUS Flash Family FPGAs

Sample Implementations

Frequency Synthesis

Figure16 on page 18 illustrates an example where the PLL

is used to multiply a 33 MHz external clock up to 133 MHz.

Figure17 on page 18 uses two dividers to synthesize a

50 MHz output clock from a 40 MHz input reference clock.

The input frequency of 40 MHz is multiplied by 5 and

divided by 4, giving an output clock (GLB) frequency of 50

MHz. When dividers are used, a given r atio can be g enerated

in multiple ways, allowing the user to stay within the

operating frequency ranges of the PLL. For example, in this

case the input divider could have been 2 and the output

divider also 2, giving us a division of the input frequency by

4 to go with the feedback loop division (effective

multiplication) by 5.

Adjustable Clock Delay

Figure18 on page 19 illustrates the delay of t he inpu t clock

by employing one of the adjustable delay lines. This is easily

done in ProASICPLUS by bypassing the PLL core entirely and

using the output delay line. Notice also that the output

clock can be effectively advanced relative to the input clock

by using th e delay line in the feedback pat h. This is shown

in Figure 19 on page 19.

Clock Skew Minimization

Figure20 on page 20 indicates how feedback from the clock

network can be used to create minimal skew between the

distributed clock network and the "input" clock. The input

clock is fed to the reference clock input of the PLL. The

output clock (GLA) feeds a clock network. The feedback

input to the PLL uses a clock input delayed by a routing

network. The PLL th en adjusts the phase of t he input clock

to match the delayed clock, thus providing nearly zero

effective skew between the two clocks. Refer to Actel’s

Using ProASICPLUS Clock Conditioning Circuits

application note for more information.

Logic Tile Timing Characteristics

Timing characteristics for ProASICPLUS devices fall into

three categories: family dependent, device dependent, and

design dependent. The input and output buffer

characteristics are common to all ProASICPLUS family

members. Internal routing delays are device dependent.

Design dependency means that actual delays are not

determined until after placement and routing of the user’s

design are complete. De lay values may then be determined

by using the Timer utility or performing simulation with

post-layout delays.

Note: When a sig nal from an I/O til e is connected to the co re, it cannot be connected to the Glo bal MUX at the same time .

Figur e 15 • Input Connectors to ProASICPLUS Clock Conditioning Circuitry

Configuration Tile

PECL Pad Cell

GLMX

Std. Pad Cell

NPECL

PPECL

CORE

Package Pins Physical I/O

Buffers Global MUX

External

Feedback

Global MUX B

OUT

Global MUX A

OUT

Legend

Physical Pin

DATA Signals to the Core

DATA Signals to the PLL Block

DATA Signals to the Global MUX

Control Signals to the Global MUX

ProASICPLUS Flash Family FPGAs

18 v3.0

Critical Nets and Typical Nets

Propagation delays are expressed only for typical nets,

which are used for initial design performance evaluation.

Critical net delays can then be applied to the most timing

critical paths. Critical nets are determined by net property

assignment prior to placement and routing. Refer to the

Actel Designer User’s Guide for details on using constraints.

Timing Derating

Since ProASICPLUS devices are manufactured with a CMOS

process, device performance will vary with temperature,

voltage, and process. Minimum timing parameters reflect

maximum operating voltage, minimum operating

temperature, and optimal process variations. Maximum

timing parameters reflect minimum operating voltage,

maximum operating temperature, and worst-case process

variations (within process specifications).

Figur e 16 • Using the PLL 33 MHz In, 133 MHz Out

Figur e 17 • Using the PLL 40 MHz In, 50 MHz Out

÷n

÷m÷u

÷v

PLL Core

External Feedback

Global MUX B OUT

Global MUX A OUT

GLB

GLA

0˚

180˚

270˚

33 MHz 133 MHz

÷4

÷1

÷n

÷m÷u

÷v

PLL Core

External Feedback

Global MUX B OUT

Global MUX A OUT

GLB

GLA

0˚

90˚

180˚

270˚

40 MHz 50 MHz

÷5

÷4

÷1

v3.0 19

ProASICPLUS Flash Family FPGAs

Figur e 18 • Using the PLL to Delay the Input Clock

Figur e 19 • Using the PLL to "Advance" the Input Clock

÷n

÷m÷u

÷v

PLL Core

External Feedback

Global MUX B OUT

Global MUX A OUT

GLB

GLA

0˚

90˚

180˚

270˚

133 MHz 133 MHz

÷1

÷n

÷m÷u

÷v

PLL Core

External Feedback

Global MUX B OUT

Global MUX A OUT

GLB

GLA

0˚

90˚

180˚

270˚

133 MHz 133 MHz

÷1

ProASICPLUS Flash Family FPGAs

20 v3.0

Figur e 20 • Using the PLL for Clock De-skewing

÷n

÷m÷u

÷v

PLL Core

External Feedback

Global MUX B OUT

Global MUX A OUT

GLB

GLA

180

270

133 MHz

÷1

SET

CLR

v3.0 21

ProASICPLUS Flash Family FPGAs

PLL Electrical Specifications

User Security

ProASICPLUS devices have FlashLock protections bits that,

once programmed, block the entire programmed contents

from being read externally. If locked, the user can only

reprogram the device employing the user-defined security

key. This protects the device from being read back and

duplicated. Since programmed data is stored in nonvolatile

memory cells (which are actually very small capacitors),

rather than in the wiring, physical deconstructi on cannot be

used to compromise data. This approach is further

hampered by the placement of the memory cells beneath

the four metal layers (whose removal cannot be

accomplished without disturbing the charge in the

capacitor). This is the highest security provided in the

industry. For more information, refer to Actel’s Design

Security in Nonvolatile Flash and Antifuse FPGAs white

paper.

Embedded Memory Floorplan

The embedded memory is located across the top and bottom

of the device in 256x9 blocks (Figure1 on page 5).

Depending upon the device, up to 88 blocks are available to

support a variety of memory configurations. Each block can

be programmed as an independent memory or combined

(using dedicated memory routing resources) to form larger,

more complex memories. A single memory configuration

cannot include blocks from both the top and bottom

memory locations.

Embedded Memory Configurations

The embedded memory in the ProASICPLUS family provides

great configuration flexibility (Table 7 on page 22). Unlike

many other programmable vendors each ProASICPLUS block

is designed and optimized as a two-port memory (1 read, 1

write). This provides 198kbits of total memory for two-port

and single port usage in the APA1000 device.

Each memory can be configured as FIFO or SRAM, with

independent selection of synchronous or asynchr onous read

and write ports (Table 8 on page 22). Additional

characteristics include programmable flags as well as parity

checking and generation. Figure 21 on page23 and

Figure22 on page 24 show the block diagrams of the basic

SRAM and FIFO blocks. Table9 on page 23 and Table 10 on

page24 describe memory block SRAM and FIFO interface

signals, r espectively . A single memory is designed to operat e

Parameter Value Notes

Freq uen cy Rang es

Reference Frequency fIN (min.) 1.5 MHz Clock conditioning circuitry (min.) lowest output

frequency

Reference Frequency fIN (max.) 180 MHz Clock conditioning circuitry (max.) highest output

frequency

OSC Frequency fVCO (min.) 24 MHz Lowest output frequency voltage controlled

oscillator

OSC Frequency fVCO (max.) 180 MHz Highest output frequency voltage controlled

oscillator

Clock Conditioning Circuitry fOUT (min.) 6 MHz Lowest input frequency clock conditioning

circuitry

Clock Conditioning Circu itry fOUT (max.) 180 MHz Highest input frequency clock conditioning

circuitry

Long Term Jitter Peak-to-Peak Max.

Temperature Frequency MHz

fVCO<10 10<fVCO<60 fVCO>60

25°C (or higher) ±1% ±2% ±1%

0°C ±1.5% ±2.5% ±1%

–40°C ±2.5% ±3.5% ±1%

Acquisition Time from Cold Start

Acquisition Time (max.) 200 cycles Period of low reference clock frequencies

Acquisiti on Time (max.) 80 µs High reference clock frequencies

Power Consumption

Analog Supply Power (max*) 6.9 mW

Digital Supply Current (max) 7 µW/MHz

Duty Cycle 50% ± 0 .5%

Note: *High clock frequency

ProASICPLUS Flash Family FPGAs

22 v3.0

at up to 150MHz (standard speed grade typical conditions).

Each block contains a 256 word, 9-bit wide (1 read port, 1

write port) memory. The memory blocks may be combined

in parallel to form wider memories or stacked to form

deeper memories (Figure 23 on page 25). This provides

optimal bit widths of 9 (1 block), 18, 36, and 72, and optimal

depths of 256, 512, 768, and 1,024. Refer to Actel’s A Guide

to ACTgen Macros for mo re in fo rma t io n .

Figure 24 on page 25 gives an example of optimal memory

usage. Ten blocks with 23,040 bits have been used to

generate three memories of various widths and depths.

Figure 25 on page 25 shows how memory can be used in

parallel to create extra read ports. In this example, using

only 10 of the 88 available blocks of the APA1000 yields an

effective 6,912 bits of multiple port memories. The Actel

ACTgen software facilitates building wider and deeper

memories for optimal memory usage.

Table 7 • ProASICPLUS Memory Configurations by Device

Device Bottom Top

Maximum Width Maximum Depth

DWDW

APA075 0 12 256 108 1,536 9

APA150 0 16 256 144 2,048 9

APA300 16 16 256 144 2,048 9

APA450 24 24 256 216 3,072 9

APA600 28 28 256 252 3,584 9

APA750 32 32 256 288 4,096 9

APA1000 44 44 256 396 5,632 9

Table 8 • Basic Memory Configur ations

Type Write Access Read Access Parity Library Cell Name

RAM Asynchronous Asynchronous Checked RAM256x9AA

RAM Asynchronous Asynchronous Generated RAM256x9AAP

RAM Asynchronous Synchronous Transparent Checked RAM256x9AST

RAM Asynchronous Synchronous Transparent Generated RAM256x9ASTP

RAM Asynchronous Synchronous Pipelined Checked RAM256x9ASR

RAM Asynchronous Synchronous Pipelined Generated RAM256x9ASRP

RAM Synchronous Asynchronous Checked RAM256x9SA

RAM Synchronous Asynchronous Generated RAM256xSAP

RAM Synchronous Synchronous Tr ansparent Checked RAM256x9SST

RAM Synchronous Synchronous Transparent Generated RAM256x9SSTP

RAM Synchronous Synchronous Pipelined Checked RAM256x9SSR

RAM Synchronous Synchronous Pipelined Generated RAM256x9SSRP

FIFO Asynchronous Asynchronous Checked FIFO256x9AA

FIFO Asynchronous Asynchronous Generated FIFO256x9AAP

FIFO Asynchronous Synchronous Transparent Checked FIFO256x9AST

FIFO Asynchronous Synchronous Transparent Generated FIFO256x9ASTP

FIFO Asynchronous Synchronous Pipelined Checked FIFO256x9ASR

FIFO Asynchronous Synchronous Pipelined Generated FIFO256x9ASRP

FIFO Synchronous Asynchronous Checked FIFO256x9SA

FIFO Synchronous Asynchronous Generated FIFO256x9SAP

FIFO Synchronous Synchronous Transparent Checked FIFO256x9SST

FIFO Synchronous Synchronous Transparent Generated FIFO256x9SSTP

FIFO Synchronous Synchronous Pipelined Checked FIFO256x9SSR

FIFO Synchronous Synchronous Pipelined Generated FIFO256x9SSRP

v3.0 23

ProASICPLUS Flash Family FPGAs

Note: To save area while using embedded memories, the memory blocks contain multiplexers (called DMUX) for each output signal. These

DMUX cells do not consume any core logic tiles and con nect direct ly to high speed routing reso urces between the memo ry blocks. They are

used when memories are cascaded and are automatically inserted by the software tools.

Figur e 21 • Ex ample SRAM Block Diagrams

Table 9 • Memory Block SRAM Interface Signals

SRAM Signal Bits In/Out Description

WCLKS 1 IN Write clock used on synchronization on write side

RCLKS 1 IN Read clock used on synchronization on read side

RADDR<0:7> 8 IN Read address

RBLKB 1 IN Read block select (active LOW)

RDB 1 IN Read pulse (active LOW)

WADDR<0:7> 8 IN Write address

WBLKB 1 IN Write block select (active LOW)

DI<0:8> 9 IN Input data bits <0:8>, <8> can be used for parity in

WRB 1 IN Write pulse (active LOW)

DO<0:8> 9 OUT Output data bits <0:8>, <8> can be used for parity out

RPE 1 OUT Read parity error

WPE 1 OUT Write parity error

PARODD 1 IN Selects odd parity generation/detect when high, even when low

Note: Not all signals shown are used in all modes.

SRAM

(256 X 9)

Sync Write &

Sync Read

Ports

DI <0:8> DO <0:8>

RADDR <0:7>

WADDR <0:7>

WRB RDB

WBLKB RBLKB

WCLKS RCLKS

RPE

PARODD

SRAM

(256 X 9)

Async Write

Async Read

Ports

DI <0:8> DO <0:8>

RADDR <0:7

WADDR <0:7>

WRB

WBLKB

RDB

RBLKB

PARODD

WPE RPE

WPE

SRAM

(256 X 9)

Sync Write

Async Read

Ports

DI <0:8> DO <0:8>

WADDR <0:7>

WRB RDB

WBLKB RBLKB

WCLKS

RPE

PARODD

WPE

RADDR <0:7>

PARODD

SRAM

(256 X 9)

Async Write

Sync Read

Ports

DI <0:8> DO <0:8>

RADDR <0:7

WADDR <0:7>

WRB RDB

WBLKB RBLKB

RCLKS

RPE

WPE

ProASICPLUS Flash Family FPGAs

24 v3.0

Note: To save area while using embedded memories, the memory blocks contain multiplexers (called DMUX) for each output signal. These

DMUX cells do not consume any core logic tiles and con nect direct ly to high speed routing reso urces between the memo ry blocks. They are

used when memories are cascaded and are automatically inserted by the software tools.

Figur e 22 • Basic FIFO Block Diagrams

Table 10 • Memory Block FIFO Inte rface Sign als

FIFO Signal Bits In/Out Description

WCLKS 1 IN Write clock used for synchronization on write side

RCLKS 1 IN R ead clock used for synchronization on read side

LEVEL <0:7> 8 IN D irect configuration implements static flag logic

RBLKB 1 IN Read block select (active LOW)

RDB 1 IN Read pulse (active LOW)

RESET 1 IN Reset for FIFO pointers (active LOW)

WBLKB 1 IN Write block select (active LOW)

DI<0:8> 9 IN Input data bits <0:8>, <8> will be generated if PARGEN is true

WRB 1 IN Write pulse (active LOW)

FULL, EMPTY 2 OUT FIFO flags. FULL prevents write and EMPTY prevents read

EQTH, GEQTH 2 OUT EQTH is true when the FIFO holds the nu mber of words specified by the

LEVEL signal. GEQTH is true when the FIFO holds (LEVEL) words or more

DO<0:8> 9 OUT Output data bits <0:8>

RPE 1 OUT Read parity error

WPE 1 OUT Write parity error

LGDEP <0:2> 3 IN Configures DEPTH of the FIFO to 2 (LGDEP+1)

PARODD 1 IN Parity generation/detect – Even when low, odd when high

FIFO

(256 X 9)

Sync Write &

Sync Read

Ports

LEVEL<0:7> DO <0:8>

DI<0:8>

WRB

RDB

WBLKB

RBLKB

RPE

PARODD

WPE

LGDEP<0:2>

FULL

EMPTY

EQTH

GEQTH

WCLKS

RCLKS

RESET

FIFO

(256 X 9)

Sync Write &

Async Read

Ports

DI <0:8> DO <0:8>

LEVEL <0:7>

WRB

RDB

WBLKB

RBLKB

RPE

PARODD

WPE

LGDEP<0:2>

FULL

EMPTY

EQTH

GEQTH

WCLKS

FIFO

(256 X 9)

Async Write &

Async Read

Ports

DI <0:8> DO <0:8>

LEVEL <0:7>

WRB

RDB

WBLKB

RBLKB

RPE

PARODD

WPE

LGDEP<0:2>

FULL

EMPTY

EQTH

GEQTH

FIFO

(256 X 9)

Async Write &

Sync Read

Ports

DI <0:8> DO <0:8>

LEVEL <0:7>

WRB

RDB

WBLKB

RBLKB

RPE

PARODD

WPE

LGDEP<0:2>

FULL

EMPTY

EQTH

GEQTH

RCLKS

RESET

v3.0 25

ProASICPLUS Flash Family FPGAs

Figur e 23 • APA1000 Memory Block Architecture

Figur e 24 • Ex ample Showing Memories with Different Widths and Depths

Figur e 25 • Multiport Memory Usage

Word

Depth

Word Width

88 blocks

256

…

Word

Depth

Word Width

1,024 words x 9 bits, 1 read, 1 write

512 words x 18 bits, 1 read, 1 write

256 words x 18 bits, 1 read, 1 write

Total Memory Blocks Used = 10

Total Memory Bits = 23,040

256

999

256

512 words x 9 bits, 4 read, 1 write

256 words x 9 bits, 2 read, 1 write

Total Memory Blocks Used = 10

Total Memory Bits = 6,912

Word

Depth

Word Width Write Port Write Port

Read Ports

999 9

256

ProASICPLUS Flash Family FPGAs

26 v3.0

Design Environment

The ProASICPLUS family of FPGAs is fully supp orted by both

Actel’s Libero™ Integrated Design Environment and Actel’s

Designer FPGA Development Software. Actel's Designer

software provides a comprehensive suite of backend

development tools for FPGA development. The Designer

software includes timing-driven place and route, a

world-class integrated static timing analyzer and

constraints editor, a design netlist schematic viewer, and

SmartPower, a tool that allows the user to quickly estimate

the power consumption in a design.

Libero IDE provides an integrated design manager that

seamlessly integrates design tools while guiding the user

through the design flow, managing all design and log files,

and passing necessary design data among tools (Figure 26).

Libero IDE includes Synplicity ® Synplify for Actel, Mentor

Graphics™ ViewDraw for Actel, Actel's own Designer

software, Model Technology™ ModelSim HDL Simulator,

and SynaptiCAD™ WaveFormer Lite.

ISP

The user can generate *.bit or *.stp programming files from

the Designer software and can use these files to program a

device.

ProASICPLUS devices can be programmed in system. For

more information on ISP of ProASICPLUS devices, refer to

the In-System Programming ProASICPLUS Devices and

Performing Internal In-System Programming Using Actel’s

ProASICPLUS Devices application notes. Prior to being

pro gramme d for th e first time , the Pro ASICPLUS device I/Os

are inputs with pull-ups.

Figur e 26 • Design Flow

Synthesis

Timing Simulation

Functional Simulation

Stimulus Generation

Simulator

Schematic Entry

Synthesis

Libraries

Fuse or Bitstream

Layout

Compile

Back-Annotate

NetlistViewer

SmartPower

ChipEdit and

ChipViewer

PinEdit

Timer

Static T iming Analyzer

and Constraints Editor

I/O Assignments

Design Synthesis and Optimization

Power Analysis

Schematic Viewer

Placement Editor

Silicon Sculptor

(Antifuse and Flash Families) Silicon Explorer II

(Antifuse and Flash Families)

FlashPro

(Flash Families)

FlashPro Lite

(ProASIC

PLUS

Family)

BP Microsystems

Programmers

Cross-Probing

User

Testbench

Actel

Device

Design Implementation Design Implementation

ProgrammingProgramming System VerificationSystem Verification

Design Creation/VerificationDesign Creation/Verification

HDL Editor

ACTgen

Macro Builder

Optimization and DRC

Timing Driven Place-and-Route

Libero

IDE Project Manager

v3.0 27

ProASICPLUS Flash Family FPGAs

Package Thermal Characteristics

The ProASICPLUS family is available in several package

types with a range of pin counts. Actel has selected

packages based on high pin count, reliability factors, and

superior thermal characteristics.

Thermal resistance defines the ability of a package to

conduct heat away from the silicon, through the package to

the surrounding air. Junction-to-ambient thermal

resistance is measured in degrees Celsius/Watt and is

represented as Theta ja (Θja). The lower the thermal

resistance, the more efficiently a package will dissipate

heat.

A package’s maximum allowed power (P) is a function of

maximum junction temperature (TJ), maximum ambient

operating temperature (TA), and junction-to-ambient

thermal resistance Θja. Maximum junction temperature is

the maximum allowable temperature on the active surface

of the IC and is 110° C. P is defined as:

Θja is a function of the rate (in linear feet per minute –

lfpm) of airflow in contact with the package. When the

estimated power consumption exceeds the maximum

allowed power, other means of cooling, such as increasing

the airflow rate, must be used.

PTJTA

–

Θja

-----------------

Package Type Pin Count Θjc Θja Still Air Θja 300 ft./min. Units

Thin Quad Flat Pack (TQFP ) 100 12 37.5 30 °C/W

Thin Quad Flat Pack (TQFP ) 144 11 3 2 24 °C/W

Plastic Quad Flat Pack (PQFP) 208 8 30 23 °C/W

PQFP with Heatspreader 208 3.8 20 17 °C/W

Plastic Ball Grid Array (PBGA) 456 3 15.6 12 °C/W

Fine Pitch Ball Grid Array (FBGA) 144 3.8 38.8 26.7 °C/W

Fine Pitch Ball Grid Array (FBGA) 256 3.8 25 22 °C/W

Fine Pitch Ball Grid Ar ray (FBGA)1484 3.2 20 15 °C/W

Fine Pitch Ball Grid Ar ray (FBGA)2484 3.2 20.5 16.6 °C/W

Fine Pitch Ball Grid Array (FBGA) 676 3.2 16.4 11.5 °C/W

Fine Pitch Ball Grid Array (FBGA) 896 2.4 13.6 10.3 °C/W

Fine Pitch Ball Grid Array (FBGA) 1152 1.8 12 8.9 °C/W

Notes:

1. Depop u la te d Ar ray

2. Full Array

ProASICPLUS Flash Family FPGAs

28 v3.0

Calculating Typical Power

Dissipation

ProASICPLUS device power is calculated with both a static

and an active component. The active component is a

function of both the number of tiles utilized and the system

speed. Power dissipation can be calculated using the

following formula: Ptotal = Pdc + Pac

where:

Pclock, the clock component of power dissipation, is given by

Pclock = (P1 + P2 * R - P7*R2) * Fs

where:

Pstorage, the storage-tile (Register) component of AC power

dissipation, is given by

Pstorage = P5 * ms * Fs

where:

Plogic, the logic-tile component of AC power dissipation, is

given by Plogic = P3 * mc * Fs

where:

Poutputs, the I/O component of AC po wer diss ipat ion, is give n by

Poutputs = (P4 + (Cload * VDDP2)) * p * Fp

where:

The input’s component of AC power dissipation is given by

Pinputs = P8 * q * Fq

where:

Ppll = P9 * Npll

where:

Finally, Pmemory, the memory component of AC power

consumption, is given by

Pmemory = P6 * Nmemory * Fmemory * Ememory

where:

•P

dc = 12.5 mW (Typically 2.5V x 5mA)

Pdc includes the static components of:

PVDDP + PVDD + PAVDD

•P

ac =P

clock + Pstorage + Plogic + Pinputs + Poutputs +

Pmemory + Ppll

• P1 = 100 µW/MHz is the basic power consumption of

the clock tree per MHz of the clock

•P2 =1.3 µW/MHz is the incr eme ntal power con su mption of

the clock tree per storage tile – also per MHz of the

clock

• P7 = 0. 00003 µW/MHz is a correction factor for highly

loaded clock-trees

• R = the number of storage tiles clocked by this clock

• Fs = the clock frequency

• P5 =1.1 µW/MHz is the average power consumption of a

storage-tile per MHz of its output toggling rate. The

maximum output toggling rate is Fs/2

• ms =the number of storage tiles (Register) switching

during each Fs cycle

• Fs = th e clock frequency

• P3 =1.4 µW/MHz, is the average power consumption

of a logic ti le per MHz of its output togg ling rate.

The maximum output toggling rate is Fs/2

• mc=the number of logic tiles switching during each

Fs cycle

• Fs =the clock frequency

• P4 = 326 µW/MHz is the intrinsic power consumption

of an output pad normalized per MHz of the

output frequency. This is the total I/O current

VDD + VDDP

•C

load = the output load

• p = the number of outputs

• Fp = the average output frequency

• P8 = 29 µW/MHz is the intrinsic power consumption of

an input pad normalized per MHz of the input

frequency

• q = the number of inputs

• Fq = the average input frequency

• P9 = 6.9 mW. This value has been estimated at

maximum PLL clock frequency

•N

Pll = number of PLLs used

• P6 = 175 µW/MHz is the ave ra ge power consu mpti on

of a me mor y blo ck per MHz of t he cloc k

•N

memory = the number of RAM/FIFO blocks

(1 block = 256 words * 9 bits)

•F

memory = the clock frequency of the memory

•E

memory = the average number of active blocks divided

by the total number of blocks (N) of the

memory.

• Ty pical values for Ememory woul d be 1/ 4 for

a 1k x 8, 9,16, 32 me mo r y an d 1/16 fo r a

4kx8, 9, 16, and 32 memory

• In addition , an application-dependent

component to Ememory can be considered.

For example, for a 1kx8 memory using only

1 cycle out of 3, Ememory = 1/4*1/3 = 1/12

v3.0 29

ProASICPLUS Flash Family FPGAs

The following is an APA750 example using a shift register

design with 13,440 st orage tiles (Register) and 0 logic tiles.

This design has one clock at 10 MHz, and 24 outputs

toggling at 5 MHz. We then calculate the various

components as follows:

Pclock

=> Pclock = (P1 + P2 * R - P7*R2) * Fs = 124.2 mW

Pstorage

=> Pstorage = P5 * ms * Fs = 147.8 mW

Plogic

=> Plogic = 0 mW

Poutputs

=> Poutputs = (P4 + Cload * VDDP2) * p * Fp = 87.3 mW

Pinputs

=> Pinputs = P8 * q * Fq = 0.3 mW

Pmemory

=> Pmemory = 0 mW

Pac => 360 mW

Ptotal

Pdc + Pac = 372 mW (Typical)

• Fs= 10 MHz

• R = 13,440

• ms = 13,440 (in a shift register 100% of storage-tiles are

toggling at each clock cycle and Fs = 10 MHz)

• mc = 0 (no logic tile in this shift-register )

•C

load = 40 pF

•V

DDP = 3.3 V

• p = 24

•Fp = 5 MHz

•q = 1

• Fq = 10 MHz

Nmemory = 0 (no RAM/FIFO in this shift-register)

ProASICPLUS Flash Family FPGAs

30 v3.0

Operating Conditions

Standard and –F parts are the same unless otherwise noted. –F parts are only available as commercial.

Absolute Maximum Ratings*

Parameter Condition Minimum Maximum Units

Supply Voltage Core (VDD)–0.33.0V

Supply Voltage I/O Ring (VDDP)–0.34.0V

DC Input V ol t ag e –0.3 VDDP + 0.3 V

PCI DC Input Voltage –1.0 VDDP + 1 .0 V

PCI DC Input Clamp Current (absolute) VIN < –1 or VIN= VDDP + 1V 10 mA

LVPECL Input Voltage –0.3 VDDP + 0.5 V

GND 00V

Note: * Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute

maximum rat ed conditi ons for extend ed period s may affect devi ce reliabil ity. Devices sho uld not be op erated ou tside the Recom mended

Operating Conditions.

Programming, Storage and Operating Limits

Product Grade Programming Cycles Program Retention

Storage Temperature Operating

Min. Max.

TJ Max

Junction

Temperature

Commercial 100 20 years –55°C 110°C 110°C

Industrial 100 20 years –55°C 110°C 110°C

Note: This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and

programming specification is not implied.

Supply Voltages

Mode VDD VDDP

Single Voltage 2.5V 2.5V

Mixed Voltage 2.5V 3. 3V

Parameter Condition

Commercial/Industrial

UnitsMinimum Maximum

VPP During Programming 15.8 16.5 V

Normal Operation10 16.5 V

VPN During Programming –13.8 –13.2 V

Normal Operation2–13.8 0 V

IPP During Programming 25 mA

IPN During Programming 10 mA

AVDD VDD VDD V

AGND GND GND V

Notes:

1. Please refer to the “VPP Programming Supply Pin” section on page60 for more information.

2. Please refer to the “VPN Programming Supply Pin” section on page61 for more information.

Recommended Operating Conditions

Parameter Symbol

Limits

Commercial Industrial

DC Supply Voltage (2.5V I/Os) VDD & VDDP 2.5V ± 0.2V 2.5V ± 0.2V

DC Supply Voltage (Mixed 2.5V, 3.3V I/Os) VDDP

VDD

3.3V ± 0.3V

2.5V ± 0.2V 3.3V ± 0.3V

2.5V ± 0.2V

Operating Ambient Temperature Range TA0°C to 70°C –40°C to 85°C

Maximum Operating Junction Temperature TJ110°C 110°C

v3.0 31

ProASICPLUS Flash Family FPGAs

DC Electrical Specifications (VDDP = 2.5V ±0.2V)1

Symbol Parameter Conditions

Commercial / Industrial1,2

Min. Typ. Max. Units

VOH

Output High Voltage

High Drive (O B25LPH)

Low Drive (OB25LPL)

IOH = –6 mA

IOH = –12 mA

IOH = –24 mA

IOH = –3 mA

IOH = –6 mA

IOH = –8 mA

2.1

2.0

1.7

2.1

1.9

1.7

VOL

Output Low Voltage

High Drive (O B25LPH)

Low Drive (OB25LPL)

IOL = 8 mA

IOL = 15 m A

IOL = 24 m A

IOL = 4 mA

IOL = 8 mA

IOL = 15 m A

0.2

0.4

0.7

0.2

0.4

0.7

VIH Input High Voltage 1.7 VDDP + 0.3 V

VIL Input Low Voltage –0.3 0.7 V

RWEAKPULLUP Weak Pull-up Resistance

(OTB25LPU) VIN ≥ 1.25V 6 56 kΩ

HYST Input Hysteresis Schmitt See Table 4 on page 11 0.3 0.35 0.45 V

IIN Input Current with pull up (VIN = GND) –240 – 20 µA

without pull up (VIN = GND or VDD) –10 10 µA

IDDQ

Quiescent Supply Current

(standby)

Commercial VIN = GND3 or VDD

Std. 5.0 15 mA

–F 5.0 25 mA

IDDQ

Quiescent Supply Current

(standby)

Industrial VIN = GND3 or V DD Std. 5.0 20 mA

IOZ 3-State Output Leakage Current VOH = GND or VDD Std. –10 10 µA

–F4–10 100 µA

IOSH

Output Short Circuit Current High

High Drive (OB2 5LP H)

Low Drive (OB25LPL) VIN = VSS

VIN = VSS

–120

–100 mA

IOSL

Output Short Circuit Current Low

High Drive (OB2 5LP H)

Low Drive (OB25LPL) VIN = VDDP

VIN = VDDP

100

30 mA

CI/O I/O Pad Capacitance 10 pF

CCLK Clock Input Pad Capacitance 10 pF

Notes:

1. All pro c ess cond i tion s. Jun ct io n Tem p erat u re: –4 0 to +1 10° C .

2. –F parts are only available as commercial.

3. No pull-up resistor.

4. This will not exceed 2mA total per device.

ProASICPLUS Flash Family FPGAs

32 v3.0

DC Electrical Specifications (VDDP = 3.3V ±0.3V and VDD 2.5V ±0.2V)1

Symbol Parameter Conditions

Commercial / Industrial1,2

UnitsMin. Typ. Max.

VOH

Output High Voltage

3.3V I/O, High Drive (OB33P)

3.3V I/O, Low Drive (OB33L)

IOH = –14 mA

IOH = –24 mA

IOH = –6 mA

IOH = –12 mA

0.9∗VDDP

2.4

0.9∗VDDP

2.4

Output High Voltage

2.5V I/O, High Drive (OB25H)

2.5V I/O, Low Drive (OB25L)

IOH = –0.1 mA

IOH = –0.5 mA

IOH = –3.0 mA

IOH = –0.1 mA

IOH = –0.5 mA

IOH = –1.0 mA

2.1

2.0

1.7

2.1

2.0

1.7

VOL

Output Low Voltage

3.3V I/O, High Drive (OB33P)

3.3V I/O, Low Drive (OB33L)

IOL = 15 mA

IOL = 20 mA

IOL = 28 mA

IOL = 7 mA

IOL = 10 mA

IOL = 15 mA

0.1VDDP

0.4

0.7

0.1VDDP

0.4

0.7

Output Low Voltage

2.5V I/O, High Drive (OB25H)

2.5V I/O, Low Drive (OB25L)

IOL = 7 mA

IOL = 14 mA

IOL = 28 mA

IOL = 5 mA

IOL = 10 mA

IOL = 15 mA

0.2

0.4

0.7

0.2

0.4

0.7

VIH

Input High Voltage

3.3V LVTTL/LVCMOS

2.5V Mode 2

1.7 VDDP + 0.3

VDDP + 0.3 V

VIL

Input Low Voltage

3.3V LVTTL/LVCMOS

2.5V Mode 0.3

0.3 0.8

0.7 V

RWEAKPULLUP Weak Pull-up Resistance

(IOB33U) VIN ≥ 1.5V 7 43 kΩ

RWEAKPULLUP Weak Pull-up Resistance

(IOB25U) VIN ≥ 1.5V 7 43 kΩ

IIN Input Current with pull up (VIN = GND) –300 –40 µA

without pull up (VIN = GN D or VDD) –10 10 µA

IDDQ

Quiescent Supply Current

(standby)

Commercial VIN = GND3 or VDD

Std. 5.0 15 mA

–F 5.0 25 mA

IDDQ

Quiescent Supply Current

(standby)

Industrial VIN = GND3 or VDD Std. 5.0 20 mA

Notes:

1. All process conditions. Junction Tem perature: –40 to +110°C.

2. –F parts are only available as commercial.

3. No pull- up resistor.

4. This wil l not exceed 2mA total per device.

v3.0 33

ProASICPLUS Flash Family FPGAs

IOZ 3-State Output Leakage Current VOH = GND or VDD Std. –10 10 µA

–F4–10 100 µA

IOSH

Output Short Circuit Curr ent High

3.3V High Drive (OB 33P)

3.3V Low Drive (OB33L)

2.5V High Drive (OB 25H)

2.5V Low Drive (OB25L)

VIN = GND

–200

–100

–20

–10

IOSL

Output Short Circuit Current Low

3.3V High Drive

3.3V Low Drive

2.5V High Drive

2.5V Low Drive

VIN = VDD

200

100

200

100

CI/O I/O Pad Capacitance 10 pF

CCLK Clock Input Pad Capacitance 10 pF

DC Specifications (3.3V PCI Operation)1

Symbol Parameter Condition

Commercial / Industrial2,3

UnitsMin. Max.

VDD Supply Voltage for Core 2.3 2.7 V

VDDP Supply Voltage for I/O Ring 3.0 3.6 V

VIH Input High Voltage 0.5VDDP VDDP + 0.5 V

VIL Input Low Voltage –0.5 0.3VDDP V

IIPU Input Pull-up Voltage40.7VDDP V

IIL Input Leakage Current50 < VIN < VCCI Std. –10 10 µA

–F6–10 100 µA

VOH Output High Voltage IOUT = –500 µA 0.9VDDP V

VOL Output Low Voltage IOUT = 1500 µA 0.1VDDP V

CIN Input Pin Capacit ance (exce pt CLK) 10 pF

CCLK CLK Pin Cap aci t ance 5 12 pF

Notes:

1. For PCI operati on, us e OTB33P H, OB33P H, IO B33P H, IB33, or IB33S macro libra ry cell only.

2. All process conditions. Junction Temperature: –40 to +110°C.

3. –F part s are av ail abl e as c om mer cia l onl y.

4. This specification is guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated network.

Designers with ap plications sensit ive to static power utilization sho uld ensure that the input buffer is conducting minimum current at this

input voltage.

5. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.

6. The sum of the leakage currents for all inputs shall not exceed 2mA per device.

DC Electrical Specifications (VDDP = 3.3V ±0.3V and VDD 2.5V ±0.2V)1 (Continued)

Symbol Parameter Conditions

Commercial / Industrial1,2

UnitsMin. Typ. Max.

Notes:

1. All process conditions. Junction Tem perature: –40 to +110°C.

2. –F parts are only available as commercial.

3. No pull- up resistor.

4. This wil l not exceed 2mA total per device.

ProASICPLUS Flash Family FPGAs

34 v3.0

AC Specifications (3.3V PCI Revision 2.2 Operation)

Symbol Parameter Condition

Commercial / Industrial

UnitsMin. Max.

IOH(AC)

Switching Current High

0 < VOUT ≤ 0.3 VCCI* –12VCCI mA

0.3VCCI ≤ VOUT <

0.9VCCI*(–17.1 + (VDDP – VOUT)) mA

0.7VCCI < VOUT < VCCI*See equatio n C – page 124

of the PCI Specification

document rev. 2.2

(Test Point) VOUT = 0.7VCC*–32V

CCI mA

IOL(AC)

Switchi ng Curr ent Low

VCCI > VOUT ≥ 0.6VCCI* 16VDDP mA

0.6VCCI > VOUT >

0.1VCCI 1 (26.7VOUT)mA

0.18VCCI > VOUT > 0* See e quat ion D – page 124

of the PCI Specification

document rev. 2.2

(Test Point) VOUT = 0.18VCC 38VCCI mA

ICL Low Clamp Current –3 < VIN ≤ –1 –25 + (VIN + 1)/0.015 mA

ICH High Cla mp Curre nt VCCI + 4 > VIN ≥ VCCI + 1 25 + (VIN – VDDP – 1 )/0. 015 mA

slewROutput Rise Slew Rate 0.2VCCI to 0.6VCCI lo ad* 1 4 V/ns

slewFOutput Fall Slew Rate 0.6VCCI to 0.2VCCI lo ad* 1 4 V/ns

Note: * Refer to the PCI Specification docu ment rev. 2.2.

output

buffer

1/2 in. max

10 pF

1kΩ

output

buffer 10 pF

1kΩ

Pad Loading Applicable to the Rising Edge PCI

Pad Loading Applicable to the Falling Edge PCI

v3.0 35

ProASICPLUS Flash Family FPGAs

Tristate Buffer Delays

(Worst-Case Commercial Conditions, VDDP = 3.0V, VDD = 2.3V, 35 pF load, TJ = 70°C)

Macro Type Description

Max tDLH1Max tDHL2Max tENZH3Max tENZL4Unit

sSTD –F STD –F STD –F STD –F

OTB33PH 3.3V, PCI Output Current, High Slew Rate 2.0 2.4 2.2 2.6 2.2 2.6 2.0 2.4 ns

OTB33PN 3.3V, High Output Current, Nominal Slew Rate 2.2 2.6 2.9 3.5 2.4 2.9 2.1 2.5 ns

OTB33PL 3.3V, High Output Current, Low Slew Rate 2.5 3.0 3.2 3.9 2.7 3.3 2.8 3.4 ns

OTB33LH 3.3V, Low Output Current, High Slew Rate 2.6 3.1 4.0 4.8 2.8 3.4 3.0 3.6 ns

OTB33LN 3.3V, Low Output Current, Nominal Slew Rate 2.9 3.5 4.3 5.2 3.2 3.8 4.1 4.9 ns

OTB33LL 3.3V, Low Output Current, Low Slew Rate 3.0 3.6 5.6 6.7 3.3 3.9 5.5 6.6 ns

OTB25HH 2.5V, High Output Current, High Slew Rate 3.1 3.8 1.8 2.2 2.8 3.4 1.7 2.0 ns

OTB25HN 2.5V, High Output Current, Nominal Slew Rate 3.1 3.7 2.7 3.3 2.9 3.5 2.7 3.2 ns

OTB25HL 2.5V, High Output Current, Low Slew Rate 3.1 3.7 3.9 4.7 2.9 3.5 3.8 4.6 ns

OTB25LH 2.5V, Low Output Current, High Slew Rate 4.6 5.6 2.9 3.5 4.6 5.5 2.9 3.4 ns

OTB25LN 2.5V, Low Output Current, Nominal Slew Rate 4.6 5.6 3.7 4.5 4.6 5.5 3.6 4.3 ns

OTB25LL 2.5V, Low Output Current, Low Slew Rate 4.6 5.6 5.1 6.1 4.5 5.4 4.8 5.8 ns

OTB25LPHH 2.5V, Low Power, High Output Current, High Slew

Rate52.0 2.4 2.1 2.5 2.3 2.7 2.0 2.4 ns

OTB25LPHN 2.5V, Low Power, High Output Current, Nominal Slew

Rate52.4 2.9 3.0 3.6 2.7 3.2 2.1 2.5 ns

OTB25LPHL 2.5V, Low Power , High Output Current, Low Slew Rate52.9 3.5 3.2 3.8 3.1 3.8 2.7 3.2 ns

OTB25LPLH 2.5V, Low Power, Low Output Current, High Slew Rate52.7 3.3 4.6 5.5 3.0 3.6 2.6 3.1 ns

OTB25LPLN 2.5V, Low Power, Low Output Current, Nominal Slew

Rate53.5 4.2 4.2 5.1 3.8 4.5 3.8 4.6 ns

OTB25LPLL 2.5V, Low Power, Low Output Current, Low Slew Rate54.0 4.8 5.3 6.4 4.2 5.1 5.1 6.1 ns

Notes:

1. tDLH=Data-to-Pad HIGH

2. tDHL=Data-to-Pad LOW

3. tENZH=Enable-to-Pad, Z to HIGH

4. tENZL = Enable-to-Pad, Z to LOW

5. Low power I/O work with VDDP=2.5V ±10% only. VDDP=2.3V for delays.

PAD

OTBx

A50%

PAD

50%

DLH

50%

DHL

EN 50%

PAD V

50%

ENZL

50%

10%

EN 50%

PAD

GND

50%

ENZH

50%

90%

35pF

ProASICPLUS Flash Family FPGAs

36 v3.0

Output Buffer Delays

PAD

OBx

A50%

PAD

VOL

VOH

50%

tDLH

50%

tDHL

35pF

(Worst-Case Commercial Conditions, VDDP = 3.0V, VDD = 2.3V, 35 pF load, TJ = 70°C)

Macro Type Description

Max tDLH1Max tDHL2

UnitsSTD –F STD –F

OB33PH 3.3V, PC I Output Current, High Slew Rate 2.0 2.4 2.2 2.6 ns

OB33PN 3.3V, High Output Current, Nominal Slew Rate 2.2 2.6 2.9 3.5 ns

OB33PL 3.3V, High Output Current, Low Slew Rate 2.5 3.0 3.2 3.9 ns

OB33LH 3.3V, Low Output Current, High Slew Rate 2.6 3.1 4.0 4.8 ns

OB33LN 3.3V, Low Output Current, Nominal Slew Rate 2.9 3.5 4.3 5.2 ns

OB33LL 3.3V, Low Output Current, Low Slew Rate 3.0 3.6 5.6 6.7 ns

OB25HH 2.5V, High Output Current, High Slew Rate 3.1 3.8 1.8 2.2 ns

OB25HN 2.5V, High Output Current, Nominal Slew Rate 3.1 3.7 2.7 3.3 ns

OB25HL 2.5V, High Output Current, Low Slew Rate 3.1 3.7 3.9 4.7 ns

OB25LH 2.5V, Low Output Current, High Slew Rate 4.6 5.6 2.9 3.5 ns

OB25LN 2.5V, Low Output Current, Nominal Slew Rate 4.6 5.6 3.7 4.5 ns

OB25LL 2.5V, Low Output Current, Low Slew Rate 4.6 5.6 5.1 6.1 ns

OB25LPHH 2.5V, Low Power, High Output Current, High Slew Rate32.0 2.4 2.1 2.6 ns

OB25LPHN 2.5V, Low Power, High Output Current, Nominal Slew Rate32.4 2.9 3.0 3.6 ns

OB25LPHL 2.5V, Low Power, High Output Current, Low Slew Rate32.9 3.5 3.2 3.8 ns

OB25LPLH 2.5V, Low Power , Low Output Current, High Slew Rate32.7 3.3 4.6 5.5 ns

OB25LPLN 2.5V, Low Power, Low Output Current, Nominal Slew Rate33.5 4.2 4.2 5.1 ns

OB25LPLL 2.5V, Low Power, Low Output Current, Low Slew Rate34.0 4.8 4.3 6.4 ns

Notes:

1. tDLH = Data-to-Pad HIGH

2. tDHL = Dat a -to- P ad LOW

3. Low power I/O work with V DDP=2.5V ±10% only. VDDP=2.3V for delays .

v3.0 37

ProASICPLUS Flash Family FPGAs

Input Buffer Delays

Global Input Buffer Delays

PAD YPAD VCC 0V

50%

GND

VCC

50%

tINYH

50%

tINYL

IBx

(Worst-Case Commercial Conditions, VDDP = 3.0V, VDD = 2.3V, TJ = 70°C

Macro Type Description

Max. tINYH1 Max. tINYL2

UnitsStd. –F Std. –F

IB25 2.5V, CMOS Input Levels3, No Pull-up Resistor 0.7 0.9 0.8 1.0 ns

IB25S 2.5V, CMOS Input Levels3, No Pull-up Resistor, Schmitt Trigger 0.7 0.9 0.8 1.0 ns

IB25LP 2.5V, CMOS Input Levels3, Low Power 0.9 1.1 0.6 0.8 ns

IB25LPS 2.5V, CMOS Input Levels3, Low Power, Schmitt Trigger 0.7 0.9 0.9 1.1 ns

IB33 3.3V, CMOS Input Levels3, No Pull-up Resistor 0.4 0.5 0.6 0.7 ns

IB33S 3.3V, CMOS Input Levels3, No Pull-up Resistor, Schmitt Trigger 0.6 0.7 0.8 0.9 ns

Notes:

1. tINYH = I nput Pa d- t o- Y HI G H

2. tINYL = Input Pad-to-Y LOW

3. LVTTL delays are the same as CMOS delays.

4. For LP Macros, VDDP=2.3V for delays.

(Worst-Case Commercial Conditions, VDDP = 3.0V, VDD = 2.3V, TJ = 70°)

Macro Type Descr iption

Max. tINYH1 Max. tINYL2 Units

Std. –F Std. –F

GL25 2.5V, CMOS Input Levels3, No Pull-up Resistor 1.3 1.6 1.0 1.2 ns

GL25S 2.5V, CMOS Input Levels3, No Pull-up Resistor, Schmitt Trigger 1.3 1.6 1.0 1.2 ns

GL25LP 2.5V, CMOS Input Levels3, Low Power 1.1 1.2 1.0 1.3 ns

GL25LPS 2.5V, CMOS Input Levels3, Low Power, Schmitt Trigger 1.3 1.6 1.0 1.1 ns

GL33 3.3V, CMOS Input Levels3, No Pull-up Resistor 1.0 1.2 1.1 1.3 ns

GL33S 3.3V, CMOS Input Levels3, No Pull-up Resistor, Schmitt Trigger 1.0 1.2 1.1 1.3 ns

PECL PPECL Input Levels 1.0 1.2 1.1 1.3 ns

Notes:

1. tINYH = I nput Pa d- t o- Y HI G H

2. tINYL = Input Pad-to-Y LOW

3. LVTTL delays are the same as CMOS delays.

4. For LP Macros, VDDP=2.3V for delays.

ProASICPLUS Flash Family FPGAs

38 v3.0

Predicted Global Routing Delay*

Global Routing Skew

(Worst-Case Commercial Conditions, VDDP = 3.0V, VDD = 2.3V, TJ = 70°C)

Parameter Description

Max.

UnitsStd. –F

tRCKH Input Low to High (fully loaded row) 1.1 1.3 ns

tRCKL Input High to Low (fully loaded row) 1.0 1.2 ns

tRCKH Input Low to High (minimally loaded row) 0.8 1.0 ns

tRCKL Input High to Low (minimally loaded row) 0.8 1.0 ns

Note: * The t iming delay diffe rence between tile locations is l ess than 15 ps.

(Worst-Case Commercial Conditions, VDDP = 3.0V, VDD = 2.3V, TJ = 70°C)

Parameter Description

Max.

UnitsStd. –F

tRCKSWH Maximum Ske w Low to High 270 320 p s

tRCKSHH Maximum Ske w High to Low 270 320 ps

v3.0 39

ProASICPLUS Flash Family FPGAs

Module Delays

Sample Macrocell Library Listing*

(Worst-Case Commercial Conditions, VDD = 2.3V, TJ = 70º C)

Cell

Name Description

Standard –F

Maximu

m Minimum Maximu

m Minimum Units

NAND2 2-Input NAND 0.5 0.6 ns

AND2 2-Input AND 0.4 0.5 ns

NOR3 3-Input NOR 0.8 1.0 ns

MUX2L 2-1 MUX with Active Low Select 0.5 0.6 ns

OA21 2-Input OR into a 2-Input AND 0.8 1.0 ns

XOR2 2-Input Exclusive OR 0.6 0.8 ns

LDL

Active Low Latch (LH/HL)

CLK-Q LH 0.9 1.1

HL 0.8 0.9

tsetup 0.7 0.8

thold 0.1 0.2

DFFL

Negative Edg e-Triggered D- type Flip- Flop (LH /HL)

CLK-Q LH 0.9 1.1

HL 0.8 1.0

tsetup 0.6 0.7

thold 0.0 0.0

Note: *Intrinsic delays have a variable componen t, coupled to the input slope of the signal. These numbers assume an input slope typical of

local interconnect.

50%

50% 50%

tDALH

C50% 50%

50%

50%50%

tDBLH

tDAHL tDBHL

tDCHL

tDCLH

50%

ProASICPLUS Flash Family FPGAs

40 v3.0

Recommended Operating Conditions

Sl ew Rates Measur ed at C = 30pF, No m inal Power Supplies and 25°C

Parameter Symbol

Limits

Commercial/Industrial

Maximum Clock Frequency* fCLOCK 180 MHz

Maximum RAM Frequency* fRAM 150 MHz

Maximum Rise/Fall Time on Inputs*

• Schmitt Mode

• Non-schmitt Mode tR/tF

tR/tF

100 ns

10 ns

Maximum LVPECL Frequency* 180 MHz

Maximum tCK Frequency (JTAG) tCK 10 MHz

Note: *–F parts will be 20% slower than standard commercial devices.

Typ e Trig. Level Rising Edge

(nS) Slew Rate

(V/ns) Falling Edge

(nS) Slew Rate

(V/ns) PCI Mod e

OB33PH 10%-90% 1.60 1.65 1.65 1.60 Yes

OB33PN 10%-90% 1.57 1.68 3.32 0.80 No

OB33PL 10%-90% 1.57 1.68 1.99 1.32 No

OB33LH 10%-90% 3.80 0.70 4.84 0.55 No

OB33LN 10%-90% 4.19 0.63 3.37 0.78 No

OB33LL 10%-90% 5.49 0.48 2.98 0.89 No

OB25HH 20%-60% 3.31 0.30 0.75 1.33 No

OB25HN 20%-60% 3.20 0.32 0.77 1.30 No

OB25HL 20%-60% 3.27 0.31 0.77 1.30 No

OB25LH 20%-60% 8.41 0.12 1.38 0.72 No

OB25LN 20%-60% 8.54 0.12 1.15 0.87 No

OB25LL 20%-60% 8.50 0.12 1.19 0.84 No

OB25LPHH 10%-90% 1.55 1.29 1.56 1.28 No

OB25LPHN 10%-90% 1.70 1.18 2.08 0.96 No

OB25LPHL 10%-90% 1.97 1.02 2.09 0.96 No

OB25LPLH 10%-90% 3.57 0.56 3.93 0.51 No

OB25LPLN 10%-90% 4.65 0.43 3.28 0.61 No

OB25LPLL 10%-90% 5.52 0.36 3.44 0.58 No

Note: Sta ndard and –F par ts .

v3.0 41

ProASICPLUS Flash Family FPGAs

Embedded Memory Specifications

This section discusses ProASICPLUS SRAM/FIFO embedded

memory and its interface signals, including timing diagram s

that show the relationships of signals as they pertain to

single embedded memory blocks (Table 11). Table8 on

page22 shows basic SRAM and FIFO configurations.

Simultaneous Read and Write to the same location must be

done with care . On such accesses the DI bus is output to the

DO bus.

Enclosed Timing Diagrams—SRAM Mode:

• Synch r on ou s SRA M Rea d, A c ce ss Ti me d O utput Str o b e

(Synchronous Transparent)

• Synchronous SRAM Read, Pipeline Mode Outputs

(S ynchronous Pipelined)

• Asynchronous SRAM Write

• Asynchronous SRAM Read, Address Controlled, RDB=0

• Asynchronous SRAM Read, RDB Controlled

• Synchronous SRAM Write

• Embedded Memory Specifications

The difference between synchronous transparent and

pipeline modes is the timing of all the output signals from

the memory. In transparent mode, the outputs will change

within the sam e c lock c ycle to refle ct the data re que s ted b y

the currently valid access to the memory. If clock cycles are

short (high clock speed), the data requires most of the

clock cycle to change to valid values (stable signals).

Processing of this data in the same clock cycle is nearly

impossible. Most designers add registers at all outputs of

the memory to push the data processing into the next clock

cycle. An entire clock cycle can then be used to process the

data. To simplify use of this memory setup, suitable

registers have been implemented as part of the memory

primitive and are available to the user in the synchronous

pipeline mode. In this mode, the output signals will change

shortly after the second rising edge, following the initiation

of the read access.

Table 11 • Memory Block SRAM Interface Signals

SRAM Signal Bits In/Out Description

WCLKS 1 IN Write clock used on synchronization on write side

RCLKS 1 IN Read clock used on synchronization on read side

RADDR<0:7> 8 IN Read address

RBLKB 1 IN True read block select (active LOW)

RDB 1 IN True read pulse (active LOW)

WADDR<0:7> 8 IN Write address

WBLKB 1 IN Write block select (active LOW)

DI<0:8> 9 IN Input data bits <0:8>, <8> can be used for parity in

WRB 1 IN Negative true write pulse

DO<0:8> 9 OUT Output data bits <0:8>, <8> can be used for parity out

RPE 1 OUT Read parity error (active HIGH)

WPE 1 OUT Write parity error (active HIGH)

PARODD 1 IN Selects odd parity generation/detect when high, even when low

Note: Not all signals shown are used in all modes.

ProASICPLUS Flash Family FPGAs

42 v3.0

Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent)

Note: The plot shows the normal operation st atus.

TJ = 0°C to 110°C; VDD = 2.3V to 2.7V

Symbol txxx Description Min. Max. Units Notes

CCYC Cycle time 7.5 ns

CMH Clock high phase 3.0 ns

CML Clock lo w phase 3.0 ns

OCA New DO access from RCLKS ↑ 7.5 ns

OCH Old DO valid from RCLKS ↑ 3.0 ns

RACH RADDR hold from RCLKS ↑ 0.5 ns

RACS RADDR setup to RCLKS ↑ 1.0 ns

RDCH RDB hold from RCLKS ↑ 0.5 ns

RDCS RDB setup to RCLKS ↑ 1.0 ns

RPCA New RPE access from RCLKS ↑ 9.5 ns

RPCH Old RPE valid from RCLKS ↑ 3.0 ns

Note: –F speed grade devices are 20% slower than th e standard numbers.

RADDR

RPE

RCLKS

RBD, RBLKB

New Valid Data Out

Cycle Start

Old Data Out

New Valid

Address

tRACS

tRDCS

tRDCH

tRACH tOCH

tRPCH

tCMH

tOCA

tRPCA

tCCYC

tCML

v3.0 43

ProASICPLUS Flash Family FPGAs

Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined)

Note: The plot shows the normal operation st atus.

TJ = 0°C to 110°C; VDD = 2.3V to 2.7V

Symbol txxx Description Min. Max. Units Notes

CCYC Cycle time 7.5 ns

CMH Clock high phase 3.0 ns

CML Clock lo w phase 3.0 ns

OCA New DO access from RCLKS ↑ 2.0 ns

OCH Old DO valid from RCLKS ↑ 0.75 ns

RACH RADDR hold from RCLKS ↑ 0.5 ns

RACS RADDR setup to RCLKS ↑ 1.0 ns

RDCH RDB hold from RCLKS ↑ 0.5 ns

RDCS RDB setup to RCLKS ↑ 1.0 ns

RPCA New RPE access from RCLKS ↑ 4.0 ns

RPCH Old RPE valid from RCLKS ↑ 1.0 ns

Note: –F speed grade devices are 20% slower than th e standard numbers.

RCLKS

RPE

DO New Valid Data Out

Cycle Start

New RPE Out

RADDR New Valid

Address

RDB, RBLKB

tRACS tOCA

tRPCH

tOCH tRPCA

tCML

tCMH

tCCYC

tRACH

tRDCH

tRDCS

Old Data Out

Old RPE Out

ProASICPLUS Flash Family FPGAs

44 v3.0

Asynchronous SRAM Write

Note: The plot shows the normal operation st atus.

TJ = 0°C to 110°C; VDD = 2.3V to 2.7V

Symbol txxx Description Min. Max. Units Notes

A WRH W AD DR hold from WB ↑ 1.0 ns

AW RS WADDR setup to WB ↓ 0.5 ns

DWRH DI hold from WB ↑ 1.5 ns

DWRS DI setup to WB ↑ 0.5 ns PARGEN is inactive

DWRS DI setup to WB ↑ 2.5 ns PARGEN is active

WPDA WPE access from DI 3.0 ns WPE is invalid while

PARGEN is active

WPDH WPE hold fr om DI 1.0 ns

WRCYC Cycle time 7.5 ns

WRMH WB high phase 3.0 ns Inactive

WRML WB low phase 3.0 ns Active

Note: –F speed grade devices are 20% slower than th e standard numbers.

WRB, WBLKB

WADDR

WPE

tAWRS

tWPDA

tAWRH

tDWRS

tWRML tWRMH

tWRCYC

tWPDH

tDWRH

v3.0 45

ProASICPLUS Flash Family FPGAs

Asynchronous SRAM Read, Address Controlled, R DB=0

Note: The plot shows the normal operation st atus.

TJ = 0°C to 110°C; VDD = 2.3V to 2.7V

Symbol txxx Description Min. Max. Units Notes

ACYC Read cycle time 7.5 ns

OAA New DO access from RADDR stable 7.5 ns

OAH Old DO hold from RADDR stable 3.0 ns

RPAA New RPE access from RADDR stable 10.0 n s

RPAH Old RPE hold from RADDR stable 3.0 ns

Note: –F speed grade devices are 20% slower than th e standard numbers.

RPE

RADDR

tOAH

tRPAH tOAA

tRPAAtACYC

ProASICPLUS Flash Family FPGAs

46 v3.0

Asynchronous SRAM Read, RDB Controlled

Note: The plot shows the normal operation st atus.

TJ = 0°C to 110°C; VDD = 2.3V to 2.7V

Symbol txxx Description Min. Max. Units Notes

ORDA New DO access from RB ↓7.5 ns

ORDH Old DO valid from RB ↓3.0 ns

RDCYC Read cycle time 7.5 ns

RDMH RB high phase 3.0 ns Inactive setup to new cycle

RDML RB low phase 3.0 ns Active

RPRDA New RPE access from RB ↓9.5 ns

RPRDH Old RPE valid from RB ↓3.0 ns

Note: –F speed grade devices are 20% slower than th e standard numbers.

RB=(RDB+RBLKB)

RPE

tORDH

tORDA

tRPRDA

tRDMLtRDCYC

tRDMH

tRPRDH

v3.0 47

ProASICPLUS Flash Family FPGAs

Synchronous SRAM Write

Note: The plot shows the normal operation st atus.

TJ = 0°C to 110°C; VDD = 2.3V to 2.7V

Symbol txxx Description Min. Max. Units Notes

CCYC Cycle time 7.5 ns

CMH Clock high phase 3.0 ns

CML Clock lo w phase 3.0 ns

DCH DI hold from WCLKS ↑ 0.5 ns

DCS DI setup to WCLKS ↑ 1.0 ns

W ACH W AD DR hold from WCLKS ↑ 0.5 ns

WDCS WA DDR setup to WCLKS ↑ 1.0 ns

WPCA New WPE access from WCLKS ↑ 3.0 ns WPE is invalid while

PARGEN is active

WPCH Old WPE va lid from WCLKS ↑ 0.5 ns

WRCH,

WBCH WRB & WBLKB hold from WCLKS ↑ 0.5 ns

WRCS,

WBCS WRB & WBLKB set up to WCLKS ↑ 1.0 ns

Notes:

1. On simultaneous read and write accesses to the same location DI is output to DO.

2. –F speed gra de devices are 20% slower than the standard numbers.

WCLKS

WPE

WADDR, DI

WRB, WBLKB

Cycle Start

tWRCH, tWBCH

tWRCS, tWBCS

tDCS, tWDCStWPCH

tDCH, tWACH tWPCA

tCMH tCML

tCCYC

ProASICPLUS Flash Family FPGAs

48 v3.0

Synchronous Write and Read to the Same Location

Note: The plot shows the normal operation st atus.

TJ = 0°C to 110°C; VDD = 2.3V to 2.7V

Symbol txxx Description Min. Max. Units Notes

CCYC Cycle time 7.5 ns

CMH Clock high phase 3.0 ns

CML Clock low phase 3.0 ns

WCLKRCLKS WCLKS ↑to RCLKS ↑setup time – 0.1 ns

WCLKRCLKH WCLKS ↑to RCLKS ↑ho ld time 7.0 ns

OCH Old DO valid from RCLKS ↑3.0 ns OCA/OCH displayed for

Access Timed Output

OCA New DO valid from RCLKS ↑7.5 ns

Notes:

1. This beh av io r is val i d fo r Acc ess Ti me d Out pu t an d Pi pe li ne d Mod e Out pu t . The tab le sho w s th e ti min gs of an Acce ss Ti m ed O utp ut.

2. During synchronous write and syn chronous read access to the same location, the new write data will be read out if the active write clock

edge occurs before or at the same time as the active read clock edge. T he negati ve setup time insures this behavior for WCLKS and RCLKS

driven by the same design signal.

3. If WCLK S changes after the hold time, the data will be read.

4. A setup or hold time violation will result in unknown output data.

5. –F speed gra de devices are 20% slower than the standard numbers.

* New data is read if WCLKS ↑occurs before setup time .

The data stored is read if WCLKS ↑occurs after hold time.

RCLKS

WCLKS

tWCLKRCLKH

New Data*

Last Cycle Data

tWCLKRCLKS

tOCH

tCCYC

tCMH tCML

tOCA

v3.0 49

ProASICPLUS Flash Family FPGAs

Asynchronous Write and Synchronous Read to the Same L ocation

Note: The plot shows the normal operation st atus.

TJ = 0°C to 110°C; VDD = 2.3V to 2.7V

Symbol txxx Description Min. Max. Units Notes

CCYC Cycle time 7.5 ns

CMH Clock high phase 3.0 ns

CML Clock low phase 3.0 ns

WBRCLKS WB ↓to RCL KS ↑setup time –0.1 ns

WBRCLKH WB ↓to RCLKS ↑ hold time 7.0 ns

OCH Old DO valid from RCLKS ↑3.0 ns OCA/OCH displayed for

Access Timed Output

OCA New DO valid from RCLKS ↑7.5 ns

DWRRCLKS DI to RCLKS ↑ setup time 0 ns

DWRH DI to WB ↑ hold time 1.5 ns

Notes:

1. This beh av io r is val i d fo r Acc ess Ti me d Out pu t an d Pi pe li ne d Mod e Out pu t . The tab le sho w s th e ti min gs of an Acce ss Ti m ed O utp ut.

2. In asynchronous write and sy nchronous read access to the same location, the new write data will be read out if the active write signal edge

occurs before or at the same time as the active read clock edge. If WB changes to low after hold time, the data will be re ad.

3. A setup or hold time violation will resul t in unknown output data.

4. –F speed gra de devices are 20% slower than the standard numbers.

* New data is read if WB ↓occurs before setup time.

The stored data is read if WB ↓occurs after hold time.

WB = {WRB + WBLKB}

RCLKS

tBRCLKH

New Data*

Last Cycle Data

tWRCKS

tOCH

tOCA

tDWRRCLKS tDWRH

tCCYC

tCMH tCML

ProASICPLUS Flash Family FPGAs

50 v3.0

Asynchronous Write and Read to the Same Location

Note: The plot shows the normal operation st atus.

TJ = 0°C to 110°C; VDD = 2.3V to 2.7V

Symbol txxx Description Min. Max. Units Notes

ORDA New DO access from RB ↓7.5 ns

ORDH Old DO valid from RB ↓3.0 ns

OWRA New DO access from WB ↑3.0 ns

OWRH Old DO valid from WB ↑0.5 ns

RAWRS RB ↓or RADDR from WB ↓5.0 ns

RAWRH RB ↑or RADDR from WB ↑5.0 ns

Notes:

1. During an asynchronous read cycl e, each write operation (synch ronous or asynchron ous) to the same location will automatically trigger

a read ope ra t io n w h ich up da te s t he r ead dat a .

2. Violati on or RAWRS wi ll distur b access to the OLD data.

3. Violatio n of RA WRH will disturb access to the NEWER data.

4. –F speed gra de devices are 20% slower than the standard numbers.

RB, RADDR

OLD NEWERNEW

tORDA

tORDH

tOWRH

tRAWRH

WB = {WRB+WBLKB}

tOWRA

tRAWRS

v3.0 51

ProASICPLUS Flash Family FPGAs

Synchronous Write and Asynchronous Read to the Same L ocation

Note: The plot shows the normal operation st atus.

TJ = 0°C to 110°C; VDD = 2.3V to 2.7V

Symbol txxx Description Min. Max. Units Notes

ORDA New DO access from RB ↓7.5 ns

ORDH Old DO valid from RB ↓3.0 ns

OWRA New DO access from WCLKS ↓3.0 ns

OWRH Old DO valid from WCLKS ↓0.5 ns

RAWCLKS RB ↓or RADDR from WCLKS ↑5.0 ns

RAWCLKH RB ↑or RADDR from WCLKS ↓5.0 ns

Notes:

1. During an asynchronous read cycl e, each write operation (synch ronous or asynchron ous) to the same location will automatically trigger

a read ope ra t io n w h ich up da te s t he r ead dat a .

2. Violati on of RAWCLKS will distu rb access to OLD data.

3. Violatio n of RAWCLKH will disturb access to NEWER data.

4. –F speed gra de devices are 20% slower than the standard numbers.

RB, RADDR

OLD NEW NEWER

tORDA

tORDH

tRAWCLKS

tRAWCLKH

WCLKS

tOWRH

tOWRA

ProASICPLUS Flash Family FPGAs

52 v3.0

Asynchronous FIFO Full and Empty Transitions

The asynchronous FIFO accepts writes and reads while not

full or not empty. When the FIFO is full, all writes are

inhibited. Conversely, when the FIFO is empty, all reads are

inhibited. A problem is created if the FIFO is written during

the transition out of full to not full or read during the

transition out of empty to not empty. The exact time at

which the write or read operation changes from inhibited to

accepted after the read (write) signal which causes the

transition from full or empty to not full or not empty is

indeterminate. This indeterminate period starts 1 ns after

the RB (WB) transition, which deactivates full or not empty

and ends 3 ns after the RB (WB) transition for slow cycles.

For fast cycles, the indeterminate period ends 3ns (7.5 ns –

RDL (WRL)) after the RB (WB) transition, whichever is

later (Table 12).

The timing diagram for write is shown in Figure 27 on

page 53. The timing diagram for read is shown in Figure 28

on page 53. For basic SRAM configurations, see Table 9 on

page 23.

Enclosed Timing Diagrams – FIFO Mode:

• Asynchronous FIFO Read

• Asynchronous FIFO Write

• Synchronous FIFO Read, Access Timed Output

Strobe (Synchronous Transparent)

• Sync hro no u s FIFO Rea d , Pi pe li ne Mo de Out p ut s

(S ync hr ono us Pi pe l ine d )

• Synchronous FIFO Write

•FIFO Reset

Table 12 • Memory Block FIFO Inte rface Sign als

FIFO Signal Bits In/Out Description

WCLKS 1 IN Write clock used for synchronization on write side

RCLKS 1 IN Read clock used for synchronization on read side

LEVEL <0:7>* 8 IN Direct configuration implements static flag logic

RBLKB 1 IN Read block select (active LOW)

RDB 1 IN Read pulse (active LOW)

RESET 1 IN Reset for FIFO pointers (active LOW)

WBLKB 1 IN Write block select (active LOW)

DI<0:8> 9 IN Input data bits <0:8>, <8> will be generated if PARGEN is true

WRB 1 IN Write pulse (active LOW)

FULL, EMPTY 2 OUT FIFO flags. FULL prevents write and E MPTY prevents read

EQTH, GEQTH 2 OUT EQTH is true when the FIFO holds the number of words specified by the

LEVEL signal. GEQTH is true when the FIFO holds (LEVEL) words or more

DO<0:8> 9 OUT Output data bits <0:8>

RPE 1 OUT Read parity error (active HIGH)

WPE 1 OUT Write parity error (active HIGH)

LGDEP <0:2> 3 IN Configures DEPTH of the FIFO to 2 (LGDEP+1)

PARODD 1 IN Selects odd parity generation/detect when high, even when low

Note: *LEVEL is a lway s ei ght bits ( 000 0.0 000 , 00 00. 00 01). Th at mean s f or v alu es of DEPT H gr eate r th an 25 6, n ot a ll va l ues wi ll be p ossibl e, e.g.

for D EPTH= 512, the LEVEL can only have the values 2, 4, . . ., 512. The LEVEL signal circuit will ge nerate sign als that indicate whether

the FIFO is exactly filled to the value of LEVEL (EQTH) or filled equal or higher (GEQTH) than the specified LEVEL. Since counting

starts at 0, EQTH will become true when the FI FO holds (LEVEL+1) wo rds for 512-bit FIFOs.

v3.0 53

ProASICPLUS Flash Family FPGAs

Note: –F speed grade devices are 20% slower than the standard number s.

Figur e 27 • Write Timin g Diagram

Note: –F speed grade devices are 20% slower than the standard number s.

Figur e 28 • Read Timing Diagram

Write acceptedWrite inhibited

FULL

Write

cycle

1 ns

3 ns

Read acceptedRead inhibited

EMPTY

Read

cycle

1 ns

3 ns

ProASICPLUS Flash Family FPGAs

54 v3.0

Asynchronous FIFO Read

TJ = 0° C to 110°C; VDD = 2.3V to 2.7V

Note: The plot shows the normal operation st atus.

Symbol txxx Description Min. Max. Units Notes

ERDH,

FRDH,

THRDH

Old EMP TY, FUL L, EQTH, & GETH valid

hold time from RB ↑0.5 ns Empty/full/thresh are invalid

from the end of hold until the

new access is complete

ERDA New EMPTY access from RB ↑3.01ns

FRDA FULL↓ access from RB ↑3.01ns

ORDA New DO access from RB ↓7.5 ns

ORDH Old DO valid from RB ↓3.0 ns

RDCYC Read cycle time 7.5 ns

RDWRS WB ↑, clearing EMPTY, setup to

RB ↓3.02ns Enabling the read operation

1.0 ns Inhibiting the read operation

RDH RB high phase 3.0 ns Inactive

RDL RB low phase 3.0 ns Active

RPRDA New RPE access from RB ↓9.5 ns

RPRDH Old RPE valid from RB ↓4.0 ns

THRDA EQTH or GETH access from RB↑4.5 ns

Notes:

1. At fa st cycles, ERDA and FRDA = MAX (7.5 ns – RDL), 3.0 ns.

2. At fa st cycles, RDWRS (for enabling read) = MAX (7.5 ns – WRL), 3.0ns.

3. –F speed gra de devices are 20% slower than the standard numbers.

RB=(RDB+RBLKB)

RPE

RDATA

EMPTY

EQTH, GETH

FULL

(Empty inhibits read)

Cycle Start

tRDWRS tERDH, tFRDH

tERDA, tFRDA

tTHRDH

tORDH

tRPRDH

tORDA

tRDL tRDH

tRPRDA

tRDL tRDH

tTHRDA

v3.0 55

ProASICPLUS Flash Family FPGAs

Asynchronous FIFO Write

TJ = 0° C to 110°C; VDD = 2.3V to 2.7V

Note: The plot shows the normal operation st atus.

Symbol txxx Description Min. Max. Units Notes

DWRH DI hold from WB ↑ 1.5 ns

DWRS DI setup to WB ↑ 0.5 ns PARGEN is inactive

DWRS DI setup to WB ↑ 2.5 ns PARGEN is active

EWRH,

FWRH,

THWRH

Old EMP TY, FUL L, EQTH, & GETH valid

hold time after WB ↑0.5 ns Empty/full/thresh are invalid

from the end of hold until the

new access is complete

EWRA EMPTY ↓ access from WB ↑ 3.01ns

FWRA New FULL access from WB ↑3.01ns

THWRA EQTH or GETH access from WB ↑4.5 ns

WPDA WPE access from DI 3.0 ns WPE is invalid while

PARGEN is active

WPDH WPE hold fr om DI 1.0 ns

WRCYC Cycle time 7.5 ns

WRRDS RB ↑, clearing FULL, setup to

WB ↓3.02ns Enabling the write operation

1.0 Inhibiting the write operation

WRH WB high phase 3.0 ns Inactive

WRL WB low phase 3.0 ns Active

Notes:

1. At fas t cycl e s, E WRA , FW R A = MAX (7.5ns – WRL), 3. 0ns.

2. At fast cycles, WRRDS (for enabling writ e) = MAX (7.5ns – RDL), 3.0ns.

3. –F speed gra de devices are 20% slower than the standard numbers.

WPE

WDATA (Full inhibits write)

WB=(WRB+WBLKB)

EMPTY

EQTH, GETH

FULL

Cycle Start

tWRRDS tDWRH

tWPDH

tWPDA

tDWRS

tEWRH, tFWRH

tEWRA, tFWRA tTHWRH

tTHWRA

tWRH

tWRL tWRCYC

ProASICPLUS Flash Family FPGAs

56 v3.0

Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent)

TJ = 0° C to 110°C; VDD = 2.3V to 2.7V

Note: The plot shows the normal operation st atus.

Symbol txxx Description Min. Max. Units Notes

CCYC Cycle time 7.5 ns

CMH Clock high phase 3.0 ns

CML Clock lo w phase 3.0 ns

ECBA New EMPTY access from RCLKS ↓3.01ns

FCBA FULL ↓ access from RCLKS ↓ 3.01ns

ECBH,

FCBH,

THCBH

Old EMP TY, FUL L, EQTH, & GETH valid

hold time from RCLKS ↓1.0 ns Empty/full/thr esh are invalid

from the end of hold until the

new access is complete

OCA New DO access from RCLKS ↑7.5 ns

OCH Old DO valid from RCLKS ↑ 3.0 ns

RDCH RDB hold from RCLKS ↑ 0.5 ns

RDCS RDB setup to RCLKS ↑ 1.0 ns

RPCA New RPE access from RCLKS ↑ 9.5 ns

RPCH Old RPE valid from RCLKS ↑ 3.0 ns

HCBA EQTH or GETH access from RCLKS ↓ 4.5 ns

Notes:

1. At fast cycles, ECBA and FCBA = MAX (7.5ns – CMH), 3 .0ns.

2. –F speed gra de devices are 20% slower than the standard numbers.

RCLK

RPE

RDATA

EMPTY

EQTH, GETH

FULL

Old Data Out New Valid Data Out (Empty Inhibits Read)

RDB

Cycle Start

tRDCH

tOCH

tRPCH

tRDCS

tECBH, tFCBH

tECBA, tFCBA

tOCA

tRPCA

tCMH tCML

tCCYC

tTHCBH

tHCBA

v3.0 57

ProASICPLUS Flash Family FPGAs

Synchronous FIFO Read, Pipeline Mode Ou tputs (Synchronous Pipelined)

TJ = 0° C to 110°C; VDD = 2.3V to 2.7V

Note: The plot shows the normal operation st atus.

Sym bol txxx Description Min. Max. Units Notes

CCYC Cycle time 7.5 ns

CMH Clock high phase 3.0 ns

CML Clock low phase 3.0 ns

ECBA New EMPTY access from RCLKS ↓ 3.01ns

FCBA FULL ↓ access from RCLKS ↓ 3.01ns

ECBH, FCBH,

THCBH Old EMPTY, FULL, EQTH, & GETH valid

hold time from RCLKS ↓ 1.0 ns Empty/full/thresh are invalid

from the end of hold until the

new access is complete

OCA New DO access from RCLKS ↑ 2.0 ns

OCH Old DO valid from RCLKS ↑ 0.75 ns

RDCH RDB hold from RCLKS ↑ 0.5 ns

RDCS RDB setup to RCLKS ↑ 1.0 ns

RPCA New RPE access from RCLKS ↑ 4.0 ns

RPCH Old RPE valid from RCLK S ↑ 1.0 ns

HCBA EQTH or GETH access from RCLKS ↓ 4.5 ns

Notes:

1. At fast cycles, ECBA and FCBA = MAX (7.5 ns – CMS), 3.0 ns.

2. –F speed grade devices are 20% slower than th e standard numbers.

RCLK

RPE

RDATA

EMPTY

EQTH, GETH

FULL

Old Data Out New Valid Data Out

RDB

Cycle Start

Old RPE Out New RPE Out

tECBH, tFCBH

tRDCH

tRDCS

tOCA

tECBA, tFCBA

tTHCBH

tHCBA

tCMH tCML

tCCYC

tRPCH

tOCH

tRPCA

ProASICPLUS Flash Family FPGAs

58 v3.0

Synchronous FIFO Write

Note: The plot shows the normal operation st atus.

TJ = 0°C to 110°C; VDD = 2.3V to 2.7V

Sym bol txxx Description Min. Max. Units Notes

CCYC Cycle time 7.5 n s

CMH Clock high phase 3.0 ns

CML Clock low phase 3.0 ns

DCH DI hold from WCLKS ↑ 0.5 ns

DCS DI setup to WCLKS ↑ 1.0 ns

FCBA New FULL access from WCLKS ↓3.01ns

ECBA EMPTY↓ access from WCLKS ↓ 3.01ns

ECBH,

FCBH,

HCBH

Old EMPTY, FULL, EQTH, & GETH valid

hold time from WCLKS ↓1.0 ns Empty/full/thresh are invalid

from the end of hold until the

new access is complete

HCBA EQTH or GETH access from WCLKS ↓ 4.5 ns

WPCA New WPE access from WCLKS ↑ 3.0 ns WPE is invalid while

PARGEN is ac ti ve

WPCH Old WPE valid from WCLKS ↑ 0.5 ns

WRCH,

WBCH WRB & WBLKB hold from WCLKS ↑ 0.5 ns

WRCS,

WBCS W RB & WBLKB setup to WCLKS ↑ 1.0 ns

Notes:

1. At fast cycles, ECBA and FCBA = MAX (7.5ns – CMH), 3.0ns.

2. –F speed grade devices are 20% slower than th e standard numbers.

WCLKS

WPE

EMPTY

EQTH, GETH

FULL

(Full Inhibits Write)

WRB, WBLKB

Cycle Start

tWRCH, tWBCH tECBH, tFCBH

tECBA, tFCBA

tHCBA

tWRCS, tWBCS

tDCS

tWPCA

tCMH tCML

tCCYC

tWPCH

tDCH

tHCBH

v3.0 59

ProASICPLUS Flash Family FPGAs

FIFO Reset

Note: *The plot shows the normal operation status.

TJ = 0°C to 110°C; VDD = 2.3V to 2.7V

Symbol txxx Description Min. Max. Units Notes

CBRSH WCLKS or RCLKS ↑ hold from RESETB ↑ 1.5 ns Synchronous mode only

CBRSS WCLKS or RC LKS ↓ setup to RESETB ↑ 1.5 ns Synchronous mode only

ERSA New EMPTY ↑ access from RESETB ↓ 3.0 ns

FRSA FULL ↓ access from RESETB ↓ 3.0 ns

RSL RESETB low phase 7.5 ns

THRSA EQTH or GETH access from RESETB ↓ 4.5 ns

WBRSH WB ↓ hold from RESETB ↑ 1.5 ns Asynchronous mode only

WBRSS WB ↑ setup to RESETB ↑ 1.5 ns Asynchronous mode only

Note: –F speed grade devices are 20% slower than th e standard numbers.

*WB = WRB + WBL RB

RESETB

EMPTY

EQTH, GETH

FULL

WB* Cycle Start

Cycle Start

WCLKS, RCLKS

tERSA, tFRSA

tTHRSA

tCBRSS

tWBRSS

tCBRSH

tWBRSH

tRSL

ProASICPLUS Flash Family FPGAs

60 v3.0

Pin Description

User Pins

I/O User Input/Output

The I/O pin functions as an input, output, tristate, or

bidirectional buffer. Input and output signal levels are

compatible with standard LVTTL and LVCMOS

specifications. Unused I/O pins are configured as inputs

with pull-up resistors.

NC No Connect

To maintain compatibility with other Actel ProASICPLUS

products, it is recommended that this pin not be connected

to the circuitry on the board.

GL Global Pin

Low skew input pin for clock or other global signals. This pin

can be configured with an internal pull-up resistor. When it

is not connected to the global network or the clock

conditioning circuit, it can be configured and used as a

normal I/O.

GLMX Global Multiplexing Pin

Low skew input pin for clock or other global signals. This pin

can be used in one of two special ways: (Please see Actel’s

ProASICPLUS Clock Cond itioning Ci rcuits application n ote

for details).

1. When the external feedback option is selected for the

PLL block, this pin is routed as the external feedback

source to the clock conditioning circuit.

2. In applications where two different signals access the

same global net (but at different times) through the use

of GLMXx and GLMXLx macros, this pin will be fixed as

one of the source pins.

This pin can be configured with an internal pull-up resistor.

When it is not connected to the global network or the clock

conditioning circuit, it can be configured and used as any

normal I/O. If not used, a global will be configured as an

input with pull-up.

Dedicated Pins

GND Ground

Common ground supply voltage.

VDD Logic Array Power Supply Pin

2.5V supply voltage.

VDDP I/O Pad Power Supply Pin

2.5V or 3.3V supply voltage.

TMS Test Mode Select

The TMS pin controls the use of boundary-scan circuitry.

This pin has an internal pull-up resistor.

TCK Tes t Clock

Clock input pin for boundary scan (maximum 10 MHz).

Actel recommends adding a nominal 20kΩ pull-up resistor

to this pin.

TDI Test Data In

Serial input for boundary scan. A dedicated p ull-up resistor

is included to pull this pin high when not being driven.

TDO Test Data Out

Serial output for boundary scan. Acte l recommends adding a

nominal 20kΩ pull-up resistor to this pin.

TRST Test Reset Input

Asynchronous, active low input pin for resetting

boundary-scan circuitry. This pin has an internal pull-up

resistor.

Special Function Pins

RCK Run ning Clock

A free running clock is needed during programming if the

programmer cannot guarantee that TCK will be

uninterrupted. If not used, this pin has an internal pull-up

and can be left floating.

NPECL User Negative Input

Provides high speed clock or data signals to the PLL block.

If unused, leave the pin unconnected.

PPECL User Positive Input

Provides high speed clock or data signals to the PLL block.

If unused, leave the pin unconnected.

AVDD PLL Power Supply

Analog VDD should be VDD ( core volta ge) 2.5 V (nominal) and

be decoupled from GND with suitable decoupling capacitors

to re d uc e n oi s e . Fo r m o re inf o r ma ti on , refer t o Act e l ’s Using

ProASICPLUS Clock Conditioning Circuits application note.

If the PLLs or clock conditioning circuitry are not used in a

design, AVDD should be tied high (2.5V normal).

AGND PLL Power Ground

Analog GND should be 0V and be decoupled from GND with

suitable decoupling capacitors to reduce noise. For more

information, refer to Actel’s ProASICPLUS Clock

Conditioning Circuits application note. If the PLLs or cl ock

conditioning circuitry are not used in a des ign, AGND should

be tied to GND.

VPP Programming Supply Pin

This pin may be connected to any voltage between GND and

16.5V during normal operation, or it can be left

unconnected.2 For information on using this pin during

programming, see the Performing Internal In-System

Programming Using Actel’s ProASICPLUS Devices

application note. Actel recommends floating the pin or

connecting it to VDDP.

2. There is a nom in al 4 0kΩ pull-up resistor on VPP.

v3.0 61

ProASICPLUS Flash Family FPGAs

VPN Programming Supply Pin

This pin may be connected to any voltage between GND and –13.8V

during normal operation, or it can be left unconnected.

For

information on using this pin during programming, see the

Performing Internal In-System Programming Using Actel’s

ProASICPLUS Devices

application note.

Actel recommends

floating the pin or connecti n g it to G ND.

Recommended Design Practice for

VPN/VPP

Bypass capacitors are required from VPP to GND and VPN to

GND for all ProASICPLUS devices during programming.

During the erase cycle, ProASICPLUS devices may have

current surges on the VPP and VPN power supplies . The only

way to maintain the integrity of the power distribution to

the ProASICPLUS device during these current surges is to

counteract the inductance of the finite length conductors

that distribute the power to the device. This can be

accomplished by providing a sufficient amount of bypass

capacitance between the VPP and VPN pins and GND (u sing

the shortest paths possible). Without sufficient bypass

capacitance to counter act the inductance, the VPP and VPN

pins may incur a voltage spike beyond the voltage that the

device can withstand. This issue applies to all programming

configurations.

The power supply voltage limits are defined in the “Supply

Voltages” table on page 30. The solution prevents spikes

fr om d am agi ng t he Pr oA SIC PLUS devices. Bypass capacitors

are required for the VPP and VPN pads. Use a 0.01 µF to 0.1

µF ceramic capacitor with a 25V or greater rating. To filter

low-frequency noise (decoupling), us e a 4.7 µF (low ESR, <1

<Ω, tantalum, 25V or greater rating) capacitor. The

capacitors should be located as close to the device pins as

possible (within 2.5cm is desirable). The smaller,

high-frequency capacitor should be placed closer to the

device pins than the larger low-frequency capacitor. The

same dual capacitor circuit should be used on both the VPP

and VPN pins (Figure 29).

3. There is a nomina l 40kΩ pull-d own resi stor on VPN.

Figur e 29 • ProASICPLUS VPP and VPN Capacitor Requirements

2.5cm

0.1µF

0.01µFProgramming

Header

Supplies

4.7µF

Actel

ProASIC

Device

VPP

VPN +

0.1µF

0.01µF4.7µF

PLUS

ProASICPLUS Flash Family FPGAs

62 v3.0

Package Pin Assignments

100-Pin TQFP

1100

v3.0 63

ProASICPLUS Flash Family FPGAs

100-Pin TQFP

Number APA075

Function APA150

Function

1GNDGND

2 I/O I/O

3 I/O I/O

4 I/O I/O

5 I/O I/O

6 I/O I/O

7 I/O I/O

8 I/O I/O

9GNDGND

10 I/O (GLMX1) I/O (GLMX1)

11 GL1 GL1

12 AGND AGND

13 NPECL1 NPECL1

14 AVDD AVDD

15 PPECL1 (I/P) PPECL1 (I/P)

16 GL2 GL2

17 VDD VDD

18 I/O I/O

19 I/O I/O

20 I/O I/O

21 I/O I/O

22 I/O I/O

23 I/O I/O

24 I/O I/O

25 GND GND

26 VDDP VDDP

27 I/O I/O

28 I/O I/O

29 I/O I/O

30 I/O I/O

31 I/O I/O

32 I/O I/O

33 I/O I/O

34 I/O I/O

35 I/O I/O

36 I/O I/O

37 VDD VDD

38 GND GND

39 VDDP VDDP

40 GND GND

41 I/O I/O

42 I/O I/O

43 I/O I/O

44 I/O I/O

45 I/O I/O

46 I/O I/O

47 TCK TCK

48 TDI TDI

49 TMS TMS

50 VDDP VDDP

51 GND GND

52 VPP VPP

53 VPN VPN

54 TDO TDO

55 TRST TRST

56 RCK RCK

57 I/O I/O

58 I/O I/O

59 I/O I/O

60 GL3 GL3

61 PPECL2 (I/P) PPECL2 (I/P)

62 AVDD AVDD

63 NPECL2 NPECL2

64 AGND AGND

65 GL4 GL4

66 I/O (GLMX2) I/O (GLMX2)

67 GND GND

68 VDD VDD

69 I/O I/O

70 I/O I/O

71 I/O I/O

72 I/O I/O

73 I/O I/O

74 I/O I/O

75 GND GND

76 VDDP VDDP

77 I/O I/O

78 I/O I/O

79 I/O I/O

80 I/O I/O

81 I/O I/O

82 I/O I/O

83 I/O I/O

84 I/O I/O

100-Pin TQFP

Number APA075

Function APA150

Function

ProASICPLUS Flash Family FPGAs

64 v3.0

85 I/O I/O

86 GND GND

87 VDDP VDDP

88 GND GND

89 VDD VDD

90 I/O I/O

91 I/O I/O

92 I/O I/O

93 I/O I/O

94 I/O I/O

95 I/O I/O

96 I/O I/O

97 I/O I/O

98 I/O I/O

99 I/O I/O

100 VDDP VDDP

100-Pin TQFP

Number APA075

Function APA150

Function

v3.0 65

ProASICPLUS Flash Family FPGAs

Package Pin Assignments

144-Pin TQFP

1144

144-Pin

TQFP

ProASICPLUS Flash Family FPGAs

66 v3.0

144-Pin TQFP

Pin Number APA075

Function

1 I/O

2 I/O

3 I/O

4 I/O

5 I/O

6 I/O

7 I/O

8 I/O

10 GND

11 VDDP

12 I/O

13 I/O

14 I/O

15 GL

16 GL

17 AGND

18 NPECL

19 AVDD

20 PPECL (I/P)

21 I/O (GLMX)

22 I/O

23 I/O

24 I/O

25 I/O

26 I/O

27 GND

28 VDDP

29 I/O

30 I/O

31 I/O

32 I/O

33 I/O

34 I/O

35 I/O

36 I/O

37 I/O

38 I/O

39 I/O

40 I/O

41 I/O

42 I/O

43 I/O

44 I/O

45 VDD

46 GND

47 VDDP

48 I/O

49 I/O

50 I/O

51 I/O

52 I/O

53 I/O

54 I/O

55 I/O

56 I/O

57 I/O

58 I/O

59 I/O

60 I/O

61 I/O

62 VDD

63 GND

64 VDDP

65 I/O

66 I/O

67 I/O

68 I/O

69 TCK

70 TDI

71 TMS

72 NC

73 VPP

74 VPN

75 TDO

76 TRST

77 RCK

78 I/O

79 I/O

80 I/O

81 VDDP

82 GND

83 I/O

84 I/O

144-Pin TQFP

Pin Number APA075

Function

85 I/O

86 I/O

87 I/O

88 I/O (GLMX)

89 PPECL (I/P)

90 AVDD

91 NPECL

92 AGND

93 GL

94 GL

95 I/O

96 I/O

97 I/O

98 VDDP

99 GND

100 VDD

101 I/O

102 I/O

103 I/O

104 I/O

105 I/O

106 I/O

107 I/O

108 I/O

109 I/O

110 I/O

111 I/O

112 I/O

113 I/O

114 I/O

115 I/O

116 I/O

117 VDDP

118 GND

119 VDD

120 I/O

121 I/O

122 I/O

123 I/O

124 I/O

125 I/O

126 I/O

144-Pin TQFP

Pin Number APA075

Function

127 I/O

128 I/O

129 I/O

130 I/O

131 I/O

132 I/O

133 I/O

134 VDDP

135 GND

136 VDD

137 I/O

138 I/O

139 I/O

140 I/O

141 I/O

142 I/O

143 I/O

144 I/O

144-Pin TQFP

Pin Number APA075

Function

v3.0 67

ProASICPLUS Flash Family FPGAs

Package Pin Assignments (Continued)

208-Pin PQFP

1208

ProASICPLUS Flash Family FPGAs

68 v3.0

208-Pin PQFP

Number APA075

Function APA150

Function APA300

Function APA450

Function APA600

Function APA750

Function APA1000

Function

1 GND GND GND GND GND GND GND

2 I/O I/O I/O I/O I/O I/O I/O

3 I/O I/O I/O I/O I/O I/O I/O

4 I/O I/O I/O I/O I/O I/O I/O

5 I/O I/O I/O I/O I/O I/O I/O

6 I/O I/O I/O I/O I/O I/O I/O

7 I/O I/O I/O I/O I/O I/O I/O

8 I/O I/O I/O I/O I/O I/O I/O

9 I/O I/O I/O I/O I/O I/O I/O

10 I/O I/O I/O I/O I/O I/O I/O

11 I/O I/O I/O I/O I/O I/O I/O

12 I/O I/O I/O I/O I/O I/O I/O

13 I/O I/O I/O I/O I/O I/O I/O

14 I/O I/O I/O I/O I/O I/O I/O

15 I/O I/O I/O I/O I/O I/O I/O

16 VDD VDD VDD VDD VDD VDD VDD

17 GND GND GND GND GND GND GND

18 I/O I/O I/O I/O I/O I/O I/O

19 I/O I/O I/O I/O I/O I/O I/O

20 I/O I/O I/O I/O I/O I/O I/O

21 I/O I/O I/O I/O I/O I/O I/O

22 VDDP VDDP VDDP VDDP VDDP VDDP VDDP

23 I/O (GLMX1) I/O (GLMX1) I/O (GLMX1) I/O (GLM X1) I/O (GLMX1) I/O (GLMX1) I/O (GLMX1)

24 GL1 GL1 GL1 GL1 GL1 GL1 GL1

25 AGND AGND AGND AGND AGND AGND AGND

26 NPECL1 NPECL1 NPECL1 NPECL1 NPECL1 NPECL1 NPECL1

27 AVDD AVDD AVDD AVDD AVDD AVDD AVDD

28 PPECL1 (I /P) PPECL1 (I/P) PPECL1 (I/P) PPECL1 (I/P) PPECL1 (I/P) PPECL1 (I/P) PPECL1 (I/P)

29 GND GND GND GND GND GND GND

30 GL2 GL2 GL2 GL2 GL2 GL2 GL2

31 I/O I/O I/O I/O I/O I/O I/O

32 I/O I/O I/O I/O I/O I/O I/O

33 I/O I/O I/O I/O I/O I/O I/O

34 I/O I/O I/O I/O I/O I/O I/O

35 I/O I/O I/O I/O I/O I/O I/O

36 VDD VDD VDD VDD VDD VDD VDD

37 I/O I/O I/O I/O I/O I/O I/O

38 I/O I/O I/O I/O I/O I/O I/O

39 I/O I/O I/O I/O I/O I/O I/O

40 VDDP VDDP VDDP VDDP VDDP VDDP VDDP

41 GND GND GND GND GND GND GND

42 I/O I/O I/O I/O I/O I/O I/O

v3.0 69

ProASICPLUS Flash Family FPGAs

43 I/O I/O I/O I/O I/O I/O I/O

44 I/O I/O I/O I/O I/O I/O I/O

45 I/O I/O I/O I/O I/O I/O I/O

46 I/O I/O I/O I/O I/O I/O I/O

47 I/O I/O I/O I/O I/O I/O I/O

48 I/O I/O I/O I/O I/O I/O I/O

49 I/O I/O I/O I/O I/O I/O I/O

50 I/O I/O I/O I/O I/O I/O I/O

51 I/O I/O I/O I/O I/O I/O I/O

52 GND GND GND GND GND GND GND

53 VDDP VDDP VDDP VDDP VDDP VDDP VDDP

54 I/O I/O I/O I/O I/O I/O I/O

55 I/O I/O I/O I/O I/O I/O I/O

56 I/O I/O I/O I/O I/O I/O I/O

57 I/O I/O I/O I/O I/O I/O I/O

58 I/O I/O I/O I/O I/O I/O I/O

59 I/O I/O I/O I/O I/O I/O I/O

60 I/O I/O I/O I/O I/O I/O I/O

61 I/O I/O I/O I/O I/O I/O I/O

62 I/O I/O I/O I/O I/O I/O I/O

63 I/O I/O I/O I/O I/O I/O I/O

64 I/O I/O I/O I/O I/O I/O I/O

65 GND GND GND GND GND GND GND

66 I/O I/O I/O I/O I/O I/O I/O

67 I/O I/O I/O I/O I/O I/O I/O

68 I/O I/O I/O I/O I/O I/O I/O

69 I/O I/O I/O I/O I/O I/O I/O

70 I/O I/O I/O I/O I/O I/O I/O

71 VDD VDD VDD VDD VDD VDD VDD

72 VDDP VDDP VDDP VDDP VDDP VDDP VDDP

73 I/O I/O I/O I/O I/O I/O I/O

74 I/O I/O I/O I/O I/O I/O I/O

75 I/O I/O I/O I/O I/O I/O I/O

76 I/O I/O I/O I/O I/O I/O I/O

77 I/O I/O I/O I/O I/O I/O I/O

78 I/O I/O I/O I/O I/O I/O I/O

79 I/O I/O I/O I/O I/O I/O I/O

80 I/O I/O I/O I/O I/O I/O I/O

81 GND GND GND GND GND GND GND

82 I/O I/O I/O I/O I/O I/O I/O

83 I/O I/O I/O I/O I/O I/O I/O

84 I/O I/O I/O I/O I/O I/O I/O

208-Pin PQFP (Continued)

Number APA075

Function APA150

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Function APA600

Function APA750

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Function

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85 I/O I/O I/O I/O I/O I/O I/O

86 I/O I/O I/O I/O I/O I/O I/O

87 I/O I/O I/O I/O I/O I/O I/O

88 VDD VDD VDD VDD VDD VDD VDD

89 VDDP VDDP VDDP VDDP VDDP VDDP VDDP

90 I/O I/O I/O I/O I/O I/O I/O

91 I/O I/O I/O I/O I/O I/O I/O

92 I/O I/O I/O I/O I/O I/O I/O

93 I/O I/O I/O I/O I/O I/O I/O

94 I/O I/O I/O I/O I/O I/O I/O

95 I/O I/O I/O I/O I/O I/O I/O

96 I/O I/O I/O I/O I/O I/O I/O

97 GND GND GND GND GND GND GND

98 I/O I/O I/O I/O I/O I/O I/O

99 I/O I/O I/O I/O I/O I/O I/O

100 I/O I/O I/O I/O I/O I/O I/O

101 TCK TCK TCK TCK TCK TCK TCK

102 TDI TDI TDI TDI TDI TDI TDI

103TMSTMSTMSTMSTMSTMSTMS

104 VDDP VDDP VDDP VDDP VDDP VDDP VDDP

105 GND GND GND GND GND GND GND

106 VPP VPP VPP VPP VPP VPP VPP

107 VPN VPN VPN VPN VPN VPN VPN

108 TDO TDO TDO TDO TDO TDO TDO

109 TRST TRST TRST TRST TRST TRST TRST

110 RCK RCK RCK RCK RCK RCK RCK

111 I/O I/O I/O I/O I/O I/O I/O

112 I/O I/O I/O I/O I/O I/O I/O

113 I/O I/O I/O I/O I/O I/O I/O

114 I/O I/O I/O I/O I/O I/O I/O

115 I/O I/O I/O I/O I/O I/O I/O

116 I/O I/O I/O I/O I/O I/O I/O

117 I/O I/O I/O I/O I/O I/O I/O

118 I/O I/O I/O I/O I/O I/O I/O

119 I/O I/O I/O I/O I/O I/O I/O

120 I/O I/O I/O I/O I/O I/O I/O

121 I/O I/O I/O I/O I/O I/O I/O

122 GND GND GND GND GND GND GND

123 VDDP VDDP VDDP VDDP VDDP VDDP VDDP

124 I/O I/O I/O I/O I/O I/O I/O

125 I/O I/O I/O I/O I/O I/O I/O

126 VDD VDD VDD VDD VDD VDD VDD

208-Pin PQFP (Continued)

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Function

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127 I/O I/O I/O I/O I/O I/O I/O

128 GL3 GL3 GL3 GL3 GL3 GL3 GL3

129 PPECL2 (I/P) PPECL2 (I/P) PPECL2 (I/P) P PECL2 (I/P) PPECL2 (I/ P) PPECL2 (I /P) PPECL2 (I /P)

130 GND GND GND GND GND GND GND

131 AVDD AVDD AVDD AVDD AVDD AVDD AVDD

132 NPECL2 NPECL2 NPECL2 NPECL2 NPECL2 NPECL2 NPECL2

133 AGND AGND AGND AGND AGND AGND AGND

134 GL4 GL4 GL4 GL4 GL4 GL4 GL4

135 I/O (GLMX2) I/O (GLMX2) I/O (GLMX2) I/O (GLMX2) I/O (GLMX2) I/O (GLMX2) I/O (GLMX2)

136 I/O I/O I/O I/O I/O I/O I/O

137 I/O I/O I/O I/O I/O I/O I/O

138 VDDP VDDP VDDP VDDP VDDP VDDP VDDP

139 I/O I/O I/O I/O I/O I/O I/O

140 I/O I/O I/O I/O I/O I/O I/O

141 GND GND GND GND GND GND GND

142 VDD VDD VDD VDD VDD VDD VDD

143 I/O I/O I/O I/O I/O I/O I/O

144 I/O I/O I/O I/O I/O I/O I/O

145 I/O I/O I/O I/O I/O I/O I/O

146 I/O I/O I/O I/O I/O I/O I/O

147 I/O I/O I/O I/O I/O I/O I/O

148 I/O I/O I/O I/O I/O I/O I/O

149 I/O I/O I/O I/O I/O I/O I/O

150 I/O I/O I/O I/O I/O I/O I/O

151 I/O I/O I/O I/O I/O I/O I/O

152 I/O I/O I/O I/O I/O I/O I/O

153 I/O I/O I/O I/O I/O I/O I/O

154 I/O I/O I/O I/O I/O I/O I/O

155 I/O I/O I/O I/O I/O I/O I/O

156 GND GND GND GND GND GND GND

157 VDDP VDDP VDDP VDDP VDDP VDDP VDDP

158 I/O I/O I/O I/O I/O I/O I/O

159 I/O I/O I/O I/O I/O I/O I/O

160 I/O I/O I/O I/O I/O I/O I/O

161 I/O I/O I/O I/O I/O I/O I/O

162 GND GND GND GND GND GND GND

163 I/O I/O I/O I/O I/O I/O I/O

164 I/O I/O I/O I/O I/O I/O I/O

165 I/O I/O I/O I/O I/O I/O I/O

166 I/O I/O I/O I/O I/O I/O I/O

167 I/O I/O I/O I/O I/O I/O I/O

168 I/O I/O I/O I/O I/O I/O I/O

208-Pin PQFP (Continued)

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169 I/O I/O I/O I/O I/O I/O I/O

170 VDDP VDDP VDDP VDDP VDDP VDDP VDDP

171 VDD VDD VDD VDD VDD VDD VDD

172 I/O I/O I/O I/O I/O I/O I/O

173 I/O I/O I/O I/O I/O I/O I/O

174 I/O I/O I/O I/O I/O I/O I/O

175 I/O I/O I/O I/O I/O I/O I/O

176 I/O I/O I/O I/O I/O I/O I/O

177 I/O I/O I/O I/O I/O I/O I/O

178 GND GND GND GND GND GND GND

179 I/O I/O I/O I/O I/O I/O I/O

180 I/O I/O I/O I/O I/O I/O I/O

181 I/O I/O I/O I/O I/O I/O I/O

182 I/O I/O I/O I/O I/O I/O I/O

183 I/O I/O I/O I/O I/O I/O I/O

184 I/O I/O I/O I/O I/O I/O I/O

185 I/O I/O I/O I/O I/O I/O I/O

186 VDDP VDDP VDDP VDDP VDDP VDDP VDDP

187 VDD VDD VDD VDD VDD VDD VDD

188 I/O I/O I/O I/O I/O I/O I/O

189 I/O I/O I/O I/O I/O I/O I/O

190 I/O I/O I/O I/O I/O I/O I/O

191 I/O I/O I/O I/O I/O I/O I/O

192 I/O I/O I/O I/O I/O I/O I/O

193 I/O I/O I/O I/O I/O I/O I/O

194 I/O I/O I/O I/O I/O I/O I/O

195 GND GND GND GND GND GND GND

196 I/O I/O I/O I/O I/O I/O I/O

197 I/O I/O I/O I/O I/O I/O I/O

198 I/O I/O I/O I/O I/O I/O I/O

199 I/O I/O I/O I/O I/O I/O I/O

200 I/O I/O I/O I/O I/O I/O I/O

201 I/O I/O I/O I/O I/O I/O I/O

202 I/O I/O I/O I/O I/O I/O I/O

203 I/O I/O I/O I/O I/O I/O I/O

204 I/O I/O I/O I/O I/O I/O I/O

205 I/O I/O I/O I/O I/O I/O I/O

206 I/O I/O I/O I/O I/O I/O I/O

207 I/O I/O I/O I/O I/O I/O I/O

208 VDDP VDDP VDDP VDDP VDDP VDDP VDDP

208-Pin PQFP (Continued)

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Function APA750

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Function

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ProASICPLUS Flash Family FPGAs

Package Pin Assignments (Continued)

456-Pin PBGA (Bottom View)

12356789101115 14 13 121617181920212223 4242526

A1 Ball Pad Corner

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74 v3.0

456-Pin PBGA

Number APA150

Function APA300

Function APA450

Function APA600

Function APA750

Function APA1000

Function

A1 VDDP VDDP VDDP VDDP VDDP VDDP

A2 VDDP VDDP VDDP VDDP VDDP VDDP

A3 NC NC I/O I/O I/O I/O

A4 NC NC I/O I/O I/O I/O

A5 NC NC I/O I/O I/O I/O

A6 NC NC I/O I/O I/O I/O

A7 NC NC I/O I/O I/O I/O

A8 I/O I/O I/O I/O I/O I/O

A9 I/O I/O I/O I/O I/O I/O

A10 I/O I/O I/O I/O I/O I/O

A11 I/O I/O I/O I/O I/O I/O

A12 I/O I/O I/O I/O I/O I/O

A13 I/O I/O I/O I/O I/O I/O

A14 I/O I/O I/O I/O I/O I/O

A15 I/O I/O I/O I/O I/O I/O

A16 I/O I/O I/O I/O I/O I/O

A17 I/O I/O I/O I/O I/O I/O

A18 I/O I/O I/O I/O I/O I/O

A19 I/O I/O I/O I/O I/O I/O

A20 NC NC I/O I/O I/O I/O

A21 NC NC I/O I/O I/O I/O

A22 NC NC I/O I/O I/O I/O

A23 NC NC I/O I/O I/O I/O

A24 NC NC I/O I/O I/O I/O

A25 VDDP VDDP VDDP VDDP VDDP VDDP

A26 VDDP VDDP VDDP VDDP VDDP VDDP

B1 VDDP VDDP VDDP VDDP VDDP VDDP

B2 VDDP VDDP VDDP VDDP VDDP VDDP

B3 NC NC NC I/O I/O I/O

B4 NC NC I/O I/O I/O I/O

B5 NC NC I/O I/O I/O I/O

B6 NC NC I/O I/O I/O I/O

B7 NC NC I/O I/O I/O I/O

B8 I/O I/O I/O I/O I/O I/O

B9 I/O I/O I/O I/O I/O I/O

B10 I/O I/O I/O I/O I/O I/O

B11 I/O I/O I/O I/O I/O I/O

B12 I/O I/O I/O I/O I/O I/O

B13 I/O I/O I/O I/O I/O I/O

B14 I/O I/O I/O I/O I/O I/O

B15 I/O I/O I/O I/O I/O I/O

B16 I/O I/O I/O I/O I/O I/O

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B17 I/O I/O I/O I/O I/O I/O

B18 I/O I/O I/O I/O I/O I/O

B19 I/O I/O I/O I/O I/O I/O

B20 NC NC I/O I/O I/O I/O

B21 NC NC I/O I/O I/O I/O

B22 NC NC I/O I/O I/O I/O

B23 NC NC I/O I/O I/O I/O

B24 NC NC I/O I/O I/O I/O

B25 VDDP VDDP VDDP VDDP VDDP VDDP

B26 VDDP VDDP VDDP VDDP VDDP VDDP

C1 VDDP VDDP VDDP VDDP VDDP VDDP

C2 NC I/O I/O I/O I/O I/O

C3 VDDP VDDP VDDP VDDP VDDP VDDP

C4 NC NC NC I/O I/O I/O

C5 NC NC I/O I/O I/O I/O

C6 NC NC I/O I/O I/O I/O

C7 I/O I/O I/O I/O I/O I/O

C8 I/O I/O I/O I/O I/O I/O

C9 I/O I/O I/O I/O I/O I/O

C10 I/O I/O I/O I/O I/O I/O

C11 I/O I/O I/O I/O I/O I/O

C12 I/O I/O I/O I/O I/O I/O

C13 I/O I/O I/O I/O I/O I/O

C14 I/O I/O I/O I/O I/O I/O

C15 I/O I/O I/O I/O I/O I/O

C16 I/O I/O I/O I/O I/O I/O

C17 I/O I/O I/O I/O I/O I/O

C18 I/O I/O I/O I/O I/O I/O

C19 I/O I/O I/O I/O I/O I/O

C20 I/O I/O I/O I/O I/O I/O

C21 NC NC I/O I/O I/O I/O

C22 NC NC I/O I/O I/O I/O

C23 NC NC I/O I/O I/O I/O

C24 VDDP VDDP VDDP VDDP VDDP VDDP

C25 NC NC NC I/O I/O I/O

C26 NC NC NC I/O I/O I/O

D1 NC NC NC I/O I/O I/O

D2 NC NC NC I/O I/O I/O

D3 NC I/O I/O I/O I/O I/O

D4 VDDP VDDP VDDP VDDP VDDP VDDP

D5 NC NC I/O I/O I/O I/O

D6 NC NC I/O I/O I/O I/O

456-Pin PBGA (Continued)

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Function

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D7 I/O I/O I/O I/O I/O I/O

D8 I/O I/O I/O I/O I/O I/O

D9 I/O I/O I/O I/O I/O I/O

D10 I/O I/O I/O I/O I/O I/O

D11 I/O I/O I/O I/O I/O I/O

D12 I/O I/O I/O I/O I/O I/O

D13 I/O I/O I/O I/O I/O I/O

D14 I/O I/O I/O I/O I/O I/O

D15 I/O I/O I/O I/O I/O I/O

D16 I/O I/O I/O I/O I/O I/O

D17 I/O I/O I/O I/O I/O I/O

D18 I/O I/O I/O I/O I/O I/O

D19 I/O I/O I/O I/O I/O I/O

D20 I/O I/O I/O I/O I/O I/O

D21 I/O I/O I/O I/O I/O I/O

D22 NC NC I/O I/O I/O I/O

D23 VDDP VDDP VDDP VDDP VDDP VDDP

D24 NC I/O I/O I/O I/O I/O

D25 NC NC NC I/O I/O I/O

D26 NC NC NC I/O I/O I/O

E1 NC I/O I/O I/O I/O I/O

E2 NC I/O I/O I/O I/O I/O

E3 NC I/O I/O I/O I/O I/O

E4 NC I/O I/O I/O I/O I/O

E5 VDD VDD VDD VDD VDD VDD

E6 VDD VDD VDD VDD VDD VDD

E7 VDD VDD VDD VDD VDD VDD

E8 VDD VDD VDD VDD VDD VDD

E9 I/O I/O I/O I/O I/O I/O

E10 I/O I/O I/O I/O I/O I/O

E11 I/O I/O I/O I/O I/O I/O

E12 I/O I/O I/O I/O I/O I/O

E13 I/O I/O I/O I/O I/O I/O

E14 I/O I/O I/O I/O I/O I/O

E15 I/O I/O I/O I/O I/O I/O

E16 I/O I/O I/O I/O I/O I/O

E17 I/O I/O I/O I/O I/O I/O

E18 I/O I/O I/O I/O I/O I/O

E19 I/O I/O I/O I/O I/O I/O

E20 VDD VDD VDD VDD VDD VDD

E21 VDD VDD VDD VDD VDD VDD

E22 VDD VDD VDD VDD VDD VDD

456-Pin PBGA (Continued)

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Function

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E23 NC I/O I/O I/O I/O I/O

E24 NC I/O I/O I/O I/O I/O

E25 NC I/O I/O I/O I/O I/O

E26 NC I/O I/O I/O I/O I/O

F1 NC I/O I/O I/O I/O I/O

F2 NC I/O I/O I/O I/O I/O

F3 NC I/O I/O I/O I/O I/O

F4 NC I/O I/O I/O I/O I/O

F5 VDD VDD VDD VDD VDD VDD

F22 VDD VDD VDD VDD VDD VDD

F23 NC I/O I/O I/O I/O I/O

F24 NC I/O I/O I/O I/O I/O

F25 NC I/O I/O I/O I/O I/O

F26 NC I/O I/O I/O I/O I/O

G1 I/O I/O I/O I/O I/O I/O

G2 I/O I/O I/O I/O I/O I/O

G3 NC I/O I/O I/O I/O I/O

G4 NC I/O I/O I/O I/O I/O

G5 VDD VDD VDD VDD VDD VDD

G22 VDD VDD VDD VDD VDD VDD

G23 NC I/O I/O I/O I/O I/O

G24 NC I/O I/O I/O I/O I/O

G25 NC I/O I/O I/O I/O I/O

G26 I/O I/O I/O I/O I/O I/O

H1 I/O I/O I/O I/O I/O I/O

H2 I/O I/O I/O I/O I/O I/O

H3 I/O I/O I/O I/O I/O I/O

H4 I/O I/O I/O I/O I/O I/O

H5 VDD VDD VDD VDD VDD VDD

H22 VDD VDD VDD VDD VDD VDD

H23 I/O I/O I/O I/O I/O I/O

H24 I/O I/O I/O I/O I/O I/O

H25 I/O I/O I/O I/O I/O I/O

H26 I/O I/O I/O I/O I/O I/O

J1 I/O I/O I/O I/O I/O I/O

J2 I/O I/O I/O I/O I/O I/O

J3 I/O I/O I/O I/O I/O I/O

J4 I/O I/O I/O I/O I/O I/O

J5 I/O I/O I/O I/O I/O I/O

J22 I/O I/O I/O I/O I/O I/O

J23 I/O I/O I/O I/O I/O I/O

J24 I/O I/O I/O I/O I/O I/O

456-Pin PBGA (Continued)

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Function

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J25 I/O I/O I/O I/O I/O I/O

J26 I/O I/O I/O I/O I/O I/O

K1 I/O I/O I/O I/O I/O I/O

K2 I/O I/O I/O I/O I/O I/O

K3 I/O I/O I/O I/O I/O I/O

K4 I/O I/O I/O I/O I/O I/O

K5 I/O I/O I/O I/O I/O I/O

K22 I/O I/O I/O I/O I/O I/O

K23 I/O I/O I/O I/O I/O I/O

K24 I/O I/O I/O I/O I/O I/O

K25 I/O I/O I/O I/O I/O I/O

K26 I/O I/O I/O I/O I/O I/O

L1 I/O I/O I/O I/O I/O I/O

L2 I/O I/O I/O I/O I/O I/O

L3 I/O I/O I/O I/O I/O I/O

L4 I/O I/O I/O I/O I/O I/O

L5 I/O I/O I/O I/O I/O I/O

L11 GND GND GND GND GND GND

L12 GND GND GND GND GND GND

L13 GND GND GND GND GND GND

L14 GND GND GND GND GND GND

L15 GND GND GND GND GND GND

L16 GND GND GND GND GND GND

L22 I/O I/O I/O I/O I/O I/O

L23 I/O I/O I/O I/O I/O I/O

L24 I/O I/O I/O I/O I/O I/O

L25 I/O I/O I/O I/O I/O I/O

L26 I/O I/O I/O I/O I/O I/O

M1 GL1GL1GL1GL1GL1GL1

M2 GL2GL2GL2GL2GL2GL2

M3 I/O I/O I/O I/O I/O I/O

M4 I/O I/O I/O I/O I/O I/O

M5 I/O I/O I/O I/O I/O I/O

M11 GND GND GND GND GND GND

M12 GND GND GND GND GND GND

M13 GND GND GND GND GND GND

M14 GND GND GND GND GND GND

M15 GND GND GND GND GND GND

M16 GND GND GND GND GND GND

M22 GL4 GL4 GL4 GL4 GL4 GL4

M23 I/O I/O I/O I/O I/O I/O

M24 I/O I/O I/O I/O I/O I/O

456-Pin PBGA (Continued)

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Function

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ProASICPLUS Flash Family FPGAs

M25 I/O I/O I/O I/O I/O I/O

M26 I/O I/O I/O I/O I/O I/O

N1 I/O I/O I/O I/O I/O I/O

N2 I/O (GLMX1) I/O (GLMX)1 I/O (GLMX1) I/O (GLMX1) I/O (GLMX1) I/O (GLMX1)

N3 AGND AGND AGND AGND AGND AGND

N4 PPECL1 (I/P) PPECL1 ( I/P) PPECL1 (I /P) PPECL1 (I/P) PPECL1 (I/P) PPECL1 (I/P)

N5 AVDD AVDD AVDD AVDD AVDD AVDD

N11 GND GND GND GND GND GND

N12 GND GND GND GND GND GND

N13 GND GND GND GND GND GND

N14 GND GND GND GND GND GND

N15 GND GND GND GND GND GND

N16 GND GND GND GND GND GND

N22 NPECL2 NPECL2 NPECL2 NPECL2 NPECL2 NPECL2

N23 GL3 GL3 GL3 GL3 GL3 GL3

N24 AVDDAVDDAVDDAVDDAVDDAVDD

N25 I/O (GLMX2) I/O (GLMX) I/O (GLMX2) I/O (GLMX2) I/O (GLMX2) I/O (GLMX2)

N26 AGND AGND AGND AGND AGND AGND

P1 I/O I/O I/O I/O I/O I/O

P2 I/O I/O I/O I/O I/O I/O

P3 I/O I/O I/O I/O I/O I/O

P4 I/O I/O I/O I/O I/O I/O

P5 NPECL1 NPECL1 NPECL1 NPECL1 NPECL1 NPECL1

P11 GND GND GND GND GND GND

P12 GND GND GND GND GND GND

P13 GND GND GND GND GND GND

P14 GND GND GND GND GND GND

P15 GND GND GND GND GND GND

P16 GND GND GND GND GND GND

P22 I/O I/O I/O I/O I/O I/O

P23 I/O I/O I/O I/O I/O I/O

P24 I/O I/O I/O I/O I/O I/O

P25 I/O I/O I/O I/O I/O I/O

P26 PPECL2 (I/P) PPECL2 (I/P) PPECL2 (I/P) PPECL 2 (I/P) PPECL2 (I/P) PPECL2 (I/P)

R1 I/O I/O I/O I/O I/O I/O

R2 I/O I/O I/O I/O I/O I/O

R3 I/O I/O I/O I/O I/O I/O

R4 I/O I/O I/O I/O I/O I/O

R5 I/O I/O I/O I/O I/O I/O

R11 GND GND GND GND GND GND

R12 GND GND GND GND GND GND

R13 GND GND GND GND GND GND

456-Pin PBGA (Continued)

Number APA150

Function APA300

Function APA450

Function APA600

Function APA750

Function APA1000

Function

ProASICPLUS Flash Family FPGAs

80 v3.0

R14 GND GND GND GND GND GND

R15 GND GND GND GND GND GND

R16 GND GND GND GND GND GND

R22 I/O I/O I/O I/O I/O I/O

R23 I/O I/O I/O I/O I/O I/O

R24 I/O I/O I/O I/O I/O I/O

R25 I/O I/O I/O I/O I/O I/O

R26 I/O I/O I/O I/O I/O I/O

T1 I/O I/O I/O I/O I/O I/O

T2 I/O I/O I/O I/O I/O I/O

T3 I/O I/O I/O I/O I/O I/O

T4 I/O I/O I/O I/O I/O I/O

T5 I/O I/O I/O I/O I/O I/O

T11 GND GND GND GND GND GND

T12 GND GND GND GND GND GND

T13 GND GND GND GND GND GND

T14 GND GND GND GND GND GND

T15 GND GND GND GND GND GND

T16 GND GND GND GND GND GND

T22 I/O I/O I/O I/O I/O I/O

T23 I/O I/O I/O I/O I/O I/O

T24 I/O I/O I/O I/O I/O I/O

T25 I/O I/O I/O I/O I/O I/O

T26 I/O I/O I/O I/O I/O I/O

U1 I/O I/O I/O I/O I/O I/O

U2 I/O I/O I/O I/O I/O I/O

U3 I/O I/O I/O I/O I/O I/O

U4 I/O I/O I/O I/O I/O I/O

U5 I/O I/O I/O I/O I/O I/O

U22 I/O I/O I/O I/O I/O I/O

U23 I/O I/O I/O I/O I/O I/O

U24 I/O I/O I/O I/O I/O I/O

U25 I/O I/O I/O I/O I/O I/O

U26 I/O I/O I/O I/O I/O I/O

V1 I/O I/O I/O I/O I/O I/O

V2 I/O I/O I/O I/O I/O I/O

V3 I/O I/O I/O I/O I/O I/O

V4 I/O I/O I/O I/O I/O I/O

V5 I/O I/O I/O I/O I/O I/O

V22 I/O I/O I/O I/O I/O I/O

V23 I/O I/O I/O I/O I/O I/O

V24 I/O I/O I/O I/O I/O I/O

456-Pin PBGA (Continued)

Number APA150

Function APA300

Function APA450

Function APA600

Function APA750

Function APA1000

Function

v3.0 81

ProASICPLUS Flash Family FPGAs

V25 I/O I/O I/O I/O I/O I/O

V26 I/O I/O I/O I/O I/O I/O

W1 I/O I/O I/O I/O I/O I/O

W2 I/O I/O I/O I/O I/O I/O

W3 I/O I/O I/O I/O I/O I/O

W4 I/O I/O I/O I/O I/O I/O

W5 VDD VDD VDD VDD VDD VDD

W22 VDD VDD VDD VDD VDD VDD

W23 I/O I/O I/O I/O I/O I/O

W24 I/O I/O I/O I/O I/O I/O

W25 I/O I/O I/O I/O I/O I/O

W26 I/O I/O I/O I/O I/O I/O

Y1 I/O I/O I/O I/O I/O I/O

Y2 I/O I/O I/O I/O I/O I/O

Y3 I/O I/O I/O I/O I/O I/O

Y4 NC I/O I/O I/O I/O I/O

Y5 VDD VDD VDD VDD VDD VDD

Y22 VDD VDD VDD VDD VDD VDD

Y23 NC I/O I/O I/O I/O I/O

Y24 NC I/O I/O I/O I/O I/O

Y25 NC I/O I/O I/O I/O I/O

Y26 NC I/O I/O I/O I/O I/O

AA1 I/O I/O I/O I/O I/O I/O

AA2 NC I/O I/O I/O I/O I/O

AA3 NC I/O I/O I/O I/O I/O

AA4 NC I/O I/O I/O I/O I/O

AA5 VDD VDD VDD VDD VDD VDD

AA22 VDD VDD VDD VDD VDD VDD

AA23 NC I/O I/O I/O I/O I/O

AA24 NC I/O I/O I/O I/O I/O

AA25 NC I/O I/O I/O I/O I/O

AA26 NC I/O I/O I/O I/O I/O

AB1 NC I/O I/O I/O I/O I/O

AB2 NC I/O I/O I/O I/O I/O

AB3 NC I/O I/O I/O I/O I/O

AB4 NC I/O I/O I/O I/O I/O

AB5 VDD VDD VDD VDD VDD VDD

AB6 VDD VDD VDD VDD VDD VDD

AB7 VDD VDD VDD VDD VDD VDD

AB8 I/O I/O I/O I/O I/O I/O

AB9 I/O I/O I/O I/O I/O I/O

AB10 I/O I/O I/O I/O I/O I/O

456-Pin PBGA (Continued)

Number APA150

Function APA300

Function APA450

Function APA600

Function APA750

Function APA1000

Function

ProASICPLUS Flash Family FPGAs

82 v3.0

AB11 I/O I/O I/O I/O I/O I/O

AB12 I/O I/O I/O I/O I/O I/O

AB13 I/O I/O I/O I/O I/O I/O

AB14 I/O I/O I/O I/O I/O I/O

AB15 I/O I/O I/O I/O I/O I/O

AB16 I/O I/O I/O I/O I/O I/O

AB17 I/O I/O I/O I/O I/O I/O

AB18 I/O I/O I/O I/O I/O I/O

AB19 I/O I/O I/O I/O I/O I/O

AB20 VDD VDD VDD VDD VDD VDD

AB21 VDD VDD VDD VDD VDD VDD

AB22 VDD VDD VDD VDD VDD VDD

AB23 NC I/O I/O I/O I/O I/O

AB24 NC I/O I/O I/O I/O I/O

AB25 NC I/O I/O I/O I/O I/O

AB26 NC NC NC I/O I/O I/O

AC1 NC I/O I/O I/O I/O I/O

AC2 NC I/O I/O I/O I/O I/O

AC3 NC I/O I/O I/O I/O I/O

AC4 VDDP VDDP VDDP VDDP VDDP VDDP

AC5 NC NC I/O I/O I/O I/O

AC6 I/O I/O I/O I/O I/O I/O

AC7 I/O I/O I/O I/O I/O I/O

AC8 I/O I/O I/O I/O I/O I/O

AC9 I/O I/O I/O I/O I/O I/O

AC10 I/O I/O I/O I/O I/O I/O

AC11 I/O I/O I/O I/O I/O I/O

AC12 I/O I/O I/O I/O I/O I/O

AC13 I/O I/O I/O I/O I/O I/O

AC14 I/O I/O I/O I/O I/O I/O

AC15 I/O I/O I/O I/O I/O I/O

AC16 I/O I/O I/O I/O I/O I/O

AC17 I/O I/O I/O I/O I/O I/O

AC18 I/O I/O I/O I/O I/O I/O

AC19 I/O I/O I/O I/O I/O I/O

AC2 0 I/O I/O I/O I/O I/O I/O

AC21 TMS TMS TMS TMS TMS TMS

AC22TDOTDOTDOTDOTDOTDO

AC23 V DDP VDDP VDDP VDDP VDDP VDDP

AC24 RCK RCK RCK RCK RCK RCK

AC25 NC NC I/O I/O I/O I/O

AC26 NC I/O I/O I/O I/O I/O

456-Pin PBGA (Continued)

Number APA150

Function APA300

Function APA450

Function APA600

Function APA750

Function APA1000

Function

v3.0 83

ProASICPLUS Flash Family FPGAs

AD1 NC NC NC I/O I/O I/O

AD2 NC I/O I/O I/O I/O I/O

AD3 VDDP VDDP VDDP VDDP VDDP VDDP

AD4 NC NC I/O I/O I/O I/O

AD5 NC NC I/O I/O I/O I/O

AD6 NC NC I/O I/O I/O I/O

AD7 I/O I/O I/O I/O I/O I/O

AD8 I/O I/O I/O I/O I/O I/O

AD9 I/O I/O I/O I/O I/O I/O

AD10 I/O I/O I/O I/O I/O I/O

AD11 I/O I/O I/O I/O I/O I/O

AD12 I/O I/O I/O I/O I/O I/O

AD13 I/O I/O I/O I/O I/O I/O

AD14 I/O I/O I/O I/O I/O I/O

AD15 I/O I/O I/O I/O I/O I/O

AD16 I/O I/O I/O I/O I/O I/O

AD17 I/O I/O I/O I/O I/O I/O

AD18 I/O I/O I/O I/O I/O I/O

AD19 I/O I/O I/O I/O I/O I/O

AD20 NC NC I/O I/O I/O I/O

AD21 TCK TCK TCK TCK TCK TCK

AD22 VPP VPP VPP VPP VPP VPP

AD23 NC NC NC I/O I/O I/O

AD24 V DDP VDDP VDDP VDDP VDDP VDDP

AD25 NC NC I/O I/O I/O I/O

AD26 NC NC I/O I/O I/O I/O

AE1 VDDP VDDP VDDP VDDP VDDP VDDP

AE2 VDDP VDDP VDDP VDDP VDDP VDDP

AE3 NC NC I/O I/O I/O I/O

AE4 NC NC I/O I/O I/O I/O

AE5 NC NC I/O I/O I/O I/O

AE6 NC NC I/O I/O I/O I/O

AE7 NC NC I/O I/O I/O I/O

AE8 I/O I/O I/O I/O I/O I/O

AE9 I/O I/O I/O I/O I/O I/O

AE10 I/O I/O I/O I/O I/O I/O

AE11 I/O I/O I/O I/O I/O I/O

AE12 I/O I/O I/O I/O I/O I/O

AE13 I/O I/O I/O I/O I/O I/O

AE14 I/O I/O I/O I/O I/O I/O

AE15 I/O I/O I/O I/O I/O I/O

AE16 I/O I/O I/O I/O I/O I/O

456-Pin PBGA (Continued)

Number APA150

Function APA300

Function APA450

Function APA600

Function APA750

Function APA1000

Function

ProASICPLUS Flash Family FPGAs

84 v3.0

AE17 I/O I/O I/O I/O I/O I/O

AE18 I/O I/O I/O I/O I/O I/O

AE19 I/O I/O I/O I/O I/O I/O

AE20 NC NC I/O I/O I/O I/O

AE21 NC NC I/O I/O I/O I/O

AE22 NC NC I/O I/O I/O I/O

AE23 VPN VPN VPN VPN VPN VPN

AE24 TRST TRST TRST TRST TRST TRST

AE25 VDDP VDDP VDDP VDDP VDDP VDDP

AE26 VDDP VDDP VDDP VDDP VDDP VDDP

AF1 VDDP VDDP VDDP VDDP VDDP VDDP

AF2 VDDP VDDP VDDP VDDP VDDP VDDP

AF3 NC NC I/O I/O I/O I/O

AF4 NC NC I/O I/O I/O I/O

AF5 NC NC I/O I/O I/O I/O

AF6 NC NC I/O I/O I/O I/O

AF7 NC NC I/O I/O I/O I/O

AF8 NC NC NC I/O I/O I/O

AF9 I/O I/O I/O I/O I/O I/O

AF10 I/O I/O I/O I/O I/O I/O

AF11 I/O I/O I/O I/O I/O I/O

AF12 I/O I/O I/O I/O I/O I/O

AF13 I/O I/O I/O I/O I/O I/O

AF14 I/O I/O I/O I/O I/O I/O

AF15 I/O I/O I/O I/O I/O I/O

AF16 I/O I/O I/O I/O I/O I/O

AF17 I/O I/O I/O I/O I/O I/O

AF18 NC NC I/O I/O I/O I/O

AF19 NC NC I/O I/O I/O I/O

AF20 NC NC I/O I/O I/O I/O

AF21 NC NC I/O I/O I/O I/O

AF22 NC NC I/O I/O I/O I/O

AF23 TDI TDI TDI TDI TDI TDI

AF24 NC NC I/O I/O I/O I/O

AF25 VDDP VDDP VDDP VDDP VDDP VDDP

AF26 VDDP VDDP VDDP VDDP VDDP VDDP

456-Pin PBGA (Continued)

Number APA150

Function APA300

Function APA450

Function APA600

Function APA750

Function APA1000

Function

v3.0 85

ProASICPLUS Flash Family FPGAs

Package Assignments (Continued)

144-FBGA (Bottom View)

34567

101112

A1 Ball Pad Corner

ProASICPLUS Flash Family FPGAs

86 v3.0

144-FBGA Pin

Number APA075

Function APA150

Function APA300

Function APA450

Function

A1 I/O I/O I/O I/O

A2 I/O I/O I/O I/O

A3 I/O I/O I/O I/O

A4 I/O I/O I/O I/O

A5 I/O I/O I/O I/O

A6 GND GND GND GND

A7 I/O I/O I/O I/O

A8 VDD VDD VDD VDD

A9 I/O I/O I/O I/O

A10 I/O I/O I/O I/O

A11 I/O I/O I/O I/O

A12 I/O I/O I/O I/O

B1 I/O I/O I/O I/O

B2 GND GND GND GND

B3 I/O I/O I/O I/O

B4 I/O I/O I/O I/O

B5 I/O I/O I/O I/O

B6 I/O I/O I/O I/O

B7 I/O I/O I/O I/O

B8 I/O I/O I/O I/O

B9 I/O I/O I/O I/O

B10 I/O I/O I/O I/O

B11 GND GND GND GND

B12 I/O I/O I/O I/O

C1 I/O I/O I/O I/O

C2 GL2 GL2 GL2 GL2

C3 I/O I/O I/O I/O

C4 VDD VDD VDD VDD

C5 I/O I/O I/O I/O

C6 I/O I/O I/O I/O

C7 I/O I/O I/O I/O

C8 I/O I/O I/O I/O

C9 I/O I/O I/O I/O

C10 I/O I/O I/O I/O

C11 I/O I/O I/O I/O

C12 I/O I/O I/O I/O

D1 I/O I/O I/O I/O

D2 I/O I/O I/O I/O

D3 I/O I/O I/O I/O

D4 I/O I/O I/O I/O

D5 I/O I/O I/O I/O

D6 I/O I/O I/O I/O

D7 I/O I/O I/O I/O

D8 I/O I/O I/O I/O

D9 I/O I/O I/O I/O

D10 I/O I/O I/O I/O

D11 I/O I/O I/O I/O

D12 I/O

(GLMX2) I/O

(GLMX2)

E1 VDD VDD VDD VDD

E2 I/O I/O I/O I/O

E3 I/O I/O I/O I/O

E4 VDDP VDDP VDDP VDDP

E5 I/O I/O I/O I/O

E6 VDDP VDDP VDDP VDDP

E7 VDDP VDDP VDDP VDDP

E8 AVDD AVDD AVDD AVDD

E9 VDDP VDDP VDDP VDDP

E10 VDD VDD VDD VDD

E11 NPECL2 NPECL2 NPECL2 NPECL2

E12 AGND AGND AGND AGND

F1GL1GL1GL1GL1

F2 AGND AGND AGND AGND

F3 I/O

(GLMX1) I/O

(GLMX1)

F4 I/O I/O I/O I/O

F5 GND GND GND GND

F6 GND GND GND GND

F7 GND GND GND GND

F8 I/O I/O I/O I/O

F9GL4GL4GL4GL4

F10 GND GND GND GND

F11 PPECL2

(I/P) PPECL2

(I/P)

F12 GL3 GL3 GL3 GL3

G1 PPECL1

(I/P) PPECL1

(I/P)

G2 GND GND GND GND

G3 AVDD AVDD AVDD AVDD

G4 NPECL1 NPECL1 NPECL1 NPECL1

G5 GND GND GND GND

G6 GND GND GND GND

G7 GND GND GND GND

G8 I/O I/O I/O I/O

G9 I/O I/O I/O I/O

144-FBGA Pin (Continued)

Number APA075

Function APA150

Function APA300

Function APA450

Function

v3.0 87

ProASICPLUS Flash Family FPGAs

G10 I/O I/O I/O I/O

G11 I/O I/O I/O I/O

G12 I/O I/O I/O I/O

H1 VDD VDD VDD VDD

H2 I/O I/O I/O I/O

H3 I/O I/O I/O I/O

H4 I/O I/O I/O I/O

H5 VDD VDD VDD VDD

H6 I/O I/O I/O I/O

H7 I/O I/O I/O I/O

H8 I/O I/O I/O I/O

H9 I/O I/O I/O I/O

H10 VDDP VDDP VDDP VDDP

H11 I/O I/O I/O I/O

H12 VDD VDD VDD VDD

J1 I/O I/O I/O I/O

J2 I/O I/O I/O I/O

J3 VDDP VDDP VDDP VDDP

J4 I/O I/O I/O I/O

J5 I/O I/O I/O I/O

J6 I/O I/O I/O I/O

J7 VDD VDD VDD VDD

J8TCKTCKTCKTCK

J9 I/O I/O I/O I/O

J10 TDO TDO TDO TDO

J11 I/O I/O I/O I/O

J12 I/O I/O I/O I/O

K1 I/O I/O I/O I/O

K2 I/O I/O I/O I/O

K3 I/O I/O I/O I/O

K4 I/O I/O I/O I/O

K5 I/O I/O I/O I/O

K6 I/O I/O I/O I/O

K7 GND GND GND GND

K8 I/O I/O I/O I/O

K9 I/O I/O I/O I/O

K10 GND GND GND GND

K11 I/O I/O I/O I/O

K12 I/O I/O I/O I/O

L1 GND GND GND GND

L2 I/O I/O I/O I/O

L3 I/O I/O I/O I/O

144-FBGA Pin (Continued)

Number APA075

Function APA150

Function APA300

Function APA450

Function

L4 I/O I/O I/O I/O

L5 VDDP VDDP VDDP VDDP

L6 I/O I/O I/O I/O

L7 I/O I/O I/O I/O

L8 I/O I/O I/O I/O

L9 TMS TMS TMS TMS

L10 RCK RCK RCK RCK

L11 I/O I/O I/O I/O

L12 TRST TRST TRST TRST

M1 I/O I/O I/O I/O

M2 I/O I/O I/O I/O

M3 I/O I/O I/O I/O

M4 I/O I/O I/O I/O

M5 I/O I/O I/O I/O

M6 I/O I/O I/O I/O

M7 I/O I/O I/O I/O

M8 I/O I/O I/O I/O

M9 TDI TDI TDI TDI

M10 VDDP VDDP VDDP VDDP

M11 VPP VPP VPP VPP

M12 VPN VPN VPN VPN

144-FBGA Pin (Continued)

Number APA075

Function APA150

Function APA300

Function APA450

Function

ProASICPLUS Flash Family FPGAs

88 v3.0

Package Assignments (Continued)

256-FBGA (Bottom View)

791113

15 246

101214

A1 Ball Pad Corner

v3.0 89

ProASICPLUS Flash Family FPGAs

256-Pin FBGA

Number APA150

Function APA300

Function APA450

Function APA600

Function

A1 GND GND GND GND

A2 I/O I/O I/O I/O

A3 I/O I/O I/O I/O

A4 I/O I/O I/O I/O

A5 I/O I/O I/O I/O

A6 I/O I/O I/O I/O

A7 I/O I/O I/O I/O

A8 I/O I/O I/O I/O

A9 I/O I/O I/O I/O

A10 I/O I/O I/O I/O

A11 I/O I/O I/O I/O

A12 I/O I/O I/O I/O

A13 I/O I/O I/O I/O

A14 I/O I/O I/O I/O

A15 I/O I/O I/O I/O

A16 GND GND GND GND

B1 I/O I/O I/O I/O

B2 I/O I/O I/O I/O

B3 I/O I/O I/O I/O

B4 I/O I/O I/O I/O

B5 I/O I/O I/O I/O

B6 I/O I/O I/O I/O

B7 I/O I/O I/O I/O

B8 I/O I/O I/O I/O

B9 I/O I/O I/O I/O

B10 I/O I/O I/O I/O

B11 I/O I/O I/O I/O

B12 I/O I/O I/O I/O

B13 I/O I/O I/O I/O

B14 I/O I/O I/O I/O

B15 I/O I/O I/O I/O

B16 I/O I/O I/O I/O

C1 I/O I/O I/O I/O

C2 I/O I/O I/O I/O

C3 I/O I/O I/O I/O

C4 I/O I/O I/O I/O

C5 I/O I/O I/O I/O

C6 I/O I/O I/O I/O

C7 I/O I/O I/O I/O

C8 I/O I/O I/O I/O

C9 I/O I/O I/O I/O

C10 I/O I/O I/O I/O

C11 I/O I/O I/O I/O

C12 I/O I/O I/O I/O

C13 I/O I/O I/O I/O

ProASICPLUS Flash Family FPGAs

90 v3.0

C14 I/O I/O I/O I/O

C15 I/O I/O I/O I/O

C16 I/O I/O I/O I/O

D1 I/O I/O I/O I/O

D2 I/O I/O I/O I/O

D3 I/O I/O I/O I/O

D4 I/O I/O I/O I/O

D5 I/O I/O I/O I/O

D6 I/O I/O I/O I/O

D7 I/O I/O I/O I/O

D8 I/O I/O I/O I/O

D9 I/O I/O I/O I/O

D10 I/O I/O I/O I/O

D11 I/O I/O I/O I/O

D12 I/O I/O I/O I/O

D13 I/O I/O I/O I/O

D14 I/O I/O I/O I/O

D15 I/O I/O I/O I/O

D16 I/O I/O I/O I/O

E1 I/O I/O I/O I/O

E2 I/O I/O I/O I/O

E3 I/O I/O I/O I/O

E4 I/O I/O I/O I/O

E5 I/O I/O I/O I/O

E6 VDDP VDDP VDDP VDDP

E7 VDDP VDDP VDDP VDDP

E8 I/O I/O I/O I/O

E9 I/O I/O I/O I/O

E1 0 VDDP VDDP VDDP VDDP

E11 VDDP VDDP VDDP VDDP

E12 I/O I/O I/O I/O

E13 I/O I/O I/O I/O

E14 I/O I/O I/O I/O

E15 I/O I/O I/O I/O

E16 I/O I/O I/O I/O

F1 I/O I/O I/O I/O

F2 I/O I/O I/O I/O

F3 I/O I/O I/O I/O

F4 I/O I/O I/O I/O

F5 VDDP VDDP VDDP VDDP

F6 GND GND GND GND

F7 VDD VDD VDD VDD

F8 VDD VDD VDD VDD

F9 VDD VDD VDD VDD

F10 VDD VDD VDD VDD

256-Pin FBGA (Continued)

Number APA150

Function APA300

Function APA450

Function APA600

Function

v3.0 91

ProASICPLUS Flash Family FPGAs

F11 GND GND GND GND

F12 VDDP VDDP VDDP VDDP

F13 I/O I/O I/O I/O

F14 I/O I/O I/O I/O

F15 I/O I/O I/O I/O

F16 I/O I/O I/O I/O

G1 I/O I/O I/O I/O

G2 I/O I/O I/O I/O

G3 I/O I/O I/O I/O

G4 I/O I/O I/O I/O

G5 VDDP VDDP VDDP VDDP

G6 VDD VDD VDD VDD

G7 GND GND GND GND

G8 GND GND GND GND

G9 GND GND GND GND

G10 GND GND GND GND

G11 VDD VDD VDD VDD

G12 VDDP VDDP VDDP VDDP

G13 I/O I/O I/O I/O

G14 I/O I/O I/O I/O

G15 I/O I/O I/O I/O

G16 I/O I/O I/O I/O

H1 GL1 GL1 GL1 GL1

H2 NPECL1 NPECL 1 NPECL1 NPECL1

H3 I/O (GLMX1) I/O (GLMX1) I/O (GLMX1) I/O (GLMX1)

H4 AGND AGND AGND AGND

H5 I/O I/O I/O I/O

H6 VDD VDD VDD VDD

H7 GND GND GND GND

H8 GND GND GND GND

H9 GND GND GND GND

H10 GND GND GND GND

H11 VDD VDD VDD VDD

H12 I/O I/O I/O I/O

H13 I/O (GLMX2) I/O (GLMX2) I/O (GLMX2) I/O (GLMX2)

H14 NPECL2 NPECL 2 NPECL2 NPECL2

H15 AGND AGND AGND AGND

H16 GL4 GL4 GL4 GL4

J1 GL2 GL2 GL2 GL2

J2 PPECL1 (I/P) PPECL1 (I/P) PPECL1 (I/P) PPECL1 (I/P)

J3 AVDD AVDD AVDD AVDD

J4 I/O I/O I/O I/O

J5 I/O I/O I/O I/O

J6 VDD VDD VDD VDD

J7 GND GND GND G ND

256-Pin FBGA (Continued)

Number APA150

Function APA300

Function APA450

Function APA600

Function

ProASICPLUS Flash Family FPGAs

92 v3.0

J8 GND GND GND GND

J9 GND GND GND GND

J10 GND GND GND GND

J11 VDD VDD VDD VDD

J12 I/O I/O I/O I/O

J13 PPECL2 (I/P) PPECL2 (I/P) PPECL2 (I/P) PPECL2 (I/P)

J14 I/O I/O I/O I/O

J15 AVDD AVDD AVDD AVDD

J16 GL3 GL3 GL3 GL3

K1 I/O I/O I/O I/O

K2 I/O I/O I/O I/O

K3 I/O I/O I/O I/O

K4 I/O I/O I/O I/O

K5 VDDP VDDP VDDP VDDP

K6 VDD VDD VDD VDD

K7 GND GND GND GND

K8 GND GND GND GND

K9 GND GND GND GND

K10 GND GND GND GND

K11 VDD VDD VDD VDD

K1 2 VDDP VDDP VDDP VDDP

K13 I/O I/O I/O I/O

K14 I/O I/O I/O I/O

K15 I/O I/O I/O I/O

K16 I/O I/O I/O I/O

L1 I/O I/O I/O I/O

L2 I/O I/O I/O I/O

L3 I/O I/O I/O I/O

L4 I/O I/O I/O I/O

L5 VDDP VDDP VDDP VDDP

L6 GND GND GND GND

L7 VDD VDD VDD VDD

L8 VDD VDD VDD VDD

L9 VDD VDD VDD VDD

L10 VDD VDD VDD VDD

L11 GND GND GND GND

L12 VDDP VDDP VDDP VDDP

L13 I/O I/O I/O I/O

L14 I/O I/O I/O I/O

L15 I/O I/O I/O I/O

L16 I/O I/O I/O I/O

M1 I/O I/O I/O I/O

M2 I/O I/O I/O I/O

M3 I/O I/O I/O I/O

M4 I/O I/O I/O I/O

256-Pin FBGA (Continued)

Number APA150

Function APA300

Function APA450

Function APA600

Function

v3.0 93

ProASICPLUS Flash Family FPGAs

M5 I/O I/O I/O I/O

M6 VDDP VDDP VDDP VDDP

M7 VDDP VDDP VDDP VDDP

M8 I/O I/O I/O I/O

M9 I/O I/O I/O I/O

M10 VDDP VDDP VDDP VDDP

M11 VDDP VDDP VDDP VDDP

M12 I/O I/O I/O I/O

M13 I/O I/O I/O I/O

M14 I/O I/O I/O I/O

M15 I/O I/O I/O I/O

M16 I/O I/O I/O I/O

N1 I/O I/O I/O I/O

N2 I/O I/O I/O I/O

N3 I/O I/O I/O I/O

N4 I/O I/O I/O I/O

N5 I/O I/O I/O I/O

N6 I/O I/O I/O I/O

N7 I/O I/O I/O I/O

N8 I/O I/O I/O I/O

N9 I/O I/O I/O I/O

N10 I/O I/O I/O I/O

N11 I/O I/O I/O I/O

N12 I/O I/O I/O I/O

N13 I/O I/O I/O I/O

N14 RCK RCK RCK RCK

N15 I/O I/O I/O I/O

N16 I/O I/O I/O I/O

P1 I/O I/O I/O I/O

P2 I/O I/O I/O I/O

P3 I/O I/O I/O I/O

P4 I/O I/O I/O I/O

P5 I/O I/O I/O I/O

P6 I/O I/O I/O I/O

P7 I/O I/O I/O I/O

P8 I/O I/O I/O I/O

P9 I/O I/O I/O I/O

P10 I/O I/O I/O I/O

P11 I/O I/O I/O I/O

P12 I/O I/O I/O I/O

P13 TCK TCK TCK TCK

P1 4 VPP VPP VPP VPP

P15 TRST T RST T RST T RST

P16 I/O I/O I/O I/O

R1 I/O I/O I/O I/O

256-Pin FBGA (Continued)

Number APA150

Function APA300

Function APA450

Function APA600

Function

ProASICPLUS Flash Family FPGAs

94 v3.0

R2 I/O I/O I/O I/O

R3 I/O I/O I/O I/O

R4 I/O I/O I/O I/O

R5 I/O I/O I/O I/O

R6 I/O I/O I/O I/O

R7 I/O I/O I/O I/O

R8 I/O I/O I/O I/O

R9 I/O I/O I/O I/O

R10 I/O I/O I/O I/O

R11 I/O I/O I/O I/O

R12 I/O I/O I/O I/O

R13 I/O I/O I/O I/O

R14 TDI TDI TDI TDI

R15 VPN VPN VPN VPN

R16 TDO TDO TDO TDO

T1 GND GND GND GND

T2 I/O I/O I/O I/O

T3 I/O I/O I/O I/O

T4 I/O I/O I/O I/O

T5 I/O I/O I/O I/O

T6 I/O I/O I/O I/O

T7 I/O I/O I/O I/O

T8 I/O I/O I/O I/O

T9 I/O I/O I/O I/O

T10 I/O I/O I/O I/O

T11 I/O I/O I/O I/O

T12 I/O I/O I/O I/O

T13 I/O I/O I/O I/O

T14 I/O I/O I/O I/O

T15 TMS TMS TMS TMS

T16 GND GND GND GND

256-Pin FBGA (Continued)

Number APA150

Function APA300

Function APA450

Function APA600

Function

v3.0 95

ProASICPLUS Flash Family FPGAs

Package Assignments (Continued)

484-Pin FBGA (Bottom View)

791113

15 246

101214

22 19 18 17 16

21 20

A1 Ball Pad Corner

ProASICPLUS Flash Family FPGAs

96 v3.0

484-Pin FBGA

Number APA450

Function APA600

Function

A1 GND GND

A2 GND GND

A3 VDDP VDDP

A4 I/O I/O

A5 I/O I/O

A6 I/O I/O

A7 I/O I/O

A8 I/O I/O

A9 I/O I/O

A10 I/O I/O

A11 I/O I/O

A12 I/O I/O

A13 I/O I/O

A14 I/O I/O

A15 I/O I/O

A16 I/O I/O

A17 I/O I/O

A18 I/O I/O

A19 I/O I/O

A20 VDDP VDDP

A21 GND GND

A22 GND GND

B1 GND GND

B2 VDDP VDDP

B3 I/O I/O

B4 I/O I/O

B5 I/O I/O

B6 I/O I/O

B7 I/O I/O

B8 I/O I/O

B9 I/O I/O

B10 I/O I/O

B11 I/O I/O

B12 I/O I/O

B13 I/O I/O

B14 I/O I/O

B15 I/O I/O

B16 I/O I/O

B17 I/O I/O

B18 I/O I/O

B19 I/O I/O

B20 I/O I/O

B21 VDDP VDDP

B22 GND GND

C1 VDDP VDDP

C2 NC I/O

C3 I/O I/O

C4 I/O I/O

C5 GND GND

C6 I/O I/O

C7 I/O I/O

C8 VDD VDD

C9 VDD VDD

C10 I/O I/O

C11 I/O I/O

C12 NC I/O

C13 NC I/O

C14 VDD VDD

C15 VDD VDD

C16 NC I/O

C17 I/O I/O

C18 GND GND

C19 I/O I/O

C20 I/O I/O

C21 I/O I/O

C22 VDDP VDDP

D1 I/O I/O

D2 I/O I/O

D3 NC I/O

D4 GND GND

D5 I/O I/O

D6 I/O I/O

D7 I/O I/O

D8 I/O I/O

D9 I/O I/O

D10 I/O I/O

D11 I/O I/O

D12 I/O I/O

D13 I/O I/O

D14 I/O I/O

D15 I/O I/O

D16 I/O I/O

D17 I/O I/O

D18 I/O I/O

484-Pin FBGA (Continued)

Number APA450

Function APA600

Function

v3.0 97

ProASICPLUS Flash Family FPGAs

D19 GND GND

D20 I/O I/O

D21 I/O I/O

D22 I/O I/O

E1 I/O I/O

E2 NC I/O

E3 GND GND

E4 I/O I/O

E5 I/O I/O

E6 I/O I/O

E7 I/O I/O

E8 I/O I/O

E9 I/O I/O

E10 I/O I/O

E11 I/O I/O

E12 I/O I/O

E13 I/O I/O

E14 I/O I/O

E15 I/O I/O

E16 I/O I/O

E17 I/O I/O

E18 I/O I/O

E19 I/O I/O

E20 GND GND

E21 I/O I/O

E22 I/O I/O

F1 I/O I/O

F2 I/O I/O

F3 I/O I/O

F4 I/O I/O

F5 I/O I/O

F6 I/O I/O

F7 I/O I/O

F8 I/O I/O

F9 I/O I/O

F10 I/O I/O

F11 I/O I/O

F12 I/O I/O

F13 I/O I/O

F14 I/O I/O

F15 I/O I/O

F16 I/O I/O

484-Pin FBGA (Continued)

Number APA450

Function APA600

Function

F17 I/O I/O

F18 I/O I/O

F19 I/O I/O

F20 I/O I/O

F21 I/O I/O

F22 NC I/O

G1 I/O I/O

G2 I/O I/O

G3 NC I/O

G4 I/O I/O

G5 I/O I/O

G6 I/O I/O

G7 I/O I/O

G8 I/O I/O

G9 I/O I/O

G10 I/O I/O

G11 I/O I/O

G12 I/O I/O

G13 I/O I/O

G14 I/O I/O

G15 I/O I/O

G16 I/O I/O

G17 I/O I/O

G18 I/O I/O

G19 I/O I/O

G20 I/O I/O

G21 I/O I/O

G22 I/O I/O

H1 I/O I/O

H2 I/O I/O

H3 VDD VDD

H4 I/O I/O

H5 I/O I/O

H6 I/O I/O

H7 I/O I/O

H8 I/O I/O

H9 VDDP VDDP

H10 VDDP VDDP

H11 I/O I/O

H12 I/O I/O

H13 VDDP VDDP

H14 VDDP VDDP

484-Pin FBGA (Continued)

Number APA450

Function APA600

Function

ProASICPLUS Flash Family FPGAs

98 v3.0

H15 I/O I/O

H16 I/O I/O

H17 I/O I/O

H18 I/O I/O

H19 I/O I/O

H20 VDD VDD

H21 I/O I/O

H22 I/O I/O

J1 I/O I/O

J2 I/O I/O

J3 NC I/O

J4 I/O I/O

J5 I/O I/O

J6 I/O I/O

J7 I/O I/O

J8 VDDP VDDP

J9 GND GND

J10 VDD VDD

J11 VDD VDD

J12 VDD VDD

J13 VDD VDD

J14 GND GND

J15 VDDP VDDP

J16 I/O I/O

J17 I/O I/O

J18 I/O I/O

J19 I/O I/O

J20 NC I/O

J21 I/O I/O

J22 I/O I/O

K1 I/O I/O

K2 I/O I/O

K3 NC I/O

K4 I/O I/O

K5 I/O I/O

K6 I/O I/O

K7 I/O I/O

K8 VDDP VDDP

K9 VDD VDD

K10 GND GND

K11 GND GND

K12 GND GND

484-Pin FBGA (Continued)

Number APA450

Function APA600

Function

K13 GND GND

K14 VDD VDD

K15 VDDP VDDP

K16 I/O I/O

K17 I/O I/O

K18 I/O I/O

K19 I/O I/O

K20 I/O I/O

K21 I/O I/O

K22 I/O I/O

L1 NC I/O

L2 I/O I/O

L3 I/O I/O

L4 GL1 GL1

L5 NPECL1 NPECL1

L6 I/O (GLMX1) I/O (GLMX1)

L7 AGND AGND

L8 I/O I/O

L9 VDD VDD

L10 GND GND

L11 GND GND

L12 GND GND

L13 GND GND

L14 VDD VDD

L15 I/O I/O

L16 I/O (GLMX2) I/O (GLMX2)

L17 NPECL2 NPECL2

L18 AGND AGND

L19 GL4 GL4

L20 I/O I/O

L21 I/O I/O

L22 I/O I/O

M1 I/O I/O

M2 I/O I/O

M3 I/O I/O

M4 GL2 GL2

M5 PPECL1 (I/P) PPECL1 (I/P)

M6 AVDD AVDD

M7 I/O I/O

M8 I/O I/O

M9 VDD VDD

M10 GND GND

484-Pin FBGA (Continued)

Number APA450

Function APA600

Function

v3.0 99

ProASICPLUS Flash Family FPGAs

M11 GND GND

M12 GND GND

M13 GND GND

M14 VDD VDD

M15 I/O I/O

M16 PPECL2 (I/P) PPECL2 (I/P)

M17 I/O I/O

M18 AVDD AVDD

M19 GL3 GL3

M20 I/O I/O

M21 I/O I/O

M22 I/O I/O

N1 I/O I/O

N2 I/O I/O

N3 NC I/O

N4 I/O I/O

N5 I/O I/O

N6 I/O I/O

N7 I/O I/O

N8 VDDP VDDP

N9 VDD VDD

N10 GND GND

N11 GND GN D

N12 GND GND

N13 GND GND

N14 VDD VDD

N15 VDDP VDDP

N16 I/O I/O

N17 I/O I/O

N18 I/O I/O

N19 I/O I/O

N20 NC I/O

N21 I/O I/O

N22 I/O I/O

P1 I/O I/O

P2 I/O I/O

P3 I/O I/O

P4 I/O I/O

P5 I/O I/O

P6 I/O I/O

P7 I/O I/O

P8 VDDP VDDP

484-Pin FBGA (Continued)

Number APA450

Function APA600

Function

P9 GND GND

P10 VDD VDD

P11 VDD VDD

P12 VDD VDD

P13 VDD VDD

P14 GND GND

P15 VDDP VDDP

P16 I/O I/O

P17 I/O I/O

P18 I/O I/O

P19 I/O I/O

P20 NC I/O

P21 I/O I/O

P22 I/O I/O

R1 I/O I/O

R2 I/O I/O

R3 VDD VDD

R4 I/O I/O

R5 I/O I/O

R6 I/O I/O

R7 I/O I/O

R8 I/O I/O

R9 VDDP VDDP

R10 VDDP VDDP

R11 I/O I/O

R12 I/O I/O

R13 VDDP VDDP

R14 VDDP VDDP

R15 I/O I/O

R16 I/O I/O

R17 I/O I/O

R18 I/O I/O

R19 I/O I/O

R20 VDD VDD

R21 I/O I/O

R22 I/O I/O

T1 I/O I/O

T2 I/O I/O

T3 NC I/O

T4 I/O I/O

T5 I/O I/O

T6 I/O I/O

484-Pin FBGA (Continued)

Number APA450

Function APA600

Function

ProASICPLUS Flash Family FPGAs

100 v3.0

T7 I/O I/O

T8 I/O I/O

T9 I/O I/O

T10 I/O I/O

T11 I/O I/O

T12 I/O I/O

T13 I/O I/O

T14 I/O I/O

T15 I/O I/O

T16 I/O I/O

T17 RCK RCK

T18 I/O I/O

T19 I/O I/O

T20 NC I/O

T21 I/O I/O

T22 I/O I/O

U1 I/O I/O

U2 I/O I/O

U3 I/O I/O

U4 I/O I/O

U5 I/O I/O

U6 I/O I/O

U7 I/O I/O

U8 I/O I/O

U9 I/O I/O

U10 I/O I/O

U11 I /O I/O

U12 I/O I/O

U13 I/O I/O

U14 I/O I/O

U15 I/O I/O

U16 TCK TCK

U17 VPP VPP

U18 TRST TRST

U19 I/O I/O

U20 NC I/O

U21 I/O I/O

U22 I/O I/O

V1 I/O I/O

V2 I/O I/O

V3 GND GND

V4 I/O I/O

484-Pin FBGA (Continued)

Number APA450

Function APA600

Function

V5 I/O I/O

V6 I/O I/O

V7 I/O I/O

V8 I/O I/O

V9 I/O I/O

V10 I/O I/O

V11 I/O I/O

V12 I/O I/O

V13 I/O I/O

V14 I/O I/O

V15 I/O I/O

V16 I/O I/O

V17 TDI TDI

V18 VPN VPN

V19 TDO TDO

V20 GND GND

V21 NC I/O

V22 I/O I/O

W1 NC I/O

W2 I/O I/O

W3 I/O I/O

W4 GND GND

W5 I/O I/O

W6 I/O I/O

W7 I/O I/O

W8 I/O I/O

W9 I/O I/O

W10 I/O I/O

W11 I/O I/O

W12 I/O I/O

W13 I/O I/O

W14 I/O I/O

W15 I/O I/O

W16 I/O I/O

W17 I/O I/O

W1 8 TMS TMS

W1 9 GN D GND

W2 0 NC I / O

W2 1 NC I / O

W22 I/O I/O

Y1 VDDP VDDP

Y2 I/O I/O

484-Pin FBGA (Continued)

Number APA450

Function APA600

Function

v3.0 101

ProASICPLUS Flash Family FPGAs

Y3 I/O I/O

Y4 I/O I/O

Y5 GND GND

Y6 I/O I/O

Y7 I/O I/O

Y8 VDD VDD

Y9 VDD VDD

Y10 I/O I/O

Y11 I/O I/O

Y12 I/O I/O

Y13 I/O I/O

Y14 VDD VDD

Y15 VDD VDD

Y16 I/O I/O

Y17 I/O I/O

Y18 GND GND

Y19 I/O I/O

Y20 I/O I/O

Y21 NC I/O

Y22 VDDP VDDP

AA1 GND GND

AA2 VDDP VDDP

AA3 I/O I/O

AA4 I/O I/O

AA5 I/O I/O

AA6 I/O I/O

AA7 I/O I/O

AA8 I/O I/O

AA9 I/O I/O

AA10 I/O I/O

AA11 I/O I/O

AA12 I/O I/O

AA13 I/O I/O

AA14 I/O I/O

AA15 I/O I/O

AA16 I/O I/O

AA17 I/O I/O

AA18 NC I/O

AA19 NC I/O

AA20 I/O I/O

AA21 VDDP VDDP

AA22 GND GND

484-Pin FBGA (Continued)

Number APA450

Function APA600

Function

AB1 GND GND

AB2 GND GND

AB3 VDDP VDDP

AB4 I/O I/O

AB5 I/O I/O

AB6 I/O I/O

AB7 I/O I/O

AB8 I/O I/O

AB9 I/O I/O

AB10 I/O I/O

AB11 I/O I/O

AB12 I/O I/O

AB13 I/O I/O

AB14 I/O I/O

AB15 I/O I/O

AB16 I/O I/O

AB17 I/O I/O

AB18 NC I/O

AB19 I/O I/O

AB2 0 VDDP VDDP

AB2 1 GND GND

AB2 2 GND GND

484-Pin FBGA (Continued)

Number APA450

Function APA600

Function

ProASICPLUS Flash Family FPGAs

102 v3.0

Package Pin Assignments (Continued)

676-Pin FBGA (Bottom View)

12356789101115 14 13 121617181920212223 4242526

A1 Ball Pad Corner

v3.0 103

ProASICPLUS Flash Family FPGAs

676-FBGA Pin

Number APA600

Function APA750

Function

A1 GND GND

A2 GND GND

A3 I/O I/O

A4 I/O I/O

A5 I/O I/O

A6 I/O I/O

A7 I/O I/O

A8 I/O I/O

A9 I/O I/O

A10 I/O I/O

A11 I/O I/O

A12 I/O I/O

A13 I/O I/O

A14 I/O I/O

A15 I/O I/O

A16 I/O I/O

A17 I/O I/O

A18 I/O I/O

A19 I/O I/O

A20 I/O I/O

A21 I/O I/O

A22 I/O I/O

A23 I/O I/O

A24 I/O I/O

A25 GND GND

A26 GND GND

B1 GND GND

B2 GND GND

B3 GND GND

B4 GND GND

B5 I/O I/O

B6 I/O I/O

B7 I/O I/O

B8 I/O I/O

B9 I/O I/O

B10 I/O I/O

B11 I/O I/O

B12 I/O I/O

B13 I/O I/O

B14 I/O I/O

B15 I/O I/O

B16 I/O I/O

B17 I/O I/O

B18 I/O I/O

B19 I/O I/O

B20 I/O I/O

B21 I/O I/O

B22 I/O I/O

B23 I/O I/O

B24 I/O I/O

B25 GND GND

B26 GND GND

C1 GND GND

C2 GND GND

C3 GND GND

C4 GND GND

C5 I/O I/O

C6 I/O I/O

C7 I/O I/O

C8 I/O I/O

C9 I/O I/O

C10 I/O I/O

C11 I/O I/O

C12 I/O I/O

C13 I/O I/O

C14 I/O I/O

C15 I/O I/O

C16 I/O I/O

C17 I/O I/O

C18 I/O I/O

C19 I/O I/O

C20 I/O I/O

C21 I/O I/O

C22 I/O I/O

C23 I/O I/O

C24 I/O I/O

C25 I/O I/O

C26 I/O I/O

D1 I/O I/O

D2 I/O I/O

D3 GND GND

D4 I/O I/O

D5 I/O I/O

D6 I/O I/O

D7 I/O I/O

D8 I/O I/O

676-FBGA Pin (Continued)

Number APA600

Function APA750

Function

ProASICPLUS Flash Family FPGAs

104 v3.0

D9 I/O I/O

D10 I/O I/O

D11 I/O I/O

D12 I/O I/O

D13 I/O I/O

D14 I/O I/O

D15 I/O I/O

D16 I/O I/O

D17 I/O I/O

D18 I/O I/O

D19 I/O I/O

D20 I/O I/O

D21 I/O I/O

D22 I/O I/O

D23 I/O I/O

D24 I/O I/O

D25 I/O I/O

D26 I/O I/O

E1 I/O I/O

E2 I/O I/O

E3 I/O I/O

E4 I/O I/O

E5 I/O I/O

E6 I/O I/O

E7 I/O I/O

E8 I/O I/O

E9 I/O I/O

E10 I/O I/O

E11 I/O I/O

E12 I/O I/O

E13 I/O I/O

E14 I/O I/O

E15 I/O I/O

E16 I/O I/O

E17 I/O I/O

E18 I/O I/O

E19 I/O I/O

E20 I/O I/O

E21 I/O I/O

E22 I/O I/O

E23 I/O I/O

E24 I/O I/O

E25 I/O I/O

676-FBGA Pin (Continued)

Number APA600

Function APA750

Function

E26 I/O I/O

F1 I/O I/O

F2 I/O I/O

F3 I/O I/O

F4 I/O I/O

F5 GND GND

F6 I/O I/O

F7 NC NC

F8 I/O I/O

F9 I/O I/O

F10 I/O I/O

F11 I/O I/O

F12 I/O I/O

F13 I/O I/O

F14 I/O I/O

F15 I/O I/O

F16 I/O I/O

F17 I/O I/O

F18 I/O I/O

F19 I/O I/O

F20 I/O I/O

F21 I/O I/O

F22 I/O I/O

F23 I/O I/O

F24 I/O I/O

F25 I/O I/O

F26 I/O I/O

G1 I/O I/O

G2 I/O I/O

G3 I/O I/O

G4 I/O I/O

G5 I/O I/O

G6 I/O I/O

G7 I/O I/O

G8 VDD VDD

G9 NC NC

G10 I/O I/O

G11 NC NC

G12 I/O I/O

G13 NC NC

G14 I/O I/O

G15 NC NC

G16 I/O I/O

676-FBGA Pin (Continued)

Number APA600

Function APA750

Function

v3.0 105

ProASICPLUS Flash Family FPGAs

G17 NC NC

G18 I/O I/O

G19 VDDP VDDP

G20 NC NC

G21 I/O I/O

G22 I/O I/O

G23 I/O I/O

G24 I/O I/O

G25 I/O I/O

G26 I/O I/O

H1 I/O I/O

H2 I/O I/O

H3 I/O I/O

H4 I/O I/O

H5 I/O I/O

H6 I/O I/O

H7 VDDP VDDP

H8 VDD VDD

H9 VDDP VDDP

H10 VDDP VDDP

H11 VDDP VDDP

H12 VDDP VDDP

H13 VDDP VDDP

H14 VDDP VDDP

H15 VDDP VDDP

H16 VDDP VDDP

H17 VDDP VDDP

H18 VDDP VDDP

H19 VDD VDD

H20 VDD VDD

H21 I/O I/O

H22 I/O I/O

H23 I/O I/O

H24 I/O I/O

H25 I/O I/O

H26 I/O I/O

J1 I/O I/O

J2 I/O I/O

J3 I/O I/O

J4 I/O I/O

J5 I/O I/O

J6 I/O I/O

J7 NC NC

676-FBGA Pin (Continued)

Number APA600

Function APA750

Function

J8 VDDP VDDP

J9 VDD VDD

J10 VDD VDD

J11 VDD VDD

J12 VDD VDD

J13 VDD VDD

J14 VDD VDD

J15 VDD VDD

J16 VDD VDD

J17 VDD VDD

J18 VDD VDD

J19 VDDP VDDP

J20 NC NC

J21 I/O I/O

J22 I/O I/O

J23 I/O I/O

J24 I/O I/O

J25 I/O I/O

J26 I/O I/O

K1 I/O I/O

K2 I/O I/O

K3 I/O I/O

K4 I/O I/O

K5 I/O I/O

K6 I/O I/O

K7 I/O I/O

K8 VDDP VDDP

K9 VDD VDD

K10 GND GND

K11 GND GND

K12 GND GND

K13 GND GND

K14 GND GND

K15 GND GND

K16 GND GND

K17 GND GND

K18 VDD VDD

K19 VDDP VDDP

K20 I/O I/O

K21 I/O I/O

K22 I/O I/O

K23 I/O I/O

K24 I/O I/O

676-FBGA Pin (Continued)

Number APA600

Function APA750

Function

ProASICPLUS Flash Family FPGAs

106 v3.0

K25 I/O I/O

K26 I/O I/O

L1 I/O I/O

L2 I/O I/O

L3 I/O I/O

L4 I/O I/O

L5 I/O I/O

L6 I/O I/O

L7 NC NC

L8 VDDP VDDP

L9 VDD VDD

L10 GND GND

L11 GND GND

L12 GND GND

L13 GND GND

L14 GND GND

L15 GND GND

L16 GND GND

L17 GND GND

L18 VDD VDD

L19 VDDP VDDP

L20 NC NC

L21 I/O I/O

L22 I/O I/O

L23 I/O I/O

L24 I/O I/O

L25 I/O I/O

L26 I/O I/O

M1 I/O I/O

M2 I/O I/O

M3 I/O I/O

M4 I/O I/O

M5 I/O I/O

M6 I/O I/O

M7 I/O I/O

M8 VDDP VDDP

M9 VDD VDD

M10 GND GND

M11 GND GND

M12 GND GND

M13 GND GND

M14 GND GND

M15 GND GND

676-FBGA Pin (Continued)

Number APA600

Function APA750

Function

M16 GND GND

M17 GND GND

M18 VDD VDD

M19 VDDP VDDP

M20 I/O I/O

M21 I/O I/O

M22 I/O I/O

M23 I/O I/O

M24 I/O I/O

M25 I/O I/O

M26 I/O I/O

N1 GL1 GL1

N2 AGND AGND

N3 I/O (GLMX1) I/O (GLMX1)

N4 I/O I/O

N5 NPECL1 NPECL1

N6 I/O I/O

N7 NC NC

N8 VDDP VDDP

N9 VDD VDD

N10 GND GND

N11 GND GND

N12 GND GND

N13 GND GND

N14 GND GND

N15 GND GND

N16 GND GND

N17 GND GND

N18 VDD VDD

N19 VDDP VDDP

N20 NC NC

N21 I/O I/O

N22 GL3 GL3

N23 I/O I/O

N24 NPECL2 NPECL2

N25 GL4 GL4

N26 I/O I/O

P1 GL2 GL2

P2 AVDD AVDD

P3 I/O I/O

P4 I/O I/O

P5 PPECL1 (I /P) PPECL1 (I/P)

P6 I/O I/O

676-FBGA Pin (Continued)

Number APA600

Function APA750

Function

v3.0 107

ProASICPLUS Flash Family FPGAs

P7 I/O I/O

P8 VDDP VDDP

P9 VDD VDD

P10 GND GND

P11 GND GND

P12 GND GND

P13 GND GND

P14 GND GND

P15 GND GND

P16 GND GND

P17 GND GND

P18 VDD VDD

P19 VDDP VDDP

P20 I/O I/O

P21 I/O I/O

P22 I/O (GLMX2) I/O (GLMX2)

P23 I/O I/O

P24 PPECL2 (I/P) PPECL2 (I/P)

P25 AVDD AVDD

P26 AGND AGND

R1 I/O I/O

R2 I/O I/O

R3 I/O I/O

R4 I/O I/O

R5 I/O I/O

R6 I/O I/O

R7 NC NC

R8 VDDP VDDP

R9 VDD VDD

R10 GND GND

R11 GND GND

R12 GND GND

R13 GND GND

R14 GND GND

R15 GND GND

R16 GND GND

R17 GND GND

R18 VDD VDD

R19 VDDP VDDP

R20 NC NC

R21 I/O I/O

R22 I/O I/O

R23 I/O I/O

676-FBGA Pin (Continued)

Number APA600

Function APA750

Function

R24 I/O I/O

R25 I/O I/O

R26 I/O I/O

T1 I/O I/O

T2 I/O I/O

T3 I/O I/O

T4 I/O I/O

T5 I/O I/O

T6 I/O I/O

T7 I/O I/O

T8 VDDP VDDP

T9 VDD VDD

T10 GND GND

T11 GND GND

T12 GND GND

T13 GND GND

T14 GND GND

T15 GND GND

T16 GND GND

T17 GND GND

T18 VDD VDD

T19 VDDP VDDP

T20 I/O I/O

T21 I/O I/O

T22 I/O I/O

T23 I/O I/O

T24 I/O I/O

T25 I/O I/O

T26 I/O I/O

U1 I/O I/O

U2 I/O I/O

U3 I/O I/O

U4 I/O I/O

U5 I/O I/O

U6 I/O I/O

U7 NC NC

U8 VDDP VDDP

U9 VDD VDD

U10 GND GND

U11 GND GND

U12 GND GND

U13 GND GND

U14 GND GND

676-FBGA Pin (Continued)

Number APA600

Function APA750

Function

ProASICPLUS Flash Family FPGAs

108 v3.0

U15 GND GND

U16 GND GND

U17 GND GND

U18 VDD VDD

U19 VDDP VDDP

U20 NC NC

U21 I/O I/O

U22 I/O I/O

U23 I/O I/O

U24 I/O I/O

U25 I/O I/O

U26 I/O I/O

V1 I/O I/O

V2 I/O I/O

V3 I/O I/O

V4 I/O I/O

V5 I/O I/O

V6 I/O I/O

V7 I/O I/O

V8 VDDP VDDP

V9 VDD VDD

V10 VDD VDD

V11 VDD VDD

V12 VDD VDD

V13 VDD VDD

V14 VDD VDD

V15 VDD VDD

V16 VDD VDD

V17 VDD VDD

V18 VDD VDD

V19 VDDP VDDP

V20 I/O I/O

V21 I/O I/O

V22 I/O I/O

V23 I/O I/O

V24 I/O I/O

V25 I/O I/O

V26 I/O I/O

W1 I/O I/O

W2 I/O I/O

W3 I/O I/O

W4 I/O I/O

W5 I/O I/O

676-FBGA Pin (Continued)

Number APA600

Function APA750

Function

W6 I/O I/O

W7 VDD VDD

W8 VDD VDD

W9 VDDP VDDP

W10 VDDP VDDP

W11 VDDP VDDP

W12 VDDP VDDP

W13 VDDP VDDP

W14 VDDP VDDP

W15 VDDP VDDP

W16 VDDP VDDP

W17 VDDP VDDP

W18 VDDP VDDP

W19 VDD VDD

W20 VDDP VDDP

W21 I/O I/O

W22 I/O I/O

W23 I/O I/O

W24 I/O I/O

W25 I/O I/O

W26 I/O I/O

Y1 I/O I/O

Y2 I/O I/O

Y3 I/O I/O

Y4 I/O I/O

Y5 I/O I/O

Y6 I/O I/O

Y7 I/O I/O

Y8 VDDP VDDP

Y9 NC NC

Y10 I/O I/O

Y11 NC NC

Y12 I/O I/O

Y13 NC NC

Y14 I/O I/O

Y15 NC NC

Y16 I/O I/O

Y17 NC NC

Y18 I/O I/O

Y19 VDD VDD

Y20 VPP VPP

Y21 I/O I/O

Y22 I/O I/O

676-FBGA Pin (Continued)

Number APA600

Function APA750

Function

v3.0 109

ProASICPLUS Flash Family FPGAs

Y23 I/O I/O

Y24 I/O I/O

Y25 I/O I/O

Y26 I/O I/O

AA1 I/O I/O

AA2 I/O I/O

AA3 I/O I/O

AA4 I/O I/O

AA5 I/O I/O

AA6 GND GND

AA7 I/O I/O

AA8 I/O I/O

AA9 I/O I/O

AA10 I/O I/O

AA11 I/O I/O

AA12 I/O I/O

AA13 I/O I/O

AA14 I/O I/O

AA15 I/O I/O

AA16 I/O I/O

AA17 I/O I/O

AA18 I/O I/O

AA19 I/O I/O

AA20 I/O I/O

AA21 TDO TDO

AA22 GND GND

AA23 GND GND

AA24 I/O I/O

AA25 I/O I/O

AA26 I/O I/O

AB1 I/O I/O

AB2 I/O I/O

AB3 I/O I/O

AB4 I/O I/O

AB5 I/O I/O

AB6 GND GND

AB7 GND GND

AB8 I/O I/O

AB9 I/O I/O

AB10 I/O I/O

AB11 I/O I/O

AB12 I/O I/O

AB13 I/O I/O

676-FBGA Pin (Continued)

Number APA600

Function APA750

Function

AB14 I/O I/O

AB15 I/O I/O

AB16 I/O I/O

AB17 I/O I/O

AB18 I/O I/O

AB19 I/O I/O

AB20 I/O I/O

AB21 TCK TCK

AB22 TRST TRST

AB23 I/O I/O

AB24 I/O I/O

AB25 I/O I/O

AB26 I/O I/O

AC1 I/O I/O

AC2 I/O I/O

AC3 I/O I/O

AC4 I/O I/O

AC5 GND GND

AC6 I/O I/O

AC7 I/O I/O

AC8 I/O I/O

AC9 GND GND

AC10 I/O I/O

AC11 I/O I/O

AC12 I/O I/O

AC13 I/O I/O

AC14 I/O I/O

AC15 I/O I/O

AC16 I/O I/O

AC17 I/O I/O

AC18 I/O I/O

AC19 I/O I/O

AC20 I/O I/O

AC21 I/O I/O

AC22 TMS TMS

AC23 RCK RCK

AC24 I/O I/O

AC25 I/O I/O

AC26 I/O I/O

AD1 I/O I/O

AD2 I/O I/O

AD3 I/O I/O

AD4 I/O I/O

676-FBGA Pin (Continued)

Number APA600

Function APA750

Function

ProASICPLUS Flash Family FPGAs

110 v3.0

AD5 I/O I/O

AD6 I/O I/O

AD7 I/O I/O

AD8 I/O I/O

AD9 I/O I/O

AD10 I/O I/O

AD11 I/O I/O

AD12 I/O I/O

AD13 I/O I/O

AD14 I/O I/O

AD15 I/O I/O

AD16 I/O I/O

AD17 I/O I/O

AD18 I/O I/O

AD19 I/O I/O

AD20 I/O I/O

AD21 I/O I/O

AD22 I/O I/O

AD23 TDI TDI

AD24 VPN VPN

AD25 I/O I/O

AD26 I/O I/O

AE1 GND GND

AE2 GND GND

AE3 GND GND

AE4 I/O I/O

AE5 I/O I/O

AE6 I/O I/O

AE7 I/O I/O

AE8 I/O I/O

AE9 I/O I/O

AE10 I/O I/O

AE11 I/O I/O

AE12 I/O I/O

AE13 I/O I/O

AE14 I/O I/O

AE15 I/O I/O

AE16 I/O I/O

AE17 I/O I/O

AE18 I/O I/O

AE19 I/O I/O

AE20 I/O I/O

AE21 I/O I/O

676-FBGA Pin (Continued)

Number APA600

Function APA750

Function

AE22 I/O I/O

AE23 I/O I/O

AE24 I/O I/O

AE25 GND GND

AE26 GND GND

AF1 GND GND

AF2 GND GND

AF3 GND GND

AF4 GND GND

AF5 I/O I/O

AF6 I/O I/O

AF7 I/O I/O

AF8 I/O I/O

AF9 I/O I/O

AF10 I/O I/O

AF11 I/O I/O

AF12 I/O I/O

AF13 I/O I/O

AF14 I/O I/O

AF15 I/O I/O

AF16 I/O I/O

AF17 I/O I/O

AF18 I/O I/O

AF19 I/O I/O

AF20 I/O I/O

AF21 I/O I/O

AF22 I/O I/O

AF23 I/O I/O

AF24 I/O I/O

AF25 GND GND

AF26 GND GND

676-FBGA Pin (Continued)

Number APA600

Function APA750

Function

v3.0 111

ProASICPLUS Flash Family FPGAs

Package Pin Assignments (Continued)

896-Pin FBGA (Bottom View)

1234567891011

12131415161718192021222324252627282930

A1 Ball Pad Corner

ProASICPLUS Flash Family FPGAs

112 v3.0

896 FBGA Pin

Number APA750

Function APA1000

Function

A2 GND GND

A3 GND GND

A4 I/O I/O

A5 GND GND

A6 I/O I/O

A7 GND GND

A8 I/O I/O

A9 I/O I/O

A10 I/O I/O

A11 I/O I/O

A12 I/O I/O

A13 I/O I/O

A14 I/O I/O

A15 I/O I/O

A16 I/O I/O

A17 I/O I/O

A18 I/O I/O

A19 I/O I/O

A20 I/O I/O

A21 I/O I/O

A22 I/O I/O

A23 I/O I/O

A24 GND GND

A25 I/O I/O

A26 GND GND

A27 I/O I/O

A28 GND GND

A29 GND GND

B1 GND GND

B2 GND GND

B3 I/O I/O

B4 VDD VDD

B5 I/O I/O

B6 VDD VDD

B7 I/O I/O

B8 I/O I/O

B9 I/O I/O

B10 I/O I/O

B11 I/O I/O

B12 I/O I/O

B13 I/O I/O

B14 I/O I/O

B15 I/O I/O

B16 I/O I/O

B17 I/O I/O

B18 I/O I/O

B19 I/O I/O

B20 I/O I/O

B21 I/O I/O

B22 I/O I/O

B23 I/O I/O

B24 I/O I/O

B25 VDD VDD

B26 I/O I/O

B27 VDD VDD

B28 I/O I/O

B29 GND GN D

B30 GND GND

C1 GND GND

C2 I/O I/O

C3 VDD VDD

C4 I/O I/O

C5 VDDP VDDP

C6 I/O I/O

C7 I/O I/O

C8 I/O I/O

C9 I/O I/O

C10 I/O I/O

C11 I/O I/O

C12 I/O I/O

C13 I/O I/O

C14 I/O I/O

C15 I/O I/O

C16 I/O I/O

C17 I/O I/O

C18 I/O I/O

C19 I/O I/O

C20 I/O I/O

C21 I/O I/O

C22 I/O I/O

C23 I/O I/O

C24 I/O I/O

C25 I/O I/O

C26 VDDP VDDP

896 FBGA Pin (Continued)

Number APA750

Function APA1000

Function

v3.0 113

ProASICPLUS Flash Family FPGAs

C27 I/O I/O

C28 VDD VDD

C29 NC I/O

C30 GND GND

D1 I/O I/O

D2 VDD VDD

D3 I/O I/O

D4 GND GND

D5 I/O I/O

D6 I/O I/O

D7 I/O I/O

D8 I/O I/O

D9 I/O I/O

D10 I/O I/O

D11 I/O I/O

D12 I/O I/O

D13 I/O I/O

D14 I/O I/O

D15 I/O I/O

D16 I/O I/O

D17 I/O I/O

D18 I/O I/O

D19 I/O I/O

D20 I/O I/O

D21 I/O I/O

D22 I/O I/O

D23 I/O I/O

D24 I/O I/O

D25 I/O I/O

D26 I/O I/O

D27 GND GND

D28 I/O I/O

D29 VDD VDD

D30 I/O I/O

E1 GND GND

E2 I/O I/O

E3 VDDP VDDP

E4 I/O I/O

E5 VDD VDD

E6 I/O I/O

E7 VDDP VDDP

E8 I/O I/O

896 FBGA Pin (Continued)

Number APA750

Function APA1000

Function

E9 I/O I/O

E10 I/O I/O

E11 I/O I/O

E12 I/O I/O

E13 I/O I/O

E14 I/O I/O

E15 I/O I/O

E16 I/O I/O

E17 I/O I/O

E18 I/O I/O

E19 I/O I/O

E20 I/O I/O

E21 I/O I/O

E22 I/O I/O

E23 I/O I/O

E24 VDDP VDDP

E25 I/O I/O

E26 VDD VDD

E27 I/O I/O

E28 VDDP VDDP

E29 I/O I/O

E30 GND GND

F1 I/O I/O

F2 VDD VDD

F3 I/O I/O

F4 I/O I/O

F5 I/O I/O

F6 GND GND

F7 I/O I/O

F8 I/O I/O

F9 I/O I/O

F10 I/O I/O

F11 I/O I/O

F12 I/O I/O

F13 I/O I/O

F14 I/O I/O

F15 I/O I/O

F16 I/O I/O

F17 I/O I/O

F18 I/O I/O

F19 I/O I/O

F20 I/O I/O

896 FBGA Pin (Continued)

Number APA750

Function APA1000

Function

ProASICPLUS Flash Family FPGAs

114 v3.0

F21 I/O I/O

F22 I/O I/O

F23 I/O I/O

F24 I/O I/O

F25 GN D GND

F26 I/O I/O

F27 I/O I/O

F28 I/O I/O

F29 VDD VDD

F30 I/O I/O

G1 GND GND

G2 I/O I/O

G3 I/O I/O

G4 I/O I/O

G5 VDDP VDDP

G6 I/O I/O

G7 VDD VDD

G8 I/O I/O

G9 VDDP VDDP

G10 I/O I/O

G11 I/O I/O

G12 I/O I/O

G13 I/O I/O

G14 I/O I/O

G15 I/O I/O

G16 I/O I/O

G17 I/O I/O

G18 I/O I/O

G19 I/O I/O

G20 I/O I/O

G21 I/O I/O

G22 VDDP VDDP

G23 I/O I/O

G24 VDD VDD

G25 I/O I/O

G26 VDDP VDDP

G27 I/O I/O

G28 I/O I/O

G29 I/O I/O

G30 GND GND

H1 I/O I/O

H2 I/O I/O

896 FBGA Pin (Continued)

Number APA750

Function APA1000

Function

H3 I/O I/O

H4 I/O I/O

H5 I/O I/O

H6 I/O I/O

H7 I/O I/O

H8 GND GND

H9 NC I/O

H10 NC I/O

H11 NC I/O

H12 NC I/O

H13 NC I/O

H14 NC I/O

H15 NC I/O

H16 NC I/O

H17 NC I/O

H18 NC I/O

H19 NC I/O

H20 NC I/O

H21 NC I/O

H22 NC I/O

H23 GND GND

H24 I/O I/O

H25 I/O I/O

H26 I/O I/O

H27 I/O I/O

H28 I/O I/O

H29 I/O I/O

H30 I/O I/O

J1 I/O I/O

J2 I/O I/O

J3 I/O I/O

J4 I/O I/O

J5 I/O I/O

J6 I/O I/O

J7 VDDP VDDP

J8 I/O I/O

J9 VDD VDD

J10 NC I/O

J11 NC I/O

J12 NC I/O

J13 NC I/O

J14 NC I/O

896 FBGA Pin (Continued)

Number APA750

Function APA1000

Function

v3.0 115

ProASICPLUS Flash Family FPGAs

J15 NC I/O

J16 NC I/O

J17 NC I/O

J18 NC I/O

J19 NC I/O

J20 NC I/O

J21 NC I/O

J22 VDD VDD

J23 I/O I/O

J24 VDDP VDDP

J25 I/O I/O

J26 I/O I/O

J27 I/O I/O

J28 I/O I/O

J29 I/O I/O

J30 I/O I/O

K1 I/O I/O

K2 I/O I/O

K3 I/O I/O

K4 I/O I/O

K5 I/O I/O

K6 I/O I/O

K7 I/O I/O

K8 I/O I/O

K9 NC I/O

K10 VDD VDD

K11 NC I/O

K12 VDDP VDDP

K13 VDDP VDDP

K14 VDDP VDDP

K15 VDDP VDDP

K16 VDDP VDDP

K17 VDDP VDDP

K18 VDDP VDDP

K19 VDDP VDDP

K20 NC I/O

K21 VDD VDD

K22 NC I/O

K23 I/O I/O

K24 I/O I/O

K25 I/O I/O

K26 I/O I/O

896 FBGA Pin (Continued)

Number APA750

Function APA1000

Function

K27 I/O I/O

K28 I/O I/O

K29 I/O I/O

K30 I/O I/O

L1 I/O I/O

L2 I/O I/O

L3 I/O I/O

L4 I/O I/O

L5 I/O I/O

L6 I/O I/O

L7 I/O I/O

L8 I/O I/O

L9 NC I/O

L10 NC I/O

L11 VDD VDD

L12 VDD VDD

L13 VDD VDD

L14 VDD VDD

L15 VDD VDD

L16 VDD VDD

L17 VDD VDD

L18 VDD VDD

L19 VDD VDD

L20 VDD VDD

L21 NC I/O

L22 NC I/O

L23 I/O I/O

L24 I/O I/O

L25 I/O I/O

L26 I/O I/O

L27 I/O I/O

L28 I/O I/O

L29 I/O I/O

L30 I/O I/O

M1 I/O I/O

M2 I/O I/O

M3 I/O I/O

M4 I/O I/O

M5 I/O I/O

M6 I/O I/O

M7 I/O I/O

M8 I/O I/O

896 FBGA Pin (Continued)

Number APA750

Function APA1000

Function

ProASICPLUS Flash Family FPGAs

116 v3.0

M9 NC I/O

M10 VDDP VDDP

M11 VDD VDD

M12 GND GND

M13 GND GND

M14 GND GND

M15 GND GND

M16 GND GND

M17 GND GND

M18 GND GND

M19 GND GND

M20 VDD VDD

M21 VDDP VDDP

M22 NC I/O

M23 I/O I/O

M24 I/O I/O

M25 I/O I/O

M26 I/O I/O

M27 I/O I/O

M28 I/O I/O

M29 I/O I/O

M30 I/O I/O

N1 I/O I/O

N2 I/O I/O

N3 I/O I/O

N4 I/O I/O

N5 I/O I/O

N6 I/O I/O

N7 I/O I/O

N8 I/O I/O

N9 NC I/O

N10 VDDP VDDP

N11 VDD VDD

N12 GND GND

N13 GND GND

N14 GND GND

N15 GND GND

N16 GND GND

N17 GND GND

N18 GND GND

N19 GND GND

N20 VDD VDD

896 FBGA Pin (Continued)

Number APA750

Function APA1000

Function

N21 VDDP VDDP

N22 NC I/O

N23 I/O I/O

N24 I/O I/O

N25 I/O I/O

N26 I/O I/O

N27 I/O I/O

N28 I/O I/O

N29 I/O I/O

N30 I/O I/O

P1 I/O I/O

P2 I/O I/O

P3 I/O I/O

P4 I/O I/O

P5 I/O I/O

P6 I/O I/O

P7 I/O I/O

P8 I/O I/O

P9 I/O I/O

P10 VDDP VDDP

P11 VDD VDD

P12 GND GN D

P13 GND GN D

P14 GND GN D

P15 GND GN D

P16 GND GN D

P17 GND GN D

P18 GND GN D

P19 GND GN D

P20 VDD VDD

P21 VDDP VDDP

P22 I/O I/O

P23 I/O I/O

P24 I/O I/O

P25 I/O I/O

P26 I/O I/O

P27 I/O I/O

P28 I/O I/O

P29 I/O I/O

P30 I/O I/O

R1 I/O I/O

R2 I/O (GLMX1) I/O (GLMX1)

896 FBGA Pin (Continued)

Number APA750

Function APA1000

Function

v3.0 117

ProASICPLUS Flash Family FPGAs

R3 AGND AGND

R4 NPECL1 NPECL1

R5 GL1 GL1

R6 I/O I/O

R7 I/O I/O

R8 I/O I/O

R9 NC I/O

R10 VDDP VDDP

R11 VDD VDD

R12 GND GND

R13 GND GND

R14 GND GND

R15 GND GND

R16 GND GND

R17 GND GND

R18 GND GND

R19 GND GND

R20 VDD VDD

R21 VDDP VDDP

R22 I/O I/O

R23 I/O I/O

R24 I/O I/O

R25 I/O I/O

R26 I/O I/O

R27 NPECL2 NPECL2

R28 AGND AGND

R29 I/O (GLMX2) I/O (GLMX2)

R30 I/O I/O

T1 I/O I/O

T2 AVDD AVDD

T3 GL2 GL2

T4 PPECL1 (I/P) PPECL1 (I/P)

T5 I/O I/O

T6 I/O I/O

T7 I/O I/O

T8 I/O I/O

T9 I/O I/O

T10 VDDP VDDP

T11 VDD VDD

T12 GND GND

T13 GND GND

T14 GND GND

896 FBGA Pin (Continued)

Number APA750

Function APA1000

Function

T15 GND GND

T16 GND GND

T17 GND GND

T18 GND GND

T19 GND GND

T20 VDD VDD

T21 VDDP VDDP

T22 I/O I/O

T23 I/O I/O

T24 I/O I/O

T25 I/O I/O

T26 PPECL2 (I/P) PPECL2 (I/P)

T27 GL4 GL4

T28 GL3 GL3

T29 AVD D AVDD

T30 I/O I/O

U1 I/O I/O

U2 I/O I/O

U3 I/O I/O

U4 I/O I/O

U5 I/O I/O

U6 I/O I/O

U7 I/O I/O

U8 I/O I/O

U9 NC I/O

U10 VDDP VDDP

U11 VDD VDD

U12 GND GND

U13 GND GND

U14 GND GND

U15 GND GND

U16 GND GND

U17 GND GND

U18 GND GND

U19 GND GND

U20 VDD VDD

U21 VDDP VDDP

U22 NC I/O

U23 I/O I/O

U24 I/O I/O

U25 I/O I/O

U26 I/O I/O

896 FBGA Pin (Continued)

Number APA750

Function APA1000

Function

ProASICPLUS Flash Family FPGAs

118 v3.0

U27 I/O I/O

U28 I/O I/O

U29 I/O I/O

U30 I/O I/O

V1 I/O I/O

V2 I/O I/O

V3 I/O I/O

V4 I/O I/O

V5 I/O I/O

V6 I/O I/O

V7 I/O I/O

V8 I/O I/O

V9 NC I/O

V10 VDDP VDDP

V11 VDD VDD

V12 GND GND

V13 GND GND

V14 GND GND

V15 GND GND

V16 GND GND

V17 GND GND

V18 GND GND

V19 GND GND

V20 VDD VDD

V21 VDDP VDDP

V22 NC I/O

V23 I/O I/O

V24 I/O I/O

V25 I/O I/O

V26 I/O I/O

V27 I/O I/O

V28 I/O I/O

V29 I/O I/O

V30 I/O I/O

W1 I/O I/O

W2 I/O I/O

W3 I/O I/O

W4 I/O I/O

W5 I/O I/O

W6 I/O I/O

W7 I/O I/O

W8 I/O I/O

896 FBGA Pin (Continued)

Number APA750

Function APA1000

Function

W9 NC I/O

W10 VDDP VDDP

W11 VDD VDD

W12 GND GND

W13 GND GND

W14 GND GND

W15 GND GND

W16 GND GND

W17 GND GND

W18 GND GND

W19 GND GND

W20 VDD VDD

W21 VDDP VDDP

W22 NC I/O

W23 I/O I/O

W24 I/O I/O

W25 I/O I/O

W26 I/O I/O

W27 I/O I/O

W28 I/O I/O

W29 I/O I/O

W30 I/O I/O

Y1 I/O I/O

Y2 I/O I/O

Y3 I/O I/O

Y4 I/O I/O

Y5 I/O I/O

Y6 I/O I/O

Y7 I/O I/O

Y8 I/O I/O

Y9 NC I/O

Y10 NC I/O

Y11 VDD VDD

Y12 VDD VDD

Y13 VDD VDD

Y14 VDD VDD

Y15 VDD VDD

Y16 VDD VDD

Y17 VDD VDD

Y18 VDD VDD

Y19 VDD VDD

Y20 VDD VDD

896 FBGA Pin (Continued)

Number APA750

Function APA1000

Function

v3.0 119

ProASICPLUS Flash Family FPGAs

Y21 NC I/O

Y22 NC I/O

Y23 I/O I/O

Y24 I/O I/O

Y25 I/O I/O

Y26 I/O I/O

Y27 I/O I/O

Y28 I/O I/O

Y29 I/O I/O

Y30 I/O I/O

AA1 I/O I/O

AA2 I/O I/O

AA3 I/O I/O

AA4 I/O I/O

AA5 I/O I/O

AA6 I/O I/O

AA7 I/O I/O

AA8 I/O I/O

AA9 NC I/O

AA10 VDD VDD

AA11 NC I/O

AA12 VDDP VDDP

AA13 VDDP VDDP

AA14 VDDP VDDP

AA15 VDDP VDDP

AA16 VDDP VDDP

AA17 VDDP VDDP

AA18 VDDP VDDP

AA19 VDDP VDDP

AA20 NC I/O

AA2 1 VDD VDD

AA22 NC I/O

AA23 I/O I /O

AA24 I/O I /O

AA25 I/O I /O

AA26 I/O I /O

AA27 I/O I /O

AA28 I/O I /O

AA29 I/O I /O

AA30 I/O I/O

AB1 I/O I/O

AB2 I/O I/O

896 FBGA Pin (Continued)

Number APA750

Function APA1000

Function

AB3 I/O I/O

AB4 I/O I/O

AB5 I/O I/O

AB6 I/O I/O

AB7 VDDP VDDP

AB8 I/O I/O

AB9 VDD VDD

AB10 NC I/O

AB11 NC I/O

AB12 NC I/O

AB13 NC I/O

AB14 NC I/O

AB15 NC I/O

AB16 NC I/O

AB17 NC I/O

AB18 NC I/O

AB19 NC I/O

AB20 NC I/O

AB21 NC I/O

AB22 VDD VDD

AB23 I/O I/O

AB24 VDDP VDDP

AB25 I/O I/O

AB26 I/O I/O

AB27 I/O I/O

AB28 I/O I/O

AB29 I/O I/O

AB30 I/O I/O

AC1 I/O I/O

AC2 I/O I/O

AC3 I/O I/O

AC4 I/O I/O

AC5 I/O I/O

AC6 I/O I/O

AC7 I/O I/O

AC8 GND GND

AC9 NC I/O

AC10 NC I/O

AC11 NC I/O

AC12 NC I/O

AC13 NC I/O

AC14 NC I/O

896 FBGA Pin (Continued)

Number APA750

Function APA1000

Function

ProASICPLUS Flash Family FPGAs

120 v3.0

AC15 NC I/O

AC16 NC I/O

AC17 NC I/O

AC18 NC I/O

AC19 NC I/O

AC20 NC I/O

AC21 NC I/O

AC22 NC I/O

AC23 GND GND

AC24 I/O I/O

AC25 I/O I/O

AC26 I/O I/O

AC27 I/O I/O

AC28 I/O I/O

AC29 I/O I/O

AC30 I/O I/O

AD1 GND GND

AD2 I/O I/O

AD3 I/O I/O

AD4 I/O I/O

AD5 VDDP VDDP

AD6 I/O I/O

AD7 VDD VDD

AD8 I/O I/O

AD9 VDDP VDDP

AD10 I/O I/O

AD11 I/O I/O

AD12 I/O I/O

AD13 I/O I/O

AD14 I/O I/O

AD15 I/O I/O

AD16 I/O I/O

AD17 I/O I/O

AD18 I/O I/O

AD19 I/O I/O

AD20 I/O I/O

AD21 I/O I/O

AD22 VDDP VDDP

AD23 TCK TCK

AD24 VDD VDD

AD25 TRST TRST

AD26 VDDP VDDP

896 FBGA Pin (Continued)

Number APA750

Function APA1000

Function

AD27 I/O I/O

AD28 I/O I/O

AD29 I/O I/O

AD30 GN D GN D

AE1 I/O I/O

AE2 VDD VDD

AE3 I/O I/O

AE4 I/O I/O

AE5 I/O I/O

AE6 GND GND

AE7 I/O I/O

AE8 I/O I/O

AE9 I/O I/O

AE10 I/O I/O

AE11 I/O I/O

AE12 I/O I/O

AE13 I/O I/O

AE14 I/O I/O

AE15 I/O I/O

AE16 I/O I/O

AE17 I/O I/O

AE18 I/O I/O

AE19 I/O I/O

AE20 I/O I/O

AE21 I/O I/O

AE22 I/O I/O

AE23 I/O I/O

AE24 I/O I/O

AE25 GND GND

AE26 I/O I/O

AE27 I/O I/O

AE28 I/O I/O

AE29 VDD VDD

AE30 I/O I/O

AF1 GND GND

AF2 I/O I/O

AF3 VDDP VDDP

AF4 I/O I/O

AF5 VDD VDD

AF6 I/O I/O

AF7 VDDP VDDP

AF8 I/O I/O

896 FBGA Pin (Continued)

Number APA750

Function APA1000

Function

v3.0 121

ProASICPLUS Flash Family FPGAs

AF9 I/O I/O

AF10 I/O I/O

AF11 I/O I/O

AF12 I/O I/O

AF13 I/O I/O

AF14 I/O I/O

AF15 I/O I/O

AF16 I/O I/O

AF17 I/O I/O

AF18 I/O I/O

AF19 I/O I/O

AF20 I/O I/O

AF21 I/O I/O

AF22 I/O I/O

AF23 I/O I/O

AF24 VDDP VDDP

AF25 I/O I/O

AF26 VDD VDD

AF27 TDO TDO

AF28 VDDP VDDP

AF29 VPN VPN

AF30 GND GND

AG1 I/O I/O

AG2 VDD VDD

AG3 I/O I/O

AG4 GND GND

AG5 I/O I/O

AG6 I/O I/O

AG7 I/O I/O

AG8 I/O I/O

AG9 I/O I/O

AG10 I/O I/O

AG11 I/O I/O

AG12 I/O I/O

AG13 I/O I/O

AG14 I/O I/O

AG15 I/O I/O

AG16 I/O I/O

AG17 I/O I/O

AG18 I/O I/O

AG19 I/O I/O

AG20 I/O I/O

896 FBGA Pin (Continued)

Number APA750

Function APA1000

Function

AG21 I/O I/O

AG22 I/O I/O

AG23 I/O I/O

AG24 I/O I/O

AG25 I/O I/O

AG26 I/O I/O

AG27 GND GND

AG28 RCK RCK

AG29 VDD VDD

AG30 I/O I/O

AH1 GND GND

AH2 I/O I/O

AH3 VDD VDD

AH4 I/O I/O

AH5 VDDP VDDP

AH6 I/O I/O

AH7 I/O I/O

AH8 I/O I/O

AH9 I/O I/O

AH10 I/O I/O

AH11 I/O I/O

AH12 I/O I/O

AH13 I/O I/O

AH14 I/O I/O

AH15 I/O I/O

AH16 I/O I/O

AH17 I/O I/O

AH18 I/O I/O

AH19 I/O I/O

AH20 I/O I/O

AH21 I/O I/O

AH22 I/O I/O

AH23 I/O I/O

AH24 I/O I/O

AH25 I/O I/O

AH26 VDDP VDDP

AH27 TDI TDI

AH28 VDD VDD

AH29 VPP VPP

AH30 GND GND

AJ1 GND GND

AJ2 GND GND

896 FBGA Pin (Continued)

Number APA750

Function APA1000

Function

ProASICPLUS Flash Family FPGAs

122 v3.0

AJ3 I/O I/O

AJ4 VDD VDD

AJ5 I/O I/O

AJ6 VDD VDD

AJ7 I/O I/O

AJ8 I/O I/O

AJ9 I/O I/O

AJ10 I/O I/O

AJ11 I/O I/O

AJ12 I/O I/O

AJ13 I/O I/O

AJ14 I/O I/O

AJ15 I/O I/O

AJ16 I/O I/O

AJ17 I/O I/O

AJ18 I/O I/O

AJ19 I/O I/O

AJ20 I/O I/O

AJ21 I/O I/O

AJ22 I/O I/O

AJ23 I/O I/O

AJ24 I/O I/O

AJ25 VDD VDD

AJ26 I/O I/O

AJ27 VDD VDD

AJ28 TMS TMS

AJ29 GND GND

AJ30 GND GND

AK2 GND GND

AK3 GND GND

AK4 I/O I/O

AK5 GND GND

AK6 I/O I/O

AK7 GND GND

AK8 I/O I/O

AK9 I/O I/O

AK10 I/O I/O

AK11 I/O I/O

AK12 I/O I /O

AK13 I/O I /O

AK14 I/O I /O

AK15 I/O I /O

896 FBGA Pin (Continued)

Number APA750

Function APA1000

Function

AK16 I/O I/O

AK17 I/O I/O

AK18 I/O I/O

AK19 I/O I/O

AK20 I/O I/O

AK21 I/O I/O

AK22 I/O I/O

AK23 I/O I/O

AK24 GND GND

AK25 I/O I/O

AK26 GND GND

AK27 I/O I/O

AK28 GND GND

AK29 GND GND

896 FBGA Pin (Continued)

Number APA750

Function APA1000

Function

v3.0 123

ProASICPLUS Flash Family FPGAs

Package Pin Assignments (Continued)

1152-Pin FBGA (Bottom View)

AGAG

1234567891011121314151617181920212324252627

28293031323334

A1 Ball Pad Corner

ProASICPLUS Flash Family FPGAs

124 v3.0

1152 FBGA Pin

Number APA1000

Function

A2 NC

A3 GND

A4 GND

A5 GND

A6 I/O

A7 VDD

A8 VDD

A9 VDD

A10 VDD

A11 I/O

A12 GND

A13 I/O

A14 VDDP

A15 VDDP

A16 I/O

A17 GND

A18 GND

A19 I/O

A20 VDDP

A21 VDDP

A22 I/O

A23 GND

A24 I/O

A25 VDD

A26 VDD

A27 VDD

A28 VDD

A29 I/O

A30 GND

A31 GND

A32 GND

A33 NC

B1 NC

B2 NC

B3 GND

B4 GND

B5 GND

B6 NC

B7 I/O

B8 NC

B9 I/O

B10 NC

B11 I/O

B12 GND

B13 I/O

B14 VDDP

B15 VDDP

B16 I/O

B17 GND

B18 GND

B19 I/O

B20 VDDP

B21 VDDP

B22 I/O

B23 GND

B24 I/O

B25 NC

B26 I/O

B27 NC

B28 I/O

B29 NC

B30 GND

B31 GND

B32 GND

B33 NC

B34 NC

C1 GND

C2 GND

C3 NC

C4 GND

C5 GND

C6 I/O

C7 GND

C8 I/O

C9 GND

C10 I/O

C11 I/O

C12 I/O

C13 I/O

C14 I/O

C15 I/O

C16 I/O

C17 I/O

C18 I/O

C19 I/O

C20 I/O

C21 I/O

C22 I/O

C23 I/O

C24 I/O

1152 FBGA Pin

Number APA1000

Function

C25 I/O

C26 GND

C27 I/O

C28 GND

C29 I/O

C30 GND

C31 GND

C32 NC

C33 GND

C34 GND

D1 GND

D2 GND

D3 GND

D4 GND

D5 I/O

D6 VDD

D7 I/O

D8 VDD

D9 I/O

D10 I/O

D11 I/O

D12 I/O

D13 I/O

D14 I/O

D15 I/O

D16 I/O

D17 I/O

D18 I/O

D19 I/O

D20 I/O

D21 I/O

D22 I/O

D23 I/O

D24 I/O

D25 I/O

D26 I/O

D27 VDD

D28 I/O

D29 VDD

D30 I/O

D31 GND

D32 GND

D33 GND

D34 GND

E1 GND

1152 FBGA Pin

Number APA1000

Function

E2 GND

E3 GND

E4 I/O

E5 VDD

E6 I/O

E7 VDDP

E8 I/O

E9 I/O

E10 I/O

E11 I/O

E12 I/O

E13 I/O

E14 I/O

E15 I/O

E16 I/O

E17 I/O

E18 I/O

E19 I/O

E20 I/O

E21 I/O

E22 I/O

E23 I/O

E24 I/O

E25 I/O

E26 I/O

E27 I/O

E28 VDDP

E29 I/O

E30 VDD

E31 I/O

E32 GND

E33 GND

E34 GND

F1 I/O

F2 NC

F3 I/O

F4 VDD

F5 I/O

F6 GND

F7 I/O

F8 I/O

F9 I/O

F10 I/O

F11 I/O

F12 I/O

1152 FBGA Pin

Number APA1000

Function

v3.0 125

ProASICPLUS Flash Family FPGAs

F13 I/O

F14 I/O

F15 I/O

F16 I/O

F17 I/O

F18 I/O

F19 I/O

F20 I/O

F21 I/O

F22 I/O

F23 I/O

F24 I/O

F25 I/O

F26 I/O

F27 I/O

F28 I/O

F29 GND

F30 I/O

F31 VDD

F32 I/O

F33 NC

F34 NC

G1 VDD

G2 I/O

G3 GND

G4 I/O

G5 VDDP

G6 I/O

G7 VDD

G8 I/O

G9 VDDP

G10 I/O

G11 I/O

G12 I/O

G13 I/O

G14 I/O

G15 I/O

G16 I/O

G17 I/O

G18 I/O

G19 I/O

G20 I/O

G21 I/O

G22 I/O

G23 I/O

1152 FBGA Pin

Number APA1000

Function

G24 I/O

G25 I/O

G26 VDDP

G27 I/O

G28 VDD

G29 I/O

G30 VDDP

G31 I/O

G32 GND

G33 I/O

G34 VDD

H1 VDD

H2 NC

H3 I/O

H4 VDD

H5 I/O

H6 I/O

H7 I/O

H8 GND

H9 I/O

H10 I/O

H11 I/O

H12 I/O

H13 I/O

H14 I/O

H15 I/O

H16 I/O

H17 I/O

H18 I/O

H19 I/O

H20 I/O

H21 I/O

H22 I/O

H23 I/O

H24 I/O

H25 I/O

H26 I/O

H27 GND

H28 I/O

H29 I/O

H30 I/O

H31 VDD

H32 I/O

H33 NC

H34 VDD

1152 FBGA Pin

Number APA1000

Function

J1 VDD

J2 I/O

J3 GND

J4 I/O

J5 I/O

J6 I/O

J7 VDDP

J8 I/O

J9 VDD

J10 I/O

J11 VDDP

J12 I/O

J13 I/O

J14 I/O

J15 I/O

J16 I/O

J17 I/O

J18 I/O

J19 I/O

J20 I/O

J21 I/O

J22 I/O

J23 I/O

J24 VDDP

J25 I/O

J26 VDD

J27 I/O

J28 VDDP

J29 I/O

J30 I/O

J31 I/O

J32 GND

J33 I/O

J34 VDD

K1 VDD

K2 NC

K3 I/O

K4 I/O

K5 I/O

K6 I/O

K7 I/O

K8 I/O

K9 I/O

K10 GND

K11 I/O

1152 FBGA Pin

Number APA1000

Function

K12 I/O

K13 I/O

K14 I/O

K15 I/O

K16 I/O

K17 I/O

K18 I/O

K19 I/O

K20 I/O

K21 I/O

K22 I/O

K23 I/O

K24 I/O

K25 GND

K26 I/O

K27 I/O

K28 I/O

K29 I/O

K30 I/O

K31 I/O

K32 I/O

K33 NC

K34 VDD

L1 I/O

L2 I/O

L3 I/O

L4 I/O

L5 I/O

L6 I/O

L7 I/O

L8 I/O

L9 VDDP

L10 I/O

L11 VDD

L12 I/O

L13 I/O

L14 I/O

L15 I/O

L16 I/O

L17 I/O

L18 I/O

L19 I/O

L20 I/O

L21 I/O

L22 I/O

1152 FBGA Pin

Number APA1000

Function

ProASICPLUS Flash Family FPGAs

126 v3.0

L23 I/O

L24 VDD

L25 I/O

L26 VDDP

L27 I/O

L28 I/O

L29 I/O

L30 I/O

L31 I/O

L32 I/O

L33 I/O

L34 I/O

M1 GND

M2 GND

M3 I/O

M4 I/O

M5 I/O

M6 I/O

M7 I/O

M8 I/O

M9 I/O

M10 I/O

M11 I/O

M12 VDD

M13 I/O

M14 VDDP

M15 VDDP

M16 VDDP

M17 VDDP

M18 VDDP

M19 VDDP

M20 VDDP

M21 VDDP

M22 I/O

M23 VDD

M24 I/O

M25 I/O

M26 I/O

M27 I/O

M28 I/O

M29 I/O

M30 I/O

M31 I/O

M32 I/O

M33 GND

1152 FBGA Pin

Number APA1000

Function

M34 GND

N1 I/O

N2 I/O

N3 I/O

N4 I/O

N5 I/O

N6 I/O

N7 I/O

N8 I/O

N9 I/O

N10 I/O

N11 I/O

N12 I/O

N13 VDD

N14 VDD

N15 VDD

N16 VDD

N17 VDD

N18 VDD

N19 VDD

N20 VDD

N21 VDD

N22 VDD

N23 I/O

N24 I/O

N25 I/O

N26 I/O

N27 I/O

N28 I/O

N29 I/O

N30 I/O

N31 I/O

N32 I/O

N33 I/O

N34 I/O

P1 VDDP

P2 VDDP

P3 I/O

P4 I/O

P5 I/O

P6 I/O

P7 I/O

P8 I/O

P9 I/O

P10 I/O

1152 FBGA Pin

Number APA1000

Function

P11 I/O

P12 VDDP

P13 VDD

P14 GND

P15 GND

P16 GND

P17 GND

P18 GND

P19 GND

P20 GND

P21 GND

P22 VDD

P23 VDDP

P24 I/O

P25 I/O

P26 I/O

P27 I/O

P28 I/O

P29 I/O

P30 I/O

P31 I/O

P32 I/O

P33 VDDP

P34 VDDP

R1 VDDP

R2 VDDP

R3 I/O

R4 I/O

R5 I/O

R6 I/O

R7 I/O

R8 I/O

R9 I/O

R10 I/O

R11 I/O

R12 VDDP

R13 VDD

R14 GND

R15 GND

R16 GND

R17 GND

R18 GND

R19 GND

R20 GND

R21 GND

1152 FBGA Pin

Number APA1000

Function

R22 VDD

R23 VDDP

R24 I/O

R25 I/O

R26 I/O

R27 I/O

R28 I/O

R29 I/O

R30 I/O

R31 I/O

R32 I/O

R33 VDDP

R34 VDDP

T1 I/O

T2 I/O

T3 I/O

T4 I/O

T5 I/O

T6 I/O

T7 I/O

T8 I/O

T9 I/O

T10 I/O

T11 I/O

T12 VDDP

T13 VDD

T14 GND

T15 GND

T16 GND

T17 GND

T18 GND

T19 GND

T20 GND

T21 GND

T22 VDD

T23 VDDP

T24 I/O

T25 I/O

T26 I/O

T27 I/O

T28 I/O

T29 I/O

T30 I/O

T31 I/O

T32 I/O

1152 FBGA Pin

Number APA1000

Function

v3.0 127

ProASICPLUS Flash Family FPGAs

T33 I/O

T34 I/O

U1 GND

U2 GND

U3 I/O

U4 I/O

(GLMX1)

U5 AGND

U6 NPECL1

U7 GL1

U8 I/O

U9 I/O

U10 I/O

U11 I/O

U12 VDDP

U13 VDD

U14 GND

U15 GND

U16 GND

U17 GND

U18 GND

U19 GND

U20 GND

U21 GND

U22 VDD

U23 VDDP

U24 I/O

U25 I/O

U26 I/O

U27 I/O

U28 I/O

U29 NPECL2

U30 AGND

U31 I/O

(GLMX2)

U32 I/O

U33 GND

U34 GND

V1 GND

V2 GND

V3 I/O

V4 AVDD

V5 GL2

V6 PPECL1

(I/P)

1152 FBGA Pin

Number APA1000

Function

V7 I/O

V8 I/O

V9 I/O

V10 I/O

V11 I/O

V12 VDDP

V13 VDD

V14 GND

V15 GND

V16 GND

V17 GND

V18 GND

V19 GND

V20 GND

V21 GND

V22 VDD

V23 VDDP

V24 I/O

V25 I/O

V26 I/O

V27 I/O

V28 PPECL2

(I/P)

V29 GL4

V30 GL3

V31 AVDD

V32 I/O

V33 GND

V34 GND

W1 I/O

W2 I/O

W3 I/O

W4 I/O

W5 I/O

W6 I/O

W7 I/O

W8 I/O

W9 I/O

W10 I/O

W11 I/O

W12 VDDP

W13 VDD

W14 GND

W15 GND

W16 GND

1152 FBGA Pin

Number APA1000

Function

W17 GND

W18 GND

W19 GND

W20 GND

W21 GND

W22 VDD

W23 VDDP

W24 I/O

W25 I/O

W26 I/O

W27 I/O

W28 I/O

W29 I/O

W30 I/O

W31 I/O

W32 I/O

W33 I/O

W34 I/O

Y1 VDDP

Y2 VDDP

Y3 I/O

Y4 I/O

Y5 I/O

Y6 I/O

Y7 I/O

Y8 I/O

Y9 I/O

Y10 I/O

Y11 I/O

Y12 VDDP

Y13 VDD

Y14 GND

Y15 GND

Y16 GND

Y17 GND

Y18 GND

Y19 GND

Y20 GND

Y21 GND

Y22 VDD

Y23 VDDP

Y24 I/O

Y25 I/O

Y26 I/O

Y27 I/O

1152 FBGA Pin

Number APA1000

Function

Y28 I/O

Y29 I/O

Y30 I/O

Y31 I/O

Y32 I/O

Y33 VDDP

Y34 VDDP

AA1 VDDP

AA2 VDDP

AA3 I/O

AA4 I/O

AA5 I/O

AA6 I/O

AA7 I/O

AA8 I/O

AA9 I/O

AA10 I/O

AA11 I/O

AA12 VDDP

AA13 VDD

AA14 GND

AA15 GND

AA16 GND

AA17 GND

AA18 GND

AA19 GND

AA20 GND

AA21 GND

AA22 VDD

AA23 VDDP

AA24 I/O

AA25 I/O

AA26 I/O

AA27 I/O

AA28 I/O

AA29 I/O

AA30 I/O

AA31 I/O

AA32 I/O

AA33 VDDP

AA34 VDDP

AB1 I/O

AB2 I/O

AB3 I/O

AB4 I/O

1152 FBGA Pin

Number APA1000

Function

ProASICPLUS Flash Family FPGAs

128 v3.0

AB5 I/O

AB6 I/O

AB7 I/O

AB8 I/O

AB9 I/O

AB10 I/O

AB11 I/O

AB12 I/O

AB13 VDD

AB14 VDD

AB15 VDD

AB16 VDD

AB17 VDD

AB18 VDD

AB19 VDD

AB20 VDD

AB21 VDD

AB22 VDD

AB23 I/O

AB24 I/O

AB25 I/O

AB26 I/O

AB27 I/O

AB28 I/O

AB29 I/O

AB30 I/O

AB31 I/O

AB32 I/O

AB33 I/O

AB34 I/O

AC1 GND

AC2 GND

AC3 I/O

AC4 I/O

AC5 I/O

AC6 I/O

AC7 I/O

AC8 I/O

AC9 I/O

AC10 I/O

AC11 I/O

AC12 VDD

AC13 I/O

AC14 VDDP

AC15 VDDP

1152 FBGA Pin

Number APA1000

Function

AC16 VDDP

AC17 VDDP

AC18 VDDP

AC19 VDDP

AC20 VDDP

AC21 VDDP

AC22 I/O

AC23 VDD

AC24 I/O

AC25 I/O

AC26 I/O

AC27 I/O

AC28 I/O

AC29 I/O

AC30 I/O

AC31 I/O

AC32 I/O

AC33 GND

AC34 GND

AD1 I/O

AD2 I/O

AD3 I/O

AD4 I/O

AD5 I/O

AD6 I/O

AD7 I/O

AD8 I/O

AD9 VDDP

AD10 I/O

AD11 VDD

AD12 I/O

AD13 I/O

AD14 I/O

AD15 I/O

AD16 I/O

AD17 I/O

AD18 I/O

AD19 I/O

AD20 I/O

AD21 I/O

AD22 I/O

AD23 I/O

AD24 VDD

AD25 I/O

AD26 VDDP

1152 FBGA Pin

Number APA1000

Function

AD27 I/O

AD28 I/O

AD29 I/O

AD30 I/O

AD31 I/O

AD32 I/O

AD33 I/O

AD34 I/O

AE1 VDD

AE2 NC

AE3 I/O

AE4 I/O

AE5 I/O

AE6 I/O

AE7 I/O

AE8 I/O

AE9 I/O

AE10 GND

AE11 I/O

AE12 I/O

AE13 I/O

AE14 I/O

AE15 I/O

AE16 I/O

AE17 I/O

AE18 I/O

AE19 I/O

AE20 I/O

AE21 I/O

AE22 I/O

AE23 I/O

AE24 I/O

AE25 GND

AE26 I/O

AE27 I/O

AE28 I/O

AE29 I/O

AE30 I/O

AE31 I/O

AE32 I/O

AE33 NC

AE34 VDD

AF1 VDD

AF2 I/O

AF3 GND

1152 FBGA Pin

Number APA1000

Function

AF4 I/O

AF5 I/O

AF6 I/O

AF7 VDDP

AF8 I/O

AF9 VDD

AF10 I/O

AF11 VDDP

AF12 I/O

AF13 I/O

AF14 I/O

AF15 I/O

AF16 I/O

AF17 I/O

AF18 I/O

AF19 I/O

AF20 I/O

AF21 I/O

AF22 I/O

AF23 I/O

AF24 VDDP

AF25 TCK

AF26 VDD

AF27 TRST

AF28 VDDP

AF29 I/O

AF30 I/O

AF31 I/O

AF32 GND

AF33 I/O

AF34 VDD

AG1 VDD

AG2 NC

AG3 I/O

AG4 VDD

AG5 I/O

AG6 I/O

AG7 I/O

AG8 GND

AG9 I/O

AG10 I/O

AG11 I/O

AG12 I/O

AG13 I/O

AG14 I/O

1152 FBGA Pin

Number APA1000

Function

v3.0 129

ProASICPLUS Flash Family FPGAs

AG15 I/O

AG16 I/O

AG17 I/O

AG18 I/O

AG19 I/O

AG20 I/O

AG21 I/O

AG22 I/O

AG23 I/O

AG24 I/O

AG25 I/O

AG26 I/O

AG27 GND

AG28 I/O

AG29 I/O

AG30 I/O

AG31 VDD

AG32 I/O

AG33 NC

AG34 VDD

AH1 VDD

AH2 I/O

AH3 GND

AH4 I/O

AH5 VDDP

AH6 I/O

AH7 VDD

AH8 I/O

AH9 VDDP

AH10 I/O

AH11 I/O

AH12 I/O

AH13 I/O

AH14 I/O

AH15 I/O

AH16 I/O

AH17 I/O

AH18 I/O

AH19 I/O

AH20 I/O

AH21 I/O

AH22 I/O

AH23 I/O

AH24 I/O

AH25 I/O

1152 FBGA Pin

Number APA1000

Function

AH26 VDDP

AH27 I/O

AH28 VDD

AH29 TDO

AH30 VDDP

AH31 VPN

AH32 GND

AH33 I/O

AH34 VDD

AJ1 I/O

AJ2 NC

AJ3 I/O

AJ4 VDD

AJ5 I/O

AJ6 GND

AJ7 I/O

AJ8 I/O

AJ9 I/O

AJ10 I/O

AJ11 I/O

AJ12 I/O

AJ13 I/O

AJ14 I/O

AJ15 I/O

AJ16 I/O

AJ17 I/O

AJ18 I/O

AJ19 I/O

AJ20 I/O

AJ21 I/O

AJ22 I/O

AJ23 I/O

AJ24 I/O

AJ25 I/O

AJ26 I/O

AJ27 I/O

AJ28 I/O

AJ29 GND

AJ30 RCK

AJ31 VDD

AJ32 I/O

AJ33 NC

AJ34 NC

AK1 GND

AK2 GND

1152 FBGA Pin

Number APA1000

Function

AK3 GND

AK4 I/O

AK5 VDD

AK6 I/O

AK7 VDDP

AK8 I/O

AK9 I/O

AK10 I/O

AK11 I/O

AK12 I/O

AK13 I/O

AK14 I/O

AK15 I/O

AK16 I/O

AK17 I/O

AK18 I/O

AK19 I/O

AK20 I/O

AK21 I/O

AK22 I/O

AK23 I/O

AK24 I/O

AK25 I/O

AK26 I/O

AK27 I/O

AK28 VDDP

AK29 TDI

AK30 VDD

AK31 VPP

AK32 GND

AK33 GND

AK34 GND

AL1 GND

AL2 GND

AL3 GND

AL4 GND

AL5 I/O

AL6 VDD

AL7 I/O

AL8 VDD

AL9 I/O

AL10 I/O

AL11 I/O

AL12 I/O

AL13 I/O

1152 FBGA Pin

Number APA1000

Function

AL14 I/O

AL15 I/O

AL16 I/O

AL17 I/O

AL18 I/O

AL19 I/O

AL20 I/O

AL21 I/O

AL22 I/O

AL23 I/O

AL24 I/O

AL25 I/O

AL26 I/O

AL27 VDD

AL28 I/O

AL29 VDD

AL30 TMS

AL31 GND

AL32 GND

AL33 GND

AL34 GND

AM1 GND

AM2 GND

AM3 NC

AM4 GND

AM5 GND

AM6 I/O

AM7 GND

AM8 I/O

AM9 GND

AM10 I/O

AM11 I/O

AM12 I/O

AM13 I/O

AM14 I/O

AM15 I/O

AM16 I/O

AM17 I/O

AM18 I/O

AM19 I/O

AM20 I/O

AM21 I/O

AM22 I/O

AM23 I/O

AM24 I/O

1152 FBGA Pin

Number APA1000

Function

ProASICPLUS Flash Family FPGAs

130 v3.0

AM25 I/O

AM26 GND

AM27 I/O

AM28 GND

AM29 I/O

AM30 GND

AM31 GND

AM32 NC

AM33 GND

AM34 GND

AN1 NC

AN2 NC

AN3 GND

AN4 GND

AN5 GND

AN6 NC

AN7 I/O

AN8 NC

AN9 I/O

AN10 NC

AN11 I/O

AN12 GND

AN13 I/O

AN14 VDDP

AN15 VDDP

AN16 I/O

AN17 GND

AN18 GND

AN19 I/O

AN20 VDDP

AN21 VDDP

AN22 I/O

AN23 GND

AN24 I/O

AN25 NC

AN26 I/O

AN27 NC

AN28 I/O

AN29 NC

AN30 GND

AN31 GND

AN32 GND

AN33 NC

AN34 NC

AP2 NC

1152 FBGA Pin

Number APA1000

Function

AP3 GND

AP4 GND

AP5 GND

AP6 I/O

AP7 VDD

AP8 VDD

AP9 VDD

AP10 VDD

AP11 I/O

AP12 GND

AP13 I/O

AP14 VDDP

AP15 VDDP

AP16 I/O

AP17 GND

AP18 GND

AP19 I/O

AP20 VDDP

AP21 VDDP

AP22 I/O

AP23 GND

AP24 I/O

AP25 VDD

AP26 VDD

AP27 VDD

AP28 VDD

AP29 I/O

AP30 GND

AP31 GND

AP32 GND

AP33 NC

1152 FBGA Pin

Number APA1000

Function

v3.0 131

ProASICPLUS Flash Family FPGAs

List of Changes

The following table lists critical changes that were made in the current version of the document.

Previ o us versi on Ch anges in cur rent version (A dvance d v3.0) Page

v2.0

The “Pro ASICPLUS Product Profile” t able on page 1 was updated. page 1

The “Ordering Information” section on page 3 was updated. page 3

The “Plastic Device Resources” table on pa ge 3 was updated. page 3

The “Pro duct Availability” table on page 4 was updated. page 4

Table 2 on page 10 was update d. page 10

Figure 8 on page 10 is new. page 10

Fig ure 11 on page 12 is new. page 12

The Introduction in the “ProASICPLUS Clock Management System” section on page 15 was

updated. page 15

The “Phys i cal Impl ementatio n” sectio n on page 15 was updated. page 15

The “Func tional Description” section on page 15 was updated. page 15

Figure 14 on page 16 through Figure 20 on page 20 were updated. page 16 to page 20

The “PLL El ectrical Specifications” table on page 21 was updated. page 21

Figure 25 on page 25 was updated. page 25

The “Calculating T ypical Power Dissipation” section on page 28 was updated. page 28

The “Sup pl y Volt ages” tabl e on page 30 was updated. page 30

The “DC Electrical Speci fications (VDDP = 3.3V ±0.3V and VD D 2.5V ±0.2V)1” table on page 32

was updated. page 32

The “Tristate Buffer Delays” table on page 35 was updated. page 35

The “Output Buffer Del ays” section on page 36 was updated. page 36

The“Input Bu ffer Delays” secti on on page 37 was updated. page 37

“Global Routing Skew” table on page 38 was updated. page 38

The“Sampl e Macrocell Library Listing*” table on page 39 was upda ted. page 39

The “Pin Description” section on p age 60 was updated. page 60

The following pins have bee n changed in the “100-Pin TQFP” table on page 63:

Pin Number Function Pin Number Function

10 I/O (GLMX1) 60 GL3

11 GL 1 61 P PE C L 2 (I /P )

13 NPECL1 63 NPECL2

15 PPE C L1 (I /P) 65 GL 4

16 GL2 66 I/O (GLMX2)

page 63

“144-Pin TQFP” table on page 65 is new. page 65

The following pins have bee n changed in the “208-Pin PQFP” table on page 68:

Pin Number Function Pin Number Function

23 I/O (GLMX1) 128 GL3

24 GL1 129 PPECL2 (I/P)

26 NPECL1 132 NPECL2

28 PPE C L1 (I /P) 134 GL4

30 GL2 135 I/O (GLMX2)

page 68

The following pins have bee n changed in the “456-Pin PBGA” table on page 74:

Pin Number Function Pin Number Function

M1 GL1 N22 NPECL2

M2 GL2 N23 GL3

M22 GL4 N25 I/O (GLMX2)

N2 I/O (GLMX1) P5 NPECL1

N4 PPECL1 (I/P) P26 PPECL2 (I/P)

page 74

ProASICPLUS Flash Family FPGAs

132 v3.0

v2.0 (continued)

The following pins have bee n changed in the “144-FBGA Pi n” tabl e on page 86:

Pin Number Function Pin Number Function

C2 GL2 F9 GL4

D12 I/O (GLMX2 )F11 PPECL2 (I/P

E11 NPECL2 F12 GL3

F1 GL 1 G1 P PE C L 1 (I/P)

F3 I/O (GLMX1) G4 NPECL1

page 86

The following pins have bee n changed in the “256-Pin FBGA” table on page 89:

Pin Number Function Pin Number Function

H1 GL1 H16 GL4

H2 NPECL1 J1 GL2

H3 I/O (GLMX1) J2 PPECL1 (I/P)

H13 I/O (GLMX2) J13 PPECL2 ( I/P)

H14 NPECL2 J16 GL3

page 89

The following pins have bee n changed in the“484-Pi n FBGA” table on page 96:

Pin Number Function Pin Number Function

L4 GL1 L19 GL4

L5 NPECL1 M4 GL2

L6 I/O (GLMX1) M5 PPECL1 (I/P)

L16 I/O (GLMX2) M16 PPECL2 ( I/P)

L17 NPECL2 M19 GL3

page 96

The following pins have bee n changed in the “676-FBGA Pi n” tabl e on page 103:

Pin Number Function Pin Number Function

N1 GL1 N25 GL4

N3 I/O (GLMX1) P1 GL2

N5 NPECL1 P5 PPECL1 (I/P)

N22 GL3 P22 I/O (GLMX 2)

N24 NPECL2 P24 PPECL2 (I/P)

page 103

The following pins have bee n changed in the “896 FBGA Pin” table on page 112:

Pin Number Function Pin Number Function

R2 I/O (GLMX1) T3 GL2

R4 NPECL1 T4 P PECL1 (I/P)

R5 GL1 T26 PPECL2 (I/P)

R27 NPECL2 T27 GL4

R29 I/O (GLMX2) T28 GL3

page 112

The following pins have bee n changed in the “1152 FBGA Pin” table on page 124:

Pin Number Function Pin Number Function

U4 I/O (GLMX 1) U29 NPECL2

U6 NPECL1 U31 I/O (GLMX2)

U7 GL1 V28 PPECL2 (I/P)

V5 GL2 V29 GL4

V6 PPECL1 (I/P ) V30 GL3

page 124

Previ o us versi on Changes in cur rent version (A dvance d v3.0) Page

ProASICPLUS Flash Family FPGAs

v3.0 133

Advanced v0.7

The “Pro duct Availability” table on page 4 was updated. page 4

The “A r r ay C o or d i nates ” s ection on pag e 10 and Table 2 are new. page 10

The “Power-up Sequencing” section on page 12 is ne w. page 12

Table 4 on page 11 was updated. page 11

The “Timing Cont rol and Characteristics” section on page 15 was upda ted. Physical

Implementation, Functional Description, Lock Sig nal, and PLL Configuration Opt ions are new. page 15 to page 16

Figure 14 on page 17 was updated. page 17

Figure 15 on page 18 was updated. page 18

Sample Implementations, Adjust able Clock Delay , and th e “Cloc k Skew Minimi zatio n” sec tion on

page 16 are new. page 16

Figure 16, Figure 17, Figure 18, Figure 19, and Figure 20 are new. page 19 to page 21

The “PLL El ectrical Specifications” table on page 22 is new . page 22

The “Des i gn Environment” section on page 27 was updated. page 27

Figure 26 on page 27 was updated. page 27

The “Calculating T ypical Power Dissipation” section on page 29 was updated. page 29

The “DC El ectrical Specific ations (VDDP = 2.5V ±0.2V)1 ” table on page 32 was updated. page 32

The “DC Electrical Speci fications (VDDP = 3.3V ±0.3V and VD D 2.5V ±0.2V)1” table on page 33

was updated. page 33

The “DC Specifications (3.3V PCI Operation)1” table on page 34 was updated. page 34

The “Tristate Buffer Delays” section on page 36 (the figure and table) have been updated. page 36

The “Output Buffer Dela ys” secti on on page 37 (the fi gure and table) have been updated. page 37

The “In put Buffer De lays” table on page 38 was updated. page 38

The “Global Input Buffer D el ays” table on page 38 was updated. page 38

The “Pre di cted Global Routing Del ay*” table on page 39 was updated. page 39

The “Global Routi ng Skew” table on page 39 was updated. page 39

The “Sample Macrocell Library Listing*” table on page 40 was updated. page 40

The “Pin Description” section on page 61 was updated. GLMX is new. page 61

The “Rec ommended Design Practice for VPN/VPP” section on page 62 was updated. page 62

Pin AK31 of FG1152 for the APA1000 changed to VPP. page 128

(Advanced v0.6)

The “Features an d Benefits” section on pa ge 1 were updated. page 1

The “Pro ASICPLUS Product Profile” t able on page 1 was updated. page 1

The “Ordering Information” section on page 3 was updated. page 3

The “Plastic Device Resources” table o n page 3 was updated. page 3

The “Product Plan” table on page 4 was updated. page 4

Table 1 on page 10 was updated. page 10

Figure 12 on page 15 was updated. page 15

The “Des i gn Environment” section on page 23 was upd ated. page 23

The “Package Thermal Characteristics” table on page 24 was updated. page 24

The “Calculating Power Dissipation” section on page 25 was updated. page 25

The “Absolute Maximum Ratings*” table on page 26 wa s updated. page 26

The “Pro grammi ng and Storage and Operating Temperatu r e Li mits” tabl e on page 26 was

updated. page 26

The “Sup pl y Voltages” table on page 26 was updated. page 26

The “Rec ommended Operatin g C onditions” t able on page 26 was updated. page 26

The “DC Electrical Sp ecifications (VDDP = 2. 5V ±0.2V) 1 ” tab l e on pag e 27 was updated. page 27

The “DC Electrical Sp ecifications (VDDP = 3.3V ±0.3V and VDD 2.5V ±0.2V)1” table on page 28

was updated. page 28

The “Sync hronous Write and Read to the Same Location” figure on page 44 was updated. page 44

The “Asy nchronous Write and Synchronous Read t o the Same Location” fi gure on pag e 45 was

updated. page 45

The “Asy nchronous FIFO Read” figure on page 50 was updated. page 50

The “Pin Description” section on p age 57 has been updated. page 57

The “Rec ommended Design Practice for VPN/VPP” section on page 57 is n ew. page 57

The “100-Pin TQFP” figure on page 62 is new. page 62

The “484 -Pin FBGA” f i gure on page 96 is new. page 96

Advan ced v0.5 The desc ri ption for the VPN pin has changed. page 57

Previ o us versi on Ch anges in cur rent version (A dvance d v3.0) Page

ProASICPLUS Flash Family FPGA

134 v3.0

Datasheet Categories

In order to provide the latest information to designers, some datasheets are published before data has been fully

characterized. Datasheets are designated as “Product Brief,” “Advanced,” “Production.” The definition of these categories

are as follows:

Product Brief

The product brief is a modified version of an advanced datasheet containing general product information. This brief

summarizes specific device and family information for un released products.

Advanced

This datasheet version contains initial es timated information based on simulation, other products, devices, or speed grades.

This information ca n be used as estimates, but not for production.

Unmarked (production)

This datasheet version contains information that is considered to be final.

Advanced v0.4

The “Plastic Device Resources” table on page 3 has been updated. page 3

Figure 12 and Figure 13 on page 15 have been updated. page 15

The “Tristate Buffer Delays” table on page 31 has been updated. page 31

The “Output Buffer Delays” table on p age 32 has been updated. page 32

The “Input Buffer Delays” table on page 33 has been updated. page 33

The “Global Input Buffer Delays” table on page 34 has been updated. page 34

The “456-Pin PBGA” table on page 74 has been updated. page 74

The “676-FBGA Pin” table on page 103 has been updated. page 103

Advanced v0.3

The “ProASICPLUS Product Profile” figure on page 1 has been changed. page 1

The “Plastic Device Resources” figure on page 3 has been updated. page 3

The Supply Voltages table on page 10 has been updated. page 10

WDATA has ben changed to DI, and RDATA has been changed to DO to make them

consistent with the signal names found in the Mac ro Library Guid e.

Figure 13 on page 19 and Figure 14 on page 20 have been updated. page 19

and page 20

The “Design Environment” figure on page 23 and Figure 18 on page 23 have been

updated. page 23

and page 23

The table in the “Packag e Thermal Characteristics” section on page 24 has been updated. page 24

The “Cal cu lating Powe r Dissipation ” section o n page 25 is new. page 25

The “Programming and Storage and Operating Temperature Limits” section on page 26 is

new. page 26

The “Supply Voltages” section on page 26 has been updated. page 26

The “DC Electrical S p ecifications (VDDP = 2.5V ±0.2V)1” table on page 27 was updated. page 27

The “DC Electrical S p ecifications (VDDP = 3.3V ±0.3V and VDD 2.5V ±0.2V)1” table on

page 28 was updated. page 28

The “AC Specifications (3.3V PCI Revision 2.2 Operation)” table on page 30 was updated. page 30

The “Clock Conditioning Circuit” section on page 14 was updated. page 14

Figure 12 on page 15 was updated. page 15

Figure 13 on page 15 is new. page 15

Tables 5, 6, and 7 from Advanced v0.3 were removed.

The “Memory Block SRAM Interface Signals” figure on page 19 was updated. page 19

The “Memory Block FIFO Interface Signals” figure on page 48 was updated. page 48

All pinout tables have been updated, and several packages are new:

208-Pin PQ FP – APA150, APA 300, APA 450, APA 600

456-Pin PBGA – APA150, APA300, APA450, APA600

144-Pin FBG A – APA150, APA 300, APA 450

256-Pin FB GA – APA150, APA 300, APA 450, APA 600

676-Pin FBG A – APA 600

Advanced v0.1 Figure 15 on page 21 has been updated page 21

Previ o us versi on Changes in cur rent version (A dvance d v3.0) Page

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