ANALOG LC*M0S DEVICES (8 + 4) Loading Dual 12-Bit DAC AD7937 REV. B 1.1 Scope. This specification covers the detail requirements for a monolithic CMOS 12-bit digital-to-analog converter. The D/A converters provide 4-quadrant multiplication capabilities with separate reference inputs and feedback resistors. Each D/A converter has a 2-byte (8 + 4) loading structure. It is designed for right-justified format. The device is easily interfaced to any 8-bit microprocessor system. 1.2 Part Number. The complete part number per Table 1 of this specification is as follows: Device Part Number! -l AD75378(X)/883B 2 AD7537T(X)/883B -3 AD7537U(X)/883B NOTE 'To complete the part number substitute the package identifier as shown in paragraph 1.2.3. 1.2.3 Case Outline. See Appendix 1 of General Specification ADI-M-1000: package outline: () Package Description Q Q-24 24-Pin Cerdip, 0.3 Width E E-28A 28-Contact LCC 1.3 Absolute Maximum Ratings. (T, = 25C unless otherwise noted, Pin numbers refer to DIP package) Vpp (Pin 20) to DGND.. 1... 2. ee 0.3V, +17V VReEFA> Vererp (Pins 4, 21) to AGNDA, AGNDB .... 2... ee tt et et es +25V Vrrpa> VeFeB (Pins 3, 22) to AGNDA, AGNDB ......... 2.0.02 eee ete ns +25V Digital Input Voltage (Pins 5~19) to DGND ..............20004 -0.3V, Vpp +0.3V Vem Vern23 toDGND .........0 0.000 eee ee he ee -0.3V, Vpop +0.3V AGNDA, AGNDBto DGND ..... 0.0... 2.2 eee es 0.3V, Vpp +0.3V Power Dissipation Upto +79 2. ee 450m W Derates above +75C 1 ww ee eee 6mW/C Operating Temperature Range .. 2... ee ee es 55C to + 125C Lead Temperature (Soldering 10sec) . 2... 0. te + 300C 1.5 Thermal Characteristics. Thermal Resistance 6j = 35C/W for Q-24 and E-28A 654 = 120C/W for Q-24 and E-28A DIGITAL-TO-ANALOG CONVERTERS 8-131 DIGITAL-TO-ANALOG CONVERTERS aAD7537 SPECIFICATIONS Table 1. Design Sub Sub Sub Limit Group| Group | Group Test Symbol | Device | Tain: Tmas| 1 2,3 4 Test Condition'/Com Units Resolution RES -1,2,3 | 12 Bits Relative Accuracy RA -1 1 1 1 Vop = 10.8V + LSB max -2,3 V2 ! 1/2 1/2 Differential Nonlinearity DNL | -1,2,3]1 1 1 All Grades Guaranteed Monotonic | + LSB max to 12 Bits from Tyun tO T nex: Vpp = 10.8V Gain Error Ay -1 6 6 6 Measured Using Ry, and Ry-g. Both| + LSB max -~2 3 6 3 3 DAC Registers Loaded with All Is. -3 2 6 2 2 Vop = 10.8V. Gain Temperature Coefficient dA;/dT | -1,2,3 15 Typical Value is lppm/C + ppm/C max) Output Leakage Current (Pin 2) foura | -1,2,3 | 250 10 250 DAC A Register Loaded with nA max All 0s; Vin = 16.5V Output Leakage Current (Pin 23) Touts | -1,2,3 | 250 10 250 DAC B Register Loaded with nA max All 0s; Von = 16.5V Reference Input Resistance R; -1,2,3 ]9 9 9 Typical Input Resistance is 14k kf min (Pin 4, Pin 21) 20 20 20 Von = 10.8V kO) max Reference Input Resistance Match RMw | -1,2 3 3 3 Typically + 0.5% + % max Varia, Vann -3 1 3 3 1 Vpn = 10.8V Digital Input High Voltage Vin -1,2,3 92.4 2.4 2.4 Von = 10.8V and 16.5V Vmin Digital Input Low Voltage Vu. -1,2,3 [0.8 0.8 0.8 Vpp = 10.8V and 16.5V Vmax Digital Input Current lin ~1,2,3 {10 1 10 Vin = Von = 16.5V A max Digital Input Capacitance Cy -1,2,3 $10 pF max Power Supply Voltage Von -1,2,3 | 10.8 Vmin 16.5 V max Power Supply Current Ipp -1,2,3 | 2 2 2 Von = 16.5V mA max Output Current Settling Time f@ 25C ts. ~1,2,3 [1.5 To0.01% of Full-Scale Range. ps max lour Load = 100. Cex = 13pF. DAC Output Measured from Rising Edge of WR. Typical Value of Settling Time is 0.8ps. AC Feedthrough Vrreat0louta FT ~1,2,3 | 65 Vrera, Vrern = 20V P-Pp 10kHz ~ dB max and Verrstoloutr Sine-Wave DAC Register Loaded with All 0s. Power Supply Rejection Ratio PSRR | -1,2,3 {0.02 0.01 0.02 AVpp= I2V +5% + %/% max (AGain/AVpp) Output Capacitance for Cour -1,2,3 170 DACA, DACB Loaded with Alls. [ pF max DAC Aand DACB 140 DAC A, DACB Loaded with All 1s, Address Valid to Write Setup Time, t)| tans 1,2,3 | 30 ns min Address Valid to Write Hold Time, t2 | tants [| 1,2,3 | 25 ns min Data Setup Time, t, tps ~1,2,3 | 80 ns min Data Hold Time, t, tpH -1,2,3 | 25 ns min Chip Select to Write Setup Time, ts . | tows -1,2,3 [0 ns min Chip Select to Write Hold Time, & lowH -1,2,3]0 ns min Write Pulse Width, t, twr -1,2,3 | 100 ns min Clear Pulse Width, ty te. ~1,2,3 | 100 ns min NOTES ; Vip = + 12Vto + 15V + 10% except where outherwise stated; Vasra = Vaera = 10V5 Vein? = Veni = OV; Veinzs = Vernze = OV. Output amplifiers are AD644. Pin numbers refer to DIP Package. 8-132 DIGITAL-TO-ANALOG CONVERTERS REV. BAD7537 5v AO-A1 ov 5V DATA ov Cs, UPD 6v " ov ~ te ov aa 5V ov NOTES 1. AILINPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF +5V. t, =t,=20ns. 2, TIMING MEASUREMENT REFERENCE LEVEL is #* Ve Figure 1. Timing Diagram for AD7537 3.2.1 Functional Block Diagram and Terminal Assignments. Voo Q Package (DIP) Gs) . AD7537 J [i | AGNDA Oy [24] AGNDB loura 23) loute DAC A MS. DAC ALS INPUT REG INPUT REG Rrea [3 Ell Rene 4 8 Vrera | 4 21) Vrers es Ls 20] Yoo DAC A REGISTER [=] avyss7 _ UPD peo [6 19] oF Urb (2) 12 TOP VIEW __ 2) loura pet CG] (Not to Scale) 8] WR DACA a1 (6) 1) AGNDA vez [| [7] cur I om om (a on Ao CONTROL 4) Vara psa [10 [a5] Ao (5) 21) Vice pes [17 14} 087 22) Fras penp [12 [ia] 08s 23) lours wa Ge) DAC A 24) AGNDB GLA (7) 12 E Package (LCC) DAC B REGISTER 4 8 < a 3 a # $2222822 |_| DACB MS DAC BLS INPUT REG INPUT REG 4 3 2 1 28 27 26 pf Vaca 5 LJ 25 Vnera > cs 6 24 Voo Cy & Ny peo 7 apres? 23 UPD DB7-080 DGND Nc 8 22 NC TOP VIEW pei 9 (Not to Seale} 21 Wa oB2 10 20 CLR Da3 11 9 OAl 12 13 14 15 16 17 16 o g29288 REV. B DIGITAL-TO-ANALOG CONVERTERS 8-133 DIGITAL-TO-ANALOG CONVERTERS aAD7537 3.2.4 Microcircuit Technology Group. This microcircuit is covered by technology group (80). 4.2.1 Life Test/Burn-In Circuit. Steady state life test is per MIL-STD-883 Method 1005. Burn-in is per MIL-STD-883 Method 1015 test condition (B). EXTERNAL INPUTS Vaer- -10V Vaer 10V Von 15V CLK GND Voc > > a > 2470 3470 3470 3 470 4 4 4 q UNUSED _ OUTPUTS wR CARRY = 12 ao BORROW 13 at DATA 3 2 6 7 OA O08 ac- ap cLK LOAD (11 < %) UP 54LS193 $470 pown (4 A B C DD. cR OrO.D=e 4 GND Voc PIN16 GNDPINE EXTERNAL INPUTS Vee 5V GND cLK ALLRESISTORS 10% 8-134 DIGITAL-TO-ANALOG CONVERTERS = w > No Vaer- Varer Al AQ DATA GNO AO, A1, DATA AND WR ARE DERIVED FROM THE 54193 CONTROL CIRCUIT. LOAD | LOAD] LOAD | LOAD A 6 c D . THERE ARE 6 CONNECTIONS TO EACH BOARD. Voo =15V Vacr = 10V Vee =5V Vaer. = 10V CLOCK GND EACH AD7537 SOCKET HAS 5 RESISTORS ASSOCIATED WITH IT. 1k ON THE Voo LINE, 10k ON THE CONTROL LINES WR, AO, A1 AND 10k COMMON TO ALL DATA LINES. . UPD IS TIED LOW SO THE DAC REAR RANK LATCHES ARE TRANSPARENT. THE DAC CODES ARE TOGGLED BETWEEN 0 AND FULL SCALE EVERY 4 CLOCK PULSES. . EACH BOARD HAS A 54193 4-BIT COUNTER CONTROLLING THE LOADING AND TOGGLING OF DATA. . THIS BOARD IS FOR DYNAMIC BURN-IN ONLY. RESISTOR TOLERANCE 10%. REV. 8AD7537 REV. B 5.0 Unipolar Binary Operation (2-Quadrant Multiplication) Figure 2 shows the circuit diagram for unipolar binary operation. With an ac input, the circuit performs 2-quadrant multiplication. The code table for Figure 2 is given in Table 2. Operational amplifiers Al and A2 can be in a single package (AD644) or separate packages (AD544, AD OP-27). Capacitors C] and C2 provide phase compensation to help prevent overshoot and ringing when high-speed op amps are used. For zero offset adjustment, the appropriate DAC register is loaded with all 0s and amplifier offset adjusted so that Voura or Vouts is OV. Full-scale trimming is accomplished by loading the DAC register with all 1s and adjusting R1 (R3) so that Voura (Vours)= Vin (4095/4096). For high temperature operation, resistors and potentiometers should have a low Temperature Coefficient. In many applications, because of the excellent Gain T.C. and Gain Error specifications of the AD7537, Gain Error trimming is not necessary. In fixed reference applications, full scale can also be adjusted by omitting R1, R2, R3, R4 and trimming the reference voltage magnitude. Voo Views Rt 1000 20 4 R2 A ese A780 c1 2 louta 33pF DB? DACA At 7) AGNDA . Vora a4 v2 , ADSe pata | i * R4 inpuT 1 AD7837 Free 47f { ez , 239 DAC B AGNDB 24 12 ours Apsas ) D OGND = 8, *CONTROL CIRCUITRY OMITTED FOR CLARITY Vine Figure 2, AD7537 Unipolar Binary Operation Table 2. Unipolar Binary Code Table for Circuit of Figure 2 Binary Number in DAC Register Analog Output, MSB LSB Voura or Vouts Wi 11 m1 ~Vin (458) 1000 0000 0000 ~Vin (age = -12Vin 0000 0000 0001 ~ Van (za38) 0000 0000 0000 ov DIGITAL-TO-ANALOG CONVERTERS 8-135 DIGITAL-TO-ANALOG CONVERTERS = |AD7937 6.0 Bipolar Operation (4-Quadrant Multiplication) The recommended circuit diagram for bipolar operation is shown in Figure 3. Offset binary coding is used. With the appropriate DAC register loaded to 1000 0000 0000, adjust R1 (R3) so that Voura (Vours) = OV. Alternatively, R1, R2 (R3, R4) may be omitted and the ratios of R6, R7 (R9, R10) varied for Voura (Vouts) = OV. Full-scale trimming can be accomplished by adjusting the amplitude of Vpy or by varying the value of R5 (R8). , If RI, R2 (R3, R4) are not used, then resistors R5, R6, R7 (R8, R9, R10) should be ratio matched to 0.01% to ensure gain error performance to the data sheet specification. When operating over a wide tem- perature range, it is important that the resistors be of the same type so that their temperature coefficients match. The code table for Figure 3 is given in Table 3. f R10 20kn + Vow *CONTROL CIRCUITRY OMITTED FOR CLAIRITY Figure 3. Bipolar Operation (Offset Binary Coding) Table 3. Bipolar Code Table for Offset Binary Circuit of Figure 3 Binary Number in DAC Register Analog Output, MSB LSB Vouta or Vours Ww wn un + Vv (3048) 1000 0000 0001 +Vmv(s00) 1000 0000 0000 ov om 1111 1111 - Viv (seu) 0000 0000 0000 Vn (3248) =-Vin 8-136 DIGITAL-TO-ANALOG CONVERTERS REV. B