www.irf.com © 2009 International Rectifier
1
Data Sheet No. PD PD60342A
November 13, 2009
IR21364(S&J)PbF
3-PHASE BRIDGE DRIVER
Features
Floating channel designed for bootstrap operation
Tolerant to negative transient voltage – dV/dt immune
Gate drive supply range from 11.5 V to 20 V
Undervoltage lockout for all channels
Over-current shutdown turns off all six drivers
Independent 3 half-bridge drivers
Matched propagation delay for all channels
Cross-conduction prevention logic
Low side and High side outputs in phase with inputs.
3.3 V logic compatible
Lower di/dt gate drive for better noise immunity
Externally programmable delay for automatic fault clear
RoHS Compliant
Typical Applications
Motor Control
Air Conditioners/ Washing Machines
General Purpose Inverters
Micro/Mini Inverter Drivers
Product Summary
Topology 3 phase bridge
driver
V
OFFSET
600 V
V
OUT
11.5 V – 20 V
I
o+
& I
o-
(typical) 200 mA & 350 mA
t
ON
& t
OFF
(typical) 500 ns & 530 ns
Package Options
28-Lead SOIC
44-Lead PLCC
w/o 12 Leads
IR21364(S&J)PbF
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2
Description
The IR21364(S&J)PBF is a high voltage, high speed power MOSFET and IGBT drivers with three
independent high and low side referenced output channels for 3-phase applications. Proprietary HVIC
technology enables ruggedized monolithic construction. Logic inputs are compatible with CMOS or LSTTL
outputs, down to 3.3V logic. A current trip function which terminates all six outputs can be derived from an
external current sense resistor. An enable function is available to terminate all six outputs simultaneously. An
open-drain FAULT signal is provided to indicate that an overcurrent or undervoltage shutdown has occurred.
Overcurrent fault conditions are cleared automatically after a delay programmed externally via an RC
network connected to the RCIN input. The output drivers feature a high pulse current buffer stage designed
for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency
applications. The floating channel can be used to drive N-channel power MOSFETs or IGBTs in the high side
configuration which operates up to 600 V.
Qualification Information
Industrial
††
Qualification Level Comments: This family of ICs has passed JEDEC’s
Industrial qualification. IR’s Consumer qualification
level is granted by extension of the higher Industrial
level.
SOIC28W MSL3
†††
, 260°C
(per IPC/JEDEC J-STD-020)
Moisture Sensitivity Level
PLCC44 MSL3
†††
, 245°C
(per IPC/JEDEC J-STD-020)
Human Body Model Class 2
(per JEDEC standard JESD22-A114)
ESD
Machine Model Class B
(per EIA/JEDEC standard EIA/JESD22-A115)
IC Latch-Up Test Class I, Level A
(per JESD78)
RoHS Compliant Yes
Qualification standards can be found at International Rectifier’s web site http://www.irf.com/
†† Higher qualification ratings may be available should the user have such requirements. Please contact
your International Rectifier sales representative for further information.
†††
Higher MSL ratings may be available for the specific package types listed here. Please contact your
International Rectifier sales representative for further information.
IR21364(S&J)PbF
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3
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are
measured under board mounted and still air conditions.
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the
recommended conditions. All voltage parameters are absolute referenced to COM. The V
S
& V
SS
offset rating are
tested with all supplies biased at a 15 V differential.
Symbol
Definition Min. Max. Units
V
B1,2,3
High side floating supply voltage IR21364 V
S1,2,3
+11.5 V
S1,2,3
+ 20
V
S 1,2,3
High side floating supply voltage Note 1 600
V
CC
Low side supply voltage IR21364
11.5 20
V
HO 1,2,3
High side output voltage V
S1,2,3
V
B1,2,3
V
LO1,2,3
Low side output voltage 0 V
CC
V
SS
Logic ground -5 5
V
FLT
FAULT output voltage V
SS
V
CC
V
RCIN
RCIN input voltage V
SS
V
CC
V
ITRIP
ITRIP input voltage V
SS
V
SS
+ 5
V
IN
Logic input voltage LIN, HIN, EN V
SS
V
SS
+ 5
V
T
A
Ambient temperature
-40
125
°C
Note 1: Logic operational for
V
S
of COM -5 V to COM + 600 V. Logic state held for
V
S
of COM -5 to COM –
V
BS.
(Please refer to the Design Tip DT97 -3 for more details).
Symbol
Definition Min Max Units
V
S
High side offset voltage V
B 1,2,3
- 25 V
B 1,2,3
+ 0.3
V
B
High side floating supply voltage -0.3 625
V
HO
High side floating output voltage V
S1,2,3
- 0.3 V
B 1,2,3
+ 0.3
V
CC
Low side and logic fixed supply voltage -0.3 25
V
SS
Logic ground V
CC
- 25 V
CC
+ 0.3
V
LO1,2,3
Low side output voltage -0.3 V
CC
+ 0.3
V
IN
Input voltage LIN, HIN, ITRIP, EN, RCIN V
SS
-0.3
lower of
V
CC
+ 0.3 or
Vss+15
V
FLT
FAULT output voltage V
SS
-0.3 V
CC
+ 0.3
V
dV/dt Allowable offset voltage slew rate 50 V/ns
(28 lead SOIC) 1.6
P
D
Package power dissipation
@ T
A
+25 °C (44 lead PLCC) 2.0
W
(28 lead SOIC) 78
Rth
JA
Thermal resistance, junction to
ambient (44 lead PLCC) 63
°C/W
T
J
Junction temperature 150
T
S
Storage temperature -55 150
T
L
Lead temperature (soldering, 10 seconds) 300
°C
IR21364(S&J)PbF
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4
Static Electrical Characteristics
V
BIAS
(V
CC
, V
BS 1,2,3
) = 15 V, TA = 25°C unless otherwise specified. The V
IN
, V
TH
and I
IN
parameters are referenced to
V
SS
and are applicable to all six channels (HIN1,2,3 and LIN1,2,3). The V
O
and I
O
parameters are referenced to COM
and V
S1,2,3
and are applicable to the respective output leads: HO1,2,3 and LO1,2,3.
Symbol Definition Min
Typ Max
Units
Test
Conditions
V
IH
Logic “0” input voltage 0.8
V
IL
Logic “1” input voltage 2.5
V
EN,TH+
Enable positive going threshold 2.5
V
EN,TH-
Enable negative going threshold 0.8
V
IT,TH+
ITRIP positive going threshold 0.37
0.46 0.55
V
IT,HYS
ITRIP hysteresis 0.07
V
RCIN, TH+
RCIN positive going threshold 8
V
RCIN, HYS
RCIN hysteresis 3
V
OH
High level output voltage, V
BIAS
- V
O
0.9 1.4
V
OL
Low level output voltage, V
O
0.4 0.6
Io = 20 mA
V
CCUV+
V
CC
supply undervoltage positive going
threshold IR21364 9.6 10.4 11.2
V
CCUV-
V
CC
supply undervoltage negative going
threshold IR21364 8.6 9.4 10.2
V
CCUVHY
V
CC
supply undervoltage hysteresis IR21364 1
V
BSUV+
V
BS
supply undervoltage positive going
threshold IR21364 9.6 10.4 11.2
V
BSUV-
V
BS
supply undervoltage negative going
threshold IR21364 8.6 9.4 10.2
V
BSUVHY
V
BS
supply undervoltage
hysteresis IR21364 1
V
llk Offset supply leakage current 50 V
B
= V
S
= 600 V
I
QBS
Quiescent V
BS
supply current 70 120 µA V
B1,2,3
= V
S1,2,3
=
600 V
I
QCC
Quiescent V
CC
supply current 0.6 1.3 mA V
IN
= 0 V or 5 V
I
LIN
+ Input bias current (LOUT = HI) 100 195 V
LIN
= 3.3 V
I
LIN
- Input bias current (LOUT = LO) -1 V
LIN
= 0 V
I
HIN
+ Input bias current (HOUT = HI) 100 195 V
HIN
= 3.3 V
I
HIN
- Input bias current (HOUT = LO) -1 V
HIN
= 0 V
I
ITRIP+
“High” ITRIP input bias current 3.3 6 V
ITRIP
= 3.3 V
I
ITRIP-
“Low” ITRIP input bias current -1 V
ITRIP
= 0 V
I
EN+
“High” ENABLE input bias current 100 V
EN
= 3.3 V
I
EN-
“Low” ENABLE input bias current -1 V
EN
= 0 V
I
RCIN
RCIN input bias current 1
µA
Vrcin = 0 V or 15
V
Io+ Output high short circuit pulsed current 120
200 Vo = 0 V,
PW 10 µs
Io- Output low short circuit pulsed current 250
350
mA Vo = 15 V,
PW 10 µs
R
on_RCIN
RCIN low on resistance 50 100
R
on_FAULT
FAULT low on resistance 50 100 I = 1.5 mA
IR21364(S&J)PbF
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5
Dynamic Electrical Characteristics
Dynamic Electrical Characteristics V
CC
= V
BS
= V
BIAS
= 15 V, V
S1,2,3
= V
SS
= COM, TA = 25°C and CL = 1000 pF
unless otherwise specified
.
Symbol Definition Min Typ
Max
Units
Test Conditions
t
on
Turn-on propagation delay 350 500 650
t
off
Turn-off propagation delay 375 530 685
t
r
Turn-on rise time 125 190
t
f
Turn-off fall time 50 75
V
IN
= 0 V & 5 V
t
EN
ENABLE low to output shutdown propagation
delay 300 450 600 V
IN,
V
EN
= 0 V or 5 V
t
ITRIP
ITRIP to output shutdown propagation delay 500 750 1000
V
ITRIP
= 5 V
t
bl
ITRIP blanking time 100 150
t
FLT
ITRIP to FAULT propagation delay 400 600 800
V
IN
= 0 V or 5 V
V
ITRIP
= 5 V
t
FILIN
Input filter time (HIN, LIN) 100 200
t
filterEn
Enable input filter time 100 200
DT Deadtime 220 290 360
V
IN
= 0 V & 5 V
MT Ton, off matching time (on all six channels) 75
MDT DT matching (Hi->Lo & Lo->Hi on all channels) 70
External dead time
>450 nsec
PM pulse width distortion (pwin-pwout) 75
ns
PW input =10 µs
t
FLTCLR
FAULT clear time RCIN: R = 2 M, C = 1 nF 1.3 1.65 2 ms V
IN
= 0 V or 5 V
V
ITRIP
= 0 V
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6
Fig. 1. Input/Output Timing Diagram
Fig. 2. Switching Time Waveforms Fig. 3. Output Enable Timing Waveform
EN
ITRIP
FAULT
HIN1,2,3
LIN1,2,3
RCIN
HO1,2,3
LO1,2,3
90%
ten
EN
50%
LIN1,2,3
HIN1,2,
50%
50%
PW
IN
t
r
10%
HO1,2,3
LO1,2,3
90%
t
f
ton
tof
f
90%
10%
HO1,2,3
LO1,2,3
PW
50
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RCIN
ITRIP
FAULT
Any
Oupu t
titrip
50%
50%
90%
tflt 5 0%
tfltclr
50%
Fig. 5. ITRIP/RCIN Timing Waveforms
Fig. 6. Input Filter Function
Fig. 4. Internal Deadtime Timing Waveforms
on
off
on
HIN/LI
t
in,fi
l
lo
w
t
in,fi
l
on
off
off
high
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Lead Definitions
Symbol
Description
V
CC
Low side supply voltage
V
SS
Logic ground
HIN1,2,3 Logic inputs for high side gate driver outputs (HO1,2,3), in phase
LIN1,2,3 Logic input for low side gate driver outputs (LO1,2,3), in phase
FAULT Indicates over-current (ITRIP) or low-side undervoltage lockout has occurred. Negative logic, open-drain
output
EN Logic input to enable I/O functionality. Positive logic, i.e. I/O logic functions When ENABLE is high. No
effect on FAULT and not latched
ITRIP
Analog input for overcurrent shutdown. When active, ITRIP shuts down outputs
and activates FAULT and
RCIN low. When ITRIP becomes inactive, FAULT stays active low for an externally set time T
FLTCLR
, then
automatically becomes inactive (open-drain high impedance).
RCIN External RC network input used to define FAULT CLEAR delay, T
FLTCLR,
approximately equal to R*C.
When RCIN > 8 V, the FAULT pin goes back into open-drain high-impedance
COM Low side gate drivers return
V
B1,2,3
High side floating supply
HO1,2,3 High side gate driver outputs
V
S1,2,3
High voltage floating supply return
LO1,2,3 Low side gate driver outputs
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Functional Block Diagram
VCC VBS ITRIP ENAB LE FAULT LO1,2,3 HO1,2,3
<UV
CC
X X X 0 (note 1) 0 0
15 V <U
VBS
0 V 5 V high imp LIN1,2,3 0
15 V 15 V 0 V 5 V high imp LIN1,2,3 HIN1,2,3
15 V 15 V >V
ITRIP
5 V 0 (note 2) 0 0
15 V 15 V 0 V 0 V high imp 0 0
Note 1: A shoot-through prevention logic prevents LO1,2,3 and HO1,2,3 for each channel from turning on simultaneously.
Note 2: U
VCC
is not latched, when V
CC
> U
VCC
, FAULT return to high impedance.
Note 3: When ITRIP <V
ITRIP
, FAULT returns to high-impedance after RCIN pin becomes greater than 8 V (@ V
CC
= 15 V)
IR21364(S&J)PbF
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Parameter Temperature Trends
Figures 7-39 provide information on the experimental performance of the IR21364 HVIC. The line plotted
in each figure is generated from actual lab data. A small number of individual samples were tested at
three temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental (Exp.) curve. The
line labeled Exp. consist of three data points (one data point at each of the tested temperatures) that have
been connected together to illustrate the understood temperature trend. The individual data points on the
curve were determined by calculating the averaged experimental value of the parameter (for a given
temperature).
Fig. 7. (Ton_Ls1 ) Turn-on Propagation Delay
vs. Temperature
0
100
200
300
400
500
600
700
800
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
t
ON
(ns)
Exp.
0
200
400
600
800
1000
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
t
OFF
(ns)
Exp.
Fig. 8. (Toff_Ls1) Turn-off Propagation Delay
vs. Temperature
0
100
200
300
400
500
600
700
800
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
t
ON
(ns)
Exp.
Fig. 9. (Ton_Hs11) Turn-on Propagation Delay
vs. Temperature
0
100
200
300
400
500
600
700
800
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
t
OFF
(ns)
Exp.
Fig. 10. (Toff_Hs21) Turn-off Propagation
Delay vs. Temperature
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0
50
100
150
200
250
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
t
R
(ns)
Exp.
Fig. 11. Turn-on Rise Time vs. Temperature
0
20
40
60
80
100
120
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
t
F
(ns)
Exp.
Fig. 12. Turn-off Fall Time vs. Temperature
0
200
400
600
800
1000
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
t
ITRIP
(ns)
Exp.
Fig. 16. ITRIP to Output Shutdown Propagation
Delay vs. Temperature
0
20
40
60
80
100
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
MT (ns)
Exp.
Fig. 13. Ton, off matching time vs.
Temperature
0
20
40
60
80
100
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
MDT (ns)
Exp.
Fig. 14. DT matching time vs. Temperature
0
20
40
60
80
100
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
PM (ns)
Exp.
Fig. 15. Pulse Width Distortion vs.
Temperature
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0
200
400
600
800
1000
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
TEN (nS)
Exp.
Figure 18. EN to Output Shutdown Time vs.
Temperature
0
100
200
300
400
500
600
700
800
900
1000
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
t
FLT
(ns)
Exp.
Fig. 19. ITRIP to FAULT Indication Delay vs.
Temperature
0.0
1.0
2.0
3.0
4.0
5.0
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
TFLTCLR (mS)
Exp.
Fig. 20. FAULT Clear Time vs. Temperature
0
200
400
600
800
1000
1200
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
DLTon1 (ns)
Exp.
Fig. 17. Dead Time vs. Temperature
0.0
1.5
3.0
4.5
6.0
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
LIN1_VTH+ (V)
Exp.
Fig. 21. Input Positive Going Threshold vs.
Temperature
0.0
0.5
1.0
1.5
2.0
2.5
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
LIN1_VTH- (V)
Exp.
Fig. 22. Input Negative Going Threshold vs.
Temperature
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13
0
100
200
300
400
500
600
700
800
-50 -25 0 25 50 75 100 125
Temperature (oC)
VIT,TH+ (mV)
EXP.
p.
Fig. 23. ITRIP Input Positive Going Threshold
vs. Temperature
0
100
200
300
400
500
600
700
800
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
V
IT,TH-
(mV)
Exp.
Fig. 24. ITRIP Input Negative Going Threshold
vs. Temperature
0
100
200
300
400
500
600
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
VOL_LO1 (mV)
Exp.
0
400
800
1200
1600
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
VOH_LO1 (mV)
Exp.
0.0
0.5
1.0
1.5
2.0
2.5
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
ileak1 (µA)
Exp.
Fig. 28. Offset Supply Leakage Current vs.
Temperature
0
20
40
60
80
100
120
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
R
ON,FLT
()
Exp.
Fig. 27. FAULT Low On-Resistance vs.
Temperature
Fig. 25. Low Level Output Voltage vs.
Temperature
Fig. 26. High Level Output Voltage vs.
Temperature
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14
0.0
0.5
1.0
1.5
2.0
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
I
QCC1
(mA)
Exp.
Fig. 29. Quiescent V
CC
Supply Current vs.
Temperature
0.0
0.5
1.0
1.5
2.0
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
I
QCC0
(mA)
Exp.
Fig. 30. Quiescent V
CC
Supply Current vs.
Temperature
0
10
20
30
40
50
60
70
80
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
I
QBS10
(µA)
Exp.
Fig. 31. Quiescent V
BS
Supply Current vs.
Temperature
0
20
40
60
80
100
120
140
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
I
QBS11
(µA)
Exp.
Fig. 32. Quiescent V
BS
Supply Current vs.
Temperature
0.0
3.0
6.0
9.0
12.0
15.0
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
V
CCUV-
(V)
Exp.
Fig. 33. V
CC
Supply Undervoltage Negative
Going Threshold vs. Temperature
0.0
3.0
6.0
9.0
12.0
15.0
18.0
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
V
CCUV+
(V)
Exp.
Fig. 34. V
CC
Supply Undervoltage Positive
Going Threshold vs. Temperature
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0.0
3.0
6.0
9.0
12.0
15.0
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
V
BSUV-
(V)
Exp.
Fig. 35. V
BS
Supply Undervoltage Negative
Going Threshold vs. Temperature
0.0
3.0
6.0
9.0
12.0
15.0
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
V
BSUV+
(V)
Exp.
Fig. 36. V
BS
Supply Undervoltage Positive
Going Threshold vs. Temperature
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
I
O+
(mA)
Exp.
p.
Fig. 37. Output High Short Circuit Pulsed
Current vs. Temperature
0.0
0.1
0.2
0.3
0.4
0.5
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
I
O-
(mA)
Exp.
Fig. 38. Output Low Short Circuit Pulsed Current
vs. Temperature
-14
-12
-10
-8
-6
-4
-2
0
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
Vs1_RST_domin (V)
Exp.
Fig. 39. Max -VS vs. Temperature
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Case Outlines
IR21364(S&J)PbF
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IR21364(S&J)PbF
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18
CARRIER TAPE DIMENSION FOR 28SOICW
Code Min Max Min Max
A 11.90 12.10 0.468 0.476
B 3.90 4.10 0.153 0.161
C 23.70 24.30 0.933 0.956
D 11.40 11.60 0.448 0.456
E 10.80 11.00 0.425 0.433
F 18.20 18.40 0.716 0.724
G 1.50 n/a 0.059 n/a
H 1.50 1.60 0.059 0.062
Metric Imperial
REEL DIMENSIONS FOR 28SOICW
Code Min Max Min Max
A 329.60 330.25 12.976 13.001
B 20.95 21.45 0.824 0.844
C 12.80 13.20 0.503 0.519
D 1.95 2.45 0.767 0.096
E 98.00 102.00 3.858 4.015
F n/a 30.40 n/a 1.196
G 26.50 29.10 1.04 1.145
H 24.40 26.40 0.96 1.039
Metric Imperial
E
F
A
C
D
G
A
BH
NOTE : CONTROLLING
DIM ENSION IN M M
LOADED TAPE FEED DIRECTION
A
H
F
E
G
D
B
C
IR21364(S&J)PbF
www.irf.com © 2009 International Rectifier
19
CARRIER TAPE DIMENSION FOR 44PLCC
Code Min Max Min Max
A 23.90 24.10 0.94 0.948
B 3.90 4.10 0.153 0.161
C 31.70 32.30 1.248 1.271
D 14.10 14.30 0.555 0.562
E 17.90 18.10 0.704 0.712
F 17.90 18.10 0.704 0.712
G 2.00 n/a 0.078 n/a
H 1.50 1.60 0.059 0.062
Metric Imperial
REEL DIMENSIONS FOR 44PLCC
Code Min Max Min Max
A 329.60 330.25 12.976 13.001
B 20.95 21.45 0.824 0.844
C 12.80 13.20 0.503 0.519
D 1.95 2.45 0.767 0.096
E 98.00 102.00 3.858 4.015
F n/a 38.4 n/a 1.511
G 34.7 35.8 1.366 1.409
H 32.6 33.1 1.283 1.303
Metric Imperial
E
F
A
C
D
G
A
BH
NOTE : CONTROLLING
DIM ENSION IN MM
LOADED TAPE FEED DIRECTION
A
H
F
E
G
D
B
C
IR21364(S&J)PbF
www.irf.com © 2009 International Rectifier
20
The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility
for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other
rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any patent or
patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This document
supersedes and replaces all information previously supplied.
For technical support, please contact IR’s Technical Assistance Center
http://www.irf.com/technical-info/
WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245
Tel: (310) 252-7105
ORDER INFORMATION
28-Lead SOIC IR21364SPbF
44-Lead PLCC IR21364JPbF
28-Lead SOIC Tape & Reel IR21364STRPbF
44-Lead PLCC Tape & Reel IR21364JTRPbF