74LVC2G34GF,132 - NXP Semiconductors

DATA SH EET

Product speciﬁcation

Supersedes data of 2003 Jul 25 2004 Sep 10

INTEGRATED CIRCUITS

74LVC2G34

Dual buffer gate

2004 Sep 10 2

Philips Semiconductors Product speciﬁcation

Dual buffer gate 74LVC2G34

FEATURES

•Wide supply voltage range from 1.65 V to 5.5 V

•5 V tolerant input/output for interfacing with 5 V logic

•High noise immunity

•Complies with JEDEC standard:

– JESD8-7 (1.65 V to 1.95 V)

– JESD8-5 (2.3 V to 2.7 V)

– JESD8B/JESD36 (2.7 V to 3.6 V).

•ESD protection:

– HBM EIA/JESD22-A114-B exceeds 2000 V

– MM EIA/JESD22-A115-A exceeds 200 V.

•±24 mA output drive (VCC = 3.0 V)

•CMOS low power consumption

•Latch-up performance exceeds 250 mA

•Direct interface with TTL levels

•Multiple package options

•Specified from −40 °C to +85 °C and

−40 °C to +125 °C.

DESCRIPTION

The 74LVC2G34 is a high-performance, low-power,

low-voltage, Si-gate CMOS device and superior to most

advanced CMOS compatible TTL families.

Inputs can be driven from either 3.3 V or 5 V devices.

These feature allows the use of these devices as

translators in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down

applications using Ioff. The Ioff circuitry disables the output,

preventing the damaging backflow current through the

device when it is powered down.

The 74LVC2G34 provides two buffers.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25°C.

Notes

1. CPD is used to determine the dynamic power dissipation (PDin µW).

PD=C

PD ×VCC2×fi×N+∑(CL×VCC2×fo) where:

fi= input frequency in MHz;

fo= output frequency in MHz;

CL= output load capacitance in pF;

VCC = supply voltage in Volts;

N = total load switching outputs;

∑(CL×VCC2×fo) = sum of outputs.

2. The condition is VI= GND to VCC.

SYMBOL PARAMETER CONDITIONS TYPICAL UNIT

tPHL/tPLH propagation delay input nA to output nY VCC = 1.8 V; CL= 30 pF; RL=1kΩ3.8 ns

VCC = 2.5 V; CL= 30 pF; RL= 500 Ω2.4 ns

VCC = 2.7 V; CL= 50 pF; RL= 500 Ω2.5 ns

VCC = 3.3 V; CL= 50 pF; RL= 500 Ω2.2 ns

VCC = 5.0 V; CL= 50 pF; RL= 500 Ω1.9 ns

CIinput capacitance 2.5 pF

CPD power dissipation capacitance VCC = 3.3 V; notes 1 and 2 20 pF

2004 Sep 10 3

Philips Semiconductors Product speciﬁcation

Dual buffer gate 74LVC2G34

FUNCTION TABLE

See note 1.

Note

1. H = HIGH voltage level;

L = LOW voltage level.

ORDERING INFORMATION

PINNING

INPUT OUTPUT

nA nY

TYPE NUMBER PACKAGE

TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE MARKING

74LVC2G34GW −40 °C to +125 °C 6 SC-88 plastic SOT363 YA

74LVC2G34GV −40 °C to +125 °C 6 SC-74 plastic SOT457 Y34

74LVC2G34GM −40 °C to +125 °C 6 XSON6 plastic SOT886 YA

PIN SYMBOL DESCRIPTION

1 1A data input

2 GND ground (0 V)

3 2A data input

4 2Y data output

CC supply voltage

6 1Y data output

1A 1Y

GND

2A 2Y

001aab676

VCC

Fig.1 Pin configuration SC-88 and SC-74.

GND

001aab677

VCC

Transparent top view

Fig.2 Pin configuration XSON6.

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Philips Semiconductors Product speciﬁcation

Dual buffer gate 74LVC2G34

handbook, halfpage

MNB063

1A 1Y16

2A 2Y34

Fig.3 Logic symbol.

handbook, halfpage

116

MNB064

314

Fig.4 Logic symbol (IEEE/IEC).

RECOMMENDED OPERATING CONDITIONS

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).

Notes

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VCC supply voltage 1.65 5.5 V

VIinput voltage 0 5.5 V

VOoutput voltage active mode 0 VCC V

VCC = 0 V; Power-down mode 0 5.5 V

Tamb operating ambient temperature −40 +125 °C

tr, tfinput rise and fall times VCC = 1.65 V to 2.7 V 0 20 ns/V

VCC = 2.7 V to 5.5 V 0 10 ns/V

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VCC supply voltage −0.5 +6.5 V

IIK input diode current VI<0V −−50 mA

VIinput voltage note 1 −0.5 +6.5 V

IOK output diode current VO>V

CC or VO<0V −±50 mA

VOoutput voltage active mode; notes 1 and 2 −0.5 VCC + 0.5 V

Power-down mode; notes 1 and 2 −0.5 +6.5 V

IOoutput source or sink current VO=0VtoV

CC −±50 mA

ICC, IGND VCC or GND current −±100 mA

Tstg storage temperature −65 +150 °C

Ptot power dissipation Tamb =−40 °C to +125 °C−300 mW

2004 Sep 10 5

Philips Semiconductors Product speciﬁcation

Dual buffer gate 74LVC2G34

DC CHARACTERISTICS

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT

OTHER VCC (V)

Tamb =−40 °C to +85 °C; note 1

VIH HIGH-level input voltage 1.65 to 1.95 0.65 ×VCC −− V

2.3 to 2.7 1.7 −− V

2.7 to 3.6 2.0 −− V

4.5 to 5.5 0.7 ×VCC −− V

VIL LOW-level input voltage 1.65 to 1.95 −−0.35 ×VCC V

2.3 to 2.7 −−0.7 V

2.7 to 3.6 −−0.8 V

4.5 to 5.5 −−0.3 ×VCC V

VOL LOW-level output voltage VI=V

IH or VIL

IO= 100 µA 1.65 to 5.5 −−0.1 V

IO= 4 mA 1.65 −−0.45 V

IO= 8 mA 2.3 −−0.3 V

IO= 12 mA 2.7 −−0.4 V

IO= 24 mA 3.0 −−0.55 V

IO= 32 mA 4.5 −−0.55 V

VOH HIGH-level output

voltage VI=V

IH or VIL

IO=−100 µA 1.65 to 5.5 VCC −0.1 −− V

IO=−4 mA 1.65 1.2 −− V

IO=−8 mA 2.3 1.9 −− V

IO=−12 mA 2.7 2.2 −− V

IO=−24 mA 3.0 2.3 −− V

IO=−32 mA 4.5 3.8 −− V

ILI input leakage current VI= 5.5 V or GND 5.5 −±0.1 ±5µA

Ioff power OFF leakage

current VIor VO= 5.5 V 0 −±0.1 ±10 µA

ICC quiescent supply current VI=V

CC or GND;

IO=0A 5.5 −0.1 10 µA

∆ICC additional quiescent

supply current per pin VI=V

CC −0.6 V;

IO=0A 2.3 to 5.5 −5 500 µA

2004 Sep 10 6

Philips Semiconductors Product speciﬁcation

Dual buffer gate 74LVC2G34

Note

1. All typical values are measured at VCC = 3.3 V and Tamb =25°C.

Tamb =−40 °C to +125 °C

VIH HIGH-level input voltage 1.65 to 1.95 0.65 ×VCC −− V

2.3 to 2.7 1.7 −− V

2.7 to 3.6 2.0 −− V

4.5 to 5.5 0.7 ×VCC −− V

VIL LOW-level input voltage 1.65 to 1.95 −−0.35 ×VCC V

2.3 to 2.7 −−0.7 V

2.7 to 3.6 −−0.8 V

4.5 to 5.5 −−0.3 ×VCC V

VOL LOW-level output voltage VI=V

IH or VIL

IO= 100 µA 1.65 to 5.5 −−0.1 V

IO= 4 mA 1.65 −−0.70 V

IO= 8 mA 2.3 −−0.45 V

IO= 12 mA 2.7 −−0.60 V

IO= 24 mA 3.0 −−0.80 V

IO= 32 mA 4.5 −−0.80 V

VOH HIGH-level output

voltage VI=V

IH or VIL

IO=−100 µA 1.65 to 5.5 VCC −0.1 −− V

IO=−4 mA 1.65 0.95 −− V

IO=−8 mA 2.3 1.7 −− V

IO=−12 mA 2.7 1.9 −− V

IO=−24 mA 3.0 2.0 −− V

IO=−32 mA 4.5 3.4 −− V

ILI input leakage current VI= 5.5 V or GND 5.5 −−±20 µA

Ioff power OFF leakage

current VIor VO= 5.5 V 0 −−±20 µA

ICC quiescent supply current VI=V

CC or GND;

IO=0A 5.5 −−40 µA

∆ICC additional quiescent

supply current per pin VI=V

CC −0.6 V;

IO=0A 2.3 to 5.5 −−5000 µA

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT

OTHER VCC (V)

2004 Sep 10 7

Philips Semiconductors Product speciﬁcation

Dual buffer gate 74LVC2G34

AC CHARACTERISTICS

GND = 0 V.

Note

1. All typical values are measured at VCC = 3.3 V and Tamb =25°C.

AC WAVEFORMS

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT

WAVEFORMS VCC (V)

Tamb =−40 °C to +85 °C; note 1

tPHL/tPLH propagation delay

input nA to output nY see Figs 5 and 6 1.65 to 1.95 1.0 3.8 8.6 ns

2.3 to 2.7 0.5 2.4 4.4 ns

2.7 0.5 2.5 5.0 ns

3.0 to 3.6 0.5 2.2 4.1 ns

4.5 to 5.5 0.5 1.9 3.2 ns

Tamb =−40 °C to +125 °C

tPHL/tPLH propagation delay

input nA to output nY see Figs 5 and 6 1.65 to 1.95 1.0 −10.8 ns

2.3 to 2.7 0.5 −5.5 ns

2.7 0.5 −6.3 ns

3.0 to 3.6 0.5 −5.1 ns

4.5 to 5.5 0.5 −4.0 ns

mnb072

nA input

nY output

tPLH tPHL

GND

VOH

VOL

Fig.5 Input nA to output nY propagation delay times.

VOL and VOH are typical output voltage drop that occur with the output

load.

VCC VMINPUT

VItr=t

1.65 V to 1.95 V 0.5 ×VCC VCC ≤2.0 ns

2.3 V to 2.7 V 0.5 ×VCC VCC ≤2.0 ns

2.7 V 1.5 V 2.7 V ≤2.5 ns

3.0 V to 3.6 V 1.5 V 2.7 V ≤2.5 ns

4.5 V to 5.5 V 0.5 ×VCC VCC ≤2.5 ns

2004 Sep 10 8

Philips Semiconductors Product speciﬁcation

Dual buffer gate 74LVC2G34

VEXT

VCC

VIVO

mna616

D.U.T.

PULSE

GENERATOR

Fig.6 Load circuitry for switching times.

Definitions for test circuit:

RL= Load resistor.

CL= Load capacitance including jig and probe capacitance.

RT= Termination resistance should be equal to the output impedance Zo of the pulse generator.

VCC VICLRLVEXT

tPLH/tPHL

1.65 V to 1.95 V VCC 30 pF 1 kΩopen

2.3 V to 2.7 V VCC 30 pF 500 Ωopen

2.7 V 2.7 V 50 pF 500 Ωopen

3.0 V to 3.6 V 2.7 V 50 pF 500 Ωopen

4.5 V to 5.5 V VCC 50 pF 500 Ωopen

2004 Sep 10 9

Philips Semiconductors Product speciﬁcation

Dual buffer gate 74LVC2G34

PACKAGE OUTLINES

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC EIAJ

SOT363 SC-88

pin 1

index A

detail X

0 1 2 mm

scale

132

Plastic surface mounted package; 6 leads SOT363

UNIT A1

max bpcDEe

HELpQywv

mm 0.1 0.30

0.20 2.2

1.8

0.25

0.10 1.35

1.15 0.65

1.3 2.2

2.0 0.2 0.10.2

DIMENSIONS (mm are the original dimensions)

0.45

0.15 0.25

0.15

1.1

0.8

97-02-28

2004 Sep 10 10

Philips Semiconductors Product speciﬁcation

Dual buffer gate 74LVC2G34

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC EIAJ

SOT457 SC-74

pin 1

index A

detail X

0 1 2 mm

scale

132

Plastic surface mounted package; 6 leads SOT457

UNIT A1bpcDEHELpQywv

mm 0.1

0.013 0.40

0.25 3.1

2.7

0.26

0.10 1.7

1.3

0.95 3.0

2.5 0.2 0.10.2

DIMENSIONS (mm are the original dimensions)

0.6

0.2 0.33

0.23

1.1

0.9

97-02-28

01-05-04

2004 Sep 10 11

Philips Semiconductors Product speciﬁcation

Dual buffer gate 74LVC2G34

terminal 1

index area

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT886 MO-252

SOT886

04-07-15

04-07-22

DIMENSIONS (mm are the original dimensions)

XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm

0 1 2 mm

scale

Notes

1. Including plating thickness.

2. Can be visible in some manufacturing processes.

UNIT

mm 0.25

0.17 1.5

1.4 0.35

0.27

max b E

1.05

0.95

Dee

0.40

0.32

0.50.6

A(1)

max

0.5 0.04

6×

(2)

4×

(2)

2004 Sep 10 12

Philips Semiconductors Product speciﬁcation

Dual buffer gate 74LVC2G34

DATA SHEET STATUS

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

LEVEL DATA SHEET

STATUS(1) PRODUCT

STATUS(2)(3) DEFINITION

I Objective data Development This data sheet contains data from the objective speciﬁcation for product

development. Philips Semiconductors reserves the right to change the

speciﬁcation in any manner without notice.

II Preliminary data Qualiﬁcation This data sheet contains data from the preliminary speciﬁcation.

Supplementary data will be published at a later date. Philips

Semiconductors reserves the right to change the speciﬁcation without

notice, in order to improve the design and supply the best possible

product.

III Product data Production This data sheet contains data from the product speciﬁcation. Philips

Semiconductors reserves the right to make changes at any time in order

to improve the design, manufacturing and supply. Relevant changes will

be communicated via a Customer Product/Process Change Notiﬁcation

(CPCN).

DEFINITIONS

Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the

same type number and title. For detailed information see

the relevant data sheet or data handbook.

Limiting values definition Limiting values given are in

accordance with the Absolute Maximum Rating System

(IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device.

These are stress ratings only and operation of the device

attheseorat anyother conditionsabove thosegiveninthe

Characteristics sections of the specification is not implied.

Exposure to limiting values for extended periods may

affect device reliability.

Application information  Applications that are

described herein for any of these products are for

illustrative purposes only. Philips Semiconductors make

norepresentationorwarrantythatsuchapplicationswillbe

suitable for the specified use without further testing or

modification.

DISCLAIMERS

Life support applications  These products are not

designed for use in life support appliances, devices, or

systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips

Semiconductorscustomersusingorsellingthese products

for use in such applications do so at their own risk and

agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Right to make changes  Philips Semiconductors

reserves the right to make changes in the products -

including circuits, standard cells, and/or software -

described or contained herein in order to improve design

and/or performance. When the product is in full production

(status ‘Production’), relevant changes will be

communicated via a Customer Product/Process Change

Notification (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these

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Printed in The Netherlands R20/02/pp13 Date of release: 2004 Sep 10 Document order number: 9397 750 13784