WM8532 w 24-bit, 192kHz Stereo DAC with 2Vrms Ground Referenced Line Output DESCRIPTION FEATURES The WM8532 is a stereo DAC with integral charge pump. This provides selectable 1VRMS or 2VRMS line driver outputs using a single 3.3V power supply rail. The device features ground-referenced outputs and the use of a DC servo to eliminate the need for line driving coupling capacitors and effectively eliminate power on pops and clicks. The device is controlled and configured via a hardware control interface. The device supports all common audio sampling rates between 8kHz and 192kHz using all common MCLK fs rates. The audio interface operates in slave mode. The WM8532 has a 3.3V tolerant digital interface, allowing logic up to 3.3V to be connected. The device is available in a 24pin QFN. High performance stereo DAC with ground referenced line driver Audio Performance 106dB SNR (`A-weighted') -87dB THD 120dB mute attenuation All common sample rates from 8kHz to 192kHz supported Hardware control mode Data formats: LJ, I2S Maximum 1mV DC offset on Line Outputs Pop/Click suppressed Power Up/Down Sequencer AVDD, LINEVDD and DBVDD can operate at +3.3V 10% allowing single supply 24-lead QFN package Operating temperature range: -40C to 85C APPLICATIONS Consumer digital audio applications requiring 2Vrms output Games Consoles Set Top Box A/V Receivers DVD Players Digital TV BLOCK DIAGRAM WOLFSON MICROELECTRONICS plc Production Data, June 2014, Rev 4.2 Copyright 2014 Wolfson Microelectronics plc WM8532 Production Data TABLE OF CONTENTS DESCRIPTION ....................................................................................................... 1 FEATURES ............................................................................................................ 1 APPLICATIONS..................................................................................................... 1 BLOCK DIAGRAM ................................................................................................ 1 TABLE OF CONTENTS ......................................................................................... 2 PIN CONFIGURATION .......................................................................................... 3 ORDERING INFORMATION .................................................................................. 3 PIN DESCRIPTION ................................................................................................ 4 ABSOLUTE MAXIMUM RATINGS ........................................................................ 5 RECOMMENDED OPERATING CONDITIONS ..................................................... 5 ELECTRICAL CHARACTERISTICS ..................................................................... 6 TERMINOLOGY ................................................................................................................ 6 POWER CONSUMPTION MEASUREMENTS....................................................... 7 SIGNAL TIMING REQUIREMENTS ...................................................................... 8 SYSTEM CLOCK TIMING ................................................................................................. 8 AUDIO INTERFACE TIMING - SLAVE MODE ................................................................ 9 POWER ON RESET CIRCUIT ........................................................................................ 10 DEVICE DESCRIPTION ...................................................................................... 12 INTRODUCTION ............................................................................................................. 12 DIGITAL AUDIO INTERFACE......................................................................................... 12 DIGITAL AUDIO DATA SAMPLING RATES .................................................................. 13 HARDWARE CONTROL INTERFACE ........................................................................... 14 POWER DOMAINS ......................................................................................................... 16 DIGITAL DE-EMPHASIS CHARACTERISTICS .................................................. 17 APPLICATIONS INFORMATION ........................................................................ 18 RECOMMENDED EXTERNAL COMPONENTS ............................................................ 18 RECOMMENDED ANALOGUE LOW PASS FILTER..................................................... 18 RELEVANT APPLICATION NOTES ............................................................................... 19 PACKAGE DIMENSIONS .................................................................................... 20 IMPORTANT NOTICE ......................................................................................... 21 ADDRESS ....................................................................................................................... 21 REVISION HISTORY ........................................................................................... 22 w PD, Rev 4.2, June 2014 2 WM8532 Production Data PIN CONFIGURATION 24-LEAD QFN (TOP VIEW) ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE WM8532CGEFL/V -40C to +85C 24-lead QFN MSL3 260oC WM8532CGEFL/RV -40C to +85C 24-lead QFN MSL3 260oC (pb-free) (pb-free, tape and reel) Note: Reel quantity = 3,500 w PD, Rev 4.2, June 2014 3 WM8532 Production Data PIN DESCRIPTION PIN NO NAME TYPE 1 BCLK Digital In Digital audio interface bit clock 2 MCLK Digital In Master clock 3 DBVDD Supply Digital Buffer Supply 4 NC 5 NC 6 LINEVDD Supply Charge Pump supply 7 NC 8 NC 9 CPCA Analogue Out 10 LINEGND Supply 11 CPCB Analogue Out Charge Pump fly back capacitor pin 12 CPVOUTN Analogue Out Charge Pump negative rail decoupling pin 13 LINEVOUTR Analogue Out Right line output 14 LINEREF Supply 15 LINEVOUTL Analogue Out 16 AGND Supply Analogue ground 17 AVDD Supply Analogue supply 18 VMID Analogue Out 19 MUTE Digital In 20 AMPLSEL Digital In 21 DEEMPH Digital In 22 AIFMODE Digital In 23 LRCLK Digital In Digital audio interface left/right clock 24 DACDAT Digital In Digital audio interface data input w DESCRIPTION Charge Pump fly back capacitor pin Charge Pump ground Ground reference for line output Left line output Analogue midrail decoupling pin 0 = Mute enabled 1 = Mute disabled 0 = 1VRMS line output 1 = 2VRMS line output 0 = De-emphasis filter disabled 1 = De-emphasis filter enabled 1 = 24-bit Left Justified 0 = 24-bit I2S PD, Rev 4.2, June 2014 4 WM8532 Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. MIN MAX AVDD, LINEVDD, DBVDD CONDITION -0.3V +4.5V Voltage range digital inputs LINEGND -0.3V DBVDD +0.3V AGND -0.3V AVDD +0.3V Temperature range, TA -40C +125C Storage temperature after soldering -65C +150C Voltage range analogue inputs Notes: 1. Analogue grounds must always be within 0.3V of each other. 2. LINEVDD and AVDD must always be within 0.3V of each other. RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL Analogue supply range AVDD, LINEVDD Ground AGND, LINEGND Digital Buffer supply range w DBVDD TEST CONDITIONS MIN TYP MAX UNIT 2.97 3.3 3.63 V 0 0.95 V 3.63 V PD, Rev 4.2, June 2014 5 WM8532 Production Data ELECTRICAL CHARACTERISTICS Test Conditions LINEVDD=AVDD=DBVDD=3.3V, LINEGND=AGND=0V, TA=+25C, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, AMPLSEL=1, unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT 0dBFS, AMPLSEL=1 2.00xAVDD 3.3 2.04xAVDD 3.3 2.06xAVDD 3.3 Vrms 0dBFS, AMPLSEL=0 1.00xAVDD 3.3 1.02xAVDD 3.3 1.03xAVDD 3.3 Vrms Analogue Output Levels Output Level Load Impedance 1 Load Capacitance k No external RC filter 330 pF With filter shown in Figure 17 1 F DAC Performance Signal to Noise Ratio SNR RL = 10k 106 dB 104 dB 104 dB A-weighted RL = 10k Un-weighted Dynamic Range DNR RL = 10k A-weighted Total Harmonic Distortion AVDD + LINEVDD THD 0dBFS -87 dB PSRR 100Hz 54 dB Power Supply Rejection Ratio Channel Separation 1kHz 54 dB 20kHz 50 dB 1kHz 100 dB 20Hz to 20kHz 93 0 degrees 0.1 dB System Absolute Phase Channel Level Matching Mute Attenuation dB -120 DC Offset at LINEVOUTL and LINEVOUTR -1 0 dB 1 mV Digital Logic Levels Input HIGH Level Input LOW Level VIH VIL 3.3V < DBVDD < 1.35V 0.7 DBVDD V 1.35 < DBVDD < 0.95V 0.9 DBVDD V 3.3V < DBVDD < 1.35V 0.3 DBVDD 1.35 < DBVDD < 0.95V 0.1 DBVDD Input Capacitance Input Leakage 10 -0.9 V V pF 0.9 A TERMINOLOGY 1. Signal-to-Noise Ratio (dB) - SNR is a measure of the difference in level between the maximum theoretical full scale output signal and the output with no input signal applied. 2. Total Harmonic Distortion (dB) - THD is the level of the rms value of the sum of harmonic distortion products relative to the amplitude of the measured output signal. 3. All performance measurements carried out with 20kHz low pass filter, and where noted an A-weighted filter. Failure to use such a filter will result in higher THD and lower SNR readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 4. Mute Attenuation - This is a measure of the difference in level between the full scale output signal and the output with mute applied. w PD, Rev 4.2, June 2014 6 WM8532 Production Data POWER CONSUMPTION MEASUREMENTS Test Conditions LINEVDD=AVDD=DBVDD=3.3V, LINEGND=AGND=0V, AMPLSEL=1, TA=+25C, Slave Mode, quiescent (no signal) TEST CONDITIONS Off IAVDD ILINEVDD DBVDD TOTAL (mA) (mA) (mA) (mA) No clocks applied 0.8 1.0 0.0 1.8 Standby MUTE = 0 0.2 2.1 0.02 2.32 Playback MUTE = 1 4.7 6.0 0.02 10.72 Standby MUTE = 0 0.2 2.7 0.03 2.93 Playback MUTE = 1 5.2 8.5 0.03 13.73 Standby MUTE = 0 0.2 2.7 0.04 2.94 Playback MUTE = 1 5.2 8.4 0.04 13.64 fs=48kHz, MCLK=256fs fs=96kHz, MCLK=256fs fs=192kHz, MCLK=128fs w PD, Rev 4.2, June 2014 7 WM8532 Production Data SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING Figure 1 System Clock Timing Requirements Test Conditions LINEVDD=AVDD=2.97~3.63V, DBVDD=0.95~3.63V, LINEGND=AGND=0V, TA=+25C PARAMETER SYMBOL MIN TYP MAX UNIT MCLK cycle time tMCLKY 27 MCLK high time 500 ns tMCLKH 11 ns MCLK low time tMCLKL 11 ns Master Clock Timing Information MCLK duty cycle (tMCLKH/tMCLKL) MCLK period jitter w 40:60 60:40 % 200 ps PD, Rev 4.2, June 2014 8 WM8532 Production Data AUDIO INTERFACE TIMING - SLAVE MODE Figure 2 Digital Audio Data Timing - Slave Mode Test Conditions LINEVDD=AVDD=2.97~3.63V, DBVDD=0.95~3.63V LINEGND=AGND=0V, TA=+25C, Slave Mode PARAMETER SYMBOL MIN TYP MAX UNIT BCLK cycle time tBCY 27 BCLK pulse width high tBCH 11 ns BCLK pulse width low tBCL 11 ns LRCLK set-up time to BCLK rising edge tLRSU 7 ns LRCLK hold time from BCLK rising edge tLRH 5 ns DACDAT hold time from LRCLK rising edge tDH 5 ns DACDAT set-up time to BCLK rising edge tDS 7 ns Audio Data Input Timing Information ns Table 1 Slave Mode Audio Interface Timing Note: BCLK period should always be greater than or equal to MCLK period. w PD, Rev 4.2, June 2014 9 WM8532 Production Data POWER ON RESET CIRCUIT Figure 3 Internal Power on Reset Circuit Schematic The WM8532 includes an internal Power-On-Reset circuit, as shown in Figure 3, which is used to reset the DAC digital logic into a default state after power up. The POR circuit is powered by AVDD and has as its inputs VMID and LINEVDD. It asserts POR low if VMID or LINEVDD are below a minimum threshold. Figure 4 Typical Power Timing Requirements Figure 4 shows a typical power-up sequence where LINEVDD comes up with AVDD. When AVDD goes above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee POR is asserted low and the chip is held in reset. In this condition, all digital inputs to the hardware control interface are ignored. After VMID rises to Vpord_hi and AVDD rises to Vpora_hi, POR is released high and access to the control interface and audio interface may take place. This assumes that DBVDD is at a level within the recommended operating conditions. w PD, Rev 4.2, June 2014 10 WM8532 Production Data On power down, PORB is asserted low whenever LINEVDD or AVDD drop below the minimum threshold Vpora_low. Test Conditions LINEVDD = AVDD = DBVDD = 3.3V AGND = LINEGND = 0V, TA = +25oC PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Power Supply Input Timing Information VDD level to POR defined (LINEVDD/AVDD rising) Vpora Measured from LINEGND 158 mV VDD level to POR rising edge (VMID rising) Vpord_hi Measured from LINEGND 0.63 0.8 1 V VDD level to POR rising edge (LINEVDD/AVDD rising) Vpora_hi Measured from LINEGND 1.44 1.8 2.18 V VDD level to POR falling edge (LINEVDD/AVDD falling) Vpora_lo Measured from LINEGND 0.96 1.46 1.97 V Table 2 Power on Reset Note: All values are simulated results w PD, Rev 4.2, June 2014 11 WM8532 Production Data DEVICE DESCRIPTION INTRODUCTION The WM8532 provides high fidelity, selectable 1VRMS or 2VRMS ground referenced stereo line output from a single supply line with minimal external components. The integrated DC servo eliminates the requirement for external mute circuitry by minimising DC transients at the output during power up/down. The device is well-suited to both stereo and multi-channel systems. The device supports all common audio sampling rates between 8kHz and 192kHz using common MCLK fs rates, with a slave mode audio interface. The WM8532 supports a simple hardware control mode, allowing access to 24-bit LJ and I2S audio interface formats, mute control, de-emphasis filter and output level select. An internal audio interface clock monitor automatically mutes the DAC output if the BCLK is interrupted. DIGITAL AUDIO INTERFACE The digital audio interface is used for inputting audio data to the WM8532. The digital audio interface uses three pins: DACDAT: DAC data input LRCLK: Left/Right data alignment clock BCLK: Bit clock, for synchronisation The WM8532 digital audio interface operates as a slave as shown in Figure 5. Figure 5 Slave Mode INTERFACE FORMATS The WM8532 supports two different audio data formats: Left justified I2 S Both of these modes are MSB first. They are described in Audio Data Formats on page 13. Refer to the "Electrical Characteristics" section for timing information. w PD, Rev 4.2, June 2014 12 WM8532 Production Data AUDIO DATA FORMATS In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition. Figure 6 Left Justified Audio Interface (assuming n-bit word length) In I2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next. Figure 7 I2S Justified Audio Interface (assuming n-bit word length) DIGITAL AUDIO DATA SAMPLING RATES The external master clock is applied directly to the MCLK input pin. In a system where there are a number of possible sources for the reference clock, it is recommended that the clock source with the lowest jitter be used for the master clock to optimise the performance of the WM8532. The WM8532 has a detection circuit that automatically determines the relationship between the master clock frequency (MCLK) and the sampling rate (LRCLK), to within 32 system clock periods. The MCLK must be synchronised with the LRCLK, although the device is tolerant of phase variations or jitter on the MCLK. The DAC supports MCLK to LRCLK ratios of 128fs to 1152fs and sampling rates of 8kHz to 192kHz. w PD, Rev 4.2, June 2014 13 WM8532 Production Data Table 3 shows typical master clock frequencies and sampling rates supported by the WM8532 DAC. MASTER CLOCK FREQUENCY (MHz) Sampling Rate LRCLK 128fs 192fs 256fs 384fs 512fs 768fs 8kHz Unavailable Unavailable 2.048 3.072 4.096 6.144 1152fs 9.216 32kHz Unavailable Unavailable 8.192 12.288 16.384 24.576 36.864 Unavailable 44.1kHz Unavailable Unavailable 11.2896 16.9344 22.5792 33.8688 48kHz Unavailable Unavailable 12.288 18.432 24.576 36.864 Unavailable 88.2kHz 11.2896 16.9344 22.5792 33.8688 Unavailable Unavailable Unavailable Unavailable 96kHz 12.288 18.432 24.576 36.864 Unavailable Unavailable 176.4kHz 22.5792 33.8688 Unavailable Unavailable Unavailable Unavailable Unavailable 192kHz 24.576 36.864 Unavailable Unavailable Unavailable Unavailable Unavailable Table 3 MCLK Frequencies and Audio Sample Rates HARDWARE CONTROL INTERFACE The device is configured according to logic levels applied to the hardware control pins as described in Table 4. PIN NAME MUTE PIN NUMBER 19 DESCRIPTION Mute Control 0 = Mute 1 = Normal operation AMPLSEL 20 Line Out Amplitude Level 1 = 2VRMS 0 = 1VRMS DEEMPH 21 Audio Interface Mode 1 = De-emphasis filter active 0 = De-emphasis filter inactive AIFMODE 22 Audio Interface Mode 1 = 24-bit LJ 0 = 24-bit I2S Table 4 Hardware Control Pin Configuration MUTE The MUTE pin controls the DAC mute to both left and right channels. If data is passing through the device when the mute is asserted, a softmute is applied to ramp the signal down in 944 samples. If no data is applied when the MUTE pin is pulled low, then the mute will be applied in one step after 4 samples. When the mute is de-asserted the signal returns to full scale in one step. AMPLSEL The analogue line out full-scale amplitude can be selected to 1VRMS or 2VRMS. When 2VRMS is selected, the full-scale output voltage at the LINEVOUTL/R pins is approximately 2VRMS. When 1VRMS is selected, the full-scale output voltage at the LINEVOUTL/R pins is approximately 1VRMS. See the Electrical Characteristics table for the full specifications of the full-scale output voltage. w PD, Rev 4.2, June 2014 14 WM8532 Production Data DE-EMPHASIS A digital de-emphasis filter may be applied to the DAC output when the sampling frequency is 44.1kHz. Operation at 48kHz and 32kHz is also possible, but with an increase in the error from the ideal response. Details of the de-emphasis filter characteristic for 32kHz, 44.1kHz and 48kHz can be seen in Figure 10 to Figure 15. POWER UP AND DOWN CONTROL The MCLK, BCLK and MUTE pins are monitored to control how the device powers up or down, and this is summarised in Figure 8 below. Figure 8 Hardware Power Sequence Diagram Off to Enable To power up the device to enabled, start MCLK and BCLK and set MUTE = 1. Off to Standby To power up the device to standby, start MCLK and BCLK and set MUTE = 0. Once the device is in standby mode, BCLK can be disabled and the device will remain in standby mode. Standby to Enable To transition from the standby state to the enabled state, set the MUTE pin to logic 1 and start BCLK. Enable to Standby To power down to a standby state leaving the charge pump running, either set the MUTE pin to logic 0 or stop BCLK. MCLK must continue to run in these situations. The device will automatically mute and power down quietly in either case. Enable to Off To power down the device completely, stop MCLK at any time. It is recommended that the device is placed into standby mode as described above before stopping MCLK to allow a quiet shutdown. w PD, Rev 4.2, June 2014 15 WM8532 Production Data POWER DOMAINS Figure 9 Power Domain Diagram POWER DOMAIN DAC Power Supplies 3.3V 10% NAME AVDD BLOCKS USING THIS DOMAIN Line Driver DOMAIN DESCRIPTION Analogue Supply DAC DC Servo 3.3V 10% LINEVDD Charge Pump Analogue Supply Digital LDO Digital Pad buffers 0.95V ~ 3.3V +10% DBVDD Digital Input Pins Digital Buffer Supply Internally Generated Power Supplies and References 1.65V 10% VMID DAC, LDO Ext decoupled resistor string -3.3V 10% Charge pump generated voltage CPVOUTN Line Driver Table 5 Power Domains w PD, Rev 4.2, June 2014 16 WM8532 Production Data DIGITAL DE-EMPHASIS CHARACTERISTICS 0 1 0.5 -2 Response (dB) Response (dB) 0 -4 -6 -0.5 -1 -1.5 -2 -8 -2.5 -10 -3 0 2 4 6 8 10 Frequency (kHz) 12 14 16 0 2 4 6 8 10 Frequency (kHz) Figure 10 De-Emphasis Frequency Response (32kHz) Figure 11 De-Emphasis Error (32kHz) Figure 12 De-Emphasis Frequency Response (44.1kHz) Figure 13 De-Emphasis Error (44.1kHz) 0 12 14 16 1 0.8 -2 0.6 Response (dB) Response (dB) 0.4 -4 -6 0.2 0 -0.2 -0.4 -8 -0.6 -0.8 -10 -1 0 5 10 15 Frequency (kHz) 20 Figure 14 De-Emphasis Frequency Response (48kHz) w 0 5 10 15 Frequency (kHz) 20 Figure 15 De-Emphasis Error (48kHz) PD, Rev 4.2, June 2014 17 WM8532 Production Data APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 16 Recommended External Components Notes: 1. Wolfson recommend using a single, common ground plane. Where this is not possible, care should be taken to optimise split ground configuration for audio performance. 2. Charge Pump fly-back capacitor C5 should be placed as close to WM8532 as possible, followed by Charge Pump decoupling capacitor C1, then LINEVDD and VMID decoupling capacitors. 3. If VMID is decoupled to AVDD, the capacitance value of the decoupling capacitor should be chosen so that VMID will collapse at the same rate or quicker than AVDD at power off 4. Capacitor types should be chosen carefully. Capacitors with very low ESR are recommended for optimum performance. RECOMMENDED ANALOGUE LOW PASS FILTER Figure 17 Recommended Analogue Low Pass Filter (one channel shown) An external single-pole RC filter is recommended if the device is driving a wideband amplifier. Other filter architectures may provide equally good results. The filter shown in Figure 17 has a -3dB cut-off at 105.26kHz and a droop of 0.15dB at 20kHz. The typical output from the WM8532 is 2.04Vrms - when a 10k load is placed at the output of this recommended filter the amplitude across this load is 1.93Vrms. w PD, Rev 4.2, June 2014 18 WM8532 Production Data RELEVANT APPLICATION NOTES The following application notes, available from www.wolfsonmicro.com, may provide additional guidance for use of the WM8532. DEVICE PERFORMANCE: WAN0223 - WM8532 Power Up/Down and mute timing WAN0129 - Decoupling and Layout Methodology for Wolfson DACs, ADCs and CODECs GENERAL: WAN0161 - Electronic End-Product Design for ESD w PD, Rev 4.2, June 2014 19 WM8532 Production Data PACKAGE DIMENSIONS FL: 24 PIN QFN PLASTIC PACKAGE 4 X 4 X 0.75 mm BODY, 0.50 mm LEAD PITCH DM070.A D D2 19 24 L 1 18 EXPOSED GROUND 6 PADDLE A INDEX AREA (D/2 X E/2) 4 E2 13 E 6 2X 7 b e 1 bbb M C A B 2X aaa C aaa C TOP VIEW BOTTOM VIEW ccc C A3 A 0.08 C C 5 A1 SIDE VIEW DETAIL 1 SEATING PLANE A3 G b Exposed lead DETAIL 1 Symbols A A1 A3 b D D2 E E2 e G L aaa bbb ccc REF: 2.4 NOM 0.75 0.35 0.203 REF 0.25 4.00 BSC 2.50 4.00 BSC 2.50 0.35 0.50 BSC 0.65 0.40 MIN 0.70 0 0.20 2.4 MAX 0.80 0.05 NOTE 0.30 1 2.6 2 2.6 2 0.45 Tolerances of Form and Position 0.1 0.1 0.1 JEDEC, MO-220 NOTES: 1. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.2 mm AND 0.30 mm FROM TERMINAL TIP. 2. FALLS WITHIN JEDEC, MO-220. 3. ALL DIMENSIONS ARE IN MILLIMETRES. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JEDEC 95-1 SPP-002. 5. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 6. REFER TO APPLICATIONS NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING . 7. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. w PD, Rev 4.2, June 2014 20 Production Data WM8532 IMPORTANT NOTICE Wolfson Microelectronics plc ("Wolfson") products and services are sold subject to Wolfson's terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. Wolfson's products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer's own risk. Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party's products or services does not constitute Wolfson's approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson's standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person's own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com w PD, Rev 4.2, June 2014 21 WM8532 Production Data REVISION HISTORY DATE REV ORIGINATOR 18/08/10 4.0 BT Status updated to Production Data CHANGES BT Added LINEREF pin to Block Diagram, p1 BT Added split VIL/VIH for two distinct DBVDD operating regions, p6 14/05/12 4.1 JMacD Order codes updated from WM8532GEFL/V and WM8532GEFL/RV to WM8532CGEFL/V and WM8532CGEFL/RV to reflect change to copper wire bonding. 09/06/14 4.2 JMacD Confidential removed. w PD, Rev 4.2, June 2014 22 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Cirrus Logic: WM8532CGEFL/RV