LT3083MPQ#TR - Linear Technology Corporation

LT3083

3083fa

TYPICAL APPLICATION

DESCRIPTION

Adjustable 3A

Single Resistor Low

Dropout Regulator

The LT

3083 is a 3A low dropout linear regulator that can

be paralleled to increase output current or spread heat on

surface mounted boards. Architected as a precision current

source and voltage follower, this new regulator ﬁnds use

in many applications requiring high current, adjustability

to zero, and no heat sink. The device also brings out the

collector of the pass transistor to allow low dropout opera-

tion—down to 310mV—when used with multiple supplies.

A key feature of the LT3083 is the capability to supply a

wide output voltage range. By using a reference current

through a single resistor, the output voltage is programmed

to any level between zero and 23V (DD-PAK and TO-220

packages). The LT3083 is stable with 10µF of capacitance

on the output, and the IC is stable with small ceramic ca-

pacitors that do not require additional ESR as is common

with other regulators.

Internal protection circuitry includes current limiting and

thermal limiting. The LT3083 is offered in the 16-lead

TSSOP (with an exposed pad for better thermal character-

istics), 12-lead 4mm × 4mm DFN (also with an exposed

pad), 5-lead TO-220, and 5-lead surface mount DD-PAK

packages.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

1.5V to 0.9V at 3A Supply (Using 3.3V VCONTROL)

FEATURES

APPLICATIONS

n Outputs May be Paralleled for Higher Current and

Heat Spreading

n Output Current: 3A

n Single Resistor Programs Output Voltage

n 50µA Set Pin Current: 1% Initial Accuracy

n Output Adjustable to 0V

n Low Output Noise: 40µVRMS (10Hz to 100kHz)

n Wide Input Voltage Range: 1.2V to 23V

(DD-Pak and TO-220 Packages)

n Low Dropout Voltage: 310mV

n <1mV Load Regulation

n <0.001%/V Line Regulation

n Minimum Load Current: 1mA

n Stable with Minimum 10µF Ceramic Capacitor

n Current Limit with Foldback and Overtemperature

Protection

n Available in 16-Lead TSSOP, 12-Lead 4mm × 4mm

DFN, 5-Lead TO-220 and 5-Lead Surface Mount

DD-PAK Packages

n High Current All Surface Mount Supply

n High Efﬁciency Linear Regulator

n Post Regulator for Switching Supplies

n Low Parts Count Variable Voltage Supply

n Low Output Voltage Power Supplies

Set Pin Current Distribution

49 51

3083 TA01b

49.5 50 50.5

SET PIN CURRENT DISTRIBUTION (µA)

N = 1052

3083 TA01a

VCONTROL

OUTIN LT3083

SET RMIN

909Ω

10µF

VOUT = 0.9V

IMAX = 3A

VIN

1.5V

4.7µF

VCONTROL

3.3V

RSET

18.2k

0.1µF

*OPTIONAL FOR

MINIMUM 1mA LOAD

REQUIREMENT

LT3083

3083fa

ABSOLUTE MAXIMUM RATINGS

CONTROL Pin Voltage .............................................±28V

IN Pin Voltage (T5, Q Packages) ....................18V, –0.3V

No Overload or Short-Circuit .....................23V, –0.3V

IN Pin Voltage (DF, FE Packages) .....................8V, –0.3V

No Overload or Short-Circuit .....................14V, –0.3V

SET Pin Current (Note 7) .....................................±25mA

SET Pin Voltage (Relative to OUT) .......................... ±10V

(Note 1) All Voltages Relative to VOUT

TOP VIEW

OUT

DF PACKAGE

12-LEAD (4mm × 4mm) PLASTIC DFN

1IN

VCONTROL

OUT

SET 67

TJMAX = 125°C, θJA = 37°C/W, θJC = 8°C/W

EXPOSED PAD (PIN 13) IS OUT, MUST BE SOLDERED TO PCB

FE PACKAGE

16-LEAD PLASTIC TSSOP

TOP VIEW

OUT

SET

OUT

VCONTROL

OUT

TJMAX = 125°C, θJA = 25°C/W, θJC = 8°C/W

EXPOSED PAD (PIN 17) IS OUT, MUST BE SOLDERED TO PCB

Q PACKAGE

5-LEAD PLASTIC DD-PAK

TAB IS

OUT

FRONT VIEW

VCONTROL

OUT

SET

TJMAX = 125°C, θJA = 15°C/W, θJC = 3°C/W

T PACKAGE

5-LEAD PLASTIC TO-220

VCONTROL

OUT

SET

FRONT VIEW

TAB IS

OUT

TJMAX = 125°C, θJA = 40°C/W, θJC = 3°C/W

PIN CONFIGURATION

Output Short-Circuit Duration .......................... Indeﬁnite

Operating Junction Temperature Range (Notes 2, 10)

E-, I-grades ........................................ –40°C to 125°C

MP-grade ........................................... –55°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

T, Q, FE Packages Only .....................................300°C

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LT3083EDF#PBF LT3083EDF#TRPBF 3083 12-Lead (4mm × 4mm) Plastic DFN –40°C to 125°C

LT3083EFE#PBF LT3083EFE#TRPBF 3083FE 16-Lead Plastic TSSOP –40°C to 125°C

LT3083EQ#PBF LT3083EQ#TRPBF LT3083Q 5-Lead Plastic DD-PAK –40°C to 125°C

LT3083ET#PBF LT3083ET#TRPBF LT3083T 5-Lead Plastic TO-220 –40°C to 125°C

LT3083IDF#PBF LT3083IDF#TRPBF 3083 12-Lead (4mm × 4mm) Plastic DFN –40°C to 125°C

LT3083IFE#PBF LT3083IFE#TRPBF 3083FE 16-Lead Plastic TSSOP –40°C to 125°C

ORDER INFORMATION

LT3083

3083fa

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LT3083IQ#PBF LT3083IQ#TRPBF LT3083Q 5-Lead Plastic DD-PAK –40°C to 125°C

LT3083IT#PBF LT3083IT#TRPBF LT3083T 5-Lead Plastic TO-220 –40°C to 125°C

LT3083MPDF#PBF LT3083MPDF#TRPBF 3083 12-Lead (4mm × 4mm) Plastic DFN –55°C to 125°C

LT3083MPFE#PBF LT3083MPFE#TRPBF 3083FE 16-Lead Plastic TSSOP –55°C to 125°C

LT3083MPQ#PBF LT3083MPQ#TRPBF LT3083Q 5-Lead Plastic DD-PAK –55°C to 125°C

LT3083MPT#PBF LT3083MPT#TRPBF LT3083T 5-Lead Plastic TO-220 –55°C to 125°C

LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LT3083EDF LT3083EDF#TR 3083 12-Lead (4mm × 4mm) Plastic DFN –40°C to 125°C

LT3083EFE LT3083EFE#TR 3083FE 16-Lead Plastic TSSOP –40°C to 125°C

LT3083EQ LT3083EQ#TR LT3083Q 5-Lead Plastic DD-PAK –40°C to 125°C

LT3083ET LT3083ET#TR LT3083T 5-Lead Plastic TO-220 –40°C to 125°C

LT3083IDF LT3083IDF#TR 3083 12-Lead (4mm × 4mm) Plastic DFN –40°C to 125°C

LT3083IFE LT3083IFE#TR 3083FE 16-Lead Plastic TSSOP –40°C to 125°C

LT3083IQ LT3083IQ#TR LT3083Q 5-Lead Plastic DD-PAK –40°C to 125°C

LT3083IT LT3083IT#TR LT3083T 5-Lead Plastic TO-220 –40°C to 125°C

LT3083MPDF LT3083MPDF#TR 3083 12-Lead (4mm × 4mm) Plastic DFN –55°C to 125°C

LT3083MPFE LT3083MPFE#TR 3083FE 16-Lead Plastic TSSOP –55°C to 125°C

LT3083MPQ LT3083MPQ#TR LT3083Q 5-Lead Plastic DD-PAK –55°C to 125°C

LT3083MPT LT3083MPT#TR LT3083T 5-Lead Plastic TO-220 –55°C to 125°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA = 25°C (Note 2).

ELECTRICAL CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX UNITS

SET Pin Current ISET VIN = 1V, VCONTROL = 2V, ILOAD = 1mA, TJ = 25°C

VIN ≥ 1V, VCONTROL ≥ 2V, 5mA ≤ ILOAD ≤ 3A (Note 9)

49.5

50.5

µA

Output Offset Voltage (VOUT – VSET) VOS

VIN = 1V, VCONTROL = 2V, ILOAD = 1mA

DF, FE Packages

–3

–4

T, Q Packages

–4

–6

Load Regulation (DF, FE Packages) ∆ISET

∆VOS

∆ILOAD = 1mA to 3A

∆ILOAD = 5mA to 3A (Note 8)

–10

–0.4

–1

Load Regulation (T, Q Packages) ∆ISET

∆VOS

∆ILOAD = 1mA to 3A

∆ILOAD = 5mA to 3A (Note 8)

–10

–0.7

–4

Line Regulation (DF, FE Packages) ∆ISET

∆VOS

∆VIN = 1V to 14V, ∆VCONTROL = 2V to 25V, ILOAD = 1mA

0.1

0.002

0.01

nA/V

mV/V

Line Regulation (T, Q Packages) ∆ISET

∆VOS

∆VIN = 1V to 23V, ∆VCONTROL = 2V to 25V, ILOAD = 1mA

0.1

0.002

0.01

nA/V

mV/V

Minimum Load Current (Notes 3, 9) VIN = 1V, VCONTROL = 2V

VIN = 14V (DF/FE) or 23V (T/Q), VCONTROL = 25V

350 500

µA

LT3083

3083fa

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA = 25°C (Note 2).

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: Unless otherwise speciﬁed, all voltages are with respect to VOUT.

The LT3083 is tested and speciﬁed under pulse load conditions such that

TJ ≅ TA. The LT3083E is 100% tested at TA = 25°C. Performance of the

LT3083E over the full –40°C to 125°C operating junction temperature

range is assured by design, characterization, and correlation with

statistical process controls. The LT3083I regulators are guaranteed

over the full –40°C to 125°C operating junction temperature range. The

LT3083MP is 100% tested and guaranteed over the –55°C to 125°C

operating junction temperature range.

Note 3: Minimum load current is equivalent to the quiescent current of

the part. Since all quiescent and drive current is delivered to the output

of the part, the minimum load current is the minimum current required to

maintain regulation.

Note 4: For the LT3083, dropout is caused by either minimum control

voltage (VCONTROL) or minimum input voltage (VIN). Both parameters are

speciﬁed with respect to the output voltage. The speciﬁcations represent

the minimum input-to-output differential voltage required to maintain

regulation.

Note 5: The VCONTROL pin current is the drive current required for the

output transistor. This current will track output current with roughly a 1:60

ratio. The minimum value is equal to the quiescent current of the device.

Note 6: Output noise is lowered by adding a small capacitor across the

voltage setting resistor. Adding this capacitor bypasses the voltage setting

resistor shot noise and reference current noise; output noise is then equal

to error ampliﬁer noise (see the Applications Information section).

Note 7: The SET pin is clamped to the output with diodes through 1k

resistors. These resistors and diodes will only carry current under

transient overloads.

Note 8: Load regulation is Kelvin sensed at the package.

Note 9: Current limit includes foldback protection circuitry. Current limit

decreases at higher input-to-output differential voltages.

Note 10: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed the maximum operating junction temperature

when overtemperature protection is active. Overtemperature protection

(thermal limit) is typically active at junction temperatures of 165°C.

Continuous operation above the speciﬁed maximum operating junction

temperature may impair device reliability.

PARAMETER CONDITIONS MIN TYP MAX UNITS

VCONTROL Dropout Voltage (Note 4) ILOAD = 100mA

ILOAD = 1A

ILOAD = 3A

1.2

1.22

1.25

1.55

1.6

VIN Dropout Voltage (Note 4) ILOAD = 100mA l10 25 mV

ILOAD = 1A, Q, T Packages

ILOAD = 1A, DF, FE Packages

120

190

160

ILOAD = 3A, Q, T Packages

ILOAD = 3A, DF, FE Packages

310

240

510

420

VCONTROL Pin Current (Note 5) ILOAD = 100mA

ILOAD = 1A

ILOAD = 3A

5.5

Current Limit VIN = 5V, VCONTROL = 5V, VSET = 0V, VOUT = –0.1V l3 3.7 A

Error Ampliﬁer RMS Output Noise (Note 6) ILOAD = 500mA, 10Hz ≤ f ≤ 100kHz, COUT = 10µF, CSET = 0.1µF 40 µVRMS

Reference Current RMS Output Noise (Note 6) 10Hz ≤ f ≤ 100kHz 1 nARMS

Ripple Rejection

VRIPPLE = 0.5VP-P, IL = 0.1A, CSET = 0.1µF,

COUT = 10µF

f = 120Hz

f = 10kHz

f = 1MHz

Thermal Regulation, ISET 10ms Pulse 0.003 %/W

LT3083

3083fa

TYPICAL PERFORMANCE CHARACTERISTICS

Offset Voltage Distribution Offset Voltage (VOUT – VSET) Offset Voltage (VOUT – VSET)

Load Regulation Minimum Load Current

Dropout Voltage, T/Q Packages

(Minimum IN Voltage)

SET Pin Current Set Pin Current Distribution

–50

SET PIN CURRENT (µA)

49.6

49.7

50 150

3083 G01

49.5

49.8

49.9

50.5

50.4

50.3

50.2

50.1

50.0

25–25 0 75 100 125

TEMPERATURE (°C)

Offset Voltage (VOUT – VSET)

OFFSET VOLTAGE (mV)

525

3083 G05

–1.00

–0.75

–0.50

1.00

0.75

0.50

0.25

–0.25

10 15 20

INPUT-TO-OUTPUT VOLTAGE (V)

ILOAD = 5mA

OFFSET VOLTAGE (mV)

0.5 3

3083 G06

–1.75

–1.50

–1.25

0.25

–0.25

–0.50

–0.75

–1.00

1 1.5 2.52

LOAD CURRENT (A)

TJ = 25°C

TJ = 125°C

–50

CHANGE IN OFFSET VOLTAGE WITH LOAD (mV)

CHANGE IN REFERENCE CURRENT WITH LOAD (nA)

50 150

3083 G07

–1.6

–1.4

–0.2

–0.6

–0.8

–1.0

–1.2

25–25 0 75 100 125

TEMPERATURE (°C)

–0.4

–300

–250

100

–50

–100

–150

–200

CHANGE IN REFERENCE CURRENT

CHANGE IN OFFSET VOLTAGE (VOUT – VSET)

∆ILOAD = 5mA TO 3A

VIN = VCONTROL = VOUT + 2V

–50

MINIMUM LOAD CURRENT (mA)

50 150

3083 G08

0.2

1.4

1.2

1.0

0.8

0.6

0.4

25–25 0 75 100 125

TEMPERATURE (°C)

VIN,CONTROL – VOUT = 1.5V

VIN,CONTROL – VOUT = 23V

VIN = VCONTROL

MINIMUM VOLTAGE (VIN – VOUT) (mV)

0.5 3

3083 G09

100

400

350

300

250

200

150

1 1.5 2 2.5

LOAD CURRENT (A)

TJ = 125°C

TJ = 25°C

TJ = –50°C

TA = 25°C, unless otherwise noted.

49 51

3083 G02

49.5 50 50.5

SET PIN CURRENT DISTRIBUTION (µA)

N = 1052

–50

OFFSET VOLTAGE (mV)

50 150

3083 G03

–1.0

–0.4

1.0

0.8

0.4

0.2

–0.2

–0.8

–0.6

25–25 0 75 100 125

TEMPERATURE (°C)

0.6

ILOAD = 5mA

–3 3

3083 G04

–2 –1 0 21

VOS DISTRIBUTION (mV)

N = 1052

LT3083

3083fa

TYPICAL PERFORMANCE CHARACTERISTICS

Dropout Voltage (Minimum

VCONTROL Pin Voltage)

Dropout Voltage (Minimum

VCONTROL Pin Voltage)

Current Limit Current Limit

Dropout Voltage, FE/DF Packages

Dropout Voltage, T/Q Packages

(Minimum IN Voltage)

Dropout Voltage, FE/DF Packages

(Minimum IN Voltage)

TA = 25°C, unless otherwise noted.

–50

MINIMUM VCONTROL PIN VOLTAGE

(VCONTROL – VOUT) (V)

50 150

3083 G14

1.6

1.2

0.8

1.4

1.0

0.6

0.4

0.2

25–25 0 75 100 125

TEMPERATURE (°C)

ILOAD = 3A

MINIMUM VOLTAGE (VIN – VOUT) (mV)

0.5 3

3083 G10

100

400

350

300

250

200

150

1 1.5 2 2.5

LOAD CURRENT (A)

TJ = –50°C

TJ = 125°C

TJ = 25°C

–50

MINIMUM IN VOLTAGE (VIN – VOUT) (mV)

50 150

3083 G11

100

500

400

300

450

350

250

200

150

25–25 0 75 100 125

TEMPERATURE (°C)

ILOAD = 100mA

ILOAD = 3A

ILOAD = 500mA

ILOAD = 1.5A

–50

MINIMUM IN VOLTAGE (VIN – VOUT) (mV)

50 150

3083 G12

100

500

400

300

450

350

250

200

150

25–25 0 75 100 125

TEMPERATURE (°C)

ILOAD = 100mA

ILOAD = 500mA

ILOAD = 3A

ILOAD = 1.5A

–50

CURRENT LIMIT (A)

50 150

3083 G15

5.0

3.0

2.0

4.5

2.5

4.0

3.5

1.5

1.0

0.5

25–25 0 75 100 125

TEMPERATURE (°C)

VIN = VCONTROL = 7V

VOUT = 0V

CURRENT LIMIT (A)

3083 G16

4.0

3.0

2.0

3.5

2.5

1.5

1.0

0.5

5 10 15

IN-TO-OUT DIFFERENTIAL (VIN – VOUT) (V)

TJ = 25°C

MINIMUM VCONTROL PIN VOLTAGE

(VCONTROL – VOUT) (V)

0.5 3

3083 G13

0.2

0.4

1.6

1.4

1.2

1.0

0.8

0.6

1 1.5 2 2.5

LOAD CURRENT (A)

TJ = 25°C

TJ = 125°C

TJ = –50°C

LT3083

3083fa

TYPICAL PERFORMANCE CHARACTERISTICS

VCONTROL Pin Current VCONTROL Pin Current

Residual Output Voltage with

Less Than Minimum Load

Line Transient Response Turn-On Response Turn-On Response

Load Transient Response Load Transient Response

TA = 25°C, unless otherwise noted.

LOAD CURRENT (A) OUTPUT VOLTAGE

DEVIATION (mV)

80 200

3083 G17

–50

100

150

–100

1.0

0.5

6020 40 140 160100 120 180

TIME (µs)

VIN = 2V

VCONTROL = 3V

VOUT = 1V

CSET = 0.1µF

∆ILOAD = 100mA TO 1A

COUT = 10µF CERAMIC

COUT = 22µF CERAMIC

IN/ VCONTROL

VOLTAGE (V)

OUTPUT VOLTAGE

DEVIATION (mV)

80 200

3083 G19

–10

–20

6020 40 140 160100 120 180

TIME (µs)

VOUT = 1V

ILOAD = 10mA

COUT = 10µF CERAMIC

CSET = 0.1µF

IN/ VCONTROL

VOLTAGE (V)

OUTPUT

VOLTAGE (V)

20 50

3083 G20

1.0

0.5

–0.5 155 10 35 4025 30 45

TIME (µs)

RSET = 20k

CSET = 0

RLOAD = 0.33Ω

COUT = 10µF CERAMIC

IN/ VCONTROL

VOLTAGE (V)

OUTPUT

VOLTAGE (V)

820

3083 G21

1.0

0.5

–0.5 62 4 14 1610 12 18

TIME (ms)

RSET = 20k

CSET = 0.1µF

RLOAD = 1Ω

COUT = 10µF CERAMIC

VCONTROL PIN CURRENT (mA)

218

3083 G22

4 6 8 10 12 14 16

IN-TO-OUT DIFFERENTIAL (VIN – VOUT) (V)

ILOAD = 3A

ILOAD = 1.5A

DEVICE IN

CURRENT LIMIT

LOAD CURRENT (A) OUTPUT VOLTAGE

DEVIATION (mV)

80 200

3083 G18

–50

150

250

–150

6020 40 140 160100 120 180

TIME (µs)

∆ILOAD = 500mA TO 3A

VIN = 2V

VCONTROL = 3V

VOUT = 1V

CSET = 0.1µF

COUT = 22µF CERAMIC

VCONTROL PIN CURRENT (mA)

0.5 3

3083 G23

1 1.5 2 2.5

LOAD CURRENT (A)

TJ = –50°C

TJ = 125°C

TJ = 25°C

VCONTROL – VOUT = 2V

VIN – VOUT = 1V

OUTPUT VOLTAGE (mV)

2000

3083 G24

100

600

500

400

300

200

500 1000 1500

RSET (Ω)

RTEST

VOUT

SET PIN = 0V

ADD 1N4148 FOR

RTEST < 1k

VIN = 20V

VIN = 5V

VIN = 10V

VIN

LT3083

3083fa

TYPICAL PERFORMANCE CHARACTERISTICS

Noise Spectral Density

Output Voltage Noise Error Ampliﬁer Gain and Phase

Ripple Rejection, Single Supply

Ripple Rejection, Dual Supply,

VCONTROL Pin

Ripple Rejection, Dual Supply,

IN Pin

RIPPLE REJECTION (dB)

100 10M

3083 G25

100

1k 10k 100k 1M

FREQUENCY (Hz)

ILOAD = 0.1A

ILOAD = 1.5A

COUT = 10µF CERAMIC

CSET = 0.1µF CERAMIC

RIPPLE = 50mVP-P

VIN – VCONTROL = VOUT(NOMINAL) + 2V

ILOAD = 0.5A

RIPPLE REJECTION (dB)

100 10M

3083 G26

120

105

1k 10k 100k 1M

FREQUENCY (Hz)

COUT = 10µF CERAMIC

CSET = 0.1µF

VIN = VOUT(NOMINAL) + 1V

VCONTROL = VOUT(NOMINAL) + 2V

ILOAD = 0.1A

ILOAD = 1.5A

RIPPLE REJECTION (dB)

100 10M

3083 G27

120

105

1k 10k 100k 1M

FREQUENCY (Hz)

COUT = 10µF CERAMIC

CSET = 0.1µF

VIN = VOUT(NOMINAL) + 1V

VCONTROL = VOUT(NOMINAL) + 2V

ILOAD = 0.5A

ILOAD = 0.1A

ILOAD = 1.5A

–50

RIPPLE REJECTOIN (dB)

50 150

3083 G28

25–25 0 75 100 125

TEMPERATURE (°C)

VIN = VCONTROL = VOUT(NOMINAL) + 2V

RIPPLE = 500mVP-P, ƒ = 120Hz

ILOAD = 0.5A

CSET = 0.1µF, COUT = 10µF

Ripple Rejection (120Hz)

ERROR AMPLIFIER NOISE

SPECTRAL DENSITY (nV/√Hz)

REFERENCE CURRENT NOISE

SPECTRAL DENSITY (pA/√Hz)

100 100k

3083 G29

1000

100

1k 10k

FREQUENCY (Hz)

3083 G30

VOUT

100µV/DIV

TIME 1ms/DIV

VOUT = 1V, RSET = 20k

CSET = 0.1µF, COUT = 10µF

ILOAD = 3A

GAIN (dB)

100 1M

3083 G31

–15

–12

–6

–3

–9

–396

–360

–108

–144

–36

–72

–180

–216

–288

–252

–324

1k 10k 100k

FREQUENCY (Hz)

PHASE

GAIN

ILOAD = 0.5A

ILOAD = 1.5A

ILOAD = 3A

TA = 25°C, unless otherwise noted.

LT3083

3083fa

PIN FUNCTIONS

OUT (Pins 1-5,13/Pins 1-6,8,9,16,17/ Pin 3, Tab/Pin 3,

Tab): Output. The exposed pad of the DF package (Pin 13)

and the FE package (Pin 17) and the Tab of the DD-PAK

and TO-220 packages is an electrical connection to OUT.

Connect the exposed pad of the DF and FE packages and

the Tab of the DD-PAK package directly to OUT on the

PCB and the respective OUT pins for each package. There

must be a minimum load current of 1mA or the output

may not regulate.

SET (Pin 6/Pin 7/Pin 2/Pin 2): Set Point. This pin is the

non-inverting input to the error ampliﬁer and the regula-

tion set point. A ﬁxed current of 50μA ﬂows out of this

pin through a single external resistor, which programs

the output voltage of the device. Output voltage range is

zero to the VIN(MAX) – VDROPOUT. Transient performance

can be improved by adding a small capacitor from the

SET pin to ground.

VCONTROL (Pins 7,8/Pins 10,11/Pin 4/Pin 4): Bias Sup-

ply. This is the supply pin for the control circuitry of the

device. Minimum input capacitance is 2.2µF (see Input

Capacitance and Stability in the Applications Information

section). The current ﬂow into this pin is about 1.7% of

the output current. For the device to regulate, this voltage

must be more than 1.2V to 1.4V greater than the output

voltage (see dropout speciﬁcations in the Electrical Char-

acteristics section).

IN (Pins 9-12/Pins 12-15/Pin 5/Pin 5): Power Input. This

is the collector to the power device of the LT3083. The

output load current is supplied through this pin. Minimum

IN capacitance is 10µF (see Input Capacitance and Stabil-

ity in Applications Information section). For the device to

regulate, the voltage at this pin must be more than 0.1V

to 0.5V greater than the output voltage (see dropout

speciﬁcations in the Electrical Characteristics section).

NC (NA/NA/Pin 1/Pin 1): No Connection. No Connect pins

have no connection to internal circuitry and may be tied

to VIN, VCONTROL, VOUT, GND, or ﬂoated.

(DF/FE/Q/T Packages)

BLOCK DIAGRAM

–

VCONTROL

50µA

3083 BD

OUTSET

LT3083

3083fa

APPLICATIONS INFORMATION

The LT3083 regulator is easy to use and has all the protection

features expected in high performance regulators. Included

are short-circuit protection and safe operating area protec-

tion, as well as thermal shutdown with hysteresis.

The LT3083 ﬁts well in applications needing multiple rails.

This new architecture adjusts down to zero with a single

resistor, handling modern low voltage digital IC’s as well as

allowing easy parallel operation and thermal management

without heat sinks. Adjusting to zero output allows shutting

off the powered circuitry. When the input is pre-regulated,

such as with a 5V or 3.3V input supply, external resistors

can help spread the heat.

A precision “0” TC 50μA reference current source connects

to the noninverting input of a power operational ampliﬁer.

The power operational ampliﬁer provides a low impedance

buffered output to the voltage on the noninverting input.

A single resistor from the noninverting input to ground

sets the output voltage. If this resistor is set to 0Ω, zero

output voltage results. Therefore, any output voltage can

be obtained between zero and the maximum deﬁned by

the input power supply.

The beneﬁt of using a true internal current source as the

reference, as opposed to a bootstrapped reference in older

regulators, is not so obvious in this architecture. A true

reference current source allows the regulator to have gain

and frequency response independent of the impedance on

the positive input. On older adjustable regulators, such as

the LT1086, loop gain changes with output voltage and

bandwidth changes if the adjustment pin is bypassed to

ground. For the LT3083, the loop gain is unchanged with

output voltage changes or bypassing. Output regulation

is not a ﬁxed percentage of output voltage, but is a ﬁxed

fraction of millivolts. Use of a true current source allows

all of the gain in the buffer ampliﬁer to provide regulation,

and none of that gain is needed to amplify up the reference

to a higher output voltage.

The LT3083 has the collector of the output transistor con-

nected to a separate pin from the control input. Since the

dropout on the collector (IN pin) is typically only 310mV,

two supplies can be used to power the LT3083 to reduce

dissipation: a higher voltage supply for the control circuitry

and a lower voltage supply for the collector. This increases

efﬁciency and reduces dissipation. To further spread the

heat, a resistor inserted in series with the collector moves

some of the heat out of the IC to spread it on the PC board

(see the section

Reducing Power Dissipation

The LT3083 can be operated in two modes. Three termi-

nal mode has the VCONTROL pin connected to the IN pin

and gives a limitation of 1.25V dropout. Alternatively, the

VCONTROL pin is separately tied to a higher voltage and the

IN pin to a lower voltage giving 310mV dropout on the IN

pin, minimizing total power dissipation. This allows for a

3A supply regulating from 2.5VIN to 1.8VOUT or 1.8VIN to

1.2VOUT with low power dissipation.

Programming Output Voltage

The LT3083 sources a 50μA reference current that ﬂows

out of the SET pin. Connecting a resistor from SET to

ground generates a voltage that becomes the reference

point for the error ampliﬁer (see Figure 1). The refer-

ence voltage equals 50µA multiplied by the value of

the SET pin resistor. Any voltage can be generated and

there is no minimum output voltage for the regulator.

Figure 1. Basic Adjustable Regulator

–

LT3083

VCONTROL

OUT

3083 F01

SET

COUT

RSET

VOUT

CSET

VIN

50µA

VOUT = 50µA • RSET

LT3083

3083fa

APPLICATIONS INFORMATION

Table 1 lists many common output voltages and the clos-

est standard 1% resistor values used to generate that

output voltage.

Regulation of the output voltage requires a minimum

load current of 1mA. For a true zero voltage output

operation, return this 1mA load current to a negative

supply voltage.

Table 1. 1% Resistors for Common Output Voltages

VOUT (V) RSET (k)

1 20

1.2 24.3

1.5 30.1

1.8 35.7

2.5 49.9

3.3 66.5

5 100

With the lower level current used to generate the refer-

ence voltage, leakage paths to or from the SET pin can

create errors in the reference and output voltages. High

quality insulation should be used (e.g., Teﬂon, Kel-F);

cleaning of all insulating surfaces to remove ﬂuxes and

other residues will probably be required. Surface coating

may be necessary to provide a moisture barrier in high

humidity environments.

Minimize board leakage by encircling the SET pin and

circuitry with a guard ring operated at a potential close

to itself. Tie the guard ring to the OUT pin. Guard rings

on both sides of the circuit board are required. Bulk leak-

age reduction depends on the guard ring width. 50nA

of leakage into or out of the SET pin and its associated

circuitry creates a 0.1% reference voltage error. Leakages

of this magnitude, coupled with other sources of leakage,

can cause signiﬁcant offset voltage and reference drift,

especially over the possible operating temperature range.

Figure 2 depicts an example of a guard ring layout.

If guard ring techniques are used, this bootstraps any

stray capacitance at the SET pin. Since the SET pin is

a high impedance node, unwanted signals may couple

into the SET pin and cause erratic behavior. This will

be most noticeable when operating with minimum

output capacitors at full load current. The easiest way

to remedy this is to bypass the SET pin with a small

amount of capacitance from SET to ground, 10pF to

20pF is sufﬁcient.

Stability and Input Capacitance

Typical minimum input capacitance is 10µF for IN and

2.2µF for VCONTROL. These amounts of capacitance work

well using low ESR ceramic capacitors when placed close

to the LT3083 and the circuit is located in close proximity

to the power source. Higher values of input capacitance

may be necessary to maintain stability depending on the

application.

Oscillating regulator circuits are often viewed as a problem

of phase margin and inadequate stability with the output

capacitor used. More and more frequently, the problem

is not the regulator operating without sufﬁcient output

capacitance, but instead with too little input capacitance.

The entire circuit must be analyzed and debugged as a

whole; conditions relating to the input of the regulator

cannot be ignored.

The LT3083 input presents a high impedance to its power

source: the output voltage and load current are independent

of input voltage variations. To maintain stability of the

regulator circuit as a whole, the LT3083 must be powered

from a low impedance supply. When using short supply

lines or powering directly from a large switching supply,

there is no issue—hundreds or thousands of microfarads

of capacitance are available through a low impedance.

Figure 2. Guard Ring Layout Example

for DF Package

3083 F02

SET PIN

GND

OUT

LT3083

3083fa

APPLICATIONS INFORMATION

When longer supply lines, ﬁlters, current sense resistors,

or other impedances exist between the supply and the

input to the LT3083, input bypassing should be reviewed

if stability concerns are seen. Just as output capacitance

supplies the instantaneous changes in load current for

output transients until the regulator is able to respond,

input capacitance supplies local power to the regulator until

the main supply responds. When impedance separates the

LT3083 from its main supply, the local input can droop

so that the output follows. The entire circuit may break

into oscillations, usually characterized by larger amplitude

oscillations on the input and coupling to the output.

Low ESR, ceramic input bypass capacitors are acceptable

for applications without long input leads. However, applica-

tions connecting a power supply to an LT3083 circuit’s IN

and GND pins with long input wires combined with low

ESR, ceramic input capacitors are prone to voltage spikes,

reliability concerns and application-speciﬁc board oscil-

lations. The input wire inductance found in many battery

powered applications, combined with the low ESR ceramic

input capacitor, forms a high-Q LC resonant tank circuit. In

some instances this resonant frequency beats against the

output current dependent LDO bandwidth and interferes

with proper operation. Simple circuit modiﬁcations/solu-

tions are then required. This behavior is not indicative of

LT3083 instability, but is a common ceramic input bypass

capacitor application issue.

The self-inductance, or isolated inductance, of a wire is

directly proportional to its length. Wire diameter is not a

major factor on its self-inductance. For example, the self-

inductance of a 2-AWG isolated wire (diameter = 0.26") is

about half the self-inductance of a 30-AWG wire (diameter

= 0.01"). One foot of 30-AWG wire has about 465nH of

self-inductance.

One of two ways reduces a wire’s self-inductance. One

method divides the current ﬂowing towards the LT3083

between two parallel conductors. In this case, the farther

apart the wires are from each other, the more the self-in-

ductance is reduced; up to a 50% reduction when placed

a few inches apart. Splitting the wires basically connects

two equal inductors in parallel, but placing them in close

proximity gives the wires mutual inductance adding to

the self-inductance. The second and most effective way

to reduce overall inductance is to place both forward and

return current conductors (the input and GND wires) in

very close proximity. Two 30-AWG wires separated by only

0.02", used as forward- and return- current conductors,

reduce the overall self-inductance to approximately one-

ﬁfth that of a single isolated wire.

If wiring modiﬁcations are not permissible for the applica-

tions, including series resistance between the power supply

and the input of the LT3083 also stabilizes the application.

As little as 0.1Ω to 0.5Ω, often less, is effective in damping

the LC resonance. If the added impedance between the

power supply and the input is unacceptable, adding ESR to

the input capacitor also provides the necessary damping of

the LC resonance. However, the required ESR is generally

higher than the series impedance required.

Stability and Output Capacitance

The LT3083 requires an output capacitor for stability. It

is designed to be stable with most low ESR capacitors

(typically ceramic, tantalum or low ESR electrolytic). A

minimum output capacitor of 10μF with an ESR of 0.5Ω

or less is recommended to prevent oscillations. Larger

values of output capacitance decrease peak deviations

and provide improved transient response for larger load

current changes. Bypass capacitors, used to decouple

individual components powered by the LT3083, increase

the effective output capacitor value. For improvement in

transient performance, place a capacitor across the volt-

age setting resistor. Capacitors up to 1μF can be used.

This bypass capacitor reduces system noise as well, but

start-up time is proportional to the time constant of the

voltage setting resistor (RSET in Figure 1) and SET pin

bypass capacitor.

Give extra consideration to the use of ceramic capacitors.

Ceramic capacitors are manufactured with a variety of di-

electrics, each with different behavior across temperature

and applied voltage. The most common dielectrics used

are speciﬁed with EIA temperature characteristic codes of

Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics are

good for providing high capacitances in a small package,

but they tend to have strong voltage and temperature

coefﬁcients as shown in Figures 3 and 4. When used with

a 5V regulator, a 16V 10μF Y5V capacitor can exhibit an

LT3083

3083fa

APPLICATIONS INFORMATION

Figure 5. Parallel Devices

effective value as low as 1μF to 2μF for the DC bias voltage

applied and over the operating temperature range. The X5R

and X7R dielectrics result in more stable characteristics

and are more suitable for use as the output capacitor.

The X7R type has better stability across temperature,

while the X5R is less expensive and is available in higher

values. Care still must be exercised when using X5R and

X7R capacitors. The X5R and X7R codes only specify

operating temperature range and maximum capacitance

change over temperature. Capacitance change due to DC

bias with X5R and X7R capacitors is better than Y5V and

Z5U capacitors, but can still be signiﬁcant enough to drop

capacitor values below appropriate levels. Capacitor DC

bias characteristics tend to improve as component case

size increases, but expected capacitance at operating

voltage should be veriﬁed.

Voltage and temperature coefﬁcients are not the only

sources of problems. Some ceramic capacitors have a

piezoelectric response. A piezoelectric device generates

voltage across its terminals due to mechanical stress. In a

ceramic capacitor, the stress can be induced by vibrations

in the system or thermal transients.

Paralleling Devices

Higher output current is obtained by paralleling multiple

LT3083s together. Tie the individual SET pins together and

tie the individual IN pins together. Connect the outputs in

common using small pieces of PC trace as ballast resistors

to promote equal current sharing. PC trace resistance in

mΩ/inch is shown in Table 2. Ballasting requires only a

tiny area on the PCB.

Table 2. PC Board Trace Resistance

WEIGHT (oz) 10mil WIDTH 20mil WIDTH

1 54.3 27.1

2 27.1 13.6

Trace resistance is measured in mΩ/in

The worst-case room temperature offset, only ±4mV

(DD-PAK, T Packages) between the SET pin and the OUT

pin, allows the use of very small ballast resistors.

As shown in Figure 5, each LT3083 has a small 10mΩ

ballast resistor, which at full output current gives better

than 80% equalized sharing of the current. The external

Figure 3. Ceramic Capacitor DC Bias Characteristics

Figure 4. Ceramic Capacitor Temperature Characteristics

DC BIAS VOLTAGE (V)

CHANGE IN VALUE (%)

3083 F03

–20

–40

–60

–80

–100 04810

2 6 12 14

X5R

Y5V

BOTH CAPACITORS ARE 16V,

1210 CASE SIZE, 10µF

TEMPERATURE (°C)

–50

–20

–40

–60

–80

–100 25 75

3083 F04

–25 0 50 100 125

Y5V

CHANGE IN VALUE (%)

X5R

BOTH CAPACITORS ARE 16V,

1210 CASE SIZE, 10µF

–

LT3083

VIN

VCONTROL

OUT

SET

10mΩ

–

LT3083

VIN

4.8V

TO 20V

VOUT

3.3V

VCONTROL

OUT

10µF

SET

33k

3083 F05

10mΩ

LT3083

3083fa

APPLICATIONS INFORMATION

resistance of 10mΩ (5mΩ for the two devices in paral-

lel) only adds about 30mV of output regulation drop at

an output of 6A. With an output voltage of 3.3V, this only

adds 1% to the regulation. Of course, paralleling more

than two LT3083s yields even higher output current.

Spreading the devices on the PC board also spreads the

heat. Series input resistors can further spread the heat if

the input-to-output difference is high.

Quieting the Noise

The LT3083 offers numerous noise performance advan-

tages. Every linear regulator has its sources of noise. In

general, a linear regulator’s critical noise source is the

reference. In addition, consider the error ampliﬁer’s noise

contribution along with the resistor divider’s noise gain.

Many traditional low noise regulators bond out the voltage

reference to an external pin (usually through a large value

resistor) to allow for bypassing and noise reduction. The

LT3083 does not use a traditional voltage reference like

other linear regulators. Instead, it uses a 50µA reference

current. The 50µA current source generates noise current

levels of 3.16pA/√Hz (1nARMS) over the 10Hz to 100kHz

bandwidth). The equivalent voltage noise equals the RMS

noise current multiplied by the resistor value.

The SET pin resistor generates spot noise equal to √4kTR

(k = Boltzmann’s constant, 1.38 • 10–23J/°K, and T is abso-

lute temperature) which is RMS summed with the voltage

noise. If the application requires lower noise performance,

bypass the voltage setting resistor with a capacitor to GND.

Note that this noise-reduction capacitor increases start-up

time as a factor of the RC time constant.

The LT3083 uses a unity-gain follower from the SET pin

to the OUT pin. Therefore, multiple possibilities exist

(besides a SET pin resistor) to set output voltage. For

example, using a high accuracy voltage reference from

SET to GND removes the errors in output voltage due to

reference current tolerance and resistor tolerance. Active

driving of the SET pin is acceptable.

The typical noise scenario for a linear regulator is that the

output voltage setting resistor divider gains up the noise

reference, especially if VOUT is much greater than VREF.

The LT3083’s noise advantage is that the unity gain follower

presents no noise gain whatsoever from the SET pin to the

output. Thus, noise ﬁgures do not increase accordingly.

Error ampliﬁer noise is typically 126.5nV/√Hz (40µVRMS)

over the 10Hz to 100kHz bandwidth). The error ampliﬁer’s

noise is RMS summed with the other noise terms to give

a ﬁnal noise ﬁgure for the regulator.

Curves in the Typical Performance Characteristics sec-

tion show noise spectral density and peak-to-peak noise

characteristics for both the reference current and error

ampliﬁer over the 10Hz to 100kHz bandwidth.

Load Regulation

The LT3083 is a ﬂoating device. No ground pin exists on

the packages. Thus, the IC delivers all quiescent current

and drive current to the load. Therefore, it is not possible

to provide true remote load sensing. The connection resis-

tance between the regulator and the load determines load

regulation performance. The data sheet’s load regulation

speciﬁcation is Kelvin sensed at the package’s pins. Nega-

tive-side sensing is a true Kelvin connection by returning

the bottom of the voltage setting resistor to the negative

side of the load (see Figure 6).

Connected as shown, system load regulation is the sum

of the LT3083’s load regulation and the parasitic line

resistance multiplied by the output current. To minimize

load regulation, keep the positive connection between the

regulator and load as short as possible. If possible, use

large diameter wire or wide PC board traces.

–

LT3083

VCONTROL

OUT

3080 F06

SET RSET

PARASITIC

RESISTANCE

LOAD

Figure 6. Connections for Best Load Regulation

LT3083

3083fa

APPLICATIONS INFORMATION

Thermal Considerations

The LT3083’s internal power and thermal limiting circuitry

protects itself under overload conditions. For continuous

normal load conditions, do not exceed the 125°C maximum

junction temperature. Carefully consider all sources of

thermal resistance from junction-to-ambient. This includes

(but is not limited to) junction-to-case, case-to-heat sink

interface, heat sink resistance or circuit board-to-ambient

as the application dictates. Consider all additional, adjacent

heat generating sources in proximity on the PCB.

Surface mount packages provide the necessary heat

sinking by using the heat spreading capabilities of the

PC board, copper traces, and planes. Surface mount heat

sinks, plated through-holes and solder-ﬁlled vias can also

spread the heat generated by power devices.

Junction-to-case thermal resistance is speciﬁed from the

IC junction to the bottom of the case directly, or the bottom

of the pin most directly in the heat path. This is the lowest

thermal resistance path for heat ﬂow. Only proper device

mounting ensures the best possible thermal ﬂow from this

area of the packages to the heat sinking material.

Note that the exposed pad of the DFN and TSSOP pack-

ages and the tab of the DD-PAK and TO-220 packages

are electrically connected to the output (VOUT).

Tables 3 through 5 list thermal resistance as a function

of copper areas on a ﬁxed board size. All measurements

were taken in still air on a 4-layer FR-4 board with 1oz

solid internal planes and 2oz external trace planes with a

total ﬁnished board thickness of 1.6mm. Layers are not

connected electrically or thermally.

Table 3. DF Package, 12-Lead DFN

COPPER AREA

BOARD AREA

THERMAL RESISTANCE

(JUNCTION-TO-AMBIENT)TOPSIDE* BACKSIDE

2500mm22500mm22500mm218°C/W

1000mm22500mm22500mm222°C/W

225mm22500mm22500mm229°C/W

100mm22500mm22500mm235°C/W

*Device is mounted on topside.

Table 4. FE Package, 16-Lead TSSOP

COPPER AREA

BOARD AREA

THERMAL RESISTANCE

(JUNCTION-TO-AMBIENT)TOPSIDE* BACKSIDE

2500mm22500mm22500mm216°C/W

1000mm22500mm22500mm220°C/W

225mm22500mm22500mm226°C/W

100mm22500mm22500mm232°C/W

*Device is mounted on topside.

Table 5. Q Package, 5-Lead DD-PAK

COPPER AREA

BOARD AREA

THERMAL RESISTANCE

(JUNCTION-TO-AMBIENT)TOPSIDE* BACKSIDE

2500mm22500mm22500mm213°C/W

1000mm22500mm22500mm214°C/W

125mm22500mm22500mm216°C/W

*Device is mounted on topside.

T Package, 5-Lead TO-220

Thermal Resistance (Junction-to-Case) = 3°C/W

For further information on thermal resistance and using

thermal information, refer to JEDEC standard JESD51,

notably JESD51-12.

PCB layers, copper weight, board layout and thermal vias

affect the resultant thermal resistance. Tables 3 through 5

provide thermal resistance numbers for best-case 4-layer

boards with 1oz internal and 2oz external copper. Modern,

multilayer PCBs may not be able to achieve quite the same

level performance as found in these tables.

Calculating Junction Temperature

Example: Given an output voltage of 0.9V, a VCONTROL

voltage of 3.3V ±10%, an IN voltage of 1.5V ±5%, output

current range from 10mA to 3A and a maximum ambient

temperature of 50°C, what will the maximum junction

temperature be for the DD-PAK on a 2500mm2 board with

topside copper of 1000mm2?

LT3083

3083fa

APPLICATIONS INFORMATION

The power in the drive circuit equals:

PDRIVE = (VCONTROL – VOUT)(ICONTROL)

where ICONTROL is equal to IOUT/60. ICONTROL is a function

of output current. A curve of ICONTROL vs IOUT can be found

in the Typical Performance Characteristics curves.

The total power equals:

PTOTAL = PDRIVE + POUTPUT

The current delivered to the SET pin is negligible and can

be ignored.

VCONTROL(MAX_CONTINUOUS) = 3.630V (3.3V + 10%)

VIN(MAX_CONTINUOUS) = 1.575V (1.5V + 5%)

VOUT = 0.9V, IOUT = 3A, TA = 50°C

Power dissipation under these conditions is equal to:

PDRIVE = (VCONTROL – VOUT)(ICONTROL)

ICONTROL =

OUT

60 =

60 =50mA

PDRIVE = (3.630V – 0.9V)(50mA) = 137mW

POUTPUT = (VIN – VOUT)(IOUT)

POUTPUT = (1.575V – 0.9V)(3A) = 2.03W

Total Power Dissipation = 2.16W

Junction Temperature will be equal to:

TJ = TA + PTOTAL • θJA (using tables)

TJ = 50°C + 2.16W • 16°C/W = 84.6°C

In this case, the junction temperature is below the maxi-

mum rating, ensuring reliable operation.

Reducing Power Dissipation

In some applications it may be necessary to reduce the

power dissipation in the LT3083 package without sacriﬁc-

ing output current capability. Two techniques are available.

The ﬁrst technique, illustrated in Figure 7, employs a

resistor in series with the regulator’s input. The voltage

drop across RS decreases the LT3083’s input-to-output

differential voltage and correspondingly decreases the

LT3083’s power dissipation.

As an example, assume: VIN = VCONTROL = 5V, VOUT = 3.3V

and IOUT(MAX) = 2A. Use the formulas from the

Calculating

Junction Temperature

section previously discussed.

Without series resistor RS, power dissipation in the LT3083

equals:

PTOTAL =5V −3.3V

( )

•2A









+5V −3.3V

( )

•2A

=3.46W

If the voltage differential (VDIFF) across the NPN pass

transistor is chosen as 0.5V, then RS equals:

RS=5V

−

3.3V

−

0.5V

=0.6Ω

Power dissipation in the LT3083 now equals:

PTOTAL =5V −3.3V

( )

•2A











+0.5V •2A =1.06W

The LT3083’s power dissipation is now only 30% compared

to no series resistor. RS dissipates 2.4W of power. Choose

appropriate wattage resistors or use multiple resistors in

parallel to handle and dissipate the power properly.

Figure 7. Reducing Power Dissipation Using a Series Resistor

–

LT3083 IN

VCONTROL

OUT VOUT

VIN′

VIN

3083 F07

SET

RSET

LT3083

3083fa

–

LT3083 IN

VCONTROL

OUT VOUT

VIN

3083 F08

SET

RSET

Figure 8. Reducing Power Dissipation Using a Parallel Resistor

The second technique for reducing power dissipation,

shown in Figure 8, uses a resistor in parallel with the

LT3083. This resistor provides a parallel path for current

ﬂow, reducing the current ﬂowing through the LT3083.

This technique works well if input voltage is reasonably

constant and output load current changes are small. This

technique also increases the maximum available output

current at the expense of minimum load requirements.

As an example, assume: VIN = VCONTROL = 5V, VIN(MAX) =

5.5V, VOUT = 3.3V, VOUT(MIN) = 3.2V, IOUT(MAX) = 2A and

IOUT(MIN) = 0.7A. Also, assuming that RP carries no more

than 90% of IOUT(MIN) = 630mA.

Calculating RP yields:

RP=

5.5V −3.2V

0.63A =3.65Ω

(5% Standard Value = 3.6Ω)

The maximum total power dissipation is (5.5V – 3.2V) •

2A = 4.6W. However, the LT3083 supplies only:

2A −5.5V

−

3.2V

3.6

Ω

=1.36A

Therefore, the LT3083’s power dissipation is only:

PDISS = (5.5V – 3.2V) • 1.36A = 3.13W

RP dissipates 1.47W of power. As with the ﬁrst technique,

choose appropriate wattage resistors to handle and dis-

sipate the power properly. With this conﬁguration, the

LT3083 supplies only 1.36A. Therefore, load current can

increase by 1.64A to a total output current of 3.64A while

keeping the LT3083 in its normal operating range.

APPLICATIONS INFORMATION

LT3083

3083fa

TYPICAL APPLICATIONS

–

LT3083

VIN

VCONTROL

OUT VOUT

3083 TA02

SET

ON OFF

SHUTDOWN

VN2222LL

Q2*

VN2222LL

Q2 INSURES ZERO OUTPUT

IN THE ABSENCE OF ANY

OUTPUT LOAD.

Adding Shutdown Current Source

Low Dropout Voltage LED Driver

DAC-Controlled Regulator

–

LT3083 IN

VCONTROL

OUT

VIN

3083 TA04

SET

20k

1Ω

–

LT3083

VCONTROL

OUT

10µF

VIN

3083 TA05

SET

450k VOUT

–

150k

LT1991

GAIN = 4

SPI LTC2641

–

LT3083

VCONTROL

OUT 0.33Ω

20k

3083 TA03

SET

IOUT

0A TO 3A

10µF

VIN

10V

10µF

LT3083

3083fa

Adding Soft-Start

Coincident Tracking

Lab Supply

TYPICAL APPLICATIONS

–

LT3083

VCONTROL

OUT

10µF

VOUT3

SET

10µF

–

LT3083

VCONTROL

OUT VOUT2

3.3V

3083 TA06

SET

16.2k

34k

10µF

–

LT3083

VCONTROL

VIN

7V TO 20V

OUT

SET

49.9k

VOUT1

2.5V

–

LT3083

VIN

4.8V to 20V

VCONTROL

OUT VOUT

3.3V

COUT

10µF

3083 TA07

SET

66.5k

0.01µF

10µF

1N4148

–

LT3083

–

LT3083 ININ

VIN

12V TO 18V

VCONTROL

OUTOUT

10µF 100µF

VOUT

0V TO 10V

3083 TA08

SETSET +

15µF R4

200k

0.33Ω

20k

0A TO 3A

15µF

LT3083

3083fa

TYPICAL APPLICATIONS

High Voltage Regulator

Ramp Generator Reference Buffer

Boosting Fixed Output Regulators

–

LT3083

6.1V

1N4148

VIN

50V

VCONTROL

OUT VOUT

3A VOUT = 20V

VOUT = 50µA • RSET

3083 TA09

SET

RSET

402k

10µF

15µF

10µF

BUZ11

10k

–

LT3083

VIN

VCONTROL

OUT VOUT

3083 TA10

SET

VN2222LL VN2222LL 10µF

10µF

10nF

–

LT3083

VIN

VCONTROL

OUT VOUT*

3083 TA11

SET

OUTPUT

INPUT

1µF

GND

10µF

LT1019

*MIN LOAD 0.5mA

3083 TA12

10mΩ

20mΩ

42Ω* 47µF

3.3VOUT

4.5A

VCONTROL

33k

*4mV DROP ENSURES LT3083 IS

OFF WITH NO LOAD

MULTIPLE LT3083’S CAN BE USED

–

LT3083

10µF

OUT

SET

LT1963-3.3

LT3083

3083fa

Low Voltage, High Current Adjustable High Efﬁciency Regulator*

TYPICAL APPLICATIONS

2.7V TO 5.5V†

2×

100µF 2.2MEG 100k 470pF

10k

1000pF

2×

100µF

294k

12.1k

0.47µH

78.7k

100k

124k

PVIN SW

2N3906

SVIN ITH

VFB

SYNC/MODE

PGOOD

RUN/SS

SGND PGND

LTC3610

–

LT3083

VCONTROL

OUT

SET

–

LT3083

VCONTROL

OUT 0V TO 4V†

12A

SET

–

LT3083

VCONTROL

OUT

SET

3083 TA13

–

LT3083

VCONTROL

OUT

100µF

SET

*DIFFERENTIAL VOLTAGE ON LT3083

IS 0.6V SET BY THE VBE OF THE 2N3906 PNP.

10mΩ

†MAXIMUM OUTPUT VOLTAGE IS 1.5V

BELOW INPUT VOLTAGE

LT3083

3083fa

Adjustable High Efﬁciency Regulator*

2 Terminal Current Source

TYPICAL APPLICATIONS

3083 TA14

4.5V TO 25V†

10µF 100k

0.1µF 68µF

4.7µH

B340A

10k

15.4k

1µF 0.47µF

TP0610L

63.4k

600kHz

–

LT3083

VCONTROL

OUT

SET 4.7µF

0V TO 10V†

*DIFFERENTIAL VOLTAGE ON LT3083

≈ 1.4V SET BY THE TPO610L P-CHANNEL THRESHOLD.

200k

†MAXIMUM OUTPUT VOLTAGE IS 2V

BELOW INPUT VOLTAGE

680pF

VIN BOOST

RUN/SS

VCONTROL

GND

LT3680

200k

3083 TA15

20k

–

LT3083

CCOMP*

VCONTROL

SET

*CCOMP

R1 ≤ 10Ω 10µF

R1 ≥ 10Ω 2.2µF

IOUT = 1V

LT3083

3083fa

PACKAGE DESCRIPTION

FE Package

16-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663 Rev H)

Exposed Pad Variation BB

FE16 (BB) TSSOP REV G 0910

0.09 – 0.20

(.0035 – .0079)

0° – 8°

0.25

REF

0.50 – 0.75

(.020 – .030)

4.30 – 4.50*

(.169 – .177)

1 3 4 5678

10 9

4.90 – 5.10*

(.193 – .201)

16 1514 13 12 11

1.10

(.0433)

MAX

0.05 – 0.15

(.002 – .006)

0.65

(.0256)

BSC

2.94

(.116)

0.195 – 0.30

(.0077 – .0118)

TYP

RECOMMENDED SOLDER PAD LAYOUT

0.45 ±0.05

0.65 BSC

4.50 ±0.10

6.60 ±0.10

1.05 ±0.10

2.94

(.116)

3.58

(.141)

3.58

(.141)

MILLIMETERS

(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

SEE NOTE 4

4. RECOMMENDED MINIMUM PCB METAL SIZE

FOR EXPOSED PAD ATTACHMENT

6.40

(.252)

BSC

FE Package

16-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663 Rev H)

Exposed Pad Variation BB

LT3083

3083fa

PACKAGE DESCRIPTION

DF Package

12-Lead Plastic DFN (4mm × 4mm)

(Reference LTC DWG # 05-08-1733 Rev Ø)

4.00 ± 0.10

(4 SIDES)

NOTE:

1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220

VARIATION (WGGD-X)—TO BE APPROVED

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(NOTE 6)

0.40 ± 0.10

127

BOTTOM VIEW—EXPOSED PAD

2.65 ± 0.10

0.75 ± 0.05

R = 0.115

TYP

0.25 ± 0.05

0.50 BSC

2.50 REF

3.38 ±0.10

0.200 REF

0.00 – 0.05

(DF12) DFN 0806 REV Ø

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.70 ±0.05

0.25 ±0.05

0.50 BSC

3.10 ± 0.05

4.50 ± 0.05

PACKAGE OUTLINE

PIN 1 NOTCH

R = 0.20 TYP OR

0.35 × 45°

CHAMFER

2.65 ± 0.05

3.38 ±0.05

2.50 REF

LT3083

3083fa

PACKAGE DESCRIPTION

Q Package

5-Lead Plastic DD-PAK

(Reference LTC DWG # 05-08-1461 Rev E)

Q(DD5) 0610 REV E

.028 – .038

(0.711 – 0.965)

TYP

.143 +.012

–.020

( )

3.632+0.305

–0.508

.067

(1.702)

BSC

.013 – .023

(0.330 – 0.584)

.095 – .115

(2.413 – 2.921)

.004 +.008

–.004

( )

0.102+0.203

–0.102

.050 ± .012

(1.270 ± 0.305)

.059

(1.499)

TYP

.045 – .055

(1.143 – 1.397)

.165 – .180

(4.191 – 4.572)

.330 – .370

(8.382 – 9.398)

.060

(1.524)

TYP

.390 – .415

(9.906 – 10.541)

15° TYP

.420

.350

.585

.090

.042

.067

RECOMMENDED SOLDER PAD LAYOUT

.325

.205

.080

.585

.090

RECOMMENDED SOLDER PAD LAYOUT

FOR THICKER SOLDER PASTE APPLICATIONS

.042

.067

.420

.276

.320

NOTE:

1. DIMENSIONS IN INCH/(MILLIMETER)

2. DRAWING NOT TO SCALE

.300

(7.620)

.075

(1.905)

.183

(4.648)

.060

(1.524)

.060

(1.524)

.256

(6.502)

BOTTOM VIEW OF DD PAK

HATCHED AREA IS SOLDER PLATED

COPPER HEAT SINK

Q Package

5-Lead Plastic DD Pak

(Reference LTC DWG # 05-08-1461 Rev E)

LT3083

3083fa

PACKAGE DESCRIPTION

T Package

5-Lead Plastic TO-220 (Standard)

(Reference LTC DWG # 05-08-1421)

T5 (TO-220) 0801

.028 – .038

(0.711 – 0.965)

.067

(1.70) .135 – .165

(3.429 – 4.191)

.700 – .728

(17.78 – 18.491)

.045 – .055

(1.143 – 1.397)

.095 – .115

(2.413 – 2.921)

.013 – .023

(0.330 – 0.584)

.620

(15.75)

TYP

.155 – .195*

(3.937 – 4.953)

.152 – .202

(3.861 – 5.131)

.260 – .320

(6.60 – 8.13)

.165 – .180

(4.191 – 4.572)

.147 – .155

(3.734 – 3.937)

DIA

.390 – .415

(9.906 – 10.541)

.330 – .370

(8.382 – 9.398)

.460 – .500

(11.684 – 12.700)

.570 – .620

(14.478 – 15.748)

.230 – .270

(5.842 – 6.858)

BSC

SEATING PLANE

* MEASURED AT THE SEATING PLANE

LT3083

3083fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

A 4/11 Revised part markings in Order Information section 3

LT3083

3083fa

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

 LINEAR TECHNOLOGY CORPORATION 2011

LT 0411 REV A • PRINTED IN USA

RELATED PARTS

TYPICAL APPLICATION

Paralleling Regulators

–

LT3083

VIN

4.8V TO 28V

VCONTROL

OUT 10mΩ VOUT

3.3V

3083 TA16

33.2k

SET

22µF

10µF

–

LT3083

VCONTROL

OUT 10mΩ

SET

PART NUMBER DESCRIPTION COMMENTS

LT1185 3A Negative Low Dropout Regulator VIN: –4.5V to –35V, 0.8V Dropout Voltage, DD-PAK and TO-220 Packages

LT1764/

LT1764A 3A, Fast Transient Response,

Low Noise LDO 340mV Dropout Voltage, Low Noise: 40µVRMS, VIN = 2.7V to 20V, TO-220 and DD Packages.

“A” Version Stable Also with Ceramic Capacitors

LT1963/A 1.5A Low Noise, Fast Transient

Response LDO 340mV Dropout Voltage, Low Noise: 40µVRMS, VIN = 2.5V to 20V, “A” Version Stable with

Ceramic Capacitors, TO-220, DD, SOT-223 and SO-8 Packages

LT1965 1.1A, Low Noise, Low Dropout

Linear Regulator 290mV Dropout Voltage, Low Noise: 40µVRMS, VIN: 1.8V to 20V, VOUT: 1.2V to 19.5V,

Stable with Ceramic Capacitors, TO-220, DD-PAK, MSOP and 3mm × 3mm DFN Packages

LT3022 1A, Low Voltage, VLDO Linear

Regulator VIN: 0.9V to 10V, Dropout Voltage: 145mV Typical, Adjustable Output (VREF = VOUT(MIN) = 200mV),

Stable with Low ESR, Ceramic Output Capacitors, 16-Pin DFN (5mm × 3mm) and

16-Lead MSOP Packages

LT3070 5A, Low Noise, Programmable VOUT,

85mV Dropout Linear Regulator with

Digital Margining

Dropout Voltage: 85mV, Digitally Programmable VOUT: 0.8V to 1.8V, Digital Output Margining:

±1%, ±3% or ±5%, Low Output Noise: 25μVRMS (10Hz to 100kHz), Parallelable: Use Two for a

10A Output, Stable with Low ESR Ceramic Output Capacitors (15μF Minimum),

28-Lead 4mm × 5mm QFN Package

LT3071 5A, Low Noise, Programmable Vout,

85mV Dropout Linear Regulator with

Analog Margining

Dropout Voltage: 85mV, Digitally Programmable VOUT: 0.8V to 1.8V, Analog Margining: ±10%,

Low Output Noise: 25μVRMS (10Hz to 100kHz), Parallelable: Use Two for a 10A Output, IMON

Output Current Monitor, Stable with Low ESR Ceramic Output Capacitors (15μF Minimum),

28-Lead 4mm × 5mm QFN Package

LT3080/

LT3080-1 1.1A, Parallelable, Low Noise, Low

Dropout Linear Regulator 300mV Dropout Voltage (2-Supply Operation), Low Noise: 40µVRMS, VIN: 1.2V to 36V, VOUT: 0V

to 35.7V, Current-Based Reference with 1-Resistor VOUT Set; Directly Parallelable (No Op Amp

Required), Stable with Ceramic Capacitors, TO-220, DD-PAK, SOT-223, MS8E and 3mm × 3mm

DFN-8 Packages; “-1” Version Has Integrated Internal Ballast Resistor

LT3082 200mA, Parallelable, Single Resistor,

Low Dropout Linear Regulator Outputs May Be Paralleled for Higher Output, Current or Heat Spreading, Wide Input Voltage

Range: 1.2V to 40V, Low Value Input/Output Capacitors Required: 0.22μF, Single Resistor Sets

Output Voltage, 8-Lead SOT-23, 3-Lead SOT-223 and 8-Lead 3mm × 3mm DFN Packages

LT3085 500mA, Parallelable, Low Noise,

Low Dropout Linear Regulator 275mV Dropout Voltage (2-Supply Operation), Low Noise: 40µVRMS, VIN: 1.2V to 36V, VOUT: 0V

to 35.7V, Current-Based Reference with 1-Resistor VOUT Set; Directly Parallelable (No Op Amp

Required), Stable with Ceramic Capacitors, MS8E and 2mm × 3mm DFN-6 Packages

LTC3026 1.5A, Low Input Voltage VLDO

Linear Regulator VIN: 1.14V to 3.5V (Boost Enabled), 1.14V to 5.5V (with External 5V), VDO = 0.1V, IQ = 950µA,

Stable with 10µF Ceramic Capacitors, 10-Lead MSOP-E and DFN-10 Packages