M24C64-WMN6TP/C - STMicroelectronics, Inc.

December 2007 Rev 12 1/38

M24128

M24C64 M24C32

128 Kbit, 64 Kbit and 32 Kbit serial I²C bus EEPROM

Features

■Two-wire I2C serial interface

supports 400 kHz protocol

■Single supply voltages (see Ta ble 1 for root

part numbers):

– 2.5 V to 5.5 V

– 1.8 V to 5.5 V

– 1.7 V to 5.5 V

■Write Control input

■Byte and Page Write

■Random and Sequential Read modes

■Self-timed programming cycle

■Automatic address incrementing

■Enhanced ESD/latch-up protection

■More than 1 Million write cycles

■More than 40-year data retention

■Packages

– ECOPACK® (RoHS compliant)

Table 1. Device summary

Reference Root part number Supply voltage

M24128

M24128-BW 2.5 V to 5.5V

M24128-BR 1.8 V to 5.5V

M24128-BF 1.7 V to 5.5V

M24C64

M24C64-W 2.5 V to 5.5V

M24C64-R 1.8 V to 5.5V

M24C64-F 1.7 V to 5.5V

M24C32

M24C32-W 2.5 V to 5.5V

M24C32-R 1.8 V to 5.5V

M24C32-F 1.7 V to 5.5V

PDIP8 (BN)

SO8 (MN)

150 mil width

TSSOP8 (DW)

169 mil width

UFDFPN8 (MB)

2 × 3 mm (MLP)

www.st.com

Contents M24128, M24C64, M24C32

2/38

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.5 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.6 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.6.1 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.6.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.3 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.4 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.5 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.6 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.7 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.8 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.9 ECC (error correction code) and Write cycling . . . . . . . . . . . . . . . . . . . . . 17

4.10 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 18

4.11 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.12 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.13 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.14 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.15 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

M24128, M24C64, M24C32 Contents

3/38

5 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

9 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

List of tables M24128, M24C64, M24C32

4/38

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 4. Address most significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 5. Address least significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 6. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 8. Operating conditions (M24xxx-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 9. Operating conditions (M24xxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 10. Operating conditions (M24xxx-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 11. AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 12. Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 13. DC characteristics (M24xxx-W, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 14. DC characteristics (M24xxx-W, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 15. DC characteristics (M24xxx-R - device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 16. DC characteristics (M24xxx-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 17. AC characteristics (M24xxx-W6, M24xxW3, M24xxR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 18. AC characteristics (M24xxx-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 19. PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package mechanical data. . . . . . . . . . . . 29

Table 20. SO8 narrow – 8 lead plastic small outline, 150 mils body width,

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 21. TSSOP8 – 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 31

Table 22. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead

2 × 3mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 23. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 24. Available M24C32 products (package, voltage range, temperature grade) . . . . . . . . . . . . 34

Table 25. Available M24C64 products (package, voltage range, temperature grade) . . . . . . . . . . . . 34

Table 26. Available M24128 products (package, voltage range, temperature grade) . . . . . . . . . . . . 34

Table 27. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

M24128, M24C64, M24C32 List of figures

5/38

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. DIP, SO, TSSOP and UFDFPN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. Maximum RP value versus bus parasitic capacitance (C) for an I2C bus . . . . . . . . . . . . . . 10

Figure 5. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 7. Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 8. Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 9. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 10. Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 11. AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 12. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 13. PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package outline . . . . . . . . . . . . . . . . . . . 29

Figure 14. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . 30

Figure 15. TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 16. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead

2 × 3mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Description M24128, M24C64, M24C32

6/38

1 Description

The M24C32, M24C64 and M24128 devices are I2C-compatible electrically erasable

programmable memories (EEPROM). They are organized as 4096 × 8 bits, 8192 × 8 bits

and 16384 × 8 bits, respectively.

In order to meet environmental requirements, ST offers these devices in ECOPACK®

packages.

ECOPACK® packages are Lead-free and RoHS compliant. ECOPACK is an ST trademark.

ECOPACK specifications are available at: www.st.com.

Figure 1. Logic diagram

I2C uses a two-wire serial interface, comprising a bi-directional data line and a clock line.

The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the

I2C bus definition.

The device behaves as a slave in the I2C protocol, with all memory operations synchronized

by the serial clock. Read and Write operations are initiated by a Start condition, generated

by the bus master. The Start condition is followed by a device select code and Read/Write

bit (RW) (as described in Ta b l e 3 ), terminated by an acknowledge bit.

When writing data to the memory, the device inserts an acknowledge bit during the 9th bit

time, following the bus master’s 8-bit transmission. When data is read by the bus master, the

bus master acknowledges the receipt of the data byte in the same way. Data transfers are

terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.

AI01844e

E0-E2 SDA

VCC

M24128

M24C64

M24C32

SCL

VSS

M24128, M24C64, M24C32 Description

7/38

Figure 2. DIP, SO, TSSOP and UFDFPN connections

1. See Package mechanical section for package dimensions, and how to identify pin-1.

Table 2. Signal names

Signal name Function Direction

E0, E1, E2 Chip Enable Input

SDA Serial Data I/O

SCL Serial Clock Input

WC Write Control Input

VCC Supply voltage

VSS Ground

SDAVSS

SCL

WCE1

E0 VCC

AI01845e

M24128

M24C64

M24C32

Signal description M24128, M24C64, M24C32

8/38

2 Signal description

2.1 Serial Clock (SCL)

This input signal is used to strobe all data in and out of the device. In applications where this

signal is used by slave devices to synchronize the bus to a slower clock, the bus master

must have an open drain output, and a pull-up resistor must be connected from Serial Clock

(SCL) to VCC. (Figure 4 indicates how the value of the pull-up resistor can be calculated). In

most applications, though, this method of synchronization is not employed, and so the pull-

up resistor is not necessary, provided that the bus master has a push-pull (rather than open

drain) output.

2.2 Serial Data (SDA)

This bi-directional signal is used to transfer data in or out of the device. It is an open drain

output that may be wire-OR’ed with other open drain or open collector signals on the bus. A

pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 4 indicates how

the value of the pull-up resistor can be calculated).

2.3 Chip Enable (E0, E1, E2)

These input signals are used to set the value that is to be looked for on the three least

significant bits (b3, b2, b1) of the 7-bit device select code. These inputs must be tied to VCC

or VSS, to establish the device select code as shown in Figure 3. When not connected (left

floating), these inputs are read as low (0,0,0).

Figure 3. Device select code

2.4 Write Control (WC)

This input signal is useful for protecting the entire contents of the memory from inadvertent

write operations. Write operations are disabled to the entire memory array when Write

Control (WC) is driven high. When unconnected, the signal is internally read as VIL, and

Write operations are allowed.

When Write Control (WC) is driven high, device select and Address bytes are

acknowledged, Data bytes are not acknowledged.

Ai12806

VCC

M24xxx

VSS

VCC

M24xxx

VSS

M24128, M24C64, M24C32 Signal description

9/38

2.5 VSS ground

VSS is the reference for the VCC supply voltage.

2.6 Supply voltage (VCC)

2.6.1 Operating supply voltage VCC

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage

within the specified [VCC(min), VCC(max)] range must be applied (see Ta bl e 9 and Ta bl e 1 0 ).

In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line

with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS

package pins.

This voltage must remain stable and valid until the end of the transmission of the instruction

and, for a Write instruction, until the completion of the internal write cycle (tW).

2.6.2 Power-up conditions

When the power supply is turned on, VCC rises from VSS to VCC. The VCC rise time must not

vary faster than 1V/µs.

2.6.3 Device reset

In order to prevent inadvertent Write operations during power-up, a power on reset (POR)

circuit is included. At power-up (continuous rise of VCC), the device does not respond to any

instruction until VCC has reached the power on reset threshold voltage (this threshold is

lower than the minimum VCC operating voltage defined in Ta b le 9 and Ta bl e 1 0 ). Until VCC

passes over the POR threshold, the device is reset and in Standby Power mode.

In a similar way, during power-down (continuous decay of VCC), as soon as VCC drops below

the POR threshold voltage, the device is reset and stops responding to any instruction sent

to it.

2.6.4 Power-down conditions

During power-down (continuous decay of VCC), the device must be in Standby Power mode

(mode reached after decoding a Stop condition, assuming that there is no internal Write

cycle in progress).

Signal description M24128, M24C64, M24C32

10/38

Figure 4. Maximum RP value versus bus parasitic capacitance (C) for an I2C bus

Figure 5. I2C bus protocol

100

10 100 1000

Bus line capacitor (pF)

Bus line pull-up resistor

(k )

fC = 400 kHz, tLOW = 1.3 µs

Rbus x Cbus time

constant must be less than

500 ns

I²C bus

master M24xxx

bus

SCL

SDA

ai14796

SCL

SDA

SCL

SDA

Start

Condition

SDA

Input

SDA

Change

AI00792B

Stop

Condition

123 789

MSB ACK

Start

Condition

SCL 123 789

MSB ACK

Stop

Condition

M24128, M24C64, M24C32 Signal description

11/38

Table 3. Device select code

Device type identifier(1)

1. The most significant bit, b7, is sent first.

Chip Enable address(2)

2. E0, E1 and E2 are compared against the respective external pins on the memory device.

b7 b6 b5 b4 b3 b2 b1 b0

Device select code 1 0 1 0 E2 E1 E0 RW

Table 4. Address most significant byte

b15 b14 b13 b12 b11 b10 b9 b8

Table 5. Address least significant byte

b7 b6 b5 b4 b3 b2 b1 b0

Memory organization M24128, M24C64, M24C32

12/38

3 Memory organization

The memory is organized as shown in Figure 6.

Figure 6. Block diagram

AI06899

E0 Control Logic High Voltage

Generator

I/O Shift Register

Address Register

and Counter

Data

1 Page

X Decoder

Y Decoder

SCL

SDA

M24128, M24C64, M24C32 Device operation

13/38

4 Device operation

The device supports the I2C protocol. This is summarized in Figure 5. Any device that sends

data on to the bus is defined to be a transmitter, and any device that reads the data to be a

receiver. The device that controls the data transfer is known as the bus master, and the

other as the slave device. A data transfer can only be initiated by the bus master, which will

also provide the serial clock for synchronization. The M24C32, M24C64 and M24128

devices are always slaves in all communications.

4.1 Start condition

Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in

the high state. A Start condition must precede any data transfer command. The device

continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock

(SCL) for a Start condition, and will not respond unless one is given.

4.2 Stop condition

Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable

and driven high. A Stop condition terminates communication between the device and the

bus master. A Read command that is followed by NoAck can be followed by a Stop condition

to force the device into the Standby mode. A Stop condition at the end of a Write command

triggers the internal Write cycle.

4.3 Acknowledge bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,

whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits

of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to

acknowledge the receipt of the eight data bits.

4.4 Data Input

During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock

(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge

of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock

(SCL) is driven low.

Device operation M24128, M24C64, M24C32

14/38

4.5 Memory addressing

To start communication between the bus master and the slave device, the bus master must

initiate a Start condition. Following this, the bus master sends the device select code, shown

in Ta b l e 3 (on Serial Data (SDA), most significant bit first).

The device select code consists of a 4-bit device type identifier, and a 3-bit Chip Enable

“Address” (E2, E1, E0). To address the memory array, the 4-bit device type identifier is

1010b.

Up to eight memory devices can be connected on a single I2C bus. Each one is given a

unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the device select code is

received, the device only responds if the Chip Enable Address is the same as the value on

the Chip Enable (E0, E1, E2) inputs.

The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.

If a match occurs on the device select code, the corresponding device gives an

acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match

the device select code, it deselects itself from the bus, and goes into Standby mode.

Table 6. Operating modes

Mode RW bit WC(1)

1. X = VIH or VIL.

Bytes Initial sequence

Current Address

Read 1 X 1 Start, device select, RW = 1

Random Address

Read

0X 1Start, device select, RW = 0, Address

1 X reStart, device select, RW = 1

Sequential Read 1 X ≥ 1 Similar to Current or Random Address

Read

Byte Write 0 VIL 1 Start, device select, RW = 0

Page Write 0 VIL

≤ 32 for M24C64

and M24C32 Start, device select, RW = 0

≤ 64 for M24128

M24128, M24C64, M24C32 Device operation

15/38

Figure 7. Write mode sequences with WC = 1 (data write inhibited)

Stop

Start

Byte Write Dev select Byte address Byte address Data in

Start

Page Write Dev select Byte address Byte address Data in 1

Data in 2

AI01120d

Page Write

(cont'd)

WC (cont'd)

Stop

Data in N

ACK ACK ACK NO ACK

R/W

ACK ACK ACK NO ACK

R/W

NO ACK NO ACK

Device operation M24128, M24C64, M24C32

16/38

4.6 Write operations

Following a Start condition the bus master sends a device select code with the Read/Write

bit (RW) reset to 0. The device acknowledges this, as shown in Figure 8, and waits for two

address bytes. The device responds to each address byte with an acknowledge bit, and

then waits for the data Byte.

Writing to the memory may be inhibited if Write Control (WC) is driven high. Any Write

instruction with Write Control (WC) driven high (during a period of time from the Start

condition until the end of the two address bytes) will not modify the memory contents, and

the accompanying data bytes are not acknowledged, as shown in Figure 7.

Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant

Byte (Ta b l e 4 ) is sent first, followed by the Least Significant Byte (Ta b le 5 ). Bits b15 to b0

form the address of the byte in memory.

When the bus master generates a Stop condition immediately after the Ack bit (in the “10th

bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle is

triggered. A Stop condition at any other time slot does not trigger the internal Write cycle.

After the Stop condition, the delay tW, and the successful completion of a Write operation,

the device’s internal address counter is incremented automatically, to point to the next byte

address after the last one that was modified.

During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does

not respond to any requests.

4.7 Byte Write

After the device select code and the address bytes, the bus master sends one data byte. If

the addressed location is Write-protected, by Write Control (WC) being driven high, the

device replies with NoAck, and the location is not modified. If, instead, the addressed

location is not Write-protected, the device replies with Ack. The bus master terminates the

transfer by generating a Stop condition, as shown in Figure 8.

4.8 Page Write

The Page Write mode allows up to 32 bytes (for the M24C32 and M24C64) or 64 bytes (for

the M24128) to be written in a single Write cycle, provided that they are all located in the

same ’row’ in the memory: that is, the most significant memory address bits (b13-b6 for

M24128, b12-b5 for M24C64, and b11-b5 for M24C32) are the same. If more bytes are sent

than will fit up to the end of the row, a condition known as ‘roll-over’ occurs. This should be

avoided, as data starts to become overwritten in an implementation dependent way.

The bus master sends from 1 to 32 bytes of data (for the M24C32 and M24C64) or 64 bytes

of data (for the M24128), each of which is acknowledged by the device if Write Control (WC)

is low. If Write Control (WC) is high, the contents of the addressed memory location are not

modified, and each data byte is followed by a NoAck. After each byte is transferred, the

internal byte address counter (inside the page) is incremented. The transfer is terminated by

the bus master generating a Stop condition.

M24128, M24C64, M24C32 Device operation

17/38

Figure 8. Write mode sequences with WC = 0 (data write enabled)

4.9 ECC (error correction code) and Write cycling

The M24128-BFMB6 and M24C64-FMB6 salestypes offer an ECC (error correction code)

logic which compares each 4-byte word with its six associated EEPROM ECC bits. As a

result, if a single bit out of 4 bytes of data happens to be erroneous during a read operation,

the ECC detects it and replaces it by the correct value. The read reliability is therefore much

improved by the use of this feature.

Note however that even if a single byte has to be written, 4 bytes are internally modified

(plus the ECC word), that is, the addressed byte is cycled together with the three other bytes

making up the word. It is therefore recommended to write by packets of 4 bytes in order to

benefit from the larger amount of write cycles.

All M24C32, M24C64 and M24128 devices are qualified at 1 million (1 000 000) write

cycles; the M24128-BFMB6 and M24C64-FMB6 are qualified (at 1 million write cycles),

using a cycling routine that writes to the device by multiples of 4-byte words.

Stop

Start

Byte Write Dev Select Byte address Byte address Data in

Start

Page Write Dev Select Byte address Byte address Data in 1

Data in 2

AI01106d

Page Write

(cont'd)

WC (cont'd)

Stop

Data in N

ACK

R/W

ACK ACK ACK

ACK ACK ACK ACK

R/W

ACKACK

Device operation M24128, M24C64, M24C32

18/38

Figure 9. Write cycle polling flowchart using ACK

4.10 Minimizing system delays by polling on ACK

During the internal Write cycle, the device disconnects itself from the bus, and writes a copy

of the data from its internal latches to the memory cells. The maximum Write time (tw) is

shown in Ta bl e 1 7 and Ta b l e 1 8 , but the typical time is shorter. To make use of this, a polling

sequence can be used by the bus master.

The sequence, as shown in Figure 9, is:

1. Initial condition: a Write cycle is in progress.

2. Step 1: the bus master issues a Start condition followed by a device select code (the

first byte of the new instruction).

3. Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and

the bus master goes back to Step 1. If the device has terminated the internal Write

cycle, it responds with an Ack, indicating that the device is ready to receive the second

part of the instruction (the first byte of this instruction having been sent during Step 1).

Write cycle

in progress

AI01847d

operation is

addressing the

memory

Start condition

Device select

with RW = 0

ACK

Returned

YES

YESNO

ReStart

Stop

Data for the

Write operation

Device select

with RW = 1

Send address

and receive ACK

First byte of instruction

with RW = 0 already

decoded by the device

YESNO Start

condition

Continue the

Write operation

Continue the

Random Read operation

M24128, M24C64, M24C32 Device operation

19/38

Figure 10. Read mode sequences

1. The seven most significant bits of the device select code of a Random Read (in the 1st and 4th bytes) must

be identical.

Start

Dev select * Byte address Byte address

Start

Dev select Data out 1

AI01105d

Data out N

Stop

Start

Current

Address

Read

Dev select Data out

Random

Address

Read

Stop

Start

Dev select * Data out

Sequential

Current

Read

Stop

Data out N

Start

Dev select * Byte address Byte address

Sequential

Random

Read

Start

Dev select * Data out 1

Stop

ACK

R/W

NO ACK

ACK

R/W

ACK ACK ACK

R/W

ACK ACK ACK NO ACK

R/W

NO ACK

ACK ACK ACK

R/W

ACK ACK

R/W

ACK NO ACK

Device operation M24128, M24C64, M24C32

20/38

4.11 Read operations

Read operations are performed independently of the state of the Write Control (WC) signal.

After the successful completion of a Read operation, the device’s internal address counter is

incremented by one, to point to the next byte address.

4.12 Random Address Read

A dummy Write is first performed to load the address into this address counter (as shown in

Figure 10) but without sending a Stop condition. Then, the bus master sends another Start

condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The

device acknowledges this, and outputs the contents of the addressed byte. The bus master

must not acknowledge the byte, and terminates the transfer with a Stop condition.

4.13 Current Address Read

For the Current Address Read operation, following a Start condition, the bus master only

sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges

this, and outputs the byte addressed by the internal address counter. The counter is then

incremented. The bus master terminates the transfer with a Stop condition, as shown in

Figure 10, without acknowledging the Byte.

4.14 Sequential Read

This operation can be used after a Current Address Read or a Random Address Read. The

bus master does acknowledge the data byte output, and sends additional clock pulses so

that the device continues to output the next byte in sequence. To terminate the stream of

bytes, the bus master must not acknowledge the last byte, and must generate a Stop

condition, as shown in Figure 10.

The output data comes from consecutive addresses, with the internal address counter

automatically incremented after each byte output. After the last memory address, the

address counter ‘rolls-over’, and the device continues to output data from memory address

00h.

4.15 Acknowledge in Read mode

For all Read commands, the device waits, after each byte read, for an acknowledgment

during the 9th bit time. If the bus master does not drive Serial Data (SDA) low during this

time, the device terminates the data transfer and switches to its Standby mode.

M24128, M24C64, M24C32 Initial delivery state

21/38

5 Initial delivery state

The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).

6 Maximum rating

Stressing the device outside the ratings listed in Ta b le 7 may cause permanent damage to

the device. These are stress ratings only, and operation of the device at these, or any other

conditions outside those indicated in the Operating sections of this specification, is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability. Refer also to the STMicroelectronics SURE Program and other relevant

quality documents.

Table 7. Absolute maximum ratings

Symbol Parameter Min. Max. Unit

TAAmbient operating temperature –40 130 °C

TSTG Storage temperature –65 150 °C

TLEAD

Lead temperature during soldering see note (1)

1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®

7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)

2002/95/EU.

°C

PDIP-specific lead temperature during soldering 260(2)

2. TLEAD max must not be applied for more than 10 s.

°C

VIO Input or output range –0.50 6.5 V

VCC Supply voltage –0.50 6.5 V

VESD Electrostatic discharge voltage (human body model)(3)

3. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500 Ω, R2=500 Ω)

–4000 4000 V

DC and AC parameters M24128, M24C64, M24C32

22/38

7 DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC characteristic tables that

follow are derived from tests performed under the measurement conditions summarized in

the relevant tables. Designers should check that the operating conditions in their circuit

match the measurement conditions when relying on the quoted parameters.

Figure 11. AC test measurement I/O waveform

Table 8. Operating conditions (M24xxx-W)

Symbol Parameter Min. Max. Unit

VCC Supply voltage 2.5 5.5 V

Ambient operating temperature (device grade 6) –40 85 °C

Ambient operating temperature (device grade 3) –40 125 °C

Table 9. Operating conditions (M24xxx-R)

Symbol Parameter Min. Max. Unit

VCC Supply voltage 1.8 5.5 V

TAAmbient operating temperature –40 85 °C

Table 10. Operating conditions (M24xxx-F)

Symbol Parameter Min. Max. Unit

VCC Supply voltage 1.7 5.5 V

Ambient operating temperature (device grade 6) –40 85 °C

Ambient operating temperature (device grade 5) –20 85 °C

Table 11. AC test measurement conditions

Symbol Parameter Min. Max. Unit

CLLoad capacitance 100 pF

Input rise and fall times 50 ns

Input levels 0.2VCC to 0.8VCC V

Input and output timing reference levels 0.3VCC to 0.7VCC V

AI00825B

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Input and Output

Timing Reference Levels

Input Levels

M24128, M24C64, M24C32 DC and AC parameters

23/38

Table 12. Input parameters

Symbol Parameter Test condition Min. Max. Unit

CIN Input capacitance (SDA) 8 pF

CIN Input capacitance (other pins) 6 pF

ZWCL(1)

1. Characterized only.

WC input impedance VIN < 0.3VCC 50 200 kΩ

ZWCH(1) WC input impedance VIN > 0.7VCC 500 kΩ

tNS(1) Pulse width ignored

(Input filter on SCL and SDA) 200 ns

Table 13. DC characteristics (M24xxx-W, device grade 6)

Symbol Parameter Test condition

(in addition to those in Tabl e 8)Min. Max. Unit

ILI

Input leakage current

(SCL, SDA, E2, E1, E0)

VIN = VSS or VCC

device in Standby mode ± 2 µA

ILO Output leakage current SDA in Hi-Z, external voltage

applied on SDA: VSS or VCC ± 2 µA

ICC Supply current (Read) 2.5 V < VCC < 5.5 V, fc = 400 kHz 2 mA

ICC0 Supply current (Write) During tW, 2.5 V < VCC < 5.5 V 5(1)

1. Characterized value, not tested in production.

ICC1

Standby supply current VIN = VSS or VCC,

VCC = 5.5 V 5µA

Standby supply current VIN = VSS or VCC,

VCC = 2.5 V 2µA

VIL

Input low voltage (SDA,

SCL, WC)–0.45 0.3VCC V

VIH

Input high voltage (SDA,

SCL, WC)0.7VCC VCC+0.6 V

VOL Output low voltage IOL = 2.1 mA, VCC = 2.5 V or

IOL = 3 mA, VCC = 5.5 V 0.4 V

DC and AC parameters M24128, M24C64, M24C32

24/38

Table 14. DC characteristics (M24xxx-W, device grade 3)

Symbol Parameter Test condition

(in addition to those in Tabl e 8)Min. Max. Unit

ILI

Input leakage current

(SCL, SDA, E2, E1, E0)

VIN = VSS or VCC

device in Standby mode ± 2 µA

ILO Output leakage current SDA in Hi-Z, external voltage

applied on SDA: VSS or VCC ± 2 µA

ICC Supply current (Read) 2.5 V < VCC < 5.5 V, fc = 400 kHz 2 mA

ICC0 Supply current (Write) During tW, 2.5 V < VCC < 5.5 V 5(1)

1. Characterized value, not tested in production.

ICC1 Standby supply current VIN = VSS or VCC,

2.5 V < VCC < 5.5 V 10 µA

VIL

Input low voltage (SDA,

SCL, WC)–0.45 0.3VCC V

VIH

Input high voltage (SDA,

SCL, WC)0.7VCC VCC+0.6 V

VOL Output low voltage IOL = 2.1 mA, VCC = 2.5 V or

IOL = 3 mA, VCC = 5.5 V 0.4 V

Table 15. DC characteristics (M24xxx-R - device grade 6)

Symbol Parameter Test condition

(in addition to those in Tabl e 9 )Min. Max. Unit

ILI

Input leakage current

(SCL, SDA, E2, E1, E0)

VIN = VSS or VCC

device in Standby mode ± 2 µA

ILO Output leakage current SDA Hi-Z, external voltage

applied on SDA: VSS or VCC

± 2 µA

ICC Supply current (Read) VCC = 1.8 V, fc = 400 kHz 0.8 mA

ICC0 Supply current (Write) During tW, 1.8 V < VCC < 2.5 V 3(1)

1. Characterized value, not tested in production.

ICC1 Standby supply current VIN = VSS or VCC,

1.8 V < VCC < 2.5 V 1µA

VIL

Input low voltage (SDA,

SCL, WC)

1.8 V ≤ VCC < 2.5 V –0.45 0.25 VCC V

2.5 V ≤ VCC < 5.5 V –0.45 0.3 VCC V

VIH

Input high voltage (SDA,

SCL, WC)

1.8 V ≤ VCC < 2.5 V 0.75VCC VCC+1 V

2.5 V ≤ VCC < 5.5 V 0.7VCC VCC+1 V

VOL Output low voltage IOL = 1 mA, VCC = 1.8 V 0.2 V

M24128, M24C64, M24C32 DC and AC parameters

25/38

Table 16. DC characteristics (M24xxx-F)(1)

1. Preliminary data.

Symbol Parameter

Test condition

(in addition to those in

Tab l e 10 )

Min. Max. Unit

ILI

Input leakage current

(SCL, SDA, E2, E1, E0)

VIN = VSS or VCC

device in Standby mode ± 2 µA

ILO Output leakage current SDA Hi-Z, external voltage

applied on SDA: VSS or VCC ± 2 µA

ICC Supply current (Read) VCC =1.7 V, fc = 400 kHz 0.8 mA

ICC0 Supply current (Write) During tW, 1.7 V < VCC < 2.5

V3(2)

2. Characterized value, not tested in production.

ICC1 Standby supply current VIN = VSS or VCC,

1.7 V < VCC < 2.5 V 1µA

VIL

Input low voltage (SDA, SCL,

WC)

1.8 V ≤ VCC < 2.5 V –0.45 0.25 VCC V

2.5 V ≤ VCC < 5.5 V –0.45 0.3 VCC V

VIH

Input high voltage (SDA, SCL,

WC)

1.8 V ≤ VCC < 2.5 V 0.75VCC VCC+1 V

2.5 V ≤ VCC < 5.5 V 0.7VCC VCC+1 V

VOL Output low voltage IOL = 0.7 mA, VCC = 1.7 V 0.2 V

DC and AC parameters M24128, M24C64, M24C32

26/38

Table 17. AC characteristics (M24xxx-W6, M24xxW3, M24xxR6)

Test conditions specified in Tabl e 8 and Tabl e 9

Symbol Alt. Parameter Min. Max. Unit

fCfSCL Clock frequency 400 kHz

tCHCL tHIGH Clock pulse width high 600 ns

tCLCH tLOW Clock pulse width low 1300 ns

tXH1XH2(1)

1. Values recommended by the I²C-bus Fast-Mode specification.

tRInput signal rise time 20 300 ns

tXL1XL2(1) tFInput signal fall time 20 300 ns

tDL1DL2 tFSDA (out) fall time 20 100 ns

tDXCX tSU:DAT Data in set up time 100 ns

tCLDX tHD:DAT Data in hold time 0 ns

tCLQX tDH Data out hold time 200 ns

tCLQV(2)(3)

2. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or

rising edge of SDA.

3. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8VCC in a

compatible way with the I2C specification (which specifies tSU:DAT (min) = 100 ns), assuming that the Rbus

× Cbus time constant is less than 500 ns (as specified in Figure 4).

tAA Clock low to next data valid (access time) 200 900 ns

tCHDX(4)

4. For a reStart condition, or following a Write cycle.

tSU:STA Start condition set up time 600 ns

tDLCL tHD:STA Start condition hold time 600 ns

tCHDH tSU:STO Stop condition set up time 600 ns

tDHDL tBUF

Time between Stop condition and next Start

condition 1300 ns

tWWrite time 5(5)

5. For production lots assembled from 1st July 2007 (data code 727: week27, year 2007), the M24xxx-R

(1.8 V to 5.5 V range) memories are specified with tW = 5 ms (instead of 10ms).

M24128, M24C64, M24C32 DC and AC parameters

27/38

Table 18. AC characteristics (M24xxx-F)

Test conditions specified in Ta bl e 1 0

Symbol Alt. Parameter Min. Max. Unit

fCfSCL Clock frequency 400 kHz

tCHCL tHIGH Clock pulse width high 600 ns

tCLCH tLOW Clock pulse width low 1300 ns

tXH1XH2(1)

1. Values recommended by the I²C-bus Fast-Mode specification.

tRInput signal rise time 20 300 ns

tXL1XL2(1) tFInput signal fall time 20 300 ns

tDL1DL2 tFSDA (out) fall time 20 100 ns

tDXCX tSU:DAT Data in set up time 100 ns

tCLDX tHD:DAT Data in hold time 0 ns

tCLQX tDH Data out hold time 200 ns

tCLQV(2)(3)

2. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or

rising edge of SDA.

3. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8VCC in a

compatible way with the I2C specification (which specifies tSU:DAT (min) = 100 ns), assuming that the Rbus

× Cbus time constant is less than 500 ns (as specified in Figure 4).

tAA Clock low to next data valid (access time) 200 900 ns

tCHDX(4)

4. For a reStart condition, or following a Write cycle.

tSU:STA Start condition set up time 600 ns

tDLCL tHD:STA Start condition hold time 600 ns

tCHDH tSU:STO Stop condition set up time 600 ns

tDHDL tBUF

Time between Stop condition and next Start

condition 1300 ns

tWWrite time 10(5)

5. For temperature range 6: tW(max) = 5 ms.

For temperature range 5: tW(max) = 10 ms.

DC and AC parameters M24128, M24C64, M24C32

28/38

Figure 12. AC waveforms

SCL

SDA In

SCL

SDA Out

SCL

SDA In

tCHCL

tDLCL

tCHDX

Start

condition

tCLCH

tDXCXtCLDX

SDA

Input

SDA

Change

tCHDH tDHDL

Stop

condition

Data valid

tCLQV tCLQX

tCHDH

Stop

condition

tCHDX

Start

condition

Write cycle

AI00795e

Start

condition

tCHCL

tXH1XH2

tXL1XL2

Data valid

tDL1DL2

M24128, M24C64, M24C32 Package mechanical

29/38

8 Package mechanical

Figure 13. PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package outline

1. Drawing is not to scale.

Table 19. PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package mechanical data

Symbol

millimeters inches(1)

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Typ. Min. Max. Typ. Min. Max.

A 5.33 0.2098

A1 0.38 0.0150

A2 3.30 2.92 4.95 0.1299 0.1150 0.1949

b 0.46 0.36 0.56 0.0181 0.0142 0.0220

b2 1.52 1.14 1.78 0.0598 0.0449 0.0701

c 0.25 0.20 0.36 0.0098 0.0079 0.0142

D 9.27 9.02 10.16 0.3650 0.3551 0.4000

E 7.87 7.62 8.26 0.3098 0.3000 0.3252

E1 6.35 6.10 7.11 0.2500 0.2402 0.2799

e 2.54 – –0.1000– –

eA 7.62 – – 0.3000 – –

eB 10.92 0.4299

L 3.30 2.92 3.81 0.1299 0.1150 0.1500

PDIP-B

Package mechanical M24128, M24C64, M24C32

30/38

Figure 14. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package

outline

1. Drawing is not to scale.

Table 20. SO8 narrow – 8 lead plastic small outline, 150 mils body width,

package mechanical data

Symbol

millimeters inches(1)

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Typ Min Max Typ Min Max

A 1.75 0.0689

A1 0.10 0.25 0.0039 0.0098

A2 1.25 0.0492

b 0.28 0.48 0.0110 0.0189

c 0.17 0.23 0.0067 0.0091

ccc 0.10 0.0039

D 4.90 4.80 5.00 0.1929 0.1890 0.1969

E 6.00 5.80 6.20 0.2362 0.2283 0.2441

E1 3.90 3.80 4.00 0.1535 0.1496 0.1575

e1.27– –0.0500– –

h 0.25 0.50

k0°8°0°8°

L 0.40 1.27 0.0157 0.0500

L1 1.04 0.0410

SO-A

ccc

h x 45˚

0.25 mm

GAUGE PLANE

M24128, M24C64, M24C32 Package mechanical

31/38

Figure 15. TSSOP8 – 8 lead thin shrink small outline, package outline

1. Drawing is not to scale.

Table 21. TSSOP8 – 8 lead thin shrink small outline, package mechanical data

Symbol

millimeters inches(1)

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Typ. Min. Max. Typ. Min. Max.

A 1.200 0.0472

A1 0.050 0.150 0.0020 0.0059

A2 1.000 0.800 1.050 0.0394 0.0315 0.0413

b 0.190 0.300 0.0075 0.0118

c 0.090 0.200 0.0035 0.0079

CP 0.100 0.0039

D 3.000 2.900 3.100 0.1181 0.1142 0.1220

e 0.650 – – 0.0256 – –

E 6.400 6.200 6.600 0.2520 0.2441 0.2598

E1 4.400 4.300 4.500 0.1732 0.1693 0.1772

L 0.600 0.450 0.750 0.0236 0.0177 0.0295

L1 1.000 0.0394

α0° 8° 0° 8°

TSSOP8AM

EE1

A2A

Package mechanical M24128, M24C64, M24C32

32/38

Figure 16. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead

2 × 3mm, package outline

1. Drawing is not to scale.

Table 22. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead

2 × 3mm, package mechanical data

Symbol

millimeters inches(1)

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Typ Min Max Typ Min Max

A 0.55 0.50 0.60 0.0217 0.0197 0.0236

A1 0.02 0.00 0.05 0.0008 0 0.0020

b 0.25 0.20 0.30 0.0098 0.0079 0.0118

D 2.00 1.90 2.10 0.0787 0.0748 0.0827

D2 1.60 1.50 1.70 0.0630 0.0591 0.0669

ddd 0.08 0.0031

E 3.00 2.90 3.10 0.1181 0.1142 0.1220

E2 0.20 0.10 0.30 0.0079 0.0039 0.0118

e0.50– –0.0197– –

L 0.45 0.40 0.50 0.0177 0.0157 0.0197

L1 0.15 0.0059

L3 0.30 0.0118

UFDFPN-01

ddd

M24128, M24C64, M24C32 Part numbering

33/38

9 Part numbering

For a list of available options (speed, package, etc.) or for further information on any aspect

of this device, please contact your nearest ST sales office.

The category of second-level interconnect is marked on the package and on the inner box

label, in compliance with JEDEC Standard JESD97. The maximum ratings related to

soldering conditions are also marked on the inner box label.

Table 23. Ordering information scheme

Example: M24C32– W MN 6 T P /C

Device type

M24 = I2C serial access EEPROM

Device function

128–B = 128 Kbit (16384 x 8)

C64– = 64 Kbit (8192 x 8)

C32– = 32 Kbit (4096 x 8)

Operating voltage

W = VCC = 2.5 V to 5.5 V

R = VCC = 1.8 V to 5.5 V

F = VCC = 1.7 V to 5.5 V

Package

BN = PDIP8

MN = SO8 (150 mil width)

DW = TSSOP8 (169 mil width)

MB = UFDFPN8 (MLP8)

Device grade

6 = Industrial: device tested with standard test flow over –40 to 85 °C

3 = Automotive: device tested with high reliability certified flow(1) over –40 to 125°C.

1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment.

The high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask your

nearest ST sales office for a copy.

5 = Consumer: device tested with standard test flow over –20 to 85°C

Option

blank = Standard Packing

T = Tape and Reel Packing

Plating technology

blank = Standard SnPb plating

P or G = ECOPACK® (RoHS compliant)

Process

P = F6DP26% Chartered

C = F6DP26% AmMokio

Part numbering M24128, M24C64, M24C32

34/38

Table 24. Available M24C32 products (package, voltage range, temperature grade)

Package M24C32-F

1.7 V to 5.5 V

M24C32-R

1.8 V to 5.5 V

M24C32-W

2.5 V to 5.5 V

DIP8 (BN) - - Grade6

SO8N (MN) - Grade 6 Grade 3

Grade 6

TSSOP8 (DW) Grade 5 Grade 6 Grade 6

MLP8 (MB) Grade 5 Grade 6 -

Table 25. Available M24C64 products (package, voltage range, temperature grade)

Package M24C64-F

1.7 V to 5.5 V

M24C64-R

1.8 V to 5.5 V

M24C64-W

2.5 V to 5.5 V

DIP8 (BN) - - Grade6

SO8N (MN) - Grade 6 Grade 3

Grade 6

TSSOP8 (DW) Grade 5 Grade 6 Grade 6

MLP8 (MB) Grade 6 Grade 6 -

Table 26. Available M24128 products (package, voltage range, temperature grade)

Package M24128-BF

1.7 V to 5.5 V

M24128-BR

1.8 V to 5.5 V

M24128-BW

2.5 V to 5.5 V

DIP8 (BN) - - -

SO8N (MN) - Grade 6 Grade 3

Grade 6

TSSOP8 (DW) - Grade 6 Grade 6

MLP8 (MB) Grade 6 Grade 6 -

M24128, M24C64, M24C32 Revision history

35/38

10 Revision history

Table 27. Document revision history

Date Revision Changes

22-Dec-1999 2.3 TSSOP8 package in place of TSSOP14 (pp 1, 2, OrderingInfo,

PackageMechData).

28-Jun-2000 2.4 TSSOP8 package data corrected

31-Oct-2000 2.5

References to Temperature Range 3 removed from Ordering Information

Voltage range -S added, and range -R removed from text and tables

throughout.

20-Apr-2001 2.6

Lead Soldering Temperature in the Absolute Maximum Ratings table

amended

Write Cycle Polling Flow Chart using ACK illustration updated

References to PSDIP changed to PDIP and Package Mechanical data

updated

16-Jan-2002 2.7

Test condition for ILI made more precise, and value of ILI for E2-E0 and

WC added

-R voltage range added

02-Aug-2002 2.8

Document reformatted using new template.

TSSOP8 (3x3mm² body size) package (MSOP8) added.

5ms write time offered for 5V and 2.5V devices

04-Feb-2003 2.9 SO8W package removed. -S voltage range removed

27-May-2003 2.10 TSSOP8 (3x3mm² body size) package (MSOP8) removed

22-Oct-2003 3.0

Table of contents, and Pb-free options added. Minor wording changes in

Summary Description, Power-On Reset, Memory Addressing, Write

Operations, Read Operations. VIL(min) improved to -0.45V.

01-Jun-2004 4.0

Absolute Maximum Ratings for VIO(min) and VCC(min) improved.

Soldering temperature information clarified for RoHS compliant devices.

Device Grade clarified

04-Nov-2004 5.0

Product List summary table added. Device Grade 3 added. 4.5-5.5V

range is Not for New Design. Some minor wording changes. AEC-Q100-

002 compliance. tNS(max) changed. VIL(min) is the same on all input

pins of the device. ZWCL changed.

05-Jan-2005 6.0 UFDFPN8 package added. Small text changes.

Revision history M24128, M24C64, M24C32

36/38

29-Jun-2006 7

Document converted to new ST template.

M24C32 and M24C64 products (4.5 to 5.5V supply voltage) removed.

M24C64 and M24C32 products (1.7 to 5.5V supply voltage) added.

Section 2.3: Chip Enable (E0, E1, E2) and Section 2.4: Write Control

(WC) modified, Section 2.6: Supply voltage (VCC) added and replaces

Power On Reset: VCC Lock-Out Write Protect section.

TA added, Note 1 updated and TLEAD specified for PDIP packages in

Table 7: Absolute maximum ratings.

ICC0 added, ICC voltage conditions changed and ICC1 specified over the

whole voltage range in Table 13: DC characteristics (M24xxx-W, device

grade 6).

ICC0 added, ICC frequency conditions changed and ICC1 specified over

the whole voltage range in Table 15: DC characteristics (M24xxx-R -

device grade 6).

tW modified in Table 17: AC characteristics (M24xxx-W6, M24xxW3,

M24xxR6).

SO8N package specifications updated (see Figure 14 and Ta bl e 2 0 ).

Device grade 5 added, B and P Process letters added to Ta ble 2 3:

Ordering information scheme. Small text changes.

03-Jul-2006 8

ICC1 modified in Table 13: DC characteristics (M24xxx-W, device grade

6).

Note 1 added to Table 16: DC characteristics (M24xxx-F) and table title

modified.

17-Oct-2006 9

UFDFPN8 package specifications updated (see Ta b l e 2 2 ). M24128-BW-

and M24128-BR part numbers added.

Generic part number corrected in Features on page 1.

ICC0 corrected in Ta bl e 1 4 and Tab l e 1 3 .

Packages are ECOPACK® compliant.

27-Apr-2007 10

Available packages and temperature ranges by product specified in

Ta bl e 2 4 , Ta b l e 2 5 and Ta bl e 2 6 .

Notes modified below Table 12: Input parameters.

VIH max modified in DC characteristics tables (see Ta b l e 1 3 , Ta bl e 1 4 ,

Ta bl e 1 5 and Tab l e 1 6 ).

C process code added to Table 23: Ordering information scheme.

For M24xxx-R (1.8 V to 5.5 V range) products assembled from July 2007

on, tW will be 5 ms (see Table 17: AC characteristics (M24xxx-W6,

M24xxW3, M24xxR6).

Table 27. Document revision history (continued)

Date Revision Changes

M24128, M24C64, M24C32 Revision history

37/38

27-Nov-2007 11

Small text changes. Section 2.5: VSS ground and Section 4.9: ECC

(error correction code) and Write cycling added.

VIL and VIH modified in Table 15: DC characteristics (M24xxx-R - device

grade 6).

JEDEC standard reference updated below Table 7: Absolute maximum

ratings.

Package mechanical data inch values calculated from mm and rounded

to 4 decimal digits (see Section 8: Package mechanical).

18-Dec-2007 12

Added Section 2.6.2: Power-up conditions, updated Section 2.6.3:

Device reset, and Section 2.6.4: Power-down conditions in Section 2.6:

Supply voltage (VCC).

Updated Figure 4: Maximum RP value versus bus parasitic capacitance

Replace M24128 and M24C64 by M24128-BFMB6 and M24C64-FMB6,

respectively, in Section 4.9: ECC (error correction code) and Write

cycling.

Added temperature grade 6 in Table 10: Operating conditions (M24xxx-

F).

Updated test conditions for ILO and VLO in Table 13: DC characteristics

(M24xxx-W, device grade 6), Table 14: DC characteristics (M24xxx-W,

device grade 3), and Table 15: DC characteristics (M24xxx-R - device

grade 6).

Test condition updated for ILO, and VIH and VIL differentiate for 1.8 V ≤

VCC < 2.5 V and 2.5 V ≤ VCC < 5.5 V in Table 16: DC characteristics

(M24xxx-F).

Updated Table 17: AC characteristics (M24xxx-W6, M24xxW3,

M24xxR6), and Table 18: AC characteristics (M24xxx-F).

Updated Figure 12: AC waveforms.

Added M24128-BF in Table 26: Available M24128 products (package,

voltage range, temperature grade).

Process B removed fromTable 23: Ordering information scheme.

Table 27. Document revision history (continued)

Date Revision Changes

M24128, M24C64, M24C32

38/38

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