gu g3e SAMSUNG WH Semiconductor FEATURES - First-In-First-Out Dual Port Memory 4Kx9 - Very High Speed 20ns Read/Write 30ns cycle time * Two Fully Configurable Almost Full and Almost Empty Flags - Register Loading via the Input or the Output pins * Flag reconfiguration on the fly Programmable HF Flag or Full/Empty Flag option eliminates external counter requirement + Fully Compatible with Existing FIFOs + Depth and Width Expandabilities - Low Power Consumption Standby: 15mA Active: 120mA BLOCK DIAGRAM WRITE WT CONTROL FLAG REGISTER AND CONTROL Logic WRITE POINTER READ CONTROL EXPANSION XO/HF/F/E KM75C104A CMOS FIFO WITH PROGRAMMABLE FLAG Preliminary DESCRIPTION The 75C104<A is a 4K x 9 dual port memory that imple- ments a special First-in-First-Out (FIFO) algorithm that loads and empties data on a first-in-first-out basis. Sev- eral fixed and configurable flags have been added for efficient device utilization. The part is fully expandable in both depth and width without any performance loss. No address information is required for read or write operation. A ring counter generates required addresses for each operation. Datais toggled in and out of the device through the use of Write (W) and Read (R) pins. The read and write operations are independent of each other. PIN CONFIGURATIONS oIP TOP VIEW w VY 28 FO Vec COO 29R8 READ POINTEA 23 (7) FL/OIR ONDA Bw = N a wo wy So p> Z|m| vu m a = m= += = xa &ug~+ O wIUUUULY moOoOoOcG Pspull 4 a a PLCC TOP VIEW 9 2 oO eaz22458 29 PD pe 28 1 07 27[0NC 26 (0 FL/oiR 250 RS 241 EF-AEF 23D XO HFFE 2219 a7 21D a6 xt FR/AFF Qo aS 01 NC FL/DIA a2 14 15 16 17 18 19 20 oo o 6622'"36 aKM75C104A Samsung DESCRIPTION (Continued) The FIFO status can be determined by its flag states. In non-configured mode, the device defaults to the standard FIFO mode, providing a Half-Fuil (HF) Flag, a Full Flag (FF) and an Empty Flag (EF). The assertion and deasser- tion timing of these flags are identical to the flag timing of the standard FIFO. In configured mode, a maximum of three Flags are provided. The first two are the Almost-Full Flag (AFF) and the Almost-Empty Flag (AEF) with programmable offset. The third flag is either the HF or the F/E flag based on bit configuration of the flag register. All three flags are recon- figurable on the fly. The 75C104 is fabricated using proprietary high speed CMOS, 1.2 micron technology. These parts are ideal for applications requiring asynchronous and simultaneous read/write operation such as multiprocessing and data acquisition. These parts are typically used as temporary data storage for system synchronization. Pin Descriptions Operating Mode RS|R DIR | Mode L H H X Device Reset L Yel L H Flag register loading through input pins Flag register loading through output pins L {Lk H X No OP H L X No OP H | X X X Normal array access X: Don't Care Pin Number Type Name and Function Symbol = 1 | WRITE: A low on this pin loads data into the device. The internal write pointer is incremented after the rising edge of the write input. DO-D8 2-6, | 24-27 tively. DATA INPUTS: Data on these lines are stored in the memory array or flag registers during array write or register programming, respec- daisy chain. EXPANSION-IN: This pin is used for depth expansion mode. In single device mode, it should be grounded. In expanded mode, it should be connected to Expansion-out of the previous device in the FULL FLAG/ALMOST FULL FLAG: This output pin indicates the FIFO status. When in non-configured mode, this pin is a Fult Flag output. In configured mode, it is an Almost Full Flag output. Q0-08 9-13, VO DATA QUTPUTS: These pins can be used for data retrieval. The 16-19 pins become inputs during register loading with DIR input high. The outputs are disabled (Three-state} during device idle (R = High). 15 a READ: A low on this pin puts data in the memory array on the output bus. The internal read pointer is incremented at the rising edge of the read signal. Outputs are Three-state when this pin is high. XO/HF/F/ 20 EXPANSION OUT/HALF FULL/FULL/EMPTY: This pin's function is determined by its operation mode. When in single device mode, this pin is either HF Flag or a Full/Empty Flag, depending on the state of the 9th bit of Almost Full Flag Register. The pin is an XO output when the part is in depth expansion mode.KM75C 104A Samsung Pin Descriptions (Continued) Symbol Pin Number Type Name and Function EF/AEF 21 EMPTY FLAG/ALMOST EMPTY FLAG: This output pin indicates the FIFO status. When in non-configured mode, this pin is an Empty Flag output. When in configured mode, it is an Almost Empty Flag output. This pin is active low. 22 RESET: This pin is used to reset the device and load internal flag registers. During device reset, all internal pointers and registers are cleared. FL/DIR 23 FIRST LOAD/DIRECTION: When in register load mode, the pin is used for register loading direction. When it is high, registers are loaded through the input pins. When it is low, registers are loaded through the output pins. In depth expansion mode, this pin should be tied low if the device is the first one in the chain and tied high if it is not the first one. GND 14 GROUND cc 28 V ccKM75C 104A Samsung ABSOLUTE MAXIMUM RATINGS Item Symbol Rating Unit Voltage on any pin relative to GND Vin -0.5 to 7.0 Vv Operating Temperature T, 0 to +70 C Temperature Under Bias Tins 55 to +125 C Storage Temperature Tog -65 to +150 C DC Output Current lout 50 mA Note: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating canditians for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltages referenced to GND, T, = 0 to 70C) {tem Symbol Min Typ Max Unit Supply Voltage Voc 45 5.0 5.5 Vv Input High Voltage Vin 2.0 Vv input Low Voltage Vie 0.8 Vv DC OPERATING CHARACTERISTICS (V,,, = 5V + 10%) Parameter Symbol Min | Typ | Max | Unit Active Supply Current?) lee 60 mA Standby Current-TTL Isa 15 mA (All inputs = V,.) Standby Current-CMOS lego 5 mA (All inputs = V., 0.2V) Input Leakage Current he 1 pA Output Leakage Current lon 10 pA Output High Voltage Level Von 2.4 Vv log = ~2MA Output Low Voltage Level Vo. 0.4 Vv IQ. = BMA Notes: 1. 1,, and I, measurements are made with outputs open. 2. Active supply current is GOmMA for 5Ons, 100mA for -35ns and 120mA for 25ns and 20ns. 3. Measurements with GND $s V,,, S Vig. 4.R2V,. GND SVS Veg ouTKM75C 104A Samsung AC ELECTRICAL CHARACTERISTICS (V,,, = 5V+ 10%, T, = 0C to +70C) (Non-Configured Mode) 75C104A-20 75C104A-25 75C104A-35 Symbol | Parameter Min Max Min Max Min Max Unit tac Read Cycle Time 30 35 45 ns t, Access Time 20 25 35 ns ter Read Recovery Time 10 10 10 ns tapw Read Pulse Width 20 25 35 ns toy Data Valid after R High 5 5 5 ns tans R High to Data Bus at High Z 15 20 20 ns twe Write Cycle Time 30 35 45 ns twew Write Pulse Width 20 25 35 ns twe Write Recovery Time 10 10 10 ns ths Data Setup Time 12 15 18 ns tos Data Hold Time 0 ns taurs R High Before RS Low 0 ns twins W High Before RS Low 0 ns tase Reset Cycle Time 30 35 45 ns tas Reset Pulse Width 20 25 35 ns tasa Reset Recovery Time 10 10 10 ns tasey Reset to Flag Output Valid (All Flags) 30 35 45 ns tace Read Low to Empty Flag Low 20 25 30 ns lace Read High to Full Flag High 20 25 30 ns twee Write High to Empty Flag High 20 25 30 ns. twer Write Low to Full Flag Low 20 25 30 ns twuae Write Low to Half-Full Flag Low 30 35 45 ns tae Read High to Half-Full Flag High 30 35 45 ns brow Expansion Out Low Delay from Clock 20 25 35 ns bron Expansion Out High Delay from Clock 20 25 35 ns tox: XI Pulse Width 20 25 35 ns ton X! Recovery Time 10 10 10 ns tis XI Set-Up to Write or Clock 12 15 15 nsKM75C 104A Samsung AC ELECTRICAL CHARACTERISTICS (V,,. = 5V 10%, T, = 0C to +70C) (Configured Mode) 75C104A-20 75C104A-25 75C104A-35 Symbol | Parameter Min Max Min Max Min Max Unit tae Read Cycle Time 30 35 45 ns t, Access Time 20 25 35 ns tan Read Recovery Time 10 10 10 ns tapw Read Pulse Width 20 25 35 ns toy Data Valid After R High 5 5 5 ns taaz R High to Data Bus at High Z 15 15 15 ns twe Write/Load Cycle Time 30 35 45 ns twew Write/Load Pulse Width 20 25 35 ns twr Write/Load Recovery Time 10 10 10 ns tos Data Setup Time 12 15 18 ns toy Data Hold Time 0 ns terns R High Before RS Low 0 ns twins W High Before RS Low 0 ns tas Reset Pulse Width or Reset to R Low | 20 25 35 ns tase Reset Cycle Time 30 35 45 ns (no Register Programming) tasee Reset and Register Programming 100 115 145 ns Cycle Time tapy R Low to DIR Valid 5 5 5 ns ( Register Load Cycle) taw R Low to Register Load 10 10 10 ns lose Reset/Register Programming 10 10 10 ns Recovery Time tasey Reset to Flag Output Valid (All Flags) 15 15 15 ns tace Read Low to Empty Flag Low 20 25 30 ns tance Read Low to Almost Empty Flag Low 30 35 45 ns .KM75C 104A Samsung AC ELECTRICAL CHARACTERISTICS (V,, = 5V + 10%, T, = 0C to +70C) (Configured Mode) 75C104A-20 75C104A-25 75C104A-35 Symbol ; Parameter Min Max Min Max Min Max Unit laer Read High to Full Flag High 20 25 30 ns laare Read High to Almost Full Flag High 30 35 45 ns twee Write High to Empty Flag High 20 25 30 ns twaer Write High to Almost Empty Flag High 30 35 45 ns twee Write Low to Full Flag Low 20 35 30 ns tware Write Low to Almost Full Flag Low 30 35 45 ns tue Write Low to Half-Full Flag Low 30 35 45 ns taur Read High to Half-Full Flag High 30 35 45 ns tro Expansion Out Low Delay From Clock 20 25 35 ns trou Expansion Out High Delay From Clock 20 25 35 ns toy; XI Pulse Width 20 25 35 ns hua XI Recovery Time 10 10 10 ns ts XI Set-up to Write or Clock 12 15 15 ns Notes: 1. Timings referenced as in AC Test Canditions. 2. Pulse widths fess than minimum value are not allowed. 3. Values guaranteed by design, not currently tested. 4. t,o, i$ guaranteed to be greater than or equal to t,,, under all conditions. AC TEST CONDITIONS Output Load Input Pulse Levels GND to 3.0V Input Rise and Fall Times - 5ns 9 Input Timing Reference Levels 1.5V aon Output Reference Levels 1.5V ? Output Load See Figure 1 TO OUTPUT 9 mA 2aV 3 3000 7 30pF* CAPACITANCE (T, = +25C, f = 1.0 MHz) Symbol Parameter) Conditions| Typ. | Unit = * INCLUDES JIG AND SCOPE CAPACITANCES c Cor [Output Capacitance {V,,,=O0V [7 = | pF Input Capacitance |V,=OV [5 pF IN Note: This parameter is sampied and not 100% tested. Note: Generating R/W Signals When using these high-speed FIFO devices, it is necessary to have clean inputs on the R and W signals. It is important not to have glitches, spikes or ringing on the R, W (that violate the V,., V,,, requirements); although the minimum pulse width low for the R and W are specified in tens of nanoseconds, a glitch of 3ns can affect the read or write pointer and cause it to increment.KM75C 104A Samsung Expansion-Out Timing Diagram WRITE TO LAST PHYSICAL LOCATION w a tkou xO READ FROM LAST PHYSICAL LOCATION txou Half Full Flag Timing (Configured or nonconfigured mode) =| DI HALF-FULL OR LESS N txou HALF-FULL OR LESS K MORE THANHALF-FULL / twee Full Flag Timing (Pin 8 or 20) FF. FE LAST WRITE | ' ' qT l { FIRST READ \_F# ADDITIONAL READS FIRST WRITE \__/ {wer |< wm) lare VSKM75C104A Empty Flag Timing (Pin 20 or 21) LAST READ FIRST WRITE =| ADDITIONAL WRITES Samsung FIRST READ OO / EF, FE 7" Pe m] free i | wer - <4 VALID DATA OUT VALID >} Expansion-!n Timing Diagram =| mt txis tex WRITE TO FIRST PHYSICAL LOCATION tun RX fxs READ FROM FIRST PHYSICAL LOCATIONKM75C104A Samsung Asynchronous Write and Read Operation tac tapw a tra r <_ 4 _ a {_, _>- trHiz toy +> DATA OUT N DATA OUT Q0-08 VALIO VALID bf {ps +>|<+- pH __ n= ZIT == STIX MT Read Data Flow Through Mode Dara in x 3v <t_ (RPE _ OV ov Ss ~<a tReF > t- twer t DATA OUT DATA OUT VALID Note: 1. (tape = taew) 10KM75C104A Samsung Write Data Flow Through Mode 3V re eU {< "wer >- W ov # tare ~- FF ov J |<s !wre <_|_ DATA IN DATA IN VALID = tos - jt _ t , _>| DATA OUT ___+{ DATA OUT VALID Note: 1. (twer * twew) Device Reset Timing (No Register Programming) <. tasc > tas o- RS \ {RHRS } Lh ~<a- tasR a twHas |__ trsFy -_____- ALL FLAGS VALID OUTPUTS x 1KM75C 104A Samsung Reset/Register Programming Cycle Timing a tasec J {ag ___- (t laser >| RS _/| R XR zx ws {aov < pin 7 Qo w VALID DATA ALL FLAGS VALIO OUTPUTS Almost Full Flag Timing (2-Byte Offset) FULL FIFO w eee KY V_YZ | | 2046 2047 2048 | FIRST SECOND DATA BYTE BYTE BYTE | | READ READ i R | | tWAFF | | (RAFF ate | FULL | FIFO | 12Samsung KM75C 104A Aimost Empty Flag Timing (10-Byte Offset) A NY ww YY N_Y om 10th DATA C at > :> LOCATION LOCATION tracer < twaeF < AEF z|KM75C 104A Samsung OPERATING MODES The 75C104A has several modes of operation. These are: 1. Device Reset Mode The 75C104Acanbe reset by loweringthe Reset (RS)pin with both Read (R) and Write (W) inputs high. In this mode, all internal pointers and registers are cleared. A reset is required upon power up to insure correct device operation. After reset, all flags are set to appropriate states. 2. Register Load Mode This mode of operation is used to reset the device and program the internal flag registers. This yields an Almost Full and an Almost Empty flag (pins 8 and 21 respec- tively) and a Haif-Fuil or F/E flag. Two 9-bit internal registers have been provided for flag configuration. One is the Almost Full Flag Register (AFFR) and the other is the Almost Empty Flag Register (AEFR). Bit configurations of the two registers are shown below. Register Set for KM75C104A Almost Empty Flag Register (AEFR) 8 | 7 0 | | | t Reset Offset Bits Locking Almost Full Flag Register (AFFR) 8 7 0 T HF/F/E Offset Bits Note that bits 0-7 are used for offset setting. The offset value ranges from 1 to 255 words. For each offset incre- ment, a four byte offset is added in the FIFO providing 1024 bytes of offset. Bit 7 is reserved for future offset expansion. Bit 8 of the AFFR is used for configuration of pin 20 (28-pin DIP pack- age). When this bit is set low, pin 20 is a HF Flag output. When it is set high, pin 20 is a F/E flag output. The 8th bit of the AEFR is used for reset locking. When this bit is set low, subsequent device reset or register loading cycle resets the device. When the bit is programmed high, subsequent reset cycles are ignored. In this mode, the flag registers can be reconfigured without device reset. The part can be reset again by writing a 0 into this location followed by a device reset (or register loading) or by repowering up the device. Flag registers are loaded by bringing RS low followed by the R input. The R pin should be brought low t,, after the RS low. The registers can then be loaded via the input pins or the output pins depending on the status of the DIR control input. Data is latched into the registers atthe rising edge of the W control pin. The first write loads the AFFR while the second write loads the AEFR. This loading order is fixed. 3. Array Read/Write Mode Reading and writing into the FIFO is accomplished via Read (R) and Write (W) pins. The part can be written or read simultaneously through the input or the output ports respectively. The read cycle is initiated on the falling edge of the R input. After the rising edge of R, the outputs will return to a high impedance state until the next read cycle. Ifthe FIFO is empty, any read aitempt is ignored (i.e. the read pointer stays intact and the outputs stay in three- state). Awrite cycle is initiated by asserting the W input low. Data is stored in the memory sequentially, independent of any read operation in progress. When the FIFO is full, addi- tional write attempts are ignored and the memory con- tents stay intact. 4. Expansion Mode The KM75C 104A facilitates expansion in width and depth. The part can be configured for depth expansion by lower- ing pin 23 (FL/DIR) for the first device in the daisy chain by asserting it high if it is not the first device. The Expansion In (XI) pin should be connected to Expansion Out (XO) pin of the previous device. In this way, a signal can be passed to the next device when the current device is full. Note that the retransmit feature is not available in this mode. 14KM75C 104A Samsung The KM75C104A can be used for width expansion. Word width may be increased simply by connecting the corre- sponding input contro! signals of multiple devices. In this mode, the XI input must be grounded. Status Flags (HF, EF, FF, AFF or AEF) of any one of the devices can be used for system interrupt. The two expansion techniques described above can be applied together to achieve deep FIFO with wide word width. 5. Bidirectional Mode Applications which require data buffering between two systems (each system capable of READ and WRITE operations), canbe achieved by using two KM75C104A's. Care must be taken to assure that the appropriate flag is monitored by each system; (i.e., FF is monitored on the device where W is used; EF is monitored on the device where R is used). Both Depth Expansion and Width Expansion may be used in this mode. Flag Timing A total of 3 flag outputs are provided in either configured ornon-contigured mode. Inthe non-configured mode, the three flags are HF flag, EF and FF. The HF fiag goes active when more than half the FIFO is full. The flag goes inactive when the FIFO is half full or less. The Fult and Empty Flags go active when the last byte is written to or read out of the FIFO respectively. Tne flags are deasserted when the first byte is loaded into an empty FIFO or read out of a full FIFO. All three flag outputs are active low. When the device is programmed, the AFF and AEF go active after a read/write cycle initiation of the location corresponding to the programmed offset value. For ex- ample if ihe AEFR is programmed with a 20 byte offset (loading a Hex value of 05H), the AEF flag goes active during reading the 20th location before FIFO empty. The flag goes inactive when there are 10 or more bytes left in the FIFO. The assertion and deassertion timing of the AFF is the same. The third flag in the program mode is either HF or F/E flag depending on the state of the Sth bit of the AFFR. If the device is programmed for HF flag, it functions like the HF flag in non-programmed mode. If the device is configured for F/E flag, it functions like FF or EF of the non configured mode. The pin goes active at the last FIFO read or FIFO write. The output is active low. Data Flow-Through Modes This section describes two special conditions when the FIFO is full, or when itis empty. For the read flow-through mode, the FIFO permits the reading of a single word after writing one word of data into an empty FIFO. The data is enabled on the bus in {t,,-- + t,)ns after the rising edge of W, called the first write edge, and it remains on the bus until the R input is raised from low-to-high, after which the bus would go into a three-state mode after t,,,. ns. The EF will output a pulse showing temporary deassertion and then will be asserted. Inthe interval of time that R was low, additional data can be written to the FIFO (the subsequent writes after the first write edge would de-assert the empty flag); however, the same word (written on the first write edge) is presented to the output bus while R is still low. The read pointer, would not be incremented when R is low. On toggling R, additional data is retrieved. In the write flow-through mode, the FIFO permits the writing of a single byte of data immediately after reading one byte of data from a full FIFO. The R line causes the FF to be de-asserted but the W line being low causes it to be asserted again in anticipation of new data. The new data is loaded into the FIFO on the rising edge of the W control pin. The W line must be toggled when FF is not asserted in order to write new data into the FIFO and to in- crement the write pointer. 15KM75C 104A Samsung TRUTH TABLES Table 1. Reset Single Device Configuration/Width Expansion Mode inputs Internal Status Outputs Mode RS | Xi Read Pointer Write Pointer EF FF HF Reset 0 0 Location Zero Location Zero 0 1 1 Read/Write 1 0 Increment(1) Increment(1) X x x Note: 1. Pointer will increment if flag is high. Table 2. Reset and First Load Truth Table ~ Depth Expansion/Compound Expansion Mode inputs Internal Status Outputs Mode RS | FL xl Read Pointer Write Pointer EF FF Reset-First Device 0 0 (1) Location Zero Location Zero 0 1 Reset all other 0 1 (1) Location Zero Location Zero 0 1 devices Read/Write 1 x (1) x x x Xx Notes: 1. Xtis connected to XO of previous device. RS = Reset Input, FL = First Load, EF = Empty Flag Output, FF = Full Flag Output, XI = Expansion Input, HF = Half-Full Flag Output. 16KM75C104A Samsung PACKAGE DIMENSIONS 32-Pin PLCC 28-Pin Plastic DIP 7.450 450 a I 0.060 <_ 0.055 WU 0.447 0.400 _ Das 0.140 0.040 0.030 ; qi 0.070 uli a0 8.300 REF. > a ; 0.042 di ' 0.048 \ q a 4 Sy . moe d : | d p on 0.585 B| | f _ 5 3 Tye t. Lito UL A ORDERING INFORMATION KM 75CXX X X XX - SAMSUNG SPEED MEMORY 20:20ns COMPONENT 25:25 ns 35: 35ns -50 :50 ns {}______} PART NUMBER TEMPERATURE Blank :0 ~ 70C 1 > -40 ~ +85C REVISION /______+ PERFORMANCE * BLANK STANDARD PACKAGE *H HIGH SPEED P : Plastic Dip, 600 mil lL -LOW POWER J : Plastic PLCC N : 300 mil 17KM75C 104A Samsung SAMSUNG SEMICONDUCTOR, INCORPORATED SALES OFFICES NORTH EASTERN NORTH CENTRAL SOUTHWEST . SOUTHWEST REGIONAL 20 Burlington Mall Rd. #205 901 Warrenville Road #120 22837 Ventura Bivd., #305 3027 Greenwich St. Burlington, MA 01803 Lisle, IL 60532-1359 Woodiand Hills, CA 91367 Carlsbad, CA 92008 617/273-4888 312/852-2011 818/346-6416 619/720-0230 FAX 617/273-9363 FAX 708/852-3096 FAX 818/346-6621 FAX 619/720-0230 NORTHWEST SOUTH SOUTHEAST 2700 Augustine Dr. #198 15851 Dailas Parkway, #840 204 Battleground Corp. Park Santa Clara, CA 95054 Dallas, TX 75248-3307 3859 Battleground Ave. 408/727-7433 214/770-7970 Greensboro, NC 27410 FAX 408/727-5071 FAX 214/770-7971 919/282-0665 FAX 919/282-0784 Circuit diagrams utilizing SAMSUNG and/or SAMSUNG SEMICONDUCTOR & TELECOMMUNICATIONS CO., LTD., products are included as @ means of illustrating typical semiconductor applications, consequentiy, complete information sufficient for construction purposes is not necessarily given. The information has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does not convey tothe purchaser of the semiconductor devices described herein any license under the patent rights of SAMSUNG and/or SAMSUNG SEMICONDUCTOR & TELECOMMUNICATIONS CO., LTD., or others. SAMSUNG and/or SAMSUNG SEMICONDUCTOR & TELECOMMUNICATIONS CO., LTD., reserve the right to change device specifications. a 3725 North First Street San Jose, CA 95134-1708 SAMSUNG Telephone: (408) 954-7000 FAX: (408) 954-7873 Semiconductor 1-800-669-5400 Printed in U.S.A. GE/5K/4 90