A43L4616A
4M X 16 Bit X 4 Banks Synchronous DRAM
(July, 2019, Version 1.0) AMIC Technology, Corp.
Document Title
4M X 16 Bit X 4 Banks Synchronous DRAM
Revision History
Rev. No . History Issue Date Remark
0.0 Initial issue April 18, 2008 Preliminary
0.1 Add Test Mode description August 13, 2008
0.2 Error Corr ection: Septem ber 14, 2009
Change Clock Frequency from 133MHz to 100MHz at CL=2
0.3 Remove the x8 confi guration February 22, 2010
0.4 Modify DC, AC spec. and add full page mode May 11, 2010
1.0 Final ve rsion rele ase July 3, 2 019 Final
A43L4616A
4M X 16 Bit X 4 Banks Synchronous DRAM
(July, 2019, Version 1.0) 1 AMIC Technology, Corp.
Features
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks / Pulse RAS
MRS cycle with address key programs
- C A S L at enc y (2,3)
- Burst Length (1,2,4,8, FP)
- Burst Type ( Sequenti al & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Clock Frequency: 166MHz @ CL=3, 100Mhz @ CL=2
143MHz @ CL=3, 100Mhz @ CL=2
133MHz @ CL=3, 100Mhz @ CL=2
Industrial temperatur e operation: -40°C to +85°C fo r -U
Automotiv e tempe rature opera tion : -40 °C to +85°C for -A
Bur st Read Si ngle-bit Write oper ati on
DQM for masking
Auto & self refresh
64ms refresh per i od (8K cycle)
54 Pin TSOP (II)
Lead-free pr oduct available
All P b-f ree (lead-free) pro duct are RoH S2.0 c omplian t
Gen eral Descriptio n
The A43L4616A is 268,435,456 bits synchronous high data
rate Dynamic RAM organized as 4 X 4,194,304 words by
16 bits, fabricated with AMIC’s high performance CMOS
technology. Synchronous design allows precise cycle
control with the use of system clock. I/O transactions are
possible on every clock cycle. Range of operating
frequencies, programmable latencies allows the same
device to be useful for a variety of high bandwidth, high
performance me mory sys tem applicat ions.
A43L4616A
(July, 2019, Ver s ion 1.0) 2 AMIC Technology, Corp.
Pin Configuration
TSOP (II)
A43L4616AV
54
53
52
51
50
49
48
47
46
45
43
44
42
41
40
39
38
37
36
35
34
33
32
31
30
1
2
3
4
5
6
7
8
9
10
12
11
13
14
15
16
17
18
19
20
21
22
23
24
25
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
UDQM
CK
CKE
A12
A9
A8
A7
A6
A5
A4
VSS
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
WE
CAS
RAS
CS
A10/AP
BS1
BS0
A0
A1
A2
26
27 28
29A3
VDD
A11
NC
A43L4616A
(July, 2019, Ver s ion 1.0) 3 AMIC Technology, Corp.
Blo ck Diagram
Bank Select
Row Buffer
Refresh Counter
Address Re gister
Row Decoder Column Bu ffer
LCBR
LRAS
CLK
ADD
Timing Register
Data In pu t Regi ster
4M X 16
Sense AMP
Column De coder
Latency & Burst Length
Pr ogrammin g Register
LRAS
LCAS
LRAS LCBR LWE LWCBR
DQM
CLK CKE CS RAS CAS WE DQM
I/O C o nt r o l Outp ut Buffer
LWE
DQM
DQi
4M X 16
4M X 16
4M X 16
Notes: This fi gure shows the A43L4616A.
A43L4616A
(July, 2019, Ver s ion 1.0) 4 AMIC Technology, Corp.
Pin Descriptio ns
Symbol Name Description
CLK System Clock Active on the positive going edge t o sample all inputs.
CS Chip Select Disables or Enables device operati on by masking or enabling all inputs except CLK,
CKE and L( U)DQM
CKE Clock Enable
Masks system clock t o freeze operation f r om the next cl ock cycle.
CKE shoul d be enabled at least one clock + tss pri or to new com m and.
Disable input buff ers for power down in standby.
A0~A12 Address Row / Column addresses are m ultiplexed on the same pins.
Row address : RA0 ~RA1 2, Col um n address: CA0 ~CA8.
BS0, BS1 Bank Select Address Selects bank t o be activated during row address latch time.
Selects band for read/write during col umn addr ess latch tim e.
RAS Row Address Strobe Latches row addresses on the positive goi ng edge of the CLK with RAS low .
Enables r ow access & precharge.
CAS Column Addr ess
Strobe Lat ches column addresses on the positive going edge of the CLK with CASlow.
Enables column access.
WE W rite Enable Enables wr it e operation and Row precharge.
L(U)DQM Data Input/Output
Mask
Makes dat a output Hi- Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM acti ve.
LDQM c or r esponds to DQ0 ~ DQ7, UDQM corr esponds to DQ8 ~ DQ15
DQ0-15 Data Input/Output Data inputs/outputs are multiplexed on the sam e pins.
VDD/VSS Power Supply/Ground
Power Supply: +3.3V±0.3V/Ground
VDDQ/VSSQ Da ta Output
Power/Ground Provide isolated Power/Ground to DQs for improved noi se immunity.
NC No Connection
A43L4616A
(July, 2019, Ver s ion 1.0) 5 AMIC Technology, Corp.
Absolute Maximum Rati ngs*
Voltage on any pin relati ve to VSS (Vin, Vout ) . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +4.6V
Voltage on VDD supply relative to VSS ( VDD, VDDQ )
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to +4.6V
Storag e Temp eratur e (TSTG) . . . . . . . . . . -55°C to + 1 5 0 °C
Soldering Temperature X Time ( TSOLDER) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C X 10sec
Power Di s si pati on (P D) . . . . . . . . . . . . . . . . . . . . . . . . .1W
Short Circuit Current (Ios) . . . . . . . . . . . . . . . . . . . . 50mA
*Comments
Permanent device damage m ay occur if “Absolute Maximum
Ratings ” are exce eded .
Functional operation should be restricted to recommended
operating cond ition.
Exposure to higher than recomm ended voltage for extended
peri ods of time could affect devi ce reliability.
Capacitance (TA=25°C, f=1 MHz)
Parameter Symbol Condition Min Typ Max
Input Capacitance CI1 A0 to A12, BS0,
BS1 2 3.5
CI2 CLK, CKE,
CS ,
RAS,CAS,WE ,
L(U)DQM
2 3.5
Data Input/Output Capaci tance CI/O DQ0 to DQ15 3.5 5.5
DC Electrical Charact eristics
Recommend operating conditions (Voltage referenced to VSS = 0V, TA = 0°C to +70°C, -40°C to +85°C for industrial
temperature range or -40°C to +85°C for auto motive te mpe rature range)
Parameter Symbol Min Typ Max Unit Note
Supply Voltage VDD,VDDQ 3.0 3.3 3.6 V
Input High Volt age VIH 2.0 VDD VDD+0.3 V Note 1
Input Low Voltage VIL -0.3 0 0.8 V Note 2
Output High Voltage VOH 2.4 - - V IOH = -2mA
Output Low Voltage VOL - - 0.4 V IOL = 2mA
Input Leakage Current I IL -10 - 10 μA Note 3
Output Leakage Current I OL -10 - 10 μA Note 4
Outp ut Lo ading Condit ion See F igure 1
Note:
1. VIH (max) = 4.6V AC (pulse width ≤ 10ns).
2. VIL (min ) = -1.5V AC ( pulse w idth ≤ 10ns).
3. Any i nput 0V ≤ VIN ≤ VDD + 0.3V, all other pins are not under test = 0V
4. Dout is disabled, 0V ≤ Vout ≤ VDD
A43L4616A
(July, 2019, Ver s ion 1.0) 6 AMIC Technology, Corp.
Decoupling Capacitance Guide Line
Recommended decoupling capacitance added to power line at board.
Parameter Symbol Value Unit
Decoupli ng Capacit ance between VDD and VSS CDC1 0.1 + 0.01 μF
Decoupli ng Capacit ance between VDDQ and VSSQ CDC2 0.1 + 0.01 μF
Note: 1. VDD an d V DDQ pin s are sep arated each other.
All VDD pi ns are connect ed in chip. All VDDQ pins ar e connected in chi p.
2. VSS and VSSQ pins ar e separat ed each other
All VSS pins are connected i n chip. All VSSQ pins are connect ed in chip.
DC Electrical Charact eristics
(Recom mended operating condition unl ess otherwise noted, TA = 0 to 70°C, -40°C to +85°C for industr ial tempera ture range o r
-40°C to +8 5 °C for automotive temperatur e range)
Symbol Parameter Test Conditions Speed Unit Notes
-6 -7 -75
Icc1 Opera t ing Curren t
(One Bank Active) Burst Length = 1
tRC = tRC(min), tCC = tCC(min), IOL = 0m A 110 110 105 mA 1
Icc2 P Precharge Standby
Current in power-down
mode
CKE = VIL(max), tCC = 10ns 12 mA
Icc2 PS CKL = VIL(max), tCC = ∞ 5
ICC2N Precharge Standby
Current in non power-
down mode
CKE = VIH(min), CS = VIH(min), tCC = 10ns
Input signals are changed one tim e during 20ns 38
mA
ICC2NS CKE = VIH(m in), CL K = VIL(max), tCC = ∞
Input signals are stable. 28
ICC3N Active Standby current
in non power-down
mode (One Bank Active)
CKE = VIH(min), CS = VIH(min), tCC = 10ns
Input signals are changed one tim e during 20ns 65 mA
ICC3NS CKE = VIH(m in), CL K = VIL(max), tCC = ∞
Input signals are stable 45 mA
ICC3P Active Standby curr ent
in power-down mode
(One Bank Active)
CKE = VIL(max), tcc=10ns 35 mA
ICC3PS CKE & CLK = VIL(max), t cc= ∞ 20 mA
ICC4 Opera t in g C urrent
(Burst Mode) IOL = 0mA, Burst Length = 4
All bank Activated, tCCD = tCCD (min ) 105 100 95 mA 1
ICC5 Refresh Current tRC = tRC (min) 150 140 130 mA 2
ICC6 Self Refresh Current CKE = 0.2V 6 6 6 m A
Note : 1. M eas ured with ou t pu ts open . Addres ses a re ch anged on ly o ne ti me during tCC(min).
2. Refresh period is 64ms. Addresses are changed onl y one time during tCC(min).
3. Unless otherwise noted, input swing IeveI is CMOS (VIH /VIL=VDDQ/VSSQ).
A43L4616A
(July, 2019, Ver s ion 1.0) 7 AMIC Technology, Corp.
AC Operating Test Conditions
(VDD = 3.3V ±0.3V, TA = 0°C to +70°C, -40°C to +85°C for industrial temperature range or -40°C to +85°C for automotive
temperature range)
Parameter Value
AC input levels VIH/VIL = 2.4V/0.4V
Input timing measu rement refe re nce leve l 1.4V
Input rise and all time (Se e note3) tr/tf = 1ns/1 ns
Output timing measu rement re fe re nce leve l 1.4V
Output load condition See Fig.2
Output
870Ω
1200Ω
(Fig. 1) DC Output Load Circuit
ZO=50Ω
OUTPUT
50Ω
VTT =1.4V
30pF
(Fig. 2) AC Output Load Circuit
3.3V
30pF
VOH(DC) = 2.4V, IOH = -2mA
VOL(DC) = 0.4V, IOL = 2mA
AC Characterist ics
(AC operating conditions unl ess otherwise noted)
Symbol Parameter CAS
Latency
-6 -7 -75 Unit Note
Min Max Min Max Min Max
tCC CLK cycle tim e 3 6
- 7 - 7.5 - ns 1
2 10 10 10
tSAC CLK to valid
Output delay
3 - 5.4 - 5.4 - 5.4 ns 1,2
2 5.4 5.4 6
tOH Output data hold time 3 2.5
- 2.5 - 2.5 - ns 2
2 2.5 2.5 2.5
tCH CLK high pulse width
2, 3
2.5 - 2.5 - 2.5 - ns 3
tCL CLK low pulse widt h 2.5 - 2.5 - 2.5 - ns 3
tSS Input setup time 1.5 - 1.5 - 1.5 - ns 3
tSH I nput hold tim e 1 - 1 - 1 - ns 3
tSLZ CLK to out put in Low-Z 1 - 1 - 1 - ns 2
tSHZ CLK to output In Hi-Z 3 - 5.4 - 5.4 - 5.4 ns -
2 5.4 5.4 6
* All AC pa ramet ers are meas ured from hal f t o half .
No te : 1. Parameters depend on programmed CAS latency.
2. If clock risin g time is longer than 1ns, (tr/2-0.5)ns should be added to the para meter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient tim e compensation should be consi dered,
i.e., [(tr + tf)/2-1 ]ns should be added to the parameter.
A43L4616A
(July, 2019, Ver s ion 1.0) 8 AMIC Technology, Corp.
Operating AC Parameter
(AC operating conditions unl ess otherwise noted)
Symbol Parameter CAS
Latency
Version Unit Note
-6 -7 -75
tRRD(min) Row active to row active delay
2,3
12 14 15 ns 1
tRCD(min) RAS to CAS delay 18 20 20 ns 1
tRP(min) Row precharge time 18 20 20 ns 1
tRAS(min) Row active time 42 45 45 ns 1
tRAS(max) 100 100 100
μs
tRC(min) Row cycle tim e 60 63 65 ns 1
tCDL(min) Last data in new col. Address delay 1 1 1 CLK 2
tRDL(min) Last data in row precharge 2 2 2 CLK 2
tDAL(min) Last data in to Acti ve delay 5 5 5 CLK
tBDL(min) Last data in to bur st stop 1 1 1 CLK 2
tCCD(min) Col. Addr ess to col. Address delay 1 1 1 CLK
tMRD(min) Mode regist er set cycle time 2 2 2 CLK
tREF(max) Refresh interval time 64 64 64 ms
tARFC(min) Auto refresh cycle time 60 70 75 ns
Note: 1. Th e m inim um n umb er of clock cycl es i s determ in ed by di vi din g th e m i nimum tim e requ ir ed wi th cloc k cy cle time a nd
then rounding off to the next higher integer .
2. Minimum delay is required to complete writ e.
A43L4616A
(July, 2019, Ver s ion 1.0) 9 AMIC Technology, Corp.
Sim p lified Truth Tab le
Command CKEn-1 CKEn CS RAS CAS WE DQM BS0
BS1 A10
/AP A9~A0,
A11,A12 Notes
Register Mode Register Set H X L L L L X OP CODE 1,2
Refresh Auto Refresh H H L L L H X X 3
Self
Refresh
Entry L 3
Exit L H
L H H H X X 3
H X X X 3
Bank Active & Row Addr. H X L L H H X V Row Addr. 4
Read &
Column Addr. Auto Prech arge Dis able H X L H L H X V
L Column
Addr. 4
Auto Precharge Enable H 4,5
Write &
Column Addr. Auto Prech arge Dis able H X L H L L X V
L Column
Addr. 4
Auto Precharge Enable H 4,5
Burst Stop H X L H H L X X
Precharge Bank Selection H X L L H L X V L X
Bot h Banks X H
Clock Suspend or
Act iv e Power Down
Entry H L
L H H H X X
H X X X
Exit L H X X X X X
Precharge Power Down Mode Entry H L
L H H H X X
H X X X
Exit L H
L V V V X
H X X X
DQM H X V X 6
No Opera tion Command H X L H H H X X
H X X X
(V = Val id, X = Don’t Care, H = Logic Hi gh, L = Logic Low)
No te : 1. OP Code: Operand Code
A0~A12, BS0, BS1: Program k eys. (@MRS)
2. MRS can be issued only when all banks are at precharge st at e.
A new command can be i ssued after 2 clock cycle of MRS.
3. Auto refresh functions as same as CBR refresh of DRAM.
The automatical precharge without Row precharge command is meant by “Auto”.
Auto/Self refresh can be issued only when all banks ar e at precharge state.
4. BS0, BS1 : Bank select address.
If both BS1 and BS0 ar e “Low” at read, write, row act ive and precharge, bank A is sel ected.
If both BS1 is “Low” and BS0 is “High” at read, write, row active and precharge, bank B is selected.
If both BS1 is “High” and BS0 is “Low” at read, write, row act ive and precharge, bank C is selected.
If both BS1 and BS0 ar e “High” at read, write, row active and precharge, bank D is sel ected.
If A10/AP is “Hi gh” at row precharge, BS1 and BS0 is ignored and all banks are selected.
5. During burst read or writ e wit h auto precharge, new read/write command cannot be issued.
Another bank read/write comm and can be i ssued at every burst length.
6. DQM sampled at positive going edge of a CLK masks t he data-in at the ver y CLK (W rite DQ M latency is 0)
but masks the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)
A43L4616A
(July, 2019, Version 1.0) 10 AMIC Technology, Corp.
Mode Register Filed Table to Program Modes
Register P r og rammed with MR S
Address BS0 BS1 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Function RFU RFU W.B.L TM CAS Latency BT Burst Length
(Note 1) (Note 2)
Test Mode CAS Latency Burst Type Burst Length
A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT=0 BT=1
0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 1
0 1 Vendor
Use
Only
0 0 1 Reserved 1 Interleave 0 0 1 2 2
1 0 0 1 0 2 0 1 0 4 4
1 1 0 1 1 3 0 1 1 8 8
Write Burst Length 1 0 0 Reserved 1 0 0 Reserved Reserved
A9 Length 1 0 1 Reserved 1 0 1 Reserved Reserved
0 Burst 1 1 0 Reserved 1 1 0 Reserved Reserved
1 Single Bit 1 1 1 Reserved 1 1 1 Full Page Reserved
Power Up Sequen ce
1. Apply power and start cl ock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200μs.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh comm ands.
5. Issue a mode r egister set command to initialize the mode register.
The devi ce is now r eady for normal operati on.
No te : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.
2. If A9 is high dur ing MRS cycle, “Burst Read Single Bit W rite” f unction will be enabl ed.
A43L4616A
(July, 2019, Version 1.0) 11 AMIC Technology, Corp.
Burst Sequence (Burst Length = 4)
Initial address Sequential Interleave
A1 A0
0 0 0 1 2 3 0 1 2 3
0 1 1 2 3 0 1 0 3 2
1 0 2 3 0 1 2 3 0 1
1 1 3 0 1 2 3 2 1 0
Burst S equ ence (Burst Lengt h = 8)
Initial address Sequential Interleave
A2 A1 A0
0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6
0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5
0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4
1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2
1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1
1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0
A43L4616A
(July, 2019, Version 1.0) 12 AMIC Technology, Corp.
Device O perations
Clock (CLK)
The clock input is used as the reference for all SDRAM
operations. All operations are synchronized to the positive
going edge of the clock. The clock transitions must be
monotonic between VIL and VIH. During operati on with CKE
high all inputs are assumed to be in valid state (low or high)
for the duration of set up and hold time around positive edge
of the clock f or proper functionalit y and ICC specif ications.
Clock Enable (CKE)
The clock enable (CKE) gates the clock onto SDRAM. If CKE
goes low synchronously with clock (set-up and hold time
same as other inputs), the internal clock is suspended from
the next clock cycle and the state of output and burst
address is frozen as long as the CKE remains low. All other
inputs are ignored from the next clock cycle after CKE goes
low. When all banks are in the idle state and CKE goes low
synchronously with clock, the SDRAM enters the power
down mode from the next clock cycle. The SDRAM remains
in the power down m ode ignoring the other inputs as long as
CKE remains low. The power down exit is synchronous as
the internal clock is suspended. When CKE goes high at
least “tSS + 1 CLOCK” before the high going edge of the
clock, then the SDRAM becom es active from the sam e clock
edge accept ing all the input commands.
Bank Select (BS0, BS1)
This SDRAM is organized as 4 independent banks of
4,194,304 words X 16 bits memory arrays. The BS0, BS1
inputs is latched at the time of assertion of RAS and CAS
to select the bank to be used for the operation. The bank
select BS0, BS1 is latched at bank acti vate, read, write mode
register set and precharge operati ons.
Address Input (A0 ~ A12)
The 22 address bits required to decode the 4,194,304 word
locations are multiplexed into 13 address input pins
(A0~A12). The 13 bit row address is latched along with
RAS , BS0 and BS1 during bank activate command. The 9
bit column address is latched along with CAS , WE, BS0
and BS1duri ng read or write command.
NOP and Devic e Desele ct
When RAS , CAS and WE are hig h, t h e SD RA M p er f orm s
no operation (NOP). NOP does not initiate any new
operation, but is needed to complete operations which
require more than single clock l ike bank activate, burst read,
auto refresh, etc. The device deselect is also a NOP and is
entered by asserting CS high. CS high disables the
command decoder so that RAS , CAS and WE , and all
the address inputs are ignored.
Power-Up
The following sequence is recom mended for POW ER UP
1. Power must be applied to either CKE and DQM inputs to
pull them high and other pins are NOP condition at the
inputs before or al ong with VDD (and VDDQ ) supply.
The clock signal must also be asserted at the same tim e.
2. After VDD reaches the desired voltage, a minimum pause
of 200 microseconds is required with inputs in NOP
condition.
3. Both banks mus t be precharge d now.
4. Perform a minimum of 2 Auto refresh cycles to stabilize
th e internal ci rcuit ry.
5. Perform a MODE REGISTER SET cycle to program the
CAS latency, burst length and burst type as the default
value of mode regist er is undefined.
At the end of one clock cycle from the mode register set
cycle, the device is ready for operation.
When the above sequence is used for Power-up, all the
out-puts will be in high impedance state. The high
impedance of outputs is not guaranteed in any other
powe r-up sequence.
Mode Register Set (MRS)
The mode register stores the data for controlling the various
operation modes of SDRAM. It programs the CAS latency,
addressing mode, burst length, test mode and various
vendor specific options to make SDRAM usef ul for variety of
different applications. The default value of the mode register
is not defined, therefore the mode register must be written
after power up to operate the SDRAM. The mode register is
written by asserting low on CS ,RAS , CAS ,WE (The
SDRAM should be in active mode with CKE already high
prior to writing the mode register). The state of address pins
A0~A11, BS0 and BS1 in the same cycle as
CS ,RAS ,CAS ,WE going low is the data written in the
mode register. One clock cycle is required to complete the
write in the mode register. The mode register contents can
be changed using the same command and clock cycle
requirem ents during oper ation as l ong as all banks are in the
idle state. The mode register is divided into various fields
depending on functionality. The burst length field uses
A0~A2, burst type uses A3, addressing mode uses A4~A6,
A7~A8, A11,A12, BS0 and BS1 are used for vendor specific
options or test mode. And the write burst length is
programmed using A9. A7~A8, A11,A12, BS0 and BS1 must
be set t o low f or normal SDRAM operation.
Refer to table for specific codes for various burst length,
addressing modes and CAS lat encies.
A43L4616A
(July, 2019, Version 1.0) 13 AMIC Technology, Corp.
Device O perations (continued)
Bank Activate
The bank activate command is used to select a random row
in an idle bank. By asserting low on RAS and CS with
desired row and bank addresses, a row access is initiated.
The read or write operation can occur after a time delay of
tRCD(min) from the time of bank activation. tRCD(min) is an
internal timing parameter of SDRAM, therefore it is
dependent on operating clock frequency. The minimum
number of clock cycles required between bank activate and
read or write command should be calculated by dividing
tRCD(min) with cycle time of the clock and then rounding off
the result to the next higher integer. The SDRAM has 4
internal banks on the same chip and shares part of the
i nt ern al cir cui tr y to r edu ce c hi p ar ea, ther efor e i t r est ri cts t he
activation of all banks simultaneously. Also the noise
generated during sensing of each bank of SDRAM is high
requiring som e time for power supplies to recover before the
other bank can be sensed reliably. tRRD(min) specifies the
minimum time required between activating different banks.
The number of clock cycles required between different bank
activation must be calculated similar to tRCD specification.
The minimum time required for the bank to be active to
initiate sensing and restoring the complete row of dynamic
cells is determined by tRAS(min) specification before a
precharge command to that active bank can be asserted.
The maximum time any bank can be in the active state is
determined by tRAS(max). The number of cycles for both
tRAS(min) and tRAS(max) can be calculated similar to tRCD
specification.
Burs t Rea d
The burst read command is used to access burst of data on
consecutive clock cycles from an active row in an active
bank. The burst read command is issued by asser ting low on
C
S
and CAS with WE being high on the positive edge of
the clock. The bank must be active for at least tRCD(min)
before the burst read command is issued. The first output
appears CAS latency number of clock cycles after the issue
of burst read command. The burst length, burst sequence
and latency from the burst read command is determined by
the mode register which is already programmed. The burst
read can be initiated on any column address of the active
row. The address wraps around if the initial address does not
start from a boundary such that number of outputs from each
I/O are equal to the burst length programmed in the mode
register. The output goes into high-impedance at the end of
the burst, unless a new burst read was initiated to keep the
data output gapless. The burst read can be terminated by
issuing anot her burst read or burst writ e in the same bank or
the other active bank or a precharge command to the same
bank. The burst stop command is valid at every page burst
length.
Burs t Wr ite
The burst write command is similar to burst read command,
and is used to write data into the SDRAM consecutive clock
cycles in adjacent addresses depending on burst length and
burst sequence. By asserting low on CS ,CAS and WE
with valid column address, a write burst is initiated. The data
inputs are provided for the initial address in the same clock
cycle as the burst write command. The input buffer is
deselected at the end of the burst length, even though the
internal writing may not have been completed yet. The burst
write can be t erm inated by issui ng a burst read and DQM for
blocking data inputs or burst write in the same or the other
active bank. The burst stop command is valid only at full
page burst length where the writing continues at the end of
burst and the burst is wrap around. The write burst can also
be terminated by using DQM for blocking data and
precharging the bank “tRDL” after the last data input to be
written into the active row. See DQM OPERATION also.
DQM Ope r a tion
The DQM is used to mask input and output operation. It
works simil ar to OE during read oper ation and inhibits writing
during write operation. The read latency is two cycles from
DQM and zero cycle for write, which means DQM masking
occurs two cycles later in the read cycle and occurs in the
same cycle during write cycle. DQM operation is
synchronous with the clock, therefor e the masking occurs for
a complete cycle. The DQM signal is important during burst
int errupts of write with read or pr echarge in the SDRAM. Due
to asynchronous nature of the internal write, the DQM
operation is critical to avoid unwanted or incomplete writes
when the com plete burst write is not required.
Precharge
The precharge operation is performed on an active bank by
as ser ti ng l ow on CS ,RAS ,WE and A10/AP wi th valid BA
of the bank to be precharged. The precharge command can
be asserted anytim e after t RAS(min) is satisfied fr om the bank
activate command in t he desi red bank. “t RP” is defi ned as t he
minimum time required to precharge a ba nk.
The minimum number of clock cycles required to complete
row precharge is calculated by dividing “tRP” with clock cycle
tim e and rounding up to the next higher integer. Care should
be taken to make sure that burst write is completed or DQM
is used to inhibit writing before precharge command is
asserted. The maximum time any bank can be active is
specified by tRAS(max). Therefore, each bank has to be
precharged within tRAS(max) from the bank activate
command. At t he end of prechar ge, the bank enters the idle
state and i s ready to be activated again.
Entry to Power Down, Auto refresh, Self refresh and Mode
register Set etc, is possible only when both banks are in idle
state.
A43L4616A
(July, 2019, Version 1.0) 14 AMIC Technology, Corp.
Device O perations (continued)
Auto Prechar ge
The precharge operation can also be performed by using
auto precharge. The SDRAM internally generates the timing
to satisfy tRAS(min) and “ tRP” for the pr ogram m ed burst length
and CAS latency. The auto precharge command is issued at
the sam e time as burst read or burst write by asserting high
on A10/AP. If burst read or burst write command is issued
with low on A10/AP, the bank is left active until a new
command is asserted. Once auto precharge command is
given, no new commands ar e possible to that particular bank
until the bank achieves idle state.
Four Banks Precharge
All banks can be precharged at the same time by using
Precharge all command. Asserting low on CS ,RAS and
WE with high on A10/AP after both banks have satisfied
tRAS(mi n) requirem ent, per forms pr echarge on both banks. At
the end of tRP after perf ormi ng precharge all, both banks are
in idle st a te.
Auto Refresh
The storage cells of SDRAM need to be refreshed every
64ms to maintain data. An auto refresh cycle accomplishes
refresh of a single row of storage cells. The internal counter
increments automatically on every auto refresh cycle to
refresh all the rows. An auto refresh command is issued by
asse rting low on CS ,RAS and CAS wi th high on CKE and
WE. The auto refresh command can only be asserted with
both banks being in idle state and the devi ce is not in power
down mode (CKE is high in the previous cycle). The time
required to complete the auto refresh operation is specified
by “tRC(min)”. The mi nimum number of clock cycl es required
can be calculated by driving “tRC” with clock cycle time and
then rounding up to t he next higher integer. The auto refresh
command must be followed by NOP’s until the auto refresh
operation is completed. Both banks will be in the idle stat e at
the end of auto refresh operation. The auto refresh is the
preferred refresh mode when the SDRAM is being used for
normal data transactions. The auto refresh cycle can be
performed once in 15.6us or a burst of 8192 auto refresh
cycles once in 64ms.
Self Refresh
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode for
data retention and low power operation of SDRAM. In self
refresh mode, the SDRAM disables the internal clock and al l
the input buffers except CKE. The refresh addressing and
timing is internally generated to reduce power consum ption.
The self refresh mode is entered from al l banks i dle state by
asserting low on CS ,RAS ,CAS and CKE with high on
WE. Once the self refresh mode is entered, only CKE state
being low matters, all the other inputs including clock are
ignored to remain in the self re f re sh.
The self refresh is exi ted by restarting the ext ernal clock and
then asserti ng hi gh on CKE. Thi s must be followed by NOP’s
for a minimum time of “tRC” before the SDRAM reaches idle
state to begin normal operation. If the system uses burst auto
refresh during normal operation, it is recommended to used
burst 8192 auto refresh cycles immediately after exiting self
refresh.
A43L4616A
(July, 2019, Version 1.0) 15 AMIC Technology, Corp.
1) Click Suspended During Write (BL=4)
Masked by CKE
Q0 Q1 Q3
Q0 Q2 Q3
Suspended Dout
2) Clock Suspended During Read (BL=4)
WR
Masked by CKE
D0 D1 D2 D3
D0 D1 D2 D3
Not Written
DQ(CL3)
DQ(CL2)
Internal
CLK
CKE
CMD
CLK
RD
Q2
Q1
Note: CLK to CLK disable/enable=1 clock
Basic f eat ure And Functio n Descri ptions
1. CLOCK Suspend
2. DQ M Operat io n
* Note : 1. DQ M makes data out Hi-Z after 2 clocks which should masked by CKE “L”.
2. DQM mask s both da ta- in a n d d a ta-out.
1) Write Mask (BL=4)
Masked by CKE
Q0 Q2 Q3
Q1 Q2 Q3
DQM to Data-out Mask = 2
2) Read Mask (BL=4)
WR
Masked by CKE
D0 D1 D3
D0 D1 D3
DQM to Data-in Mask = 0CLK
DQ(CL3)
DQ(CL2)
DQM
CMD
CLK
RD
Hi-Z
Hi-Z
Q0 Q2 Q4
2) Read Mask (BL=4)
RD
Hi-Z
Hi-Z
Hi-Z Q6 Q7 Q8
Hi-Z
Q1 Q3
Hi-Z Hi-Z Q5 Q6 Q7
CLK
CMD
CKE
DQM
DQ(CL2)
DQ(CL3)
A43L4616A
(July, 2019, Version 1.0) 16 AMIC Technology, Corp.
3. CAS Interrupt (I)
Note : 1. By “Interrupt”, It is possi ble to stop burst read/wr it e by external command before the end of burst.
By “CAS Interrupt”, to stop burst read/write by CAS access; read, write and block write.
2. tCCD : CAS to CAS delay. (=1CLK)
3. tCDL : Last dat a in to new column addr ess del ay. (= 1CLK).
1) Read interrupted by Read (BL=4)
Note 1
RD RD
AB
QA0 QB0 QB1 QB2 QB3
QA0 QB0 QB1 QB2 QB3
CLK
CMD
ADD
DQ(CL2)
DQ(CL3) t
CCD
Note2
2) Write interrupted by Write (BL =2)
WR WR
AB
CLK
CMD
ADD t
CCD Note2
DA0 DB0 DB1
t
CDL
Note3
DQ
3) Write interrupted by Read (BL =2)
WR RD
AB
t
CCD Note2
DA0 QB0 QB1
t
CDL
Note3
DQ(CL2)
QB0 QB1
DQ(CL3) DA0
A43L4616A
(July, 2019, Version 1.0) 17 AMIC Technology, Corp.
4. CAS Interrupt (II) : Read Interrupted Write & DQM
* Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.
2. To prevent bus contention, DQ M should be issued which makes a least one gap between data in and data out.
RD WR
D0 D1 D2 D3
RD WR
D0 D1 D2 D3
WRRD
Hi-Z
Hi-Z D0 D1 D2 D3
RD WR
D0 D1 D2 D3Q0 Hi-Z
Note 1
RD WR
D0 D1 D2 D3
RD WR
D0 D1 D2 D3
WRRD
Hi-Z D0 D1 D2 D3
RD
WR
D0 D1 D2Q0 Hi-Z
Note 2
D0 D1 D2 D3
RD WR
WR
(1) CL=2, BL=4
CLK
i) CMD
DQM
DQ
ii) CMD
DQM
DQ
iii) CMD
DQM
DQ
iv) CMD
DQM
DQ
(2) CL=3, BL=4
CLK
i) CMD
DQM
DQ
ii) CMD
DQM
DQ
iii) CMD
DQM
DQ
iv) CMD
DQM
DQ
v) CMD
DQM
DQ D3
A43L4616A
(July, 2019, Version 1.0) 18 AMIC Technology, Corp.
5. Write I nterrupt ed b y Precharge & DQM
Note : 1. To inhibit invalid write, DQM should be issued.
2. This pr echarge command and bur st write comm and should be of the same bank, otherwise i t is not pr echarge
int errupt but only another bank pr echarge of dual banks operation.
6. Precharge
7. Auto Precharge
* Note : 1. The r ow acti ve command of the precharge bank can be issued after tRP fr om thi s poi n t.
The new read/write command of other active bank can be issued fr om thi s point.
At burst read/write with auto precharge, CAS interr upt of the same/another bank is illegal.
WR PRE
D0 D1 D2 D3
CLK
CMD
DQ
1) Normal Write (BL=4)
t
RDL
RD PRE
Q0 Q1 Q2 Q3
CLK
CMD
DQ(CL2)
2) Read (BL=4)
Q0 Q1 Q2 Q3DQ(CL3)
WR
D0 D1 D2 D3
CLK
CMD
DQ
1) Normal Write (BL=4)
Note 1
RD
Q0 Q1 Q2 Q3
CLK
CMD
DQ(CL2)
2) Read (BL=4)
Q0 Q1 Q2 Q3DQ(CL3)
Auto Precharge Starts
Note 1
Auto Precharge Starts
WR PRE
Note 2
Note 1
D0 D1 D2 D3
Masked by DQM
CLK
CMD
DQM
DQ
A43L4616A
(July, 2019, Version 1.0) 19 AMIC Technology, Corp.
8. Bu rst Stop & Interrup t ed by Prech arge
WR
D0 D1 D2 D3
CLK
CMD
DQM
DQ
1) Normal Write (BL=4)
PRE
t
RDL
Note 1
WR
D0 D1 D2 D3
CLK
CMD
DQM
DQ
2) Write Burst Stop (BL=8)
STOP
t
BDL
Note 2
D4 D5
RD
Q0 Q1
CLK
CMD
DQ(CL2)
1) Read Interrupted by Precharge (BL=4)
PRE
Note 3
DQ(CL3) Q0 Q1
1
2
RD
Q0 Q1
CLK
CMD
DQ(CL2)
4) Read Burst Stop (BL=4)
STOP
DQ(CL3) Q0 Q1
1
2
9. MRS
Not e : 1. tRDL: 1CLK
2. tBDL: 1CLK; Last data in to bur st stop del ay.
Read or write burst stop command is valid at ev ery burst length.
3. Number of vali d output dat a after row precharge or burst stop: 1,2 for CAS latency = 2, 3 respectively.
4. PRE: All banks precharge if necessar y.
MRS can be issued only when all banks are in precharged st ate.
PRE MRS
Note 1
CLK
CMD
Mode Register Set
2CLK
ACT
t
RP
A43L4616A
(July, 2019, Version 1.0) 20 AMIC Technology, Corp.
10. Clock Suspend Exit & Power Down Exit
11. Auto Refresh & Self Refresh
* Note : 1. Active power down : one or more bank active state.
2. Precharge power down : both bank precharge state.
3. The auto refresh is the same as CBR refr esh of conventional DRAM.
No prechar ge commands are required aft er Auto Refr esh command.
During tRC from auto refresh command, ot her comm and can not be accept ed.
4. Before executing auto/self refresh com m and, both banks must be i dle state.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. Du r ing self re fresh mode , refresh inte rva l and refresh oper ation are perfor med internally.
After self refres h entry, self refresh mode is kep t while CK E is LO W.
During self refresh mode, all inputs expect CKE will be don’t cared, and out puts will be in Hi-Z state.
During tRC from self refresh exit command, any other command can not be accepted.
Before/After self refresh mode, burst auto refresh cycle (8K cycles ) is recommended.
2) Self Refresh
CLK
CMD
1) Auto Refresh
CKE
Internal
CLK
CLK
CMD SR
CKE
PRE
Note 4
PRE AR CMD
Note 5
~
~
~
~
~
~
~
~
t
RP
t
RC
Note 3
Note 6
~
~
CMD
~
~
Note 4
t
RP
t
RC
~
~
~
~
~
~
2) Power Down (=Precharge Power Down) Exit
Note 1
CLK
CMD
1) Clock Suspend (=Active Power Down) Exit
RD
t
SS
CKE
Internal
CLK
Note 2
CLK
CMD ACT
CKE
Internal
CLK
t
SS
NOP
A43L4616A
(July, 2019, Version 1.0) 21 AMIC Technology, Corp.
12. About Burst Type Control
Basic
MODE Sequential coun ting At MRS A3=”0”. See the BURST SEQUENCE TABE.(BL=4,8)
BL=1,2,4,8 and Full Page
Int erleave counting At MRS A3=” 1”. See the BURST SEQUENCE TABE.(BL=4,8)
BL=4,8 At BL=1,2 Interleave Counti ng = Sequential Counting
Random
MODE Random column Access
tCCD = 1 CLK Every cycle Read/W rite Command with random column address can realize
Random Column Access.
That is simila r to Extended Data Ou t (ED O) Operation of con ve ntion DRAM .
13. About Burst Length Control
Basic
MODE
1 At MRS A2,1,0 = “000”.
At auto precharge, tRAS should not be violated.
2 At MRS A2,1,0 = “001”.
At auto precharge, tRAS should not be violated.
4 At MRS A2,1,0 = “010”
8 At MRS A2,1,0 = “011”.
Full Page At MRS A2,1,0 = “111”
Special
MODE
BRSW At MRS A9=” 1”.
Read burst = 1,2,4,8, FP write Burst =1
At auto precharge of wri te, tRAS s hou ld n ot be violated.
Interrupt
MODE
RAS Inte rrupt
(Interrupted by Prec ha rg e)
Befor e the end of burst, Row precharge comm and of the same bank
Stops read/wr ite burs t with Row precharge.
tRDL=2 with DQM, valid DQ after burst stop is 1,2 for CL=2,3 re spectively
During read /wr ite b urst with au to prec ha rge, RAS interrupt canno t be issued.
CAS Inte rrupt Before the end of burst, new read
/
write stops read/write burst and starts new
read/w rite b urs t or bloc k write.
During read /wr ite b urst with au to prec ha rge, CAS interrupt can not be issued.
A43L4616A
(July, 2019, Version 1.0) 22 AMIC Technology, Corp.
Power On Sequence & Auto Refresh
KEY Ra
BS
Ra
High level is necessary
High level is necessary
High-Z
t
RP
t
RC
0 12345678910111213141516171819
CLOCK
CKE
CS
RAS
CAS
ADDR
BS0, BS1
A10/AP
WE
DQM
DQ
Precharge
(All Banks) Auto Refresh Auto Refresh Mode Regiser Set
Row Active
(A-Bank)
: Don't care
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
A43L4616A
(July, 2019, Version 1.0) 23 AMIC Technology, Corp.
Single Bit Read-Wri t e- Read Cycles (Same Page) @CAS Latency=3, Burst Length= 1
Rb
High
t
RCD
t
RP
0 12345678910111213141516171819
CLOCK
CKE
CS
RAS
CAS
ADDR
BS0, BS1
A10/AP
WE
DQM
DQ
Row Active Read Write Row Active
: Don't care
t
CH
t
CL
t
CC
Ra Ca Cb Cc
BS BS BS BS BS BS
Ra Rb
Qa Db Qc
t
RA
S
t
RC
t
SH
t
SS
*Note 1
t
SH
t
SS
t
CCD
t
SH
t
SS
t
SH
t
SS
t
SS
t
SH
*Note 2 *Note 2,3 *Note 2,3 *Note 2,3 *Note 4 *Note 2
*Note 3 *Note 3 *Note 3 *Note 4
t
SH
t
SS
t
SH
t
SS
t
SH
t
SS
t
RA
C
t
SA
C
t
SLZ
t
OH
t
SHZ
Read
Precharge
A43L4616A
(July, 2019, Version 1.0) 24 AMIC Technology, Corp.
* Note : 1. Al l inputs can be don’t care when CS is high at the CLK high going edge.
2. Bank acti ve & r ead/write are control led by BS0, BS1.
BS1 BS0 Active & Read/ Write
0 0 Bank A
0 1 Bank B
1 0 Bank C
1 1 Bank D
3. Enable and disable auto precharge functi on are controll ed by A10/AP in read/write command.
A10/AP BS1 BS0 Operation
0
0 0 Disable auto precharge, leave bank A acti ve at end of burst.
0 1 Disable auto precharge, leave bank B acti ve at end of burst.
1 0 Disable auto precharge, leave bank C acti ve at end of burst.
1 1 Disable auto precharge, leave bank D acti ve at end of burst.
1
0 0 Enable auto precharge, precharge bank A at end of burst.
0 1 Enable auto precharge, precharge bank B at end of burst.
1 0 Enable auto precharge, precharge bank C at end of burst.
1 1 Enable auto precharge, precharge bank D at end of burst.
4. A10/AP and BS0, BS1 control bank pr echarge when precharge command is asser ted.
A10/AP BS1 BS0 Precharge
0 0 0 Bank A
0 0 1 Bank B
0 1 0 Bank C
0 1 1 Bank D
1 X X All Banks
A43L4616A
(July, 2019, Version 1.0) 25 AMIC Technology, Corp.
Read & Wri t e Cycle at Same Bank @Burst Length=4
High
t
RC
t
RCD
0 12345678910111213141516171819
CLOCK
CKE
CS
RAS
CAS
ADDR
BS0
WE
DQM
DQ
(CL = 2)
Row Active
(A-Bank) Read
(A-Bank) Precharge
(A-Bank) Row Active
(A-Bank) Precharge
(A-Bank)
: Don't care
*Note 1
*Note 2
Ra Ca0 Rb Cb0
Ra RbA10/AP
Qa0
t
OH
Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3
t
RAC
t
SAC
*Note 3 t
SHZ
*Note 4
Qa0
t
OH
Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3
t
RAC
t
SAC
*Note 3 t
SHZ
*Note 4 t
RDL
Write
(A-Bank)
DQ
(CL = 3)
BS1
t
RDL
*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row pr echarg e c an inter r upt burst on an y c yc l e. [CA S latency-1] vali d outp ut d ata av ai labl e after Row
ent ers prech ar g e. L ast val id ou t p ut w il l be H i-Z aft er tSHZ from the clock.
3. Access time from Row address. tCC*(tRCD + CAS latency -1) + tSAC
4. O utp ut wil l be H i-Z aft er th e end of burst. (1, 2, 4 & 8)
A43L4616A
(July, 2019, Version 1.0) 26 AMIC Technology, Corp.
Page Read & Write Cycle at Same Ban k @Burst Length=4
t
RDL
High
t
RCD
0 12345678910111213141516171819
CLOCK
CKE
CS
RAS
CAS
ADDR
BS0
WE
DQM
DQ
(CL=2)
Row Active
(A-Bank) Read
(A-Bank) Precharge
(A-Bank)
: Don't care
*Note 2
Ra Ca Cb Cc
RaA10/AP
Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 Dd1
Qa0 Qa1 Qb0
Write
(A-Bank)
Cd
t
CDL
*Note1 *Note3
Dc0 Dc1 Dd0 Dd1
Read
(A-Bank) Write
(A-Bank)
DQ
(CL=3)
BS1
Qb2
Qb1
*Note : 1. To write data before burst read ends, DQM should be asserted three cy cle prio r to write
command to avoid bus contention.
2. Row pr ech ar g e w il l int er ru pt wr it in g. Last d at a input, t RDL before Row precharge, will be wri tten.
3. DQM should ma sk invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
A43L4616A
(July, 2019, Version 1.0) 27 AMIC Technology, Corp.
Page Read Cycle at Different Bank @Burst Length = 4
Read
(C-Bank)
Row Active
(D-Bank)
Read
(B-Bank)
Read
(A-Bank)
High
0 1 2 3 4 5 6 7 8 9 10111213141516171819
CLOCK
CKE
CS
RAS
CAS
ADDR
BS1
Row Active
(A-Bank)
Row Active
(B-Bank) : Don't care
RAa RBb
A10/AP
CBb
Row Active
(C-Bank)
*Note 1
*Note 2
CAa
RAa
WE
DQM
QBb2QBb1QAa0 QAa1 QAa2 QBb0 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
QBb2QBb1QAa0 QAa1 QAa2 QBb0 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
Read
(D-Bank)
Precharge
(C-Bank)
Precharge
(D-Bank)
DQ
(CL=2)
DQ
(CL=3)
BS0
RBb RCc RDd
Precharge
(A-Bank) Precharge
(B-Bank)
RCc CCcRDd CDd
* Note : 1. CS can be don’t care when RAS, CAS and WE are high at the clo ck high going edge.
2. To interrupt a burst read by row precharge, both the read ad the precharge banks must be the same.
A43L4616A
(July, 2019, Version 1.0) 28 AMIC Technology, Corp.
Pag e Wri t e Cycle at Different Bank @Burst Length=4
High
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
CS
RAS
CAS
ADDR
BS1
Row Active
(A-Bank)
Row Active
(B-Bank)
: Don't care
A10/AP
Write
(A-Bank)
WE
DBb1DBb0DAa0 DAa1 DAa2 DAa3 DBb2 DBb3 DCc0 DCc1
Write
(C-Bank)
Precharge
(All Banks)
DQM
DQ t
CDL
DDd0 DDd1
*Note 2
t
RDL
*Note 1
Write
(D-Bank)
Write
(B-Bank)
Row Active
(C-Bank)
Row Active
(D-Bank)
RAa RBb CBbCAa RCc RDd CCc CDd
RAa
BS0
RBb RCc RDd
CDd2
* Note:
1. To in te rrupt bu rs t write by Row pre charge, DQM should be asserted to mask inval id input data.
2. To interr upt burst wri te by Row precharge, bot h the writ e and prec har ge banks must be the sam e.
A43L4616A
(July, 2019, Version 1.0) 29 AMIC Technology, Corp.
Read & Wri t e Cycle at Different Bank @Burst Length=4
High
0 1 2 3 4 5 6 7 8 9 10111213141516171819
CLOCK
CKE
CS
RAS
CAS
ADDR
BS1
Row Active
(A-Bank) Read
(A-Bank)
: Don't care
RAa CAa
A10/AP
RDb
Precharge
(A-Bank)
CDb CBc
RAa
WE
QAa2QAa1QAa0 QAa3 DDb0
Write
(D-Bank) Read
(B-Bank)
DQM
QBc0 QBc1
RBc
RBCRDb t
CDL
*Note 1
QAa3QAa2QAa0 QAa1 DDb0 DDb1 QBc0DDb2 DDb3 QBc1 QBc2
DQ
(CL=2)
DDb1 DDb2 DDb3
DQ
(CL=3)
Row Active
(B-Bank)
Row Active
(D-Bank)
BS0
* Note : tCDL should be met to complete write.
A43L4616A
(July, 2019, Version 1.0) 30 AMIC Technology, Corp.
Read & Wri t e Cycle with Auto P recharge @Burst L eng th=4
High
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
CS
RAS
CAS
ADDR
BS1
Row Active
(A-Bank)
Row Active
(D-Bank)
: Don't care
RAa RBb
A10/AP
CAa
Auto Precharge
Start Point
(A-Bank/CL=2)
RAa
WE
QAa2QAa1QAa0 QAa3 DDb0
Auto Precharge
Start Point
(D-Bank)
DQM
CBb
QAa3QAa2QAa0 QAa1 DDb0 DDb1 DDb2 DDb3
DQ
(CL=2)
DDb1 DDb2 DDb3
DQ
(CL=3)
Write with
Auto Precharge
(D-Bank)
RBb
Read with
Auto Precharge
(A-Bank)
BS0
Auto Precharge
Start Point
(A-Bank/CL=3)
*Note : tRCD should be controlled to meet minimum tRAS before internal precharge start.
(In the case of Burs t L eng th=1 & 2, BRSW mode)
A43L4616A
(July, 2019, Version 1.0) 31 AMIC Technology, Corp.
Clock Suspensi on & DQM Operatio n Cycl e @ C AS Latency = 2, Burst Length=4
0 12345678910111213141516171819
CLOCK
CKE
CS
RAS
CAS
ADDR
BS1
Row Active
: Don't care
Ra
A10/AP
Ca
Ra
WE
DQM
Qa1 Qb0 Qb1 Dc0
DQ
Clock
Suspension
Read
Bank 0
Cb
Read
Bank 0
Qa0 Dc2
* Note 1
Qa2
Cc
Clock
Suspension
t
SHZ
Qa3
t
SHZ
Write
DQM
Write
Bank 0
Read DQM
BS0
* Note : DQM needed to prevent bus contention.
A43L4616A
(July, 2019, Version 1.0) 32 AMIC Technology, Corp.
Read In t errupt ed by Prech arge Command & Read Burst S top Cycl e @Burst Leng th= 8
High
0 1 2 3 4 5 6 7 8 9 10111213141516171819
CLOCK
CKE
CS
RAS
CAS
ADDR
BS1
Row Active
(A-Bank)
: Don't care
RAa
A10/AP
CAa
WE
QAa3QAa2QAa1 QAa4 QAb0
DQM
QAa4QAa3QAa1 QAa2 QAb0 QAb1 QAb2 QAb3
DQ
(CL=2)
QAb1 QAb2 QAb3
DQ
(CL=3)
Precharge
(A-Bank)
Read
(A-Bank)
CAb
Read
(A-Bank)
Burst Stop
1
QAa0 QAb4 QAb5
1
QAa0
2
QAb4 QAb5
2
BS0
RAa
* Not e : 1. At ful l p ag e mod e, bu rs t is wrap-arou nd at th e en d of bur s t . So aut o pr ec h arge is im p oss i bl e.
2. About the valid DQ’s after burst stop, it is same as the case of RAS inte rrupt.
Both cases are illustr ated above timing diagram. See the label 1,2 on them.
But at burst write, burst stop and RAS interr upt shoul d be compared carefully.
Refer t he timing diagram of “Full page write burst stop cycle”.
3. B urst stop is vali d at every bu rst length.
A43L4616A
(July, 2019, Version 1.0) 33 AMIC Technology, Corp.
Write Int errup t ed b y Prech arge Command & Write Burst Stop Cycle @ Burst Leng t h = 8
High
0 12345678910111213141516171819
CLOCK
CKE
CS
RAS
CAS
ADDR
BS1
Row Active
(A-Bank)
: Don't care
RAa
A10/AP
CAa
WE
DQM
DAa4DAa3DAa1 DAa2 DAb0 DAb1 DAb2 DAb3
DQ
Precharge
(A-Bank)
Write
(A-Bank)
CAb
Write
(A-Bank)
Burst Stop
DAa0 DAb4 DAb5
t
RDL
t
BDL
* Note 2
BS0
RAa
* Not e : 1. At ful l p ag e mod e, bu rs t is wrap-arou nd at th e en d of bur s t . So aut o pr ec h arge is im p oss i bl e.
2. Data-in at the cycle of inte rrupted by precharge cannot be written into the corresponding memory cell.
It is define d by AC parameter of tRDL(=2CLK).
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQ M sh ould m as k in val i d input data on prech arg e com m an d c ycl e w h en asser ti ng prec harge bef ore end of bur s t .
Input data after Row prec harge cycle will be masked internally.
3. Burs t st op is val id at every bur s t len gt h .
A43L4616A
(July, 2019, Version 1.0) 34 AMIC Technology, Corp.
Active/P recharge P ower Down Mode @CAS L antency= 2, Burst Leng th=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
CS
RAS
CAS
ADDR
BS1
Precharge
Power-down
Exit
: Don't care
A10/AP
Active
Power-down
Entry
Row
Active
WE
Qa2
Read Precharge
DQM
DQ Qa0 Qa1
Precharge
Power-down
Entry
t
SS
t
SS
* Note 2
* Note 1
*Note 3
t
SS
t
SS
Ra Ca
Ra
Active
Power-down
Exit
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
BS0
~
~
~
~
~
~
~
~
t
SHZ
* Note : 1. All banks should be in idle state prior to ente ring precha rge power down mode.
2. CKE should be set high at least “1CLK + tSS” prior to Row active command.
3. Cannot violate minimum refresh specification. (64ms)
A43L4616A
(July, 2019, Version 1.0) 35 AMIC Technology, Corp.
Self Refresh Entry & Exit Cycle
* Note : TO ENTER SELF REFRESH MODE
1.
CS, RAS & CAS and CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the sy stem clock can be don’t care except for CKE.
3. The device remains in self refresh mode a s long as CKE stays “Low”.
(cf.) Once the device enters self refresh mode, minimum tRAS is required be fo re exit from self re fresh.
TO EXIT SELF REFRESH MODE
4. System clo ck restart and be stable before returning CKE high.
5.
CS starts from high.
6. Minimum tRC is required after CKE going high to complete self refresh exit.
7. 8K cycle of burst auto refresh is required before self refre sh entry and after self refresh exit.
If the system uses burst refre sh.
0 12345678910111213141516171819
CLOCK
CKE
CS
RAS
CAS
ADDR
BS0, BS1
: Don't care
A10/AP
WE
Self Refresh Exit Auto Refresh
DQM
DQ
Self Refresh Entry
t
SS
* Note 4
* Note 1
~
~
~
~
~
~
~
~
~
~
* Note 3
* Note 2
~
~
t
SS
* Note 6
t
RC
min.
~
~
~
~
* Note 5
~
~
~
~
* Note 7 * Note 7
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
Hi-ZHi-Z
A43L4616A
(July, 2019, Version 1.0) 36 AMIC Technology, Corp.
Mo de Register Set Cycl e Auto Ref resh Cycle
0 123456 012345678910
CLOCK
CKE
CS
RAS
CAS
ADDR
: Don't care
WE
Auto Refresh New Command
DQM
DQ
MRS
~
~~
~
* Note 1
~
~
~
~
Hi-ZHi-Z
High High
~
~
~
~
t
RC
*Note 2
~
~
~
~
~
~
~
~
~
~
Key
* Note 3
~
~
~
~
New
Command
~
~
~
~
Ra
* All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
* Note : 1. CS, RAS , CAS & WE activation at the same clock cycle with address key will set internal
mode register.
2. Mi ni mu m 2 cl ock c yc l es is r equ ired b efore new RAS ac tivation.
3. Please refer to M ode Register S et table.
A43L4616A
(July, 2019, Version 1.0) 37 AMIC Technology, Corp.
Func t i on Tru t h Tab le ( Ta ble 1 )
Current
State CS RA
S
CAS WE BA Address Action Note
IDLE
H X X X X X NOP
L H H H X X NOP
L H H L X X ILLEGAL 2
L H L X BA CA, A10/AP ILLEGAL 2
L L H H BA RA Row Ac tive; Latc h Row Address
L L H L BA A10/PA NOP 4
L L L H X X Auto Refresh or Self Refresh 5
L L L L OP Code Mode Register Access 5
Row
Active
H X X X X X NOP
L H H H X X NOP
L H H L X X ILLEGAL 2
L H L H BA CA,A10/AP Begin Read; Latch CA; Determine AP
L H L L BA CA,A10/AP Begin Write ; Latch CA ; De te r mine AP
L L H H BA RA ILLEGAL 2
L L H L BA PA Precharge
L L L X X X ILLEGAL
Read
H X X X X X NO P(Contin u e Burst to En d →Row Activ e)
L H H H X X NOP(Continue Burst to En d →Row Activ e)
L H H L X X Term burst →Row Activ e
L H L H BA CA,A10/AP Term burst; Begin Read; Latch CA; Determine AP 3
L H L L BA CA,A10/AP Term burst; Begin Write; Latch CA; Determi ne AP 3
L L H H BA RA ILLEGAL 2
L L H L BA CA,A10/AP Term Burst; Precharge timi ng for Reads 3
L L L X X X ILLEGAL
Write
H X X X X X NOP( Conti n u e Burst to End →Row Ac tive)
L H H H X X NO P(Contin ue Burst to En d →Row Active)
L H H L X X Term burst →Row Act iv e
L H L H BA CA,A10/AP Term burst; Begin Read; Latc h CA; Determi ne AP 3
L H L L BA CA,A10/AP Term burst; Begin Write; Latch CA; Determine AP 3
L L H H BA RA ILLEGAL 2
L L H L BA A10/AP Term Burst; Precharge timing for Writes 3
L L L X X X ILLEGAL
Read wi th
Auto
Precharge
H X X X X X NOP( Conti n u e Burst to End →Pre charge )
L H H H X X NO P(Contin ue Burst to En d →Precharge)
L H H L X X ILLEGAL
L H L H BA CA,A10/AP ILLEGAL 2
L H L L BA CA,A10/AP ILLEGAL 2
L L H X BA RA, PA ILLEGAL
L L L X X X ILLEGAL 2
A43L4616A
(July, 2019, Version 1.0) 38 AMIC Technology, Corp.
Function Truth Table (Table 1, Continued)
Current
State CS RA
S
CAS WE BS Address Action Note
Write with
Auto
Precharge
H X X X X X NOP( Conti n u e Burst to End →Pre charge )
L H H H X X NO P(Contin ue Burst to En d →Precharge)
L H H L X X ILLEGAL
L H L H BA CA,A10/AP ILLEGAL 2
L H L L BA CA,A10/AP ILLEGAL 2
L L H X BA RA, PA ILLEGAL
L L L X X X ILLEGAL 2
Precharge
H X X X X X NOP→Idle after tRP
L H H H X X NOP→Idle after tRP
L H H L X X ILLEGAL
L H L X BA CA,A10/AP ILLEGAL 2
L L H H BA RA ILLEGAL 2
L L H L BA A10/PA
NOP→Idle after tRP 2
L L L X X X ILLEGAL 4
Row
Activating
H X X X X X NOP→Row Active af ter tRCD
L H H H X X NOP→Row Active after tRCD
L H H L X X ILLEGAL
L H L X BA CA,A10/AP ILLEGAL 2
L L H H BA RA ILLEGAL 2
L L H L BA A10/PA ILLEGAL 2
L L L X X X ILLEGAL 2
Refre shing
H X X X X X NOP→Idle after tRC
L H H X X X NOP→Idle after tRC
L H L X X X ILLEGAL
L L H X X X ILLEGAL
L L L X X X ILLEGAL
Mode
Register
Accessing
H X X X X X NOP→Idle after 2 cl ocks
L H H H H X NOP→Idle after 2 clocks
L H H L X X ILLEGAL
L H L X X X ILLEGAL
L L X X X X ILLEGAL
Abbreviations
RA = Row Address BS = Ban k Address AP = Auto Precharge
NOP = No Operation Comm and CA = Col umn Address PA = Precharge All
Note: 1. All entries assume that CKE was active (High) during the precedi ng clock cycle and the current clock cycle.
2. Ille gal to bank in spe cifie d state : Function may be le gal in the bank indicated by BA, de pending on the state of that bank.
3. Must satisf y bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharging or in idl e stat e. May precharge bank indicated by BS (and PA).
5. Illegal if any banks is not idle.
A43L4616A
(July, 2019, Version 1.0) 39 AMIC Technology, Corp.
Func t i on Tru t h Tab le f or CK E (Ta ble 2)
Current
State CKE
n-1 CKE
n CS RA
S
CAS WE Address Action Note
Self
Refresh
H X X X X X X INVALID
L H H X X X X
Exit Sel f Ref resh→ABI af ter tRC 6
L H L H H H X
Exit Sel f Ref resh→ABI af ter tRC 6
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
L L X X X X X NOP(Maintain Self Refresh)
Both
Bank
Precharge
Power
Down
H X X X X X X INVALID
L H H X X X X
Exit Power Down→ABI 7
L H L H H H X
Exit Power Down→ABI 7
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
L L X X X X X NOP(Maintain Power Down Mode)
All
Banks
Idle
H H X X X X X Refer to Table 1
H L H X X X X Enter Power Down 8
H L L H H H X Enter Power Down 8
H L L H H L X ILLEGAL
H L L H L X X ILLEGAL
H L L L H H RA Row ( & Bank ) Activ e
H L L L L H X Enter Self Refresh 8
H L L L L L OPCODE MRS
L L X X X X X NOP
Any State
Other than
Listed
Above
H H X X X X X Refer to Operations in Table 1
H L X X X X X Begin Clock Suspend next cycle 9
L H X X X X X Exit Clock Suspend next cycle 9
L L X X X X X Maintain clock Suspend
Abbr eviati ons : ABI = All Banks Idl e
Note: 6. After CKE’s low to high transition to exit self refresh mode, a minimum of tRC(min) has to be elapse before issuing a
new command.
7. CKE low to high transit ion is asynch ronou s as if it rest ar ts internal clock.
A mi nimum setup t ime “tSS + one clock” must be sati sfi ed before any command can be issued other than exit .
8. Power-down and self refresh can be ent ered only when al l the banks are in idle state.
9. Must be a l egal command.
A43L4616A
(July, 2019, Version 1.0) 40 AMIC Technology, Corp.
Part Numb erin g Scheme
A43 XX
Package Type
V: TSOP
G: CSP
Operating Vcc
L: 3V~3.6V
P: 2.3V~2.7V
E: 1.7V~2.0V
Device Version*
Device Type
A43: AMIC SDRAM
Device Density
06: 1M
16: 2M
26: 4M
36: 8M
46: 16M
56: 32M
83: 256K
Temperature
X
Package Material
Blank: normal
F: PB free
X
* Optional
XX
XX X
Mobile Function*
XX
C70~C0:Blank °° gradeIndustrial C85~C-40:U °°
Speed
95: 105 MHz
75: 133 MHz
7: 143 MHz
6: 166 MHz
55: 183 MHz
5: 200 MHz
I/O Width
08: 8 I/O
16: 16 I/O
32: 32 I/O
C85~C-40:A °° Automative grade
A43L4616A
(July, 2019, Version 1.0) 41 AMIC Technology, Corp.
Orde r ing Infor m a tion
Part No. Cycle Time (ns) Clock Frequency (MHz) Access Time Package
A43L4616AV-6F 6 166@ CL = 3 5.4 ns 54 Pb- Free TSOP (II)
A43L4616AV-6UF 54 Pb-Fr ee TSOP (II)
A43L4616AV-7F
7 143@ CL = 3 5.4 ns
54 Pb-Fr ee TSOP (II)
A43L4616AV-7UF 54 Pb-Fr ee TSOP (II)
A43L4616AV-7AF 54 Pb-Fr ee TSOP (II)
A43L4616AV-75F 7.5 133@ CL = 3 5.4 ns 54 Pb-Fr ee TSOP (II)
A43L4616AV-75UF 54 Pb-Fr ee TSOP (II)
Note: -U is for industrial operating temperature range -40ºC to +85ºC .
-A is for automotive operati ng temperature range -40ºC to +85ºC.
A43L4616A
(July, 2019, Version 1.0) 42 AMIC Technology, Corp.
Package Information
TSOP 54L (Type II) Outline Dimensions unit: mm
c
b
E
127
54 28
D
ZD
e
A2
A
C
Detail "A"
E1
L
A1
Detail "A"
θ
D
0.10 C
Symbol Dimensions in mm
Min Nom Max
A - - 1.20
A1 0.05 - 0.15
A2 0.95 1.00 1.05
b 0.28 - 0.45
c 0.12 - 0.21
D 22.12 22.22 22.32
E 11.56 11.76 11.96
E1 10.06 10.16 10.26
L 0.40 0.50 0.60
e 0.80 BSC
θ 0° - 8°
ZD 0.71 REF
Notes:
1. Dim ensi on D does not include mold pr otr usions or gate bur r s.
2. Dimension E1 does not include interlead mold protrusions .
3. Dimens ion b doe s not include damber protrusion / intrusion.
4. All dim ensions and t olerances take reference to JEDEC MS- 024 FA.
