Alt er a Cor pora t ion 1
FLEX 10KE
Embedded Programmable
Logic Device
Jan uary 2003, ver. 2.5 Data Sheet
DS-F10KE-2.5
®
Features... Embedded programmable logic devices (PLDs), providing
system-on-a-programmable-chip (SOPC) integration in a single
device
Enhanced embe dded array for imp l ementing megafuncti o ns
such as efficient memory and specialized logic functions
Dual-port capability with up to 16-bit width per embedded array
block (EAB)
Logic a rray for general logic functions
High density
30,000 to 200,000 typical gates (see Tables 1 and 2)
Up to 98,304 RAM bits (4,096 bits per EAB), all of which can be
used with out red ucin g logi c capacity
System-le vel features
MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or
5.0-V de vice s
Low power consumption
Bidire ctio nal I/ O performance (tSU and tCO) up to 212 MHz
Fully compliant with the PCI Special Interest Group (PCI SIG)
PCI Local Bus Specification, Revision 2.2 for 3. 3-V ope r ation at
33 MHz or 66 MHz
-1 speed grade dev ices are comp lian t with PCI Local Bus
Specification, Revision 2.2, for 5.0-V operation
Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) cir cuitry compliant with IEEE Std. 11 49.1-1990, available
without consuming additional device logic
fFor information on 5.0- V FLEX® 10K or 3.3-V FLEX 10KA devices, see the
FLEX 10K Embedded Programmable Logic Family Data Sheet.
Table 1. FLEX 10KE Device Features
Feature EPF10K30E EPF10K50E
EPF10K50S
Typical gates (1) 30,000 50,000
Maximum system gates 119,000 199,000
Logic ele m ent s (LE s) 1,72 8 2,88 0
EABs 6 10
Total RA M bits 24,576 40,960
Maximu m us er I/O pin s 220 254
2Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Note to ta bles:
(1) The embedded IEEE S td. 1149.1 JTAG circuitry adds up to 31,250 gates in addition to the listed typical or maximum
system gates.
(2) New E PF10K 100B designs sh ould use EPF10K 100E devices.
...and More
Features
Fa bric a ted on an advanced pr ocess an d ope r ate with a 2.5-V
inte rnal supp ly voltage
In-circuit reconfigurability (ICR) via external configuration
devices, intelligent controller, or JTAG port
ClockLockTM a nd ClockBoostTM options for reduced clock
delay/skew and clock multiplication
Built-in low-skew clock distribution trees
–100% functiona l te st ing of a ll device s; test vectors or scan cha ins
are not required
Pull-up on I/O pins before and during configura tion
F lexible interconnect
–FastTrack
® Interconnect continuous routing structure for fast,
predictable interconnect delays
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
softw are tools and megafunctions)
Dedicated cascade chain that implements high-speed,
high-fan-in logic functi ons (automat ically used by software tools
and megafunctions)
Tri-state emulation that implements internal tri-state buses
Up to six global clock signals and four global clear signals
Powerful I/O pins
Individual tri-state output enable control for each pin
Open-drain option on each I/O pin
Programmable output slew-rate control to reduce switching
noise
–Clamp to V
CCIO user-sel ectabl e on a pin-by -pin basis
Supports hot-socketing
Tabl e 2. FLEX 10 KE Dev ic e Fea t ures
Feature EPF10K100E (2) EPF10K130E EPF10K200E
EPF10K200S
Typic al gat es (1) 100,000 130,000 200,000
Maxim um sys te m ga tes 257, 000 342,000 513 ,00 0
Logic elements (LEs) 4,992 6,656 9,984
EABs 12 16 24
Total R AM bits 49,1 52 65,53 6 98,304
Maxim um us er I/O pins 338 413 470
Altera Corporation 3
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Soft ware des ign sup port and automat ic place- and-rou te provi ded by
Altera’s development systems for Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800
Flexible package options
Ava ilable in a var iety of packag es with 144 to 6 72 pins, inclu ding
the innovative FineLine BGATM packa ge s ( see Tables 3 and 4)
–SameFrame
TM pin-out compatibility between FLEX 10KA and
FLEX 10KE devices across a range of device densiti es an d pin
counts
Additi ona l design entry and simula tion support pr ovide d by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Design War e compone nts , Verilog HDL, VHDL, a nd othe r interfa ce s
to popular EDA tools from manufacturers such as Cadence,
Exemplar Logic, Men tor Graphics, OrCAD, Synopsys, Synplici ty,
VeriBes t, an d V i ew logic
Notes:
(1) FLEX 10KE device package types include thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat
pack (R QF P), pin-gri d array (PGA) , and bal l-g r id ar ray (BGA) pa cka ges.
(2) D ev i c es in the same pac k age are pin-comp at ib le, although so me devices h av e more I/O pins than ot h er s . Wh en
planning device migra tion, use the I/O pins that are common to all devices.
(3) Th is op t ion is supported with a 484-pin FineL i ne BG A package. B y us ing SameF rame pin migration, all
Fi ne Lin e BGA p ac ka ges a re pi n- com pat i bl e. Fo r e xam pl e, a b oar d ca n b e d es i gne d t o su pp or t 256 - pi n, 4 84- p in, an d
672-pin FineLine BGA packages. The Altera software automatically avoids conflicting pins when future migration
is set.
Table 3. FLEX 10KE Package O ptions & I/O Pin Count Notes (1), (2)
Device 144-Pin
TQFP 208-Pin
PQFP 240-Pin
PQFP
RQFP
256-Pin
FineLine
BGA
356-Pin
BGA 484-Pin
FineLine
BGA
599-Pin
PGA 600-Pin
BGA 672-Pin
FineLine
BGA
EPF10K30E 102 147 176 220 220 (3)
EPF10K50E 102 147 189 191 254 254 (3)
EPF10K50S 102 147 189 191 220 254 254 (3)
EPF10K100E 147 189 191 274 338 338 (3)
EPF10K130E 186 274 369 424 413
EPF10K200E 470 470 470
EPF10K200S 182 274 369 470 470 470
4Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
General
Description
Altera FLEX 10 KE devices are enhanced versions of FLEX 10K devices.
Based on reconfigurable CMOS SRAM elements, the FLEX architectur e
incorporates all features necessary to implement common gate array
megafunctions. With up to 200,000 typical gates, FLEX 10KE devices
provide the density, speed, and features to integrate entire systems,
including multiple 32-bit buses, into a single device.
The ability to reconfigure FLEX 10KE devices enables 100% testing prior
to shipment and allows the designer to focus on simulation and design
verification. FLEX 10KE reconfigurability eliminates inventory
manag ement for gate arr ay designs a nd gener ation of te st vector s for fault
coverage.
Table 5 shows FLEX 10KE performance for some common designs. All
performance values were obtained with Synopsys DesignWare or LPM
functions. Special design techniques are not requir ed to implement the
applications; the designer simply infers or instantiates a function in a
Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or
schematic design file.
Table 4. FLEX 10KE Package Sizes
Device 144-
Pin
TQFP
208-Pin
PQFP 240-Pin
PQFP
RQFP
256-Pin
FineLine
BGA
356-
Pin
BGA
484-Pin
FineLine
BGA
599-Pin
PGA 600-
Pin
BGA
672-Pin
FineLine
BGA
Pitch (mm) 0.50 0.50 0.50 1.0 1.27 1.0 1.27 1.0
Area (mm2) 484 936 1,197 289 1,225 529 3,904 2,025 729
Length × wi dth
(mm × mm) 22 × 22 30.6 × 30.6 34.6 × 34.6 17 × 17 35 × 35 23 × 23 62.5 × 62.5 45 × 45 27 × 27
Altera Corporation 5
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Notes:
(1 ) Th is application uses combinat o r ial inputs and outputs.
(2) This application uses registered inputs and outputs.
Table 6 shows F L EX 1 0KE pe r for m anc e for mo re com pl ex designs. T he se
designs are available as Altera MegaCore® functions.
Note:
(1) These values are for calculation time. Calculation time = number of clocks required/fmax. Number of clocks
requir ed = ceilin g [lo g 2 (poin t s)/ 2] × [points +14 + ceiling]
Table 5. FLEX 10KE Performance
Applic ation Resourc es Used Perfo rmance Unit s
LEs EABs -1 Speed Grade -2 Speed Grade -3 Speed Grade
16-bit loadable counter 16 0 285 250 200 MHz
16-bit accumulator 16 0 285 250 200 MHz
16-to- 1 mu ltip lex er (1) 10 0 3.5 4.9 7.0 ns
16-bit multiplier with 3-stage
pipeline (2) 592 0 156 131 93 MHz
256 × 16 RAM read cycle
speed (2) 0 1 196 154 118 MHz
256 × 16 RAM wr ite cycle
speed (2) 0 1 185 143 106 MHz
Table 6. FLEX 10KE Performance for Complex Designs
Application LEs Used Performance Units
-1 Speed Grade -2 Speed Grade -3 Speed Grade
8-bit, 16-tap parallel finite impulse
resp onse (F IR) fi l te r 597 192 156 116 MSPS
8-bit, 512-point fast Fou rier
tran sfo r m (F FT) fu nc ti o n 1,854 23.4 28.7 38.9 µs (1)
113 92 68 MHz
a16450 universal async hronous
receiver/transmitter (UART) 342 36 28 20.5 MHz
6Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Similar to the FLEX 10KE architecture, embedded gate arrays are the
fastest- g row ing segment of th e g ate array mar k et . As with stand ard gat e
arrays, embedded gate arrays implement general logic in a conventional
“sea-of-gates” architecture. Additionally, embedded gate arrays have
dedicated die areas for implementing large, specialized functions. By
embedding functions in silicon, embedded gate arrays reduce die area
and increase speed when compare d to standard gate arrays. While
embedded megafunctions typically cannot be customized, FLEX 10KE
devices are programmable, providing the designer with full control over
embedded megafunctions a nd general logic, while facilitating iterative
desig n c hanges during debuggi ng.
Each FLEX 10KE device contains an embedded array and a logi c ar ray.
The em be dded array i s used to impl ement a var iety of memor y fu nctio ns
or complex logic functions, such as digital signal processing (DSP), wide
data-path manipulation, microcontroller applications, and data-
transformation functions. The logic array performs the same function as
the sea-of-gates in the gate array and is us ed to implemen t general logi c
such as counters, adders, state machine s, and multiplexers. The
combination of embedded and logic arrays provides the high
performan ce and hi gh densit y of emb edded gate arrays, enablin g
desi gn ers to implem e nt an ent i re sys te m on a single devic e.
FLEX 10KE devices are configured at system power-up with data stored
in an Altera serial configuration device or provided by a system
controller. Altera offers the EPC1, EPC2, and EPC16 configuration
devi ce s, whi ch configur e FLEX 10KE devices via a serial data stream.
Configurat ion d ata ca n a lso b e dow nloa ded fr om syste m RAM or via th e
Altera B it Bla st er TM, ByteB lasterMVTM, or MasterBlas te r dow nloa d cabl e s.
After a FLEX 10KE device has been configured, it can be reconfigured
in-circuit by resetting the device and loading new data. Because
reconfiguration requires less than 85 ms, real-time changes can be made
during system operation.
FLEX 10KE devices contain an interface that permits microprocessors to
configure FLEX 10KE d evices se ri ally or in-parallel, a nd synchrono usly or
asynchronously. The interface also enables microprocessors to treat a
FLEX 10KE device as memory and configure it by writing to a virtual
memory location, making it easy to reconfigure the device.
Altera Corporation 7
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
fFor more information on FLEX device configuration, see the following
documents:
Configuration Devices for APEX & FLEX Devices Data Sheet
BitBlaster Serial Download Cable Data Sheet
ByteBlasterMV Parallel Port Download Cable Data Sheet
MasterBlaster Download Cable Data Sheet
Appl i cat i on Note 116 (Con f ig u r ing APEX 20K, F L EX 10K, & FL E X 60 00
Devices)
FLEX 10KE devices are supported by the Altera development systems,
which are integrated packages that offer sche matic, text (including
AHD L), and wavefo rm design entr y, compil ation and lo gi c synthesi s, full
simula tion and w orst-case timi ng ana lysis, and d evice con figuration . The
Alte ra software prov ides ED IF 2 0 0 and 3 0 0, LPM , VHDL, Ve rilog HDL,
and other interfaces for additional design entry and simulation support
from other indu stry-standard PC- and U NIX w o rkstation-base d EDA
tools.
The Altera software works easily with common gate array EDA tools for
synthesis and simulation. For example, the Altera software can generate
Verilog HDL files for simulation with tools such as Cadence Verilog-XL.
Additionally, the Altera software contains EDA libraries that use device-
specific features such as carry chains, which are used for fast counter and
arithme tic funct ions . Fo r insta nce , the Synop sy s Desig n Compiler libr ary
supplied with the Altera development system includes DesignWare
fu nct ions tha t are o ptimized fo r the FLEX 10K E ar chit ec tur e .
The Altera development system runs on Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800.
fSee the MAX+PLUS II Programmable Logic Development System & Software
Data Sheet and the Quartus Programmable Logic Development System &
Software Data Sheet for more information.
8Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Functional
Description
Each FLEX 10KE device contains an enhanced embedded array to
implement memory and specialized logic functions, and a logic array to
implement general logic.
The embedded array consists of a series of EABs. When implementing
memory functions, each EAB provides 4,096 bits, which can be used to
create RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions.
When implementing logic, each EAB can contribute 100 to 600 gates
towards complex logic functions, such as mult ipliers, microcontrollers,
state machines, and DSP functions. EABs can be used independently, or
multiple EABs can be combined to implement larger functions.
The logic array consists of logic array blocks (LABs). Each LAB contains
eight LEs and a local int erconnec t. An LE consists of a four-input look-up
table (LUT), a programmable flipflop, and dedicated signal paths for carry
and cascade functions. The eight LEs can be used to create medium-sized
blocks of logic—such as 8-bit counters, address decoders, or state
machines—or combined across LABs to create larger logic blocks. Each
LAB represents about 96 usable gates of logic.
Signal inte rconnect ions within FLEX 10KE devices (as well as to and from
device pin s) ar e provided by the Fas tT rac k Intercon nect routin g structur e,
which is a serie s of fast, continuous r ow and column ch annels that run th e
entire length and width of the dev ice.
Each I/O pin is fed by an I/O element (IOE) located at the end of each row
and column of the FastTrack Interconnect routing structure. Each IOE
contains a bidirectional I/O buffer and a flipflop that can be used as either
an output or input register to feed input, output, or bidirectional signals.
When used with a dedicated clock pin, these registers provide exceptional
performance. As inputs, they provide setup times as low as 0.9 ns and
hold times of 0 ns. As outputs, these registers provide clock-to-output
times as low as 3.0 ns. IOEs provide a variety of features, such as JTAG
BST support, sle w-rat e cont ro l, tri-s tate buf fers, and open-drain outp uts .
Altera Corporation 9
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Figure 1 shows a block diagram of the FLEX 10KE architecture. Each
group of LE s is combine d i nto an L AB; grou ps of L ABs a re arra ng ed int o
rows and column s. Each row also co ntains a single EAB . The LABs and
EABs ar e in ter c onnected by the FastTr ac k In te rconne ct routing st ru cture.
IOEs are located at the end of each row and column of the FastTrack
Interconnect routing structure.
Figure 1. FLEX 10KE Device Bl ock Di agram
FLEX 10KE devices provide six dedicated inputs that drive the flipflops
control inputs and ensure the efficient dist ribution of high-speed, low-
skew (less than 1.5 ns) control signals. These signals use dedicated routing
chan ne ls t hat provide s hor te r d ela ys an d lowe r sk ew s tha n t he Fa stTr ac k
Interconnect routing structure. Four of the dedicated inputs drive four
global signals. These four global sig nals can also be driven by internal
logic, providing an ideal solution for a clock divider or an internally
generat ed asynchro nous clear signal that clears many register s in the
device.
I/O Element
(IOE)
Logic Array
Block (LAB)
Row
Interconnect
IOEIOE
IOEIOE
IOE
IOE
IOE
Local Interconnec
t
IOEIOE
IOEIOE IOEIOE
IOEIOE
IOEIOE
Logic Element (LE
)
Column
Interconnect
IOE
EAB
EAB
Logic
Array
IOEIOE
IOEIOE IOEIOE
Embedded Array Block (EAB)
Embedded Array
IOE
IOE
Logic Array
IOE
IOE
10 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Embed ded A rray Bloc k
The EAB is a flexible block of RAM, wit h registers on the inpu t and output
ports, that is used to implement common gate array megafunctions.
Because it is large and flexible, the EAB is suitable for functions such as
multipliers, vector scalars, and error correction circuits. These functions
can be combined in applications such as digital filters and
microcontrollers.
Logic functions are implemented by programming the EAB with a read-
only patte rn during configuration, thereby creating a large LUT. With
LUTs, combinatorial functions are implemented by looking up the results,
rather than by computing them. This implementation of combinatorial
functions can be faster than using algorithms implemented in general
logic, a performan ce advanta ge that is furt her enhanc ed by the fast a ccess
times of EABs. The large capacity of EABs enables designers to implement
complex fun ctions in on e logic leve l without t he routin g delays as sociated
with linked LEs or field-programmable gate array (FPGA) RAM blocks.
For exam ple, a single EA B can imple ment any function with 8 inp uts an d
16 outputs. Parameterized functions such as LPM functions can take
advantage of the EAB automatically.
The FLEX 10KE EAB provides adva ntages over FPGAs, which implement
on-board RAM as arrays of small, distributed RAM blocks. These small
FPGA RAM blocks must be connected together to make RAM blocks of
manageable size. The RA M blocks ar e conne cted together us ing
multiplexers implemented with more logic blocks. These extra
multiple xers cause extra del ay, which slo ws down the RAM block . FPGA
RAM blocks are also prone to routing problems because small blocks of
RAM m ust be connec ted tog ether to m ake larger bl ocks. In co ntrast, E ABs
can be used to implement large, dedicated blocks of RAM that eliminate
th ese timing and routing con cerns.
The FLEX 10KE e nhanced EAB adds dual-p o rt capability to the existing
EAB structure. The dual-port structure is ideal for FIFO buffers with one
or two clocks. The FLEX 10KE EAB can also support up to 16-bit-wide
RAM blocks and is backward-compatible with any design containing
FLEX 10K EABs. The FLEX 10KE EAB can act in dual-port or single-port
mode. When in dual-port mode, separate clocks may be used for EAB read
and write sections, which allows the EAB to be written and read at
differ e nt rate s. It also has sep ar a te sy nch ro nous cloc k ena b le sig nals for
the EAB read and write sections, which allow independent control of
these s ections.
Altera Corporation 11
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
The EAB can also be used for bidirectional, dual-port memory
applications where two ports read or write simultaneously. To implement
this type of dual-port memory, two EABs are used to support two
simulta neous r ead or writes.
Alte rnat ivel y, one clock and clock en able ca n b e use d to con tr ol t he inp ut
registers of the EAB, while a different clock and clock enable cont rol the
out put r e gister s (see Figure 2).
Figure 2. FLEX 10KE Device in Dual-Port RAM Mode Notes (1)
Notes:
(1) All registers can be asynchronously cleared by EAB local interconnect signals, global signals, or the chip-wide reset.
(2) EP F10K30E and E PF10K50E dev i c es ha ve 88 EA B local intercon ne ct chan n el s; EP F1 0K 100E, EPF10 K 130E, and
EPF10K200E devices have 104 EAB local interconnect channels.
Column Interconnect
E
AB Local
I
nterconnect (2)
Dedicated Clocks
24
D
ENA Q
D
ENA
Q
D
ENA Q
D
ENA Q
D
ENA
Q
data[ ]
rdaddress[ ]
wraddress[ ]
RAM/ROM
256 × 16
512 × 8
1,024 × 4
2,048 × 2
Data In
Read Address
Write Address
Read Enable
Write Enable
Data Out
4, 8, 16, 32
4, 8, 16, 32
outclocken
inclocken
inclock
outclock
D
ENA Q
Write
Pulse
Generator
rden
wren
Multiplexers allow read
address and read
enable registers to be
clocked by inclock or
outclock signals.
Row Interconnect
4, 8
Dedicated Inputs &
Global Signals
12 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
The EAB can also use Altera megafunctions to implement dual-port RAM
applications where both ports can read or write, as shown in Figure 3.
Figure 3. FLEX 10KE EAB in Dual-Port RAM Mode
The FLEX 10KE EAB can be used in a single-port mode, which is useful for
backward-compatibility with FLEX 10K designs (see Figure 4).
Port A Port B
address_a[] address_b[]
data_a[] data_b[]
we_a we_b
clkena_a clkena_b
Clock A Clock B
Altera Corporation 13
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Figure 4. FLEX 10KE Device in Single-Port RAM Mode
Note:
(1) EPF10K30E, EPF10K50E, and EPF10K50S devices have 88 EAB local interconnect channels; EPF10K100E,
EPF1 0K 130E, EPF1 0K 200E, and EPF10K200S dev ices h ave 104 EAB local interconnect chann els.
EABs can be us ed to imple ment sy nchronous RAM, wh ich is easie r to u se
than asynchronous RAM. A circuit using asynchronous RAM must
generate the RAM write enable signal, while ensuring that its data and
address signals meet setup and hold time specifications relative to the
write enable s ignal. I n contr ast, t he EAB’ s synchron ous RAM g enerates its
own write enable signal and is self-timed with respect to the input or write
clock . A circuit using the EAB’ s self-tim ed RAM must onl y meet the setup
and hold time specifications of the global clock.
Column Interconnect
EAB Local
Interconnect (1)
Dedicated Inputs
& Global Signals
DQ
DQ
RAM/ROM
256 × 16
512 × 8
1,024 × 4
2,048 × 2
Data In
Address
Write Enable
Data Out
4, 8, 16, 32
4, 8, 16, 32
DQ
DQ
4
8, 4, 2, 1
8, 9, 10, 11
Row Interconnect
Dedicated
Clocks
2
4, 8
Chip-Wide
Reset
14 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
When used as RAM, each EAB can be configured in any of the following
si zes: 256 ×16, 512 ×8, 1,024 ×4, or 2,048 ×2 (see Figure 5).
Fig ure 5. F LE X 10 KE EAB Memory Con figuratio ns
Larger blocks of RAM are created by combining multiple EABs. For
example, two 256 × 16 RAM blocks can be combined to form a 256 ×32
block; two 512 ×8 RAM blocks can be combi ned to for m a 512 ×16 block
(see Figure 6).
Figure 6. Examples of Combining FLEX 10KE EABs
If necessary, all EABs in a device can be cascaded to form a single RAM
block. EABs can be cascaded to form RAM blocks of up to 2,048 words
without impacting timin g. Th e Alte r a softw are aut om ati cally combines
EABs to me et a designer’s RAM specificati o ns.
256 × 16 512 × 8 1,024 × 4 2,048 × 2
512 × 8
512 × 8
256 × 16
256 × 16
256
×
32
512 × 16
Altera Corporation 15
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
EABs provide flexible options for driving and controlling clock signals.
Different clocks an d clock enables can be used for r ead ing and writing to
the EAB. Registers can be independently inserted on the data input, EAB
output, write address, write enable signals, read address, and read enable
sign als. The glo bal signal s and the EAB loc al intercon nect ca n drive write
enable, read enable, and clock enable signals. The global signals,
dedicated clock pins, and EAB local interconnect can drive the EAB clock
signals. Because the LEs driv e t he EAB local interconn ec t, the LEs can
control write enable, read enable, clear, clock, and clock enable signals.
An EAB is fed by a row in terconnect and can drive out to row and colu mn
inte rconnect s. Ea ch EAB ou tput ca n drive u p to two row channe ls and up
to two column channels; the unused row channe l can be driven by other
LEs. This feature increases the routing resources available for EAB
outpu ts (see Figures 2 and 4). T he c olumn int erc onne ct, which is adjac en t
to the EAB, has twice as many channels a s other columns in the device.
Logic Array Bloc k
An LAB consists of eight LEs, their associated ca rry and cascade chains,
LAB contr ol s i gnals, and the LA B l ocal interconnect. The LA B provides
the coarse-grained structure to the FLEX 10KE architecture, facilitating
efficient routing with optimum device utilization and high performance
(see Figure 7).
16 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Figure 7. FLEX 10KE LAB
Notes:
(1) EPF 10K30E, EPF 10K 50E, and EPF 10K50S devices have 22 i np u ts to th e LA B local interconn ect channel from the
row; EPF10K100E, EPF10K130E, EPF10K200E, and EPF10K200S devices have 26.
(2) EPF 10K30E, EPF 10K 50E, and EPF 10K50S devices have 30 LAB local intercon n ec t chan n els; EPF10K 100E,
EPF10 K1 30E, E PF10K200E, an d EPF 10K 200S devic es ha ve 34.
2
8
Carry-In
Cascade-In
LE1
LE8
LE2
LE3
LE4
LE5
LE6
LE7
Column
Inter
connect
ter
connect
ter
Row Inter
connect
ter
connect
ter
(1
)
LAB Local
Inter
connect (2
ter
connect (2
ter
)
(2
)
(2
Column-to-Row
Inter
connect
ter
connect
ter
Carry-Out
Cascade-Out
16
24 to 48
to
to
LAB Contro
l
Signal
s
nal
s
nal
See Figure 12
for details
.
6
Dedicated Inputs
Global Signal
s
16
6
8
4
4
4
4
4
4
4
4
4
4
2
8
Altera Corporation 17
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Each LAB provides four control signals with programmable inversion
that can be used in all eight LEs. Two of these signals can be used as clocks,
the oth er t wo ca n b e use d for c lea r /pre set control. The L AB clocks can b e
driven by the dedicated clock input pins, global signals, I/O signals, or
internal signals via the LAB local interconnect. The LAB preset and clear
control signals can be driven by the global signals, I/O signals, or internal
signals via the LAB local interconnect. The global control signals are
typi ca lly used for global clock, clear , or preset signa ls because they
provide asynchronous control with very low skew across the device. If
logic is require d on a contr ol sig nal, it can b e genera ted in one or more LE
in any LAB and driven into the local inte rconnect of the target LAB. In
addition, the global control signals can be generated from LE outputs.
Logic Element
The LE, the smallest unit of logic in the FLEX 10KE architecture, has a
compact size that provides efficient logic utilization. Each LE contains a
four-input LUT, which is a function generator that can quickly compute
any function of four variables. In addition, each LE contains a
programmable flipflop with a synchronous clock enable, a carry chain,
and a cascade chain . Each LE dr ives b oth th e loc al and the FastTrack
Interconnect routing structure (see Figure 8).
Figure 8. FLEX 10KE Logic Element
LAB Local
Interconnect
Carry-In
Clock
Select
Carry-Out
Look-Up
Table
(LUT)
Clear/
Preset
Logic
Carry
Chain Cascade
Chain
Cascade-In
Cascade-Out
FastTrack
Interconnect
Programmable
Register
PRN
CLRN
DQ
ENA
Register Bypass
data1
data2
data3
data4
labctrl1
labctrl2
labctrl4
labctrl3
Chip-Wide
Reset
18 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
The programmabl e flipflop in the LE can be config ured for D, T, JK, or SR
operation. The clock, clear, and preset control signals on the flipflop can
be driven by global signals, general-purpose I/O pins, or any internal
logic. For combina toria l funct ions, the flipflop is bypa ssed and the output
of the LUT drives the output of the LE.
The LE has two outputs that drive the interconnect: one drives the local
interconnect and the other drives either the row or column FastTrack
Interconnect routing structure. The two outputs can be controlled
independently. For example, the LUT can drive one output while the
regist er driv es th e oth er outp ut. T his fe atu re, ca lled r egister pac ki ng, can
improve LE utilization because the register and the LUT can be used for
unrelated functions.
The FLEX 10KE arc hitecture provides two ty pe s of ded ica te d h igh -spe ed
data paths that connect adjacent LEs without using local interconnect
paths: carry chains and ca scade chains. The carry chain supports
hi gh-speed counters and ad d e rs and the cascade chain implements
wide-inp ut fu nct ions wit h min i mum del ay . Carry and cascade chains
connect all LEs in a LAB as well as all LABs in the same row. Inte nsive use
of carry and cascade chains can reduce routing flexibility. Therefore, the
use of these chains should be limit ed to speed- critica l portion s o f a des ign.
Carry Chain
The carry chain provides a very fast (as low as 0.2 ns) carry-forward
function be tween LEs. The ca rry-i n signal from a lower - or der bit drives
forward into the higher-order bit via the carry chain, and feeds into both
the LUT and the next portion of the carry chain. This fe ature allows the
FLEX 10KE architecture to implement high-speed counters, adders, and
comparators of arbitrary width efficiently. Carry chain logic can be
creat e d aut omatic ally b y th e Altera Compiler d uri ng design processing,
or manually by the designer during design entry. Parameterized functions
such as LPM and Design Ware function s aut omat ica lly take advan ta ge of
carry chains.
Carry chains longer than eight LEs are automatically implemented by
linking LABs together. For enhanced fitting, a long carry chain skips
al ternate LABs in a r ow. A carry chain longer than one LA B skips either
from even-numbered LAB to even-numbered LAB, or from odd-
nu mbered LAB to odd-number ed LAB. For example, the last LE of the
first LAB in a row carries to the first LE of the third LAB in the row. The
carry c hain does no t c ro ss the EAB at the mi dd le of the r ow. For instance,
in the E PF10 K50E de vice, th e car ry chain stop s at the eight eenth LAB and
a new one beg ins at the nin e tee nth LAB.
Altera Corporation 19
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Figure 9 shows how an n- bit full adde r can be impleme nte d in n+1 LEs
with the car ry chain. One port ion of th e LUT gene rates the sum of t wo bits
using the input signals and the carry-in signal; the sum is routed to the
output of the LE. The register can be bypassed for simple adders or used
for an accumulator function. Another portion of the LUT and th e carry
chain logic generates th e carry-out signal, which is routed directly to the
carry-in signal of the next-higher-order bit. The final carry-out signal is
routed to an LE, where it can be used as a general-purpose signal.
Figure 9. FLEX 10KE Carry Chain Ope rati on (n-Bit Full Adder)
LUT
a1
b1
Carry Chain
s1
LE1
Register
a2
b2
Carry Chain
s2
LE2
Register
Carry Chain
sn
LEn
Register
an
bn
Carry Chain
Carry-Out
LEn + 1
Register
Carry-In
LUT
LUT
LUT
20 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Cascade Chain
With the cascade chain, the FLEX 10KE architecture can implement
functions that have a very wide fan-in. Adjacent LUTs can be used to
compute portions of the function in parallel; the cascade chain serially
connec ts the i ntermediat e value s. The ca scade ch ain can use a logica l AND
or logical OR (via De Morgan’s inversion) to connect the outputs of
adjace nt LEs. An a delay as low as 0.6 ns per LE, each additional LE
provides four more inputs to the effective width of a function. Cascade
chain logic can be created automatically by the Altera Compiler during
design processing, or manually by the designer during design entry.
Cascade chains longer than eight bits are implemented automatically by
linking se veral LABs together. For easier routing, a long cascade chain
skips every other LAB in a row. A cascade chain longer than one LAB
skips ei ther from even-numbere d LAB to even-n umbered LAB, or fro m
odd-numbe red LAB to odd-numbered LA B (e.g., the last LE of the first
LAB in a row cascades to the first LE of the third LAB). The cascade chain
does not cross the center of the row (e.g., in the EPF10K50E device, the
cascade chain stops at the eighteenth LAB and a new one begins at the
ninet eenth LAB). This break is du e to the EAB’s placement in the middl e
of the row.
Figure 10 shows how the cascade function can connect adjacent LEs to
form functions with a wide fan-in. These examples show functions of
4n variables implemented with n LEs. The LE del ay is 0.9 ns ; th e c as cade
chain delay is 0.6 ns. Wi th the cascade chain, 2. 7 ns are needed to dec ode
a 16-bit address.
Figure 10. FLEX 10KE Cascade Chain Operation
LE1
LUT
LE2
LUT
d[3..0]
d[7..4]
d[(4n – 1)..(4n – 4)]
d[3..0]
d[7..4]
LEn
LE1
LE2
LEn
LUT
LUT
LUT
LUT
AND Cascade Chain OR Cascade Chain
d[(4n – 1)..(4n – 4)]
Altera Corporation 21
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
LE Operat ing M ode s
The FLEX 10KE LE can operate in the follow ing four modes:
Normal mode
Arithmet ic mode
Up/down counter mo de
Clea r able cou nter mo d e
Each of these modes u ses LE resources differently . In ea ch mode, seven
available inputs to the LE—the four data inputs from the LAB local
interconnect, the feedback from the programmable register, and the
carry-in and casc ade- i n from t he previous LE—are directed to different
destinations to implement the desired logic function. Three inputs to the
LE provide clock, clear, and preset control for the register. The Altera
software, in conjunction with parameterized functions such as LPM and
DesignWare functions, automatically chooses the appropriate mode for
common functions such as counters, adders, and multipliers. If required,
the designer can also create special-purpose functions that use a specific
LE operating mode for optimal performance.
The a rchitect ure provid es a sy nchro nous cloc k enable t o the register in all
four modes. The Altera software can set DATA1 to enable the register
synchronously, providing easy implementation of fully synchronous
designs.
22 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Figure 11 shows the LE operating modes.
Figure 11. FLEX 10KE LE Operating Modes
ENA
PRN
CLRN
DQ
4-Input
LUT
Carry-In
Cascade-Out
Cascade-In
LE-Out to F astTrack
Interconnect
LE-Out to Local
Interconnect
ENA
Normal Mode
PRN
CLRN
DQ
Cascade-Out
LE-Out
Cascade-In
3-Input
LUT
Carry-In
3-Input
LUT
Carry-Out
Arithmetic Mode
Up/Down Counter Mode
PRN
CLRN
DQ
3-Input
LUT
Carry-In Cascade-In
LE-Out
3-Input
LUT
Carry-Out
1
0
Cascade-Out
Clearable Counter Mode
PRN
CLRN
DQ
3-Input
LUT
Carry-In
LE-Out
3-Input
LUT
Carry-Out
1
0
Cascade-Out
ENA
ENA
data1
data4
data3
data2
data1
data2
data1 (ena)
data2 (u/d)
data4 (nload)
data3 (data)
data1 (ena)
data2 (nclr)
data4 (nload)
data3 (data)
Altera Corporation 23
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Normal Mode
The normal mode is suitable for general logic applica tions and wide
de cod ing f un ctions that can take adv a nt ag e of a cas ca de chain. In normal
mode, four data inputs from the LAB local interconnect and th e carry-in
are inpu ts to a fou r-input LUT . The A lte ra Com piler aut omati cally select s
the ca rry-in or the DATA3 signal as one of the inputs to the LUT. The LUT
output can be combined with the cascade-in signal to form a cascade chain
thr ough th e casc ade -out sign al. Either the reg ister or th e LUT ca n be used
to drive both the local interconnect and the FastTrack Interconnect routing
str uct ur e at the same time .
The LUT and the regist er in the LE can be used indep endently (regi ster
packin g). To suppor t regi ster pa cking , the LE h as tw o outputs ; one dr ives
the local interconnect, and the other drives the FastTrack Interconnect
routing st ructure. The DATA4 si gnal can drive the reg ister dir ectly,
allowing the LUT to compute a function that is independent of the
regis tered s ignal; a thre e-input function can be compute d in the LUT, and
a fourth independent signal can be registered. Alternatively, a four-input
function can be generated, and one of the in puts to this function can be
used to drive the register. The register in a packed LE can still use the clock
enable, clear, and preset signals in the LE. In a packed LE, the register can
drive the FastTrack Interconnect routing structure while the LUT drives
the local interconnect, or vice versa.
Arithmetic Mode
The arithmetic mode offers 2 three-input L UTs th at are ideal for
implementing adders, accumulators, and comparators. One LUT
computes a three-input function; the other generates a carr y output. As
shown in Figure 11 on page 22, the first LUT uses the car r y-in si gnal and
two data inputs from the LAB local interconnect to generate a
combi nator ial o r regi ste r ed out put. For e xample , in a n a dde r, th is output
is the sum of three signals: a, b, and carry-in. The second LUT uses the
same thr e e signals to ge ne rate a carry-out signal, th er eb y cre ating a carr y
chai n. The ar ithmetic m ode al so support s simultane ous use of the casc ade
chain.
Up/Down Counter Mode
The up/down counter mode offers counter enable, clock enable,
synchronous up/down control, and data loading options. These control
sign als ar e g e ner a te d by the da ta inpu ts f rom th e L AB loca l int er co nne ct,
the carry-in signal, and output feedback from the programmable register.
Use 2 three-input LUTs: one generates the counter data, and the other
generates the fast carry bit. A 2-to-1 multiplexer provides synchronous
loading. Data can also be loaded asynchronously with the clear and preset
regist er co ntrol signals wi thout using t he LU T reso urc e s.
24 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Cleara ble Counter Mode
The clearable counter mode is similar to the up/down counter mode, but
supports a synchronous clear instead of the up/down control. The clear
function is substituted for the cascade-in signal in the up/down counter
mode. Use 2 three-input LUTs: one generates the counter data, and the
other generates the fast carry bit. Synchronous loading is provided by a
2-to-1 multiplexer. The output of this multiplexer is AND ed with a
synchronou s clear signal.
Internal Tri-State Emulation
Inter nal tri- st at e emulation provide s intern al tr i-st ate s with out the
limitations of a physical tri-state bus. In a physica l tri-state bus, the
tri-st at e bu f fer s’ output enable (OE) signals se lec t whic h sig nal drive s the
bus. Howeve r, if multiple OE sig nals a re ac tive, c ontendi ng si gnals c an be
driven onto the bus. Conversely, if no OE signals are act i ve , the bus will
float. Int ernal tri-st ate em ulation resolve s conte nding tri-s tate buffe rs to a
low value and floating buses to a high value, thereby eliminating these
problems. The Altera software automatically implements tri-state bus
functionality with a multiplexer.
Clear & Preset Logic Control
Logic for the programmable register’s clear and preset functions is
controlled by the DATA3, LABCTRL1, and LABCTRL2 inputs to the LE. The
clear and pres et control str uc ture of the LE asynch r onous ly loads signals
into a register. Either LABCTRL1 or LABCTRL2 can control the
asynchronous clear. Alternatively, the registe r can be set up so that
LABCTRL1 implements an asynchronous load. The data to be loaded is
driven t o DATA3; w hen LABCTRL1 is asserte d , DATA3 is loaded into the
register.
During compil ati on, the Altera Compile r automat ica lly se lects the best
control s i gnal imple m entat ion. Because the c lea r an d pre set fun cti ons are
active-low, the Compiler automatically assigns a logic high to an unused
clear or preset.
The clear and preset logic is implemented in one of the following six
modes ch osen during design entry:
Asynchronous clear
Asynchronous preset
As ynchronou s clear and p r eset
Asynchronous load with cle ar
Asynchronous load with preset
Asynchronous load without clear or preset
Altera Corporation 25
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
In ad dition t o the six cle ar an d prese t mode s, FLEX 10KE device s provide
a chip-wide reset pin that can reset all registers in the device. Use of this
feature is set during design entry. In any of the clear and preset modes, the
chip-w ide reset overrides all other si gna ls. R e gisters with asynchronous
presets may be preset when the chip-wide reset is asserted. Inversion can
be used to implement the asynchronous preset. Figure 12 shows examples
of how to setup the p reset and c lear inputs fo r the de sire d func tionality.
Figure 12. FL EX 10K E LE Clear & Preset Mo des
Asynchronous Clear Asynchronous Preset Asynchronous Preset & Clear
Asynchronous Load without Clear or Preset
labctrl1
(Asynchronous
Load) PRN
CLRN
DQ
NOT
NOT
labctrl1
(Asynchronous
Load)
Asynchronous Load with Clear
labctrl2
(Clear)
PRN
CLRN
DQ
NOT
NOT
(Asynchronous
Load)
Asynchronous Load with Preset
NOT
NOT
PRN
CLRN
DQ
labctrl1 or
labctrl2
PRN
CLRN
DQ
VCC
Chip-Wide Reset
Chip-Wide Reset
Chip-Wide Reset
Chip-Wide Reset
PRN
CLRN
DQ
PRN
CLRN
DQ
VCC
Chip-Wide Reset
Chip-Wide Reset
data3
(Data)
labctrl1
labctrl2
(Preset)
data3
(Data)
data3
(Data)
labctrl1 or
labctrl2
labctrl1
labctrl2
26 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Asynchronous Clear
The flipflop can be cleared by either LABCTRL1 or LABCTRL2. In this
mod e, the preset signal is tied to VCC to de activate it.
Async hronous Pres et
An asynchronous preset is implemented as an asynchronous load, or with
an asynchronous clear. If DATA3 is tied to VCC, asserting LABCTRL1
asynchronously loads a one into the register. Alternatively, the Altera
software can provide preset control by using the clear and inverting the
input and output of the register. Inve rsion control is available for the
inputs to both LEs and IOEs. Therefore, if a register is preset by only one
of the two LABCTRL signa ls, the DATA3 input is not needed and can be
used for one of the LE operating modes.
Async hronous Pres et & Clear
When implementing asynchronous clear and preset , LABCTRL1 controls
the pr es et an d LABCTRL2 controls the clear. DATA3 is t ied to VCC, so that
asserting LABCTRL1 asynchronously loads a one into the register,
effectively presetting the register. Asserting LABCTRL2 clear s th e reg iste r.
Async hr onous Load with Clear
When implem enting an async hr onou s loa d in conjunction with t he clea r ,
LABCTRL1 implements the asynchronous load of DATA3 by controlling
th e regi ster pr eset and cl ear. LABCTRL2 imple ments the clear by
controlling the register clear; LABCTRL2 do es not hav e to fe ed the pres et
circuits.
Async hr onous Load with Preset
When implementing an asynchronous load in conjunction with preset, the
Altera software provides preset control by using the clear and inverting
the input and output of the regist er. Asserting LABCTRL2 presets the
register, while assertin g LABCTRL1 loads the register. The Altera software
inverts the signal that drives DATA3 to account for the inversion of the
register’s output.
Async hr onous Load without Pr es et or Clear
When implementing an asynchronous load without preset or clear,
LABCTRL1 implements the asynchronous load of DATA3 by controlling
th e regi ster pr eset and cl ear.
Altera Corporation 27
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
FastTrack Int er co nnec t Rout ing Structure
In the FLEX 10KE architecture, connections between LEs, EABs, and
device I/O pins are provided by the FastTrack Interconnect routing
structure, which is a series of continuous horizontal and vertical routing
chan ne ls t hat trav er se s t he devic e. This global routing st r uctu r e prov id es
pred icta ble perf orm ance, even in complex designs. In contrast, the
segmented routing in FPGAs requires switch matrices to connect a
variable number of routing paths, increasing the delays between logic
resour c es and re ducing perfor ma nce .
The F ast Tra ck I nte rconn ec t r outing structure cons ist s of ro w an d colum n
interconnect channe ls that span the entire device . Each row of LABs is
served by a de di ca te d ro w interconnect . The ro w interconnect ca n drive
I/O pi ns and feed ot her LA Bs in the row. The c olumn inte rconnect routes
signals be twee n row s and can dri ve I/O pin s.
Row channels drive into the LAB or EAB local interconnect. The row
signal is buffered at every LAB or EAB to reduce t he effect of fan-out on
delay. A row channel can be driven by an LE or by one of three column
chan ne ls. T he se fo ur sig nals feed dual 4- to-1 mu ltip lex e rs tha t con ne ct t o
two specific row channels. T hese multiplexers, which are connected to
each LE, allow column channels to drive row channels even when all eight
LEs in a LAB drive the row interconnec t.
Each column of LABs or EABs is served by a dedicated c o l umn
interconnect. The column interconnect that serves the EABs has twice as
many channels as other column interconnects. The column interconnect
can t hen drive I/O pins or anoth er row’s int erconnect t o route the signals
to other LABs or EABs in the device. A signal from the column
interconnect, which can be either the output of a LE or an input from an
I/O pin, must be routed to the row interconnect before it can enter a LAB
or EAB. Each row channel that is driven by an IOE or EAB can drive one
specific column channel.
Access to row and column channels can be switched between LEs in
adjacent pairs of LABs. For example, a LE in one LAB can drive the row
and column channels normally driven by a particular LE in the adjacent
LAB in the same row, and vice versa. This flexibility enables routing
resource s to be used more efficiently (see Figure 13).
28 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Figure 13. FLEX 10KE LAB Connections to Row & Column Interconnect
From Adjacent LAB
Row Channels
Column
Channels
Each LE can drive two
row channels.
LE 2
LE 8
LE 1 To Adjacent LAB
Each LE can switch
interconnect access
with an LE in the
adjacent LAB.
At each intersection,
six row channels can
drive column channels.
To Other Rows
To LAB Local
Interconnect
To Other
Columns
Altera Corporation 29
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
For improved routing, the row interconnect consists of a combination of
full-length and half-length channels. The full-length channels connect to
all LABs in a row; the half-length channels connect to the LABs in half of
the r ow. The EAB c an be driven by the h alf-length channels in th e left ha lf
of the row and b y th e fu ll-lengt h c hannel s. T he E AB d rive s out to the full-
length channels. In addition to providing a predictable, row-wide
inte r conn ect , t his architecture pro vid es inc reas ed r ou ting r e sourc es. T wo
neighboring LABs can be connected us ing a half-row channel, thereby
saving the other half of the channel for the other half of the row.
Table 7 summarizes the FastTrack Interconnect routing structure
resource s available in each FLEX 10KE device.
In addition t o gen eral-purpos e I/O pins, FLEX 10KE devices have six
ded icated in put pin s that pr ovide low -skew sig nal distr ibution across t he
device. These six inputs can be used for global clock, clear, preset, and
peripheral output enable and clock enable control signals. These signals
are available as control signals for all LABs and IOEs in the device. The
dedicated inputs can also be used as general-purpose data inputs because
they can feed the local interconnect of each LAB in the device.
Figure 14 sh o ws the interconnecti on of adja ce nt LABs and EABs, with
row, column, and local interconnects, as well as the associated ca scade
and carry chains. Each LAB is labeled according to its location: a letter
represents the row and a number represents the column. For example,
LAB B3 is in row B, column 3 .
Table 7. FLEX 10KE FastTrack Interconnect Resources
Device Rows C hannels per
Row Co lu mn s Cha nn el s pe r
Column
EPF10K30E 6 216 36 24
EPF10K50E
EPF10K50S 10 216 36 24
EPF10K100E 12 312 52 24
EPF10K130E 16 312 52 32
EPF10K200E
EPF10K200S 24 312 52 48