101673HMC252QS24 - ANALOG DEVICES

October, 2015 − Rev. 6 1Publication Order Number:

NCP1397/D

NCP1397A/B, NCV1397A/B

High Performance Resonant

Mode Controller with

Integrated High-Voltage

Drivers

The NCP1397 is a high performance controller that can be utilized

in half bridge resonant topologies such as series resonant, parallel

resonant and LLC resonant converters. It integrates 600 V gate

drivers, simplifying layout and reducing external component count.

With its unique architecture, including a 500 kHz Voltage Controlled

Oscillator whose control mode permits flexibility when an ORing

function is required, the NCP1397 delivers everything needed to build

a reliable and rugged resonant mode power supply.

The NCP1397 provides a suite of protection features with

configurable settings to optimize any application. These include:

auto−recovery or fault latch−off, brown−out, open optocoupler,

soft−start and short−circuit protection. Deadtime is also adjustable to

overcome shoot through current.

Features

•High−Frequency Operation from 50 kHz up to 500 kHz

•600 V High−Voltage Floating Driver

•Adjustable Minimum Switching Frequency with ±3% Accuracy

•Adjustable Deadtime from 100 ns to 2 ms.

•Startup Sequence Via an Externally Adjustable Soft−Start

•Brown−Out Protection for a Simpler PFC Association

•Latched Input for Severe Fault Conditions, e.g. Over Temperature

or OVP

•Timer−Based Input with Auto−Recovery Operation for Delayed

Event Reaction

•Latched Overcurrent Protection

•Disable Input for Immediate Event Reaction or Simple ON/OFF

Control

•VCC Operation up to 20 V

•Low Startup Current of 300 mA

•1 A/0.5 A Peak Current Sink/Source Drive Capability

•Common Collector Optocoupler Connection for Easier ORing

•Optional Common Emitter Optocoupler Connection

•Internal Temperature Shutdown

•NCV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Typical Applications

•Flat Panel Display Power Converters

•High Power ac−dc Adapters for Notebooks

•Computing Power Supplies

•Industrial and Medical Power Sources

•Offline Battery Chargers

PIN CONNECTIONS

MARKING DIAGRAMS

x = P (standard) or V (automotive)

y = A or B

A = Assembly Location

WL = Wafer Lot

Y = Year

WW = Work Week

G = Pb−Free Package

SO−16, LESS PIN 13

D SUFFIX

CASE 751AM

(Top View)

CSS(dis)

Fmax

Ctimer

Skip/Disable

Vboot

Mupper

VCC

Mlower

Fault

GND

See detailed ordering and shipping information in the package

dimensions section on page 26 of this data sheet.

ORDERING INFORMATION

NCx1397yG

AWLYWW

www.onsemi.com

NCP1397A/B, NCV1397A/B

www.onsemi.com

Figure 1. Typical Application Example

R18

PIN FUNCTION DESCRIPTION

Pin # Pin Name Function Pin Description

1 CSS(dis) Soft−Start Discharge Soft−start capacitor discharge pin. Connect to the soft−start capacitor to reset it

before startup or during overload conditions.

2 Fmax Maximum frequency clamp A resistor sets the maximum frequency excursion

3 Ctimer Timer duration Sets the timer duration in presence of a fault

4 Rt Minimum frequency clamp Connecting a resistor to this pin, sets the minimum oscillator frequency reached

for VFB = 1 V.

5 BO Brown−Out Detects low input voltage conditions. When brought above Vlatch (4 V typically), it

fully latches off the controller.

6 FB Feedback Injecting current into this pin increases the oscillation frequency up to Fmax.

7 DT Deadtime A simple resistor adjusts the dead−time width

8 Skip/Disable Skip or Disable input Upon release, a clean startup sequence occurs if VFB < 0.3 V. During the skip

mode, when FB doesn’t drop below 0.3 V, the IC restarts without soft−start

sequence.

9 Fault Fault detection input When asserted, the external timer starts to countdown and shuts down the

controller at the end of its time duration. Simultaneously the Soft−Start discharge

switch is activated so the converter operating frequency goes up to protect

application power stage. This input features also second fault comparator with

higher threshold (1.5 V typically) that:

A) Speeds up the timer capacitor charging current 8 times – NCP1397A

B) latches off the IC permanently – NCP1397B

In both versions the second fault comparator helps to protect application in case

of short circuit on the output or transformer secondary winding.

10 GND Analog ground −

11 Mlower Low side output Drives the lower side MOSFET

12 VCC Supplies the controller The controller accepts up to 20 V

13 NC Not connected Increases the creepage distance

14 HB Half−bridge connection Connects to the half−bridge output

15 Mupper High side output Drives the higher side MOSFET

16 Vboot Bootstrap pin The floating VCC supply for the upper stage

NCP1397A/B, NCV1397A/B

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Figure 2. Internal Circuit Architecture (NCP1397A)

Vref

VDD

CIDT

−

DT Adj.

I = Imax for Vfb = 5.3 V

I = 0 for Vfb < Vfb(min)

Imin

VFB  VFB(o )

Vref

VDD

Imax

VFB = 5

Fmax

VDD

Itimer1

−−

imer

+Vref

PON Reset

Vtimer OFF

Reset

SS(dis)

RFB −

−

+VFB(fault)

−−

+G = 1

> 0 only

V=V (FB) −− VFB(min)

IDT

Vref

VDD

VFB(min)

DT Deadtime

Adjustment

VDD

−

+VBO

−

+Vlatch

Clk

Q Q

RPON Reset

50% DC

Temperature

Shutdown

VCC

Management

PON

Reset

Fault

Timeout

Fault

Vref

Reset

−

Vref Skip/Disable

Skip/

Disabl

VCC

Timeout

Fault

Mlowe

GND

IBO

20 ns Noise

Filter

−

Fault

+Vref(fault)

VBOOT

Muppe

UVLO

Fast

Fault

−−

Vref(OCP)

Vdd

Itimer2

Level

Shifter

20 ms Noise

Filter

Fault

PON Reset

Enable

(if Vfb<0.3V)

20 ms Noise

Filter

1 ms Noise

Filter

NCP1397A/B, NCV1397A/B

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Figure 3. Internal Circuit Architecture (NCP1397B)

Vref

VDD

CIDT

−

DT Adj.

I = Imax for Vfb = 5.3 V

I = 0 for Vfb < Vfb_min

Vref

Imin

VFB  VFB(o )

Vref

VDD

Imax

Vfb = 5

Fmax

VDD

Itimer1

If FAULT Itimer else 0

−−

Timer

+Vref

SS(dis)

RFB −

−

+VFB(fault)

−

+G = 1

> 0 only

V=V (FB) −− VFB(min)

IDT

Vref

VDD

VFB(min)

DT Deadtime

Adjustment

VDD

−

+VBO

−−

+Vlatch

Clk

Q Q

RPON Reset

50% DC

Temperature

Shutdown

VCC

Management

PON

Reset

Fault

Timeout

Fault

Vref

Reset

−−

Vref Skip

Skip/

Disable

VCC

Timeout

Fault

Mlower

GND

IBO

20 ns Noise

Filter

−

Fault

+Vref(fault)

VBOOT

Muppe

UVLO

Level

Shifter

Fast

Fault

−−

Vref(OCP)

PON Reset

Vtimer OFF

Reset

Fault

PON Reset

Enable

(if Vfb<0.3V)

20 ms Noise

Filter

20 ms Noise

Filter

1 ms Noise

Filter

NCP1397A/B, NCV1397A/B

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MAXIMUM RATINGS

Rating Symbol Value Unit

High Voltage bridge pin, pin 14 VBRIDGE −1 to 600 V

Floating supply voltage, ground referenced VBOOT − VBRIDGE 0 to 20 V

High side output voltage VDRV(HI) VBRIDGE−0.3 to

VBOOT+0.3 V

Low side output voltage VDRV(LO) −0.3 to VCC+0.3 V

Allowable output slew rate dVBRIDGE/dt 50 V/ns

Power Supply voltage, pin 12 VCC 20 V

Maximum voltage, all pins (except pin 11 and 10) −−0.3 to 10 V

Thermal Resistance Junction−to−Air, SOIC version RqJA 130 °C/W

Storage Temperature Range −−60 to +150 °C

ESD Capability, Human Body Model (HBM) (All pins except HV pins) − 2 kV

ESD Capability, Machine Model (MM) − 200 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be af fected.

1. This device(s) contains ESD protection and exceeds the following tests:

Human Body Model 2000 V per JEDEC Standard JESD22−A114E

Machine Model 200 V per JEDEC Standard JESD22−A115−A

2. This device meets latchup tests defined by JEDEC Standard JESD78.

NCP1397A/B, NCV1397A/B

www.onsemi.com

ELECTRICAL CHARACTERISTICS

(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted)

Symbol Rating Pin Min Typ Max Unit

SUPPLY SECTION

VCC(on) Turn−on threshold level, VCC going up 12 9.7 10.5 11.3 V

VCC(min) Minimum operating voltage after turn−on 12 8.7 9.5 10.3 V

Vboot(on) Startup voltage on the floating section 16−14 8 9 10 V

Vboot(min) Cutoff voltage on the floating section 16−14 7.4 8.4 9.4 V

Istartup Startup current, VCC < VCC(on) 12 − − 300 mA

VCC(reset) VCC level at which the internal logic gets reset 12 − 6.6 − V

ICC1 Internal IC consumption, no output load on pin 15/14 – 11/10,

FSW = 300 kHz 12 − 4 − mA

ICC2 Internal IC consumption, 1 nF output load on pin 15/14 – 11/10,

FSW = 300 kHz 12 − 11 − mA

ICC3 Consumption in fault or disable mode (All drivers disabled,

Rt = 34 kW, RDT = 10 kW)12 − 1.5 − mA

VOLTAGE CONTROL OSCILLATOR (VCO)

FSW(min) Minimum switching frequency, Rt = 34 kW on pin 4, Vpin6 = 0.8 V,

DT = 300 ns 4 58.2 60 61.8 kHz

FSW(max) Maximum switching frequency, Rf(max) = 1.9 kW on pin 2, Vpin6 >

5.3 V, Rt = 34 kW, DT = 300 ns 2 440 500 560 kHz

FBSW Feedback pin swing above which Df = 0 6 − 5.3 − V

DC Operating duty−cycle symmetry 11−15 48 50 52 %

Tdel1 Delay before driver restart from fault or disable mode − − 700 − ns

Tdel2 Delay before driver restart after VCC(on) event (Note 4) − − 11 −ms

Vref(Rt) Reference voltage for Rt pin 4 2.18 2.3 2.42 V

FEEDBACK SECTION

RFB Internal pulldown resistor 6 − 20 − kW

VFB(min) Voltage on pin 6 below which the FB level has no VCO action 6 − 1.1 − V

VFB(off) Voltage on pin 6 below which the controller considers the FB fault 6 240 280 320 mV

VFBoff(hyste) Feedback fault comparator hysteresis 6 − 45 − mV

DRIVE OUTPUT

TrOutput voltage risetime @ CL = 1 nF, 10−90% of output signal 15−14/11−10 − 40 − ns

TfOutput voltage falltime @ CL = 1 nF, 10−90% of output signal 15−14/11−10 − 20 − ns

ROH Source resistance 15−14/11−10 − 13 − W

ROL Sink resistance 15−14/11−10 − 5.5 − W

Tdead Deadtime with RDT = 10 kW from pin 7 to GND 7 250 290 340 ns

Tdead(max) Maximum deadtime with RDT = 82 kW from pin 7 to GND 7 − 2 − ms

Tdead(min) Minimum deadtime, RDT = 3 kW from pin 7 to GND 7 − 100 − ns

IHV(LEAK) Leakage current on high voltage pins to GND 14, 15,16 − − 5 mA

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

3. The IC does not activate soft−start (unless the feedback pin voltage is below 0.3 V) when the skip/disable input is released, this is for skip

cycle implementation.

4. Guaranteed by design.

NCP1397A/B, NCV1397A/B

www.onsemi.com

ELECTRICAL CHARACTERISTICS (continued)

(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted)

Symbol UnitMaxTypMinPinRating

TIMERS

Itimer1 Timer capacitor charge current during feedback fault or when

Vref(fault) < Vpin9 < Vref(OCP) 3 150 175 190 mA

Itimer2 Timer capacitor charge current when Vpin9 > Vref(OCP) (Icharge1 +

Icharge2) – A version only 3 1.1 1.3 1.5 mA

Ttimer Timer duration with a 1 mF capacitor and a 1 MW resistor, Itimer1

current applied 3 − 24 − ms

TtimerR Timer recurrence in permanent fault, same values as above 3 − 1.4 − s

Vtimer(on) Voltage at which pin 3 stops output pulses 3 3.8 4 4.2 V

Vtimer(off) Voltage at which pin 3 restarts output pulses 3 0.95 1 1.05 V

RSS(dis) Soft−start discharge switch channel resistance 1 − 100 − W

PROTECTION

Vref(Skip) Reference voltage for Skip/Disable input (Note 4) 8 630 660 690 mV

Hyste(Skip) Hysteresis for Skip/Disable (Note 4) 8 − 45 − mV

Vref(Fault) Reference voltage for Fault comparator 9 0.99 1.04 1.09 V

Hyste(Fault) Hysteresis for fault comparator input 9 − 60 − mV

Vref(OCP) Reference voltage for OCP comparator 9 1.47 1.55 1.63 V

Hyste(OCP) Hysteresis for OCP comparator input 9 − 90 − mV

Tp(Disable) Propagation delay from disable input to the drive shutdown 8 − 60 100 ns

IBO(bias) Brown−Out input bias current 5 − 0.02 − mA

VBO Brown−Out level 5 0.99 1.04 1.09 V

IBO Hysteresis current, Vpin5 > VBO 5 25 28 31 mA

Vlatch Latching voltage 5 3.7 4 4.3 V

TSD Temperature shutdown − 140 − − °C

TSD(hyste) Hysteresis − − 30 − °C

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

3. The IC does not activate soft−start (unless the feedback pin voltage is below 0.3 V) when the skip/disable input is released, this is for skip

cycle implementation.

4. Guaranteed by design.

NCP1397A/B, NCV1397A/B

www.onsemi.com

TYPICAL CHARACTERISTICS

10.35

10.40

10.45

10.50

10.55

−40 −25 −10 5 20 35 50 65 80 95 110 125

Figure 4. VCC(on) Threshold

CC(on)

(V)

TEMPERATURE (°C)

Figure 5. VCC(min) Threshold

9.38

9.40

9.42

9.44

9.46

9.48

9.50

9.52

−40 −25 −10 5 20 35 50 65 80 95 110 12

TEMPERATURE (°C)

VCC(min) (V)

SW(min)

(kHz)

TEMPERATURE (°C)

Figure 6. FSW(min) Frequency Clamp

503

504

505

506

507

508

509

510

−40 −25 −10 5 20 35 50 65 80 95 110 12

FSW(max) (kHz)

TEMPERATURE (°C)

Figure 7. FSW(max) Frequency Clamp

18.5

19.0

19.5

20.0

20.5

21.0

21.5

22.0

22.5

23.0

−40 −25 −10 5 20 35 50 65 80 95 110 125

Figure 8. Pulldown Resistor (R

)

TEMPERATURE (°C)

)

0.655

0.656

0.657

0.658

0.659

0.660

0.661

−40 −25 −10 5 20 35 50 65 80 95 110 1

Vref(skip) (V)

TEMPERATURE (°C)

Figure 9. Skip/Disable Threshold (V

ref(skip)

)

59.75

59.8

59.85

59.9

59.95

60.05

−40 −20 0 20 40 60 80 100 120

NCP1397A/B, NCV1397A/B

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TYPICAL CHARACTERISTICS

Figure 10. Source Resistance (ROH)

8.0

9.0

10.0

11.0

12.0

13.0

14.0

15.0

16.0

17.0

−40 −25 −10 5 20 35 50 65 80 95 110 125

ROHA (

)

TEMPERATURE (°C)

104

105

106

107

108

109

110

111

112

113

114

−40 −25 −10 5 20 35 50 65 80 95 110 125

TEMPERATURE (°C)

dead(min)

(ns)

4.0

4.5

5.0

5.5

6.0

6.5

7.0

7.5

8.0

8.5

9.0

−40 −25 −10 5 20 35 50 65 80 95 110 12

TEMPERATURE (°C)

ROLA (W)

Figure 11. Sink Resistance (ROL)

Figure 12. Tdead(min)

286

287

288

289

290

291

292

293

294

295

296

297

−40 −25 −10 5 20 35 50 65 80 95 110 1

TEMPERATURE (°C)

Tdead(nom) (ns)

Figure 13. Tdead(nom)

2.035

2.040

2.045

2.050

2.055

2.060

2.065

−40−25−105 203550658095110125

dead(max)

(

TEMPERATURE (°C)

Figure 14. T

dead(max)

4.005

4.010

4.015

4.020

4.025

4.030

4.035

−40 −25 −10 5 20 35 50 65 80 95 110 1

TEMPERATURE (°C)

Vlatch (V)

Figure 15. Latch Level (V

latch

)

NCP1397A/B, NCV1397A/B

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TYPICAL CHARACTERISTICS

1.022

1.024

1.026

1.028

1.030

1.032

1.034

1.036

1.038

−40 −25 −10 5 20 35 50 65 80 95 110 125

VBO (V)

TEMPERATURE (°C)

Figure 16. Brown−Out Reference (VBO)

27.0

27.2

27.4

27.6

27.8

28.0

28.2

28.4

28.6

28.8

−40 −25 −10 5 20 35 50 65 80 95 110 12

TEMPERATURE (°C)

IBO (mA)

Figure 17. Brown−Out Hysteresis Current

(IBO)

1.032

1.034

1.036

1.038

1.040

1.042

1.044

1.046

1.048

1.050

−40 −25 −10 5 20 35 50 65 80 95 110 125

ref(fault)

(V)

TEMPERATURE (°C)

Figure 18. Fault Input Reference (Vref(fault))

166

168

170

172

174

176

178

−40 −25 −10 5 20 35 50 65 80 95 110 1

TEMPERATURE (°C)

Itimer1 (mA)

Figure 19. Ctimer 1st Current (Itimer1)

1.530

1.535

1.540

1.545

1.550

1.555

1.560

1.565

−40 −25 −10 5 20 35 50 65 80 95 110 125

ref(OCP)

(V)

TEMPERATURE (°C)

Figure 20. OCP reference (V

ref(OCP)

)

1.25

1.26

1.27

1.28

1.29

1.30

1.31

1.32

1.33

1.34

−40 −25 −10 5 20 35 50 65 80 95 110 1

TEMPERATURE (°C)

Itimer2 (mA)

Figure 21. C

timer

2nd Current (I

timer2

)

NCP1397A/B, NCV1397A/B

www.onsemi.com

TYPICAL CHARACTERISTICS

4.005

4.010

4.015

4.020

4.025

4.030

4.035

−40 −25 −10 5 20 35 50 65 80 95 110 125

TEMPERATURE (°C)

timer(on)

(V)

Figure 22. Fault Timer Ending Voltage

timer(on)

)

0.274

0.276

0.278

0.280

0.282

0.284

0.286

0.288

−40 −25 −10 5 20 35 50 65 80 95 110 1

TEMPERATURE (°C)

Figure 23. FB Fault Detection Threshold

FB(fault)

)

VFB(off) (V)

0.992

0.993

0.994

0.995

0.996

0.997

0.998

0.999

1.000

−40 −25 −10 5 20 35 50 65 80 95 110 125

Figure 24. Fault Timer Reset Voltage (Vtimer(off))

TEMPERATURE (°C)

Vtimer(off) (V)

NCP1397A/B, NCV1397A/B

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APPLICATION INFORMATION

The NCP1397A/B includes all necessary features to help

building a rugged and safe switch−mode power supply

featuring an extremely low standby power. The below

bullets detail the benefits brought by implementing the

NCP1397A/B controller:

•Wide frequency range: A high−speed Voltage Control

Oscillator allows an output frequency excursion from

50 kHz up to 500 kHz on Mlower and Mupper outputs.

•Adjustable dead−time: Due to a single resistor wired

to ground, the user has the ability to include some

dead−time, helping to fight cross−conduction between

the upper and the lower transistor.

•Adjustable soft−start: Every time the controller starts

to operate (power on), the switching frequency is

pushed to the programmed starting value by external

components (RFmin//RFstart) and slowly moves down

toward the minimum frequency, until the feedback loop

closes. The soft−start discharge input (SS(dis))

discharges the Soft−Start capacitor before any IC restart

excluding the restart after Disable is released AND FB

voltage is higher than 0.3 V. The Soft−Start dischar ge

switch also activates in case the Fault input detects the

overload conditions.

•Adjustable minimum and maximum frequency

excursion: In resonant applications, it is important to

stay away from the resonating peak to keep operating

the converter in the right region. Thanks to a single

external resistor, the designer can program its lowest

frequency point, obtained in lack of feedback voltage

(during the startup sequence or in short−circuit

conditions). Internally trimmed capacitors offer a $3%

precision on the selection of the minimum switching

frequency. The adjustable upper stop being less precise

to $12%.

•Low startup current: When directly powered from the

high−voltage DC rail, the device only requires 300 mA

to startup.

•Brown−Out detection: To avoid operation from a low

input voltage, it is interesting to prevent the controller

from switching if the high−voltage rail is not within the

right boundaries. Also, when teamed with a PFC

front−end circuitry, the brown−out detection can ensure

a clean startup sequence with soft−start, ensuring that

the PFC is stabilized before energizing the resonant

tank. The BO input features a 28 mA hysteresis current

for the lowest consumption.

•Adjustable fault timer duration: When a fault is

detected on the Fault input or when the FB path is

broken, timer pin starts to charge an external capacitor.

If the fault is removed, the timer opens the charging

path and nothing happens. When the timer reaches its

selected duration (via a capacitor on Pin 3), all pulses

are stopped. The controller now waits for the discharge

via an external resistor on Pin 3 to issue a new clean

startup sequence via soft−start.

•Cumulative fault events: In the NCP1397A/B, the

timer capacitor is not reset when the fault disappears. It

actually integrates the information and cumulates the

occurrences. A resistor placed in parallel with the

capacitor will offer a simple way to adjust the discharge

rate and thus the auto−recovery retry rate.

•Overcurrent detection using Fault input: The fault

input is specifically designed to protect LLC

application in case of short circuit or overload. In case

the voltage on this input grows above first threshold the

Itimer current source is activated and Fault timer

capacitor starts charging. Simultaneously the Soft−Start

discharge switch is activated to increase operating

frequency of the converter. The IC stops operation in

case the Fault timer elapses. The Fault input includes

also second fault comparator that:

− Speeds up the fault timer capacitor charging by

increasing the Itimer1 current to Itimer2 – NCP1397A

− Latches off the device – NCP1397B

The second fault comparator thus helps to protect the power

stage in case of hard short circuit (like shorted transformer

winding etc.)

•Skip cycle possibility: The absence of the soft−start on

the Skip/Disable input (in case the VFB > 0.3 V) offers

an easy way to implement skip cycle when power

saving features are necessary. A simple resistive divider

from the feedback pin to the Skip/Disable input, and

skip can be implemented.

•Broken feedback loop detection: Upon startup or any

time during operation, if the FB signal is missing, the

timer starts to charge timer capacitor. If the loop is

really broken, the FB level does not grow−up before the

timer ends charging. The controller then stops all pulses

and waits until the timer pin voltage collapses to 1 V

typically before a new attempt to restart, via the

soft−start. If the optocoupler is permanently broken, a

hiccup takes place.

•Common collector or common emitter optocoupler

connection options: This IC allows the designer to

select from two possible optocoupler configurations.

Voltage−Controlled Oscillator

The VCO section features a high−speed circuitry allowing

operation from 100 kHz up to 1 MHz. However , as a division

by two internally creates the two Q and /Q outputs, the final

effective signal on output Mlower and Mupper switches

between 50 kHz and 500 kHz. The VCO is configured in

such a way that if the feedback pin voltage goes up, the

switching frequency also goes up. Figure 25 shows the

architecture of the VCO oscillator.

NCP1397A/B, NCV1397A/B

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Figure 25. The Simplified VCO Architecture

Vref

VDD

Rt sets

Fmin for V(FB) = 0 Cint

Imin

0 to IFmax

IDT

FBinternal

max

FSW

max

Clk

DSQ

Vref

VDD

RDT sets

the deadtime

Imin

VDD

Fmax

Fmax sets

the maximum FSW

VCC

RFB

20 k

VFB < VFB(off)

Start fault timer

Vb(off)

The designer needs to program the maximum switching

frequency and the minimum switching frequency. In LLC

configurations, for circuits working above the resonant

frequency, a high precision is required on the minimum

frequency, hence the $3% specification. This minimum

switching frequency is actually reached when no feedback

closes the loop. It can happen during the startup sequence,

a strong output transient loading or in a short−circuit

condition. By installing a resistor from Pin 4 to GND, the

minimum frequency is set. Using the same philosophy,

wiring a resistor from Pin 2 to GND will set the maximum

frequency excursion. To improve the circuit protection

features, we have purposely created a dead zone, where the

feedback loop has no action. This is typically below 1.1 V.

Figure 26 details the arrangement where the internal voltage

(that drives the VCO) varies between 0 and 2.3 V. However,

to create this swing, the feedback pin (to which the

optocoupler emitter connects), will need to swing typically

between 1.1 V and 5.3 V.

Figure 26. The OPAMP Arrangement Limits the

VCO Modulation Signal between 0.5 and 2.3 V

VCC

FB R1

11.3 k −

Vref

0.5 V

8.7 k

100 k D1

2.3 V

RFmax

Fmax

NCP1397A/B, NCV1397A/B

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This techniques allows us to detect a fault on the converter

in case the FB pin cannot rise above 0.3 V (to actually close

the loop) in less than a duration imposed by the

programmable timer. Please refer to the fault section for

detailed operation of this mode.

As shown on Figure 26, the internal dynamics of the VCO

control voltage will be constrained between 0.5 V and 2.3 V,

whereas the feedback loop will drive Pin 6 (FB) between

1.1 V and 5.3 V. If we take the default FB pin excursion

numbers, 1.1 V = 50 kHz, 5.3 V = 500 kHz, then the VCO

maximum slope will be:

500 k *50 k

4.2 +107 kHz/V

Figures 27 and 28 portray the frequency evolution

depending on the feedback pin voltage level in a different

frequency clamp combination.

Figure 27. Maximal Default Excursion,

Rt = 41 kW on Pin 4 and R

F(max)

= 1.9 kW on Pin 2

Figure 28. Here a Different Minimum Frequency was

Programmed as well as a Maximum Frequency

Excursion

Please note that the previous small−signal VCO slope has

now been reduced to 300k / 4.1 = 71 kHz / V on M upper and

Mlower outputs. This offers a mean to magnify the feedback

excursion o n systems where the load range does not generate

a wide switching frequency excursion. Due to this option,

we will see how it becomes possible to observe the feedback

level and implement skip cycle at light loads. It is important

to note that the frequency evolution does not have a real

linear relationship with the feedback voltage. This is due to

the deadtime presence which stays constant as the switching

period changes.

The selection of the three setting resistors (Fmax, Fmin and

deadtime) requires the usage of the selection charts

displayed below:

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150

250

350

450

550

1.9 11.9 21.9 31.9 41.9

Figure 29. Maximum Switching Frequency Resistor

Selection Depending on the Adopted Minimum

Switching Frequency

RFmax (kW)

Fmax (kHz)

VCC = 15 V

VFB = 6.5 V

DT = 300 ns

Fmin = 200 kHz

Fmin = 50 kHz

100

150

200

250

300

350

400

450

500

2468101214161820

RFmin (kW)

Fmin (kHz)

100

20 30 40 50 60 70 80 90 100 110

Figure 30. Minimum Switching Frequency Resistor

Selection (Fmin = 100 kHz to 500 kHz)

Figure 31. Minimum Switching Frequency Resistor

Selection (Fmin = 20 kHz to 100 kHz)

RFmin (kW)

Fmin (kHz)

VCC = 15 V

VFB = 1 V

DT = 300 ns

VCC = 15 V

VFB = 1 V

DT = 300 ns

100

300

500

700

900

1100

1300

1500

1700

1900

3.5 13.5 23.5 33.5 43.5 53.5 63.5 73.583.5

RDT (kW)

DT (ns)

Figure 32. Deadtime Resistor Selection

ORing capability and optocoupler connection

configurations

If for any particular reason, there is a need for a frequency

variation linked to an event appearance (instead of abruptly

stopping pulses), then the FB pin lends itself very well to the

addition of other sweeping loops. Several diodes can easily

be used perform the job in case of reaction to a fault event

or to regulate on the output current (CC operation).

Figure 33 shows how to do it.

Figure 33. Thanks to the FB Configuration, Loop

ORing is Easy to Implement

VCC

In1

In2 20 k

VCO

The VCO configuration used in this IC also offers an easy

way to connect optocoupler (or pulldown bipolar) directly

to the Rt pin instead of FB pin (refer to Figures 34 and 35).

The optocoupler is then configured as “common emitter”

and the operating frequency is controlled by the current that

is taken out from the Rt pin – we have current controller

oscillator (CCO). If one uses this configuration it is needed

to maintain FB pin voltage between 0.3 V and 1 V otherwise

the FB fault will be detected. The FB pin can be still used for

open FB loop detection in some applications – to do so it is

needed to keep optcoupler emitter voltage higher then 0.3 V

for nominal load conditions. One needs to take RFB

pulldown resistor into account when using this

configuration. It is possible to implement skip mode using

Skip/disable input and emitter resistors Rskip1 and Rskip2.

NCP1397A/B, NCV1397A/B

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Figure 34. Feedback Configuration Using Direct Connection to the Rt Pin

Fmax

Skip/Disable

VCC

GND

NCP1397

Rskip2

Rskip1

OK1

RFstart

RFmin

CSS

Fstart(adj) − RFstart/RFmin

Fmin(adj) − RFmin

Fmax(adj) − Rc + Rskip1 + Rskip2

Figure 35. Feedback Configuration Using Direct Connection to the Rt Pin – No Open FB Loop Detection

Fmax

Skip/Disable

VCC

GND

NCP1397

Rskip2

Rskip1

OK1

RFstart

RFmin

CSS

Fstart(adj) − RFstart/RFmin

Fmin(adj) − RFmin

Fmax(adj) − Rc + Rskip1 + Rskip2

1N4148

Rbias

Dead−Time Control

Deadtime control is an absolute necessity when the

half−bridge configuration comes to play. The deadtime

technique consists in inserting a period during which both

high and low side switches are off. Of course, the deadtime

amount d i f fers depending on the switching frequency, hence

the ability to adjust it on this controller. The option ranges

between 100 ns and 2 ms. The deadtime is actually made by

controlling the oscillator discharge current. Figure 36

portrays a simplified VCO circuit based on Figure 25.

During the dischar ge time, the clock comparator is high and

invalidates the AND gates: both outputs are low. When the

comparator goes back to the low level, during the timing

capacitor Ct recharge time, A and B outputs are validated.

By connecting a resistor RDT to ground, it creates a current

whose image serves to discharge the Ct capacitor: we control

the dead−time. The typical range evolves between 100 ns

(RDT = 3.5 kW) and 2 ms (RDT = 83.5 kW). Figure 39 shows

the typical waveforms.

NCP1397A/B, NCV1397A/B

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Figure 36. Dead−time Generation

VDD

Icharge:

FSW(min) + FSW(max)

Idis

RDT

Vref

+3 V−1 V

−

+Clk

DSQ

Soft−Start Sequence

In resonant controllers, a soft−start is needed to avoid

suddenly applying the full current into the resonating circuit.

W ith this controller the soft−start duration is fully adjustable

using eternal components. The purpose of the Soft−Start pin

is to discharge Soft−Start capacitor before IC restart and in

case of fault conditions detected by Fault input.

Once the controller starts operation, the Soft−Start

capacitor (refer to Figure 37) is fully discharged and thus it

starts charging from the Rt pin. The charging current

increases operating frequency of the controller above Fmin.

As the soft−start capacitor charges, the frequency smoothly

decreases down to Fmin. Of course, practically, the feedback

loop is supposed to take over the VCO lead as soon as the

output voltage has reached the target. If not, then the

minimum switching frequency is reached and a fault is

detected on the feedback pin (typically below 300 mV).

Figure 38 depicts a typical LLC startup using NCP1397A/B

controller.

Figure 37. Soft−Start Components Arrangement

Fmax

GND

NCP1397

RF(start)

RFmin

RFmax

CSS

Fstart(adj) − RFstart/RFmin

Fmin(adj) − RFmin

Fmax(adj) − RFmax

Figure 38. A Typical Startup Sequence on a LLC

Converter Using NCP1397

Action

Target is

Reached

Please note that the soft−start capacitor is discharged in the

following conditions:

− A startup sequence

− During auto−recovery burst mode

− A brown−out recovery

− A temperature shutdown recovery

The skip/disable input undergoes a special treatment.

Since we want to implement skip cycle using this input, we

cannot activate the soft−start every time the feedback pin

stops the operations in low power mode. Therefore, when

the skip/enable pin is released, no soft−start occurs to offer

the best skip cycle behavior. However, it is very possible to

combine skip cycle and true disable, e.g. via ORing diodes

driving Pin 8. In that case, if a signal maintains the

skip/disable input high long enough to bring the feedback

level down (below 0.3 V) since the output voltage starts to

fall down, then the soft−start discharge switch is activated.

NCP1397A/B, NCV1397A/B

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1.00

2.00

3.00

4.00

8.00

12.0

16.0

time in seconds

−8.00

−4.00

4.00

8.00

Figure 39. Typical Oscillator Waveforms

Ct Voltage

56.2 m65.9 m75.7 m85.4 m95.1 m

Plot3

Difference in Volts Plot2

Clock in Volts Plot1

Vct in Volts

Clock Pulses DT

A − B

Brown−Out protection

The Brown−Out circuitry (BO) offers a way to protect the

resonant converter from low DC input voltages. Below a

given level, the controller blocks the output pulses, above it,

it authorizes them. The internal circuitry, depicted by

Figure 40, offers a way to observe the high−voltage (HV)

rail. A resistive divider made of Rupper and Rlower, brings a

portion of the HV rail on Pin 5. Below the turn−on level, the

28 mA current source IBO is off. Therefore, the turn−on

level solely depends on the division ratio brought by the

resistive divider.

Figure 40. The Internal Brown−out Configuration with

an Offset Current Source

VDD

+VBO

−

ON/OFF

IBO

Vbulk

Rupper

Rlower

NCP1397A/B, NCV1397A/B

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time in seconds

4.0

8.0

12.0

16.0

150

250

350

450

Figure 41. Simulation Results for 350 / 250 ON / OFF Levels

20 m60 m100 m140 m180 m

Vin

250 V

351 V

Plot1 Vin in Volts

Vcmp in Volts

To the contrary, when the internal BO signal is high

(Mlower and Mupper pulse), the IBO source is activated and

creates a hysteresis. As a result, it becomes possible to select

the turn−on and turn−off levels via a few lines of algebra:

IBO is off

V())+Vbulk1 Rlower

Rlower )Rupper (eq. 1)

IBO is on

V())+Vbulk2 Rlower

Rlower )Rupper (eq. 2)

)IBO ǒRlower Rupper

Rlower )RupperǓ

We can now extract Rlower from Equation 1 and plug it into

Equation 2, then solve for Rupper:

Rupper +Rlower Vbulk1 *VBO

VBO

Rlowerer +VBO Vbulk1 *Vbulk2

IBO ǒVbulk1 *VBOǓ

If we decide to turn−on our converter for Vbulk1 equals

350 V and turn it off for Vbulk2 equals 250 V, then we obtain:

Rupper = 3.57 MW

Rlower = 10.64 kW

The bridge power dissipation is 4002 / 3.781 MW =

45 mW when front−end PFC stage delivers 400 V.

Figure 41 simulation result confirms our calculations.

Latchoff Protection

There are some situations where the converter shall be

fully turned−off and stay latched. This can happen in

presence of a n overvoltage (the feedback loop is drifting) or

when an over temperature is detected. Thanks to the addition

of a comparator on the BO pin, a simple external circuit can

lift up this pin above Vlatch (4 V typical) and permanently

disable pulses. The VCC needs to be cycled down below

6.5 V typically to reset the controller.

NCP1397A/B, NCV1397A/B

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Figure 42. Adding a Comparator on the BO Pin Offers a way to Latch−off the Controller

−

+20 ms

RC To permanent

latch

Vlatch

VDD

−

+BO

VBO

Rlower

Rupper

VbulkVCC

NTC

Vout

IBO

On Figure 42, Q1 is blocked and does not bother the BO

measurement a s long as the NTC and the optocoupler are not

activated. As soon as the secondary optocoupler senses an

OVP condition, or the NTC reacts to a high ambient

temperature, Q1 base is brought to ground and the BO pin

goes up, permanently latching off the controller.

Protection Circuitry

This resonant controller offers a dedicated input (Fault

input) to detect primary overcurrent conditions and protect

power stage from damage.

Once the voltage on the Fault input exceeds 1.04 V

threshold the external timer capacitor starts charging by

Itimer1 current. Simultaneously the Soft−Start discharge

switch is activated to shift operating frequency up to keep

primary current at acceptable level. In case the overload

disappears fast enough the Soft−Start discharge switch is

open, Itimer1 current turned−off and timer capacitor

discharges via an external parallel resistor. In case the

overload lasts for more than timer duration (given by Itimer,

Vtimer, C timer and Rtimer) the IC stops the operation and waits

until the Ctimer will discharge to 1 V. The application then

restarts via Soft−Start.

In case of heavy overload, like transformer short circuit,

the primary current grows very fast and thus could reach

danger level prior the fault timer elapses. The NCP1397B

therefore features additional comparator (1.55 V) on the

Fault input to permanently latch the application and protect

against destruction. Figure 44 depicts the architecture of the

fault circuitry for NCP1397B controller.

The NCP1397A features second fault comparator as well

but in this case it doesn’t latches off the IC but speeds up the

Fault timer capacitor charging by turning on additional

current source Itimer2 – refer to Figure 43. The NCP1397A

can thus be used in applications that have to recover

automatically from any fault conditions.

NCP1397A/B, NCV1397A/B

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Figure 43. Fault Input Logic for NCP1397A

VDD

Itimer1

Reset

UVLO

Rtimer

CtimerCtimer

Vref(fault)

VtimerON

VtimerOFF 1 = ok

0 = fault

Vref(skip)

Skip/Disable

1 = ok

0 = fault

DRIVING

LOGIC SS

Reset

Fault

Average

Input

Current

To Primary

Skip

VCC

SS(dis) Css

discharge at VCC(on)/

restart if VFB < 0.3 V

Vref(OCP)

VDD

Itimer2

Current Sensing

Circuitry

NCP1397A/B, NCV1397A/B

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Figure 44. Fault Input Logic for NCP1397B

VDD

Itimer1

Reset

UVLO

Rtimer

CtimerCtimer

Vref(fault)

VtimerON

VtimerOFF 1 = ok

0 = fault

Vref(skip)

Skip/Disable

1 = ok

0 = fault

DRIVING

LOGIC SS

Reset

Fault

Average

Input

Current

To Primary

Skip

VCC

SS(dis) Css

discharge at VCC(on)/

restart if VFB < 0.3 V

Vref(OCP)

Current Sensing

Circuitry

to latch

On Figures 43 and 44 examples, a voltage proportional to

primary current, once averaged, gives an image of the input

power in case Vin is kept constant via a PFC circuit. If the

output loading increases above a certain level, the voltage on

this pin will pass the 1 V threshold and start the timer. If the

overload stays there, after a few tens of milli −seconds,

switching pulses will disappear and a protective

auto−recovery cycle will take place. Adjusting the resistor

R in parallel with the timer capacitor will give the flexibility

to adjust the fault burst mode (refer to Figure 45).

NCP1397A/B, NCV1397A/B

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Figure 45. A Resistor Can Easily Program the Capacitor Discharge Time

4 V

1 V

SMPS Re−starts

SMPS Stops

Reset at Re−start

Fault is Gone

Skip/Disable

VCC

Figure 46. Skip Cycle Can Be Implemented Via Two

Resistors on the FB Pin to the Fast Fault Input

Skip/Disable

The Skip/Disable input is not af fected by a delayed action.

As soon as its voltage exceeds 0.66 V typical, all pulses are

off and maintained off as long as the fault is present. When

the pin is released, pulses come back and the soft−start is

activated (in case the VFB < 0.3 V).

Thanks t o the low activation level, this pin can observe the

feedback pin via a resistive divided and thus implement skip

cycle operation. The resonant converter can be designed to

lose regulation in light load conditions, forcing the FB level

to increase. When it reaches the programmed level, it

triggers the skip input and stops pulses. Then Vout slowly

drops, the loop reacts by decreasing the feedback level

which, in turn, unlocks the pulses, Vout goes up again and so

on: we are in skip cycle mode. As the feedback voltage does

not drop below 0.3 V the Soft−Start discharge switch is not

activated in this case. Please refer also to Figure 35 for skip

mode function implementation when optocoupler is

connected directly to Rt pin.

Startup Behavior

When the VCC voltage increases, the internal current

consumption is kept below Istrup. When VCC reaches the

VCC(on) level, output Mlower goes high first and then output

Mupper. This sequence will always be the same whatever

triggers the pulse delivery: fault, OFF to ON etc… Pulsing

the output Mlower high first gives an immediate charge of the

bootstrap capacitor. Then, the rest of pulses follow,

delivered at the highest switching value, set by the RFstart

resistor in parallel with RFmin resistor on Pin 4. The

soft−start capacitor ensures a smooth frequency decrease to

either the programmed minimum value (in case of fault) or

to a value corresponding to the operating point if the

feedback loop closes first. Figure 47 shows typical signals

evolution at power on.

NCP1397A/B, NCV1397A/B

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Figure 47. At Power On, Output A is First Activated and the Frequency Slowly Decreases Based on the Soft−Start

Capacitor Voltage

Figure 47 depicts an auto−recovery situation, where the

timer has triggered the end of output pulses. In that case, the

VCC level was given by an auxiliary power supply, hence its

stability during the hiccup. A similar situation can arise if the

user selects a more traditional startup method, with an

auxiliary winding. In that case, the VCC(min) comparator

stops the output pulses whenever it is activated, that is to say,

when VCC falls below 9.5 V typical. At this time, the VCC

pin still receives its bias current from the startup resistor and

increases toward VCC(on). When the voltage reaches

VCC(on), a standard sequence takes place, involving a

soft−start. Figure 48 portrays this behavior.

NCP1397A/B, NCV1397A/B

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Figure 48. When the VCC is to Low, All Pulses are Stopped Until VCC Goes Back to the Startup Voltage

The High−Voltage Driver

The driver features a traditional bootstrap circuitry,

requiring an external high−voltage diode for the capacitor refueling path. Figure 49 shows the internal architecture of

the high−voltage section.

Figure 49. The Internal High−voltage Section of the NCP1397

Vboot

Mupper

Cboot

Dboot

aux

VCC

GND

VCC

Mlower

UVLO

Delay

Level

Shifter

Pulse

Trigger

Fault

NCP1397A/B, NCV1397A/B

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The device incorporates an upper UVLO circuitry that

makes sure enough Vgs is available for the upper side

MOSFET. The B and A outputs are delivered by the internal

logic, as Figure 43 testifies. A delay is inserted in the lower

rail to ensure good matching between these propagating

signals.

As stated in the maximum rating section, the floating

portion can go up to 600 VDC and makes the IC perfectly

suitable for offline applications featuring a 400 V PFC

front−end stage.

ORDERING INFORMATION

Device Package Shipping†

NCP1397ADR2G

SOIC−16, Less Pin 13

(Pb−Free) 2500 / Tape & Reel

NCV1397ADR2G*

NCP1397BDR2G

NCV1397BDR2G*

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specification Brochure, BRD8011/D.

*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP

Capable.

NCP1397A/B, NCV1397A/B

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PACKAGE DIMENSIONS

SOIC−16 NB, LESS PIN 13

CASE 751AM

ISSUE O

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION SHALL BE

0.13 TOTAL IN EXCESS OF THE b DIMENSION AT

MAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD

PROTRUSIONS.

5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

16 9

SEATING

PLANE

hx 45_

15X

0.25 B M

DIM MIN MAX

MILLIMETERS

D9.80 10.00

E3.80 4.00

A1.35 1.75

b0.35 0.49

L0.40 1.25

e1.27 BSC

C0.19 0.25

A1 0.10 0.25

M0 7

H5.80 6.20

h0.25 0.50

6.40

15X

0.58

15X 1.12

1.27

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT*

0.25 A S

b15X

TBS

A B

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.

SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed

at www.onsemi.com/site/pdf/Patent − Marking.pdf. S CILLC r eserves the r ight to make changes without f urther n otice to any product s herein. S CILLC makes n o warranty, represent ation

or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and

specifically disclaims any and all l iabilit y, i ncluding w it hout limitation special, consequential or incidental damages. “Typical” paramet ers w hich m ay be provided in SCILLC data sheets

and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each

customer application b y c ust omer’s technical e xperts. SCILLC does not c onvey a ny l icense u nder its patent r ight s n or the rights of o thers. SCILLC products a re n ot d esigned, i nt ended,

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the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or

unauthorized application, Buyer shall indemnify and hold SCILLC an d it s officers, employees, subsidiar ies, a ffiliates, and distributors harmless against all claims, costs, damages, and

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Phone: 81−3−5817−1050

NCP1397/D

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