This is information on a product in full production.
June 2012 Doc ID 11110 Rev 12 1/31
1
STM6321, STM6322, STM6821, STM6822,
STM6823, STM6824, STM6825
5-pin supervisor with watchdog timer and push-button reset
Datasheet production data
Features
Precision VCC monitoring of 5, 3.3, 3, or 2.5 V
power supplies
RST outputs (active low, push-pull or open
drain)
RST outputs (active high, push-pull)
Reset pulse width of 1.4 ms, 200 ms and
240 ms (typ.)
Watchdog timeout period of 1.6 s (typ.)
Manual reset input (MR)
Low supply current - 3 µA (typ.)
Guaranteed RST (RST) assertion down to
VCC = 1.0 V
Operating temperature: –40 to +85 °C
(industrial grade)
RoHS compliance
Lead-free components are compliant with the
RoHS directive
SOT23-5 (WY)
Table 1. Device summary
Part number Watchdog input Manual reset
input
Reset output
Active low
(push-pull)
Active high
(push-pull)
Active low
(open drain)
STM6321 ✔✔
STM6322 ✔✔
STM6821 ✔✔
STM6822 ✔✔
STM6823 ✔✔
STM6824 ✔✔
STM6825 ✔✔✔
www.st.com
Contents STM6321, STM6322, STM6821, STM6822, STM6823, STM6824, STM6825
2/31 Doc ID 11110 Rev 12
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.1 Active low, push-pull reset output (RST) - 6823/6824/6825 . . . . . . . . . . . 7
1.1.2 Active low, open drain reset output (RST) - STM6321/6322/6822 . . . . . . 7
1.1.3 Push-button reset input (MR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.4 Watchdog input (WDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.5 Active high reset output (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Open drain RST output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Push-button reset input (STM6322/6821/6822/6823/6825) . . . . . . . . . . . 11
2.4 Watchdog input (STM6321/6821/6822/6823/6824) . . . . . . . . . . . . . . . . . 11
2.5 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5.1 Watchdog input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5.2 Ensuring a valid reset output down to VCC = 0 V . . . . . . . . . . . . . . . . . . 11
2.6 Interfacing to microprocessors with bidirectional reset pins . . . . . . . . . . . 12
3 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
STM6321, STM6322, STM6821, STM6822, STM6823, STM6824, STM6825 List of tables
Doc ID 11110 Rev 12 3/31
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. DC and AC characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. SOT23-5 – 5-lead small outline transistor package mechanical data. . . . . . . . . . . . . . . . . 25
Table 8. Carrier tape dimensions for SOT23-5 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 9. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 10. Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 11. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
List of figures STM6321, STM6322, STM6821, STM6822, STM6823, STM6824, STM6825
4/31 Doc ID 11110 Rev 12
List of figures
Figure 1. Logic diagram (STM6821/6822/6823) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic diagram (STM6321/6322/6824/6825) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. STM6822/6823 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. STM6821 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. STM6322/6825 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 6. STM6321/6824 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 7. Block diagram (STM6821/6822/6823) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8. Block diagram (STM6321/6824) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 9. Block diagram (STM6322/6825) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 10. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 11. STM6321/6322/6822 open drain RST output with multiple supplies . . . . . . . . . . . . . . . . . 10
Figure 12. Ensuring RST valid to VCC = 0, (active low push-pull outputs) . . . . . . . . . . . . . . . . . . . . . . 12
Figure 13. Ensuring RST valid to VCC = 0, (active high, push-pull outputs) . . . . . . . . . . . . . . . . . . . . 12
Figure 14. Interfacing to microprocessors with bidirectional reset I/O . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 15. VCC-to-reset output delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 16. Supply current vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 17. MR-to-reset output delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 18. Normalized power-up trec vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 19. Normalized reset threshold voltage vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 20. Normalized power-up watchdog timeout period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 21. Voltage output low vs. ISINK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 22. Voltage output high vs. ISOURCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 23. Maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 24. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 25. MR timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 26. Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 27. SOT23-5 – 5-lead small outline transistor package mechanical drawing . . . . . . . . . . . . . . 25
Figure 28. Carrier tape for SOT23-5 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
STM6321, STM6322, STM6821, STM6822, STM6823, STM6824, STM6825 Description
Doc ID 11110 Rev 12 5/31
1 Description
The STM6xxx supervisors are self-contained devices which provide microprocessor
supervisory functions. A precision voltage reference and comparator monitors the VCC input
for an out-of-tolerance condition. When an invalid VCC condition occurs, the reset output
(RST) is forced low (or high in the case of RST). These devices also offer a watchdog timer
(except for STM6322/6825) and/or a push-button (MR) reset input.
These devices are available in a standard 5-pin SOT23 package.
Figure 1. Logic diagram (STM6821/6822/6823)
1. For STM6821 only.
Figure 2. Logic diagram (STM6321/6322/6824/6825)
1. For STM6321/6824.
Table 2. Signal names
Name Function
MR Push-button reset input
WDI Watchdog input
RST Active low reset output
RST Active high reset output
VCC Supply voltage
VSS Ground
AI09128
VCC
STM6XXX
VSS
RST (RST)(1)
WDI
MR
AI09129
V
CC
STM6XXX
V
SS
RST
RST
(WDI)
(1)
MR
Description STM6321, STM6322, STM6821, STM6822, STM6823, STM6824, STM6825
6/31 Doc ID 11110 Rev 12
Figure 3. STM6822/6823 SOT23-5 connections
1. Open drain for STM6822.
Figure 4. STM6821 SOT23-5 connections
1. Push-pull only.
Figure 5. STM6322/6825 SOT23-5 connections
1. Open drain for STM6322.
2. Push-pull only.
Figure 6. STM6321/6824 SOT23-5 connections
1. Open drain for STM6321.
2. Push-pull only.
1
WDI
RST
(1)
V
CC
MR
V
SS
AI09130a
SOT23-5
2
34
5
1
WDI
RST
(1)
V
CC
MR
V
SS
AI12285
SOT23-5
2
34
5
1V
CC
V
SS
AI09131a
SOT23-5
2
34
5
MR
RST
(1)
RST
(2)
1V
CC
V
SS
AI12286
SOT23-5
2
34
5
WDI
RST
(1)
RST
(2)
STM6321, STM6322, STM6821, STM6822, STM6823, STM6824, STM6825 Description
Doc ID 11110 Rev 12 7/31
1.1 Pin descriptions
1.1.1 Active low, push-pull reset output (RST) - 6823/6824/6825
Pulses low when triggered, and stays low whenever VCC is below the reset threshold or
when MR is a logic low. It remains low for trec after either VCC rises above the reset
threshold, the watchdog triggers a reset, or MR goes from low to high.
1.1.2 Active low, open drain reset output (RST) - STM6321/6322/6822
Pulses low when triggered, and stays low whenever VCC is below the reset threshold or
when MR is a logic low. It remains low for trec after either VCC rises above the reset
threshold, the watchdog triggers a reset, or MR goes from low to high. Connect a pull-up
resistor to supply voltage.
1.1.3 Push-button reset input (MR)
A logic low on MR asserts the reset output. Reset remains asserted as long as MR is low
and for trec after MR returns high. This active low input has an internal 52 kΩ pull-up. It can
be driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if
unused.
1.1.4 Watchdog input (WDI)
If WDI remains high or low for at least 1.6 s, the internal watchdog timer expires and reset is
asserted. The internal watchdog timer clears while reset is asserted or when WDI sees
a rising or falling edge. The watchdog function CAN be disabled if WDI is left unconnected
or is connected to a tristate buffer output.
1.1.5 Active high reset output (RST)
Active high, push-pull reset output; inverse of RST.
Table 3. Pin functions
Pin
Name Function
STM6822
STM6823 STM6821 STM6321
STM6824
STM6322
STM6825
1—1 1RST
Active low reset output
334MR
Push-button reset input
4 4 4 WDI Watchdog Input
1 3 3 RST Active high reset output
5555V
CC Supply voltage
2222V
SS Ground
Description STM6321, STM6322, STM6821, STM6822, STM6823, STM6824, STM6825
8/31 Doc ID 11110 Rev 12
Figure 7. Block diagram (STM6821/6822/6823)
1. Push-pull for STM6823, open drain for STM6822.
2. Active high (push-pull) for STM6821.
Figure 8. Block diagram (STM6321/6824)
3. Active low (open drain) for STM6321, active low (push-pull) for STM6824.
4. Push-pull only.
Figure 9. Block diagram (STM6322/6825)
1. Active low (open drain) for STM6322, active low (push-pull) for STM6825.
2. Push-pull only.
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STM6321, STM6322, STM6821, STM6822, STM6823, STM6824, STM6825 Description
Doc ID 11110 Rev 12 9/31
Figure 10. Hardware hookup
1. For STM6321/6821/6822/6823/6824.
2. For STM6322/6821/6822/6823/6825.
3. For STM6821/ (RST output only).
4. For STM6321/6322/6824/6825 (both RST and RST outputs).
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Operation STM6321, STM6322, STM6821, STM6822, STM6823, STM6824, STM6825
10/31 Doc ID 11110 Rev 12
2 Operation
2.1 Reset output
The STM6xxx supervisor asserts a reset signal to the MCU whenever VCC goes below the
reset threshold (VRST), a watchdog timeout occurs, or when the push-button reset input
(MR) is taken low. Reset is guaranteed valid for VCC < VRST down to VCC =1 V for
TA = 0 to 85 °C.
During power-up, once VCC exceeds the reset threshold an internal timer keeps reset low for
the reset timeout period, trec. After this interval reset is de-asserted.
Each time RST is asserted, it stays low for at least the reset timeout period (trec). Any time
VCC goes below the reset threshold the internal timer clears. The reset timer starts when
VCC returns above the reset threshold.
2.2 Open drain RST output
The STM6321/6322/6822 have an active low, open drain reset output. This output structure
will sink current when RST is asserted. Connect a pull-up resistor from RST to any supply
voltage up to 6 V (see Figure 11). Select a resistor value large enough to register a logic
low, and small enough to register a logic high while supplying all input current and leakage
paths connected to the reset output line. A 10 kΩ pull-up resistor is sufficient in most
applications.
Figure 11. STM6321/6322/6822 open drain RST output with multiple supplies
1. STM6322/6822.
2. STM6321/6822.
3. STM6321/6322.
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STM6321, STM6322, STM6821, STM6822, STM6823, STM6824, STM6825 Operation
Doc ID 11110 Rev 12 11/31
2.3 Push-button reset input (STM6322/6821/6822/6823/6825)
A logic low on MR asserts reset. Reset remains asserted while MR is low, and for trec (see
Figure 25 on page 19) after it returns high. The MR input has an internal 52 kΩ pull-up
resistor, allowing it to be left open if not used. This input can be driven with TTL/CMOS-logic
levels or with open drain/collector outputs. Connect a normally open momentary switch from
MR to GND to create a manual reset function; external debounce circuitry is not required. If
MR is driven from long cables or the device is used in a noisy environment, connect a 0.1 µF
capacitor from MR to GND to provide additional noise immunity. MR may float, or be tied to
VCC when not used.
2.4 Watchdog input (STM6321/6821/6822/6823/6824)
The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not
toggle the Watchdog Input (WDI) within tWD (1.6 sec), the reset is asserted. The internal
watchdog timer is cleared by either:
1. a reset pulse, or
2. by toggling WDI (high to low or low to high), which can detect pulses as short as 50 ns.
The timer remains cleared and does not count for as long as reset is asserted. As soon as
reset is released, the timer starts counting.
Note: The watchdog function may be disabled by floating WDI or tristating the driver connected to
WDI. When tristated or disconnected, the maximum allowable leakage current is 10 µA and
the maximum allowable load capacitance is 200 pF.
2.5 Applications information
2.5.1 Watchdog input current
The WDI input is internally driven through a buffer and series resistor from the watchdog
counter. For minimum watchdog input current (minimum overall power consumption), leave
WDI low for the majority of the watchdog timeout period. When high, WDI can draw as much
as 160 µA. Pulsing WDI high at a low duty cycle will reduce the effect of the large input
current. When WDI is left unconnected, the watchdog timer is serviced within the watchdog
timeout period by a low-high-low pulse from the counter chain.
2.5.2 Ensuring a valid reset output down to VCC =0 V
The STM6xxx supervisors are guaranteed to operate properly down to VCC = 1 V. In
applications that require valid reset levels down to VCC = 0, a pull-down resistor to active low
outputs (push/pull only, see Figure 12 on page 12) and a pull-up resistor to active high
outputs (push/pull only, see Figure 13 on page 12) will ensure that the reset line is valid
while the reset output can no longer sink or source current. This scheme does not work with
the open drain outputs of the STM6321/6322/6822.
The resistor value used is not critical, but it must be large enough not to load the reset
output when VCC is above the reset threshold. For most applications, 100 kΩ is adequate.
Operation STM6321, STM6322, STM6821, STM6822, STM6823, STM6824, STM6825
12/31 Doc ID 11110 Rev 12
Figure 12. Ensuring RST valid to VCC = 0, (active low push-pull outputs)
Figure 13. Ensuring RST valid to VCC = 0, (active high, push-pull outputs)
1. This configuration does not work on open drain outputs of the STM6321/6322/6822.
2.6 Interfacing to microprocessors with bidirectional reset pins
Microprocessors with bidirectional reset pins can contend with the STM6321
/
6322
/
6821
/
6822
/
6823
/
6824
/
6825 reset output. For example, if the reset output is driven high and the
microprocessor wants to pull it low, signal contention will result. To prevent this from
occurring, connect a 4.7 kΩ resistor between the reset output and the microprocessor’s
reset I/O as in Figure 14.
Figure 14. Interfacing to microprocessors with bidirectional reset I/O
AI09138
STM6XXX
RSTGND
VCC
VCC
R1
AI09139
STM6XXX
RST
GND
VCC
VCC
R1
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STM6321, STM6322, STM6821, STM6822, STM6823, STM6824, STM6825 Typical operating charac-
Doc ID 11110 Rev 12 13/31
3 Typical operating characteristics
Figure 15. VCC-to-reset output delay vs. temperature
Figure 16. Supply current vs. temperature
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Typical operating characteristics STM6321, STM6322, STM6821, STM6822, STM6823, STM6824,
14/31 Doc ID 11110 Rev 12
Figure 17. MR-to-reset output delay vs. temperature
Figure 18. Normalized power-up trec vs. temperature
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STM6321, STM6322, STM6821, STM6822, STM6823, STM6824, STM6825 Typical operating charac-
Doc ID 11110 Rev 12 15/31
Figure 19. Normalized reset threshold voltage vs. temperature
Figure 20. Normalized power-up watchdog timeout period
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Typical operating characteristics STM6321, STM6322, STM6821, STM6822, STM6823, STM6824,
16/31 Doc ID 11110 Rev 12
Figure 21. Voltage output low vs. ISINK
Figure 22. Voltage output high vs. ISOURCE
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STM6321, STM6322, STM6821, STM6822, STM6823, STM6824, STM6825 Typical operating charac-
Doc ID 11110 Rev 12 17/31
Figure 23. Maximum transient duration vs. reset threshold overdrive
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3
:
,
Maximum ratings STM6321, STM6322, STM6821, STM6822, STM6823, STM6824, STM6825
18/31 Doc ID 11110 Rev 12
4 Maximum ratings
Stressing the device above the rating listed in Table 4: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in Table 5: Operating and AC
measurement conditions of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability. Refer also to the
STMicroelectronicsSURE program and other relevant quality documents.
Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
TSTG Storage temperature (VCC off) –55 to 150 °C
TSLD(1)
1. Reflo
w at peak temperature of 260 °C (total thermal budget not to exceed 245 °C for greater than 30 seconds)
.
Lead solder temperature for 10 seconds 260 °C
VIO Input or output voltage –0.3 to VCC + 0.3 V
VCC Supply voltage –0.3 to 7.0 V
IOOutput current 20 mA
PDPower dissipation 320 mW
STM6321, STM6322, STM6821, STM6822, STM6823, STM6824, STM6825 DC and AC parameters
Doc ID 11110 Rev 12 19/31
5 DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in Table 6: DC and AC characteristic, are
derived from tests performed under the measurement conditions summarized in Table 5:
Operating and AC measurement conditions. Designers should check that the operating
conditions in their circuit match the operating conditions when relying on the quoted
parameters.
Figure 24. AC testing input/output waveforms
Figure 25. MR timing waveform
1. RST for STM6322/6821/6825.
Table 5. Operating and AC measurement conditions
Parameter STM6xxx Unit
VCC supply voltage 1.0 to 5.5 V
Ambient operating temperature (TA) –40 to 85 °C
Input rise and fall times
5ns
Input pulse voltages 0.2 to 0.8 VCC V
Input and output timing ref. voltages 0.3 to 0.7 VCC V
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DC and AC parameters STM6321, STM6322, STM6821, STM6822, STM6823, STM6824, STM6825
20/31 Doc ID 11110 Rev 12
Figure 26. Watchdog timing
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STM6321, STM6322, STM6821, STM6822, STM6823, STM6824, STM6825 Package mechanical data
Doc ID 11110 Rev 12 21/31
6 Package mechanical data
Table 6. DC and AC characteristic
Sym-
bol
Alter-
native Description Test condition(1) Min. Typ. Max. Unit
VCC Operating voltage 1.2 (2) 5.5 V
ICC
VCC supply current
(MR and WDI unconnected)
T/S/R/Z/Y (VCC < 3.6 V) 4 12 µA
L/M (VCC < 5.5 V) 6 17 µA
VCC supply current
(MR unconnected;
STM6322/6825)
T/S/R/Z/Y (VCC < 3.6 V) 3 8 µA
L/M (VCC < 5.5 V) 3 12 µA
ILI
Input leakage current 0 V = VIN = VCC –1 +1 µA
Input leakage current
(WDI)(3)
WDI = VCC, time average 120 160 µA
WDI = GND, time average –20 –15 µA
ILO
Open drain reset output
leakage current
VCC > VRST
,
Reset not asserted –1 +1 µA
VIH Input high voltage (MR)VRST > 4.0 V 2.0 V
VRST < 4.0 V 0.7 VCC V
VIH Input high voltage (WDI)(4) VRST (max.) < VCC < 5.5 V 0.7 VCC V
VIL Input low voltage (MR)
VRST > 4.0 V 0.8 V
VRST < 4.0 V 0.3 VCC V
VIL Input low voltage (WDI)(4) VRST (max.) < VCC < 5.5 V 0.3 VCC V
VOL
Output low voltage (RST;
push-pull or open drain)
VCC 1.0 V, ISINK = 50 µA,
Reset asserted 0.3 V
VCC 1.2 V, ISINK = 100 µA,
Reset asserted 0.3 V
VCC 2.7 V, ISINK = 1.2 mA,
Reset asserted 0.3 V
VCC 4.5 V, ISINK = 3.2 mA,
Reset asserted 0.4 V
Output low voltage (RST;
push-pull only)
VCC 2.7 V, ISINK = 1.2 mA,
Reset not asserted 0.3 V
VCC 4.5 V, ISINK = 3.2 mA,
Reset not asserted 0.4 V
Package mechanical data STM6321, STM6322, STM6821, STM6822, STM6823, STM6824, STM6825
22/31 Doc ID 11110 Rev 12
VOH
Output high voltage (RST)
VCC 2.7 V, ISOURCE = 500 µA,
Reset not asserted 0.8 VCC V
VCC 4.5 V, ISOURCE = 800 µA
, Reset not asserted 0.8 VCC V
Output high voltage (RST)
VCC 1.0 V, ISOURCE = 1 µA,
Reset asserted (0 °C to 85 °C) 0.8 VCC V
VCC 1.5 V, ISOURCE = 100 µA,
Reset asserted 0.8 VCC V
VCC 2.55 V, ISOURCE = 500 µA,
Reset asserted 0.8 VCC V
VCC 4.25 V, ISOURCE = 800 µA,
Reset asserted 0.8 VCC V
Reset thresholds
VRST(5) Reset threshold
STM6xxxL 25 °C 4.561 4.630 4.699 V
–40 to 85 °C 4.514 4.746 V
STM6xxxM 25 °C 4.314 4.390 4.446 V
–40 to 85 °C 4.270 4.490 V
STM6xxxT
25 °C 3.040 3.080 3.110 V
–40 to 85 °C 3.000 3.150 V
STM6xxxS 25 °C 2.890 2.930 2.960 V
–40 to 85 °C 2.857 3.000 V
STM6xxxR 25 °C 2.590 2.630 2.660 V
–40 to 85 °C 2.564 2.696 V
STM6xxxZ
25 °C 2.266 2.300 2.335 V
–40 to 85 °C 2.243 2.358 V
STM6xxxY 25 °C 1.970 2.000 2.030 V
–40 to 85 °C 1.950 2.050 V
Reset threshold hysteresis L/M versions 10 mV
T/S/R/Z/Y versions 5 mV
VCC to RST delay
(VRST – VCC = 100 mV, VCC
falling at 1 mV/µs)
20 µs
trec (6) Reset pulse width
A11.42ms
Blank 140 200 280 ms
J 240 360 480 ms
Table 6. DC and AC characteristic (continued)
Sym-
bol
Alter-
native Description Test condition(1) Min. Typ. Max. Unit
STM6321, STM6322, STM6821, STM6822, STM6823, STM6824, STM6825 Package mechanical data
Doc ID 11110 Rev 12 23/31
Reset threshold
temperature coefficient 40 ppm/
C
Push-button reset input
tMLMH tMR MR pulse width 1 µs
tMLRL tMRD MR to RST output delay 500 ns
MR glitch immunity 100 ns
MR pull-up resistor 35 52 75 kΩ
Watchdog timer
tWD (6) Watchdog timeout period 1.12 1.60 2.24 s
WDI pulse width(7) VCC 3.0 V 50 ns
1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 4.5 to 5.5 V for “L/M” versions; VCC = 2.7 to 3.6 V for
“T/S/R” versions; and VCC = 1.2 to 2.75 V for “Z/Y” version (except where noted).
2. VCC (min.) = 1.0 V for TA = 0 to +85 °C.
3. WDI input is designed to be driven by a three-state output device. To float WDI, the “high-impedance mode” of the output
device must have a maximum leakage current of 10 µA and a maximum output capacitance of 200 pF. The output device
must also be able to source and sink at least 200 µA when active.
4. WDI is internally serviced within the watchdog period if WDI is left unconnected.
5. The leakage current measured on the RST pin is tested with the reset asserted (output high impedance).
6. Other trec and watchdog timings are offered. Minimum order quantities may apply. Contact local sales office for availability.
7. For VCC < 3.0 V, tWD(min.) = 100 ns.
Table 6. DC and AC characteristic (continued)
Sym-
bol
Alter-
native Description Test condition(1) Min. Typ. Max. Unit
Package mechanical data STM6321, STM6322, STM6821, STM6822, STM6823, STM6824, STM6825
24/31 Doc ID 11110 Rev 12
7 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
STM6321, STM6322, STM6821, STM6822, STM6823, STM6824, STM6825 Package mechanical data
Doc ID 11110 Rev 12 25/31
Figure 27. SOT23-5 – 5-lead small outline transistor package mechanical drawing
1. Drawing is not to scale.