FEATURES n n n n n n n n n n n n n n n n n Complete Switch Mode Power Supply Wide Input Voltage Range: 4.5V to 28V 12A DC Typical, 14A Peak Output Current 0.6V to 5V Output Voltage Output Voltage Tracking and Margining Parallel Multiple Module(R) Regulators for Current Sharing Differential Remote Sensing for Precision Regulation PLL Frequency Synchronization 1.5% Regulation Current Foldback Protection (Disabled at Start-Up) RoHS Compliant with Pb-Free Finish, Gold Finish LGA (e4) or SAC 305 BGA (e1) Ultrafast Transient Response Current Mode Control Up to 95% Efficiency at 5VIN, 3.3VOUT Programmable Soft-Start Output Overvoltage Protection Small Footprint, Low Profile (15mm x 15mm x 2.82mm) Surface Mount LGA and (15mm x 15mm x 3.42mm) BGA Packages APPLICATIONS Telecom and Networking Equipment Servers n Industrial Equipment n Point of Load Regulation n LTM4601HV 12A 28VIN DC/DC Module Regulator with PLL, Output Tracking and Margining DESCRIPTION The LTM(R)4601HV is a complete 12A step-down switch mode DC/DC power supply with onboard switching controller, MOSFETs, inductor and all support components. The Module regulator is housed in small surface mount 15mm x 15mm x 2.82mm LGA and 15mm x 15mm x 3.42mm BGA packages. Operating over an input voltage range of 4.5V to 28V, the LTM4601HV supports an output voltage range of 0.6V to 5V as well as output voltage tracking and margining. The high efficiency design delivers 12A continuous current (14A peak). Only bulk input and output capacitors are needed to complete the design. The low profile and light weight package easily mounts in unused space on the back side of PC boards for high density point of load regulation. The Module regulator can be synchronized with an external clock for reducing undesirable frequency harmonics and allows PolyPhase(R) operation for high load currents. A high switching frequency and adaptive on-time current mode architecture deliver a very fast transient response to line and load changes without sacrificing stability. An onboard differential remote sense amplifier can be used to accurately regulate an output voltage independent of load current. L, LT, LTC, LTM, Linear Technology, the Linear logo, Module and PolyPhase are registered trademarks and LTpowerCAD is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611, 6677210. n TYPICAL APPLICATION Efficiency and Power Loss vs Load Current 2.5V/12A Power Supply with 4.5V to 28V Input 95 CLOCK SYNC TRACK/SS CONTROL ON/OFF CIN R1 392k 5% MARGIN RUN COMP INTVCC DRVCC MPGM SGND PLLIN TRACK/SS VOUT LTM4601HV PGND VFB MARG0 MARG1 VOUT 2.5V 12A 100pF MARGIN CONTROL COUT VOUT_LCL DIFFVOUT VOSNS+ VOSNS- fSET 5 85 24VIN 80 70 4601HV TA01a 3 24VIN 65 12VIN 60 2 POWER LOSS 55 RSET 19.1k 4 EFFICIENCY 75 1 50 45 POWER LOSS (W) VIN PGOOD 6 12VIN 90 EFFICIENCY (%) VIN 4.5V TO 28V 0 2 8 6 4 10 LOAD CURRENT (A) 12 14 0 4601HV TA01b 4601hvfb 1 LTM4601HV ABSOLUTE MAXIMUM RATINGS (Note 1) INTVCC, DRVCC, VOUT_LCL, VOUT (VOUT 3.3V with Remote Sense Amp)..................................... -0.3V to 6V PLLIN, TRACK/SS, MPGM, MARG0, MARG1, PGOOD, fSET...............................-0.3V to INTVCC + 0.3V RUN.............................................................. -0.3V to 5V VFB, COMP................................................. -0.3V to 2.7V VIN.............................................................. -0.3V to 28V VOSNS+, VOSNS -...........................-0.3V to INTVCC + 0.3V Operating Temperature Range (Note 2)....-40C to 85C Junction Temperature............................................ 125C Storage Temperature Range................... -55C to 125C fSET VIN MARG0 MARG1 MARG1 DRVCC DRVCC VFB PGND PGOOD PGOOD SGND SGND VOSNS+ VOSNS+ VOUT_LCL DIFFVOUT VOUT VOUT_LCL - VOSNS- VOSNS BGA PACKAGE 118-LEAD (15mm x 15mm x 3.42mm) LGA PACKAGE 118-LEAD (15mm x 15mm x 2.82mm) TJMAX = 125C, JA = 15C/W, JC = 6C/W, JA DERIVED FROM 95mm x 76mm PCB WITH 4 LAYERS WEIGHT = 1.7g MPGM COMP RUN fSET MARG0 DIFFVOUT VOUT TRACK/SS VIN VFB PGND PLLIN INTVCC MPGM COMP TOP VIEW RUN PLLIN INTVCC TOP VIEW TRACK/SS PIN CONFIGURATION TJMAX = 125C, JA = 15.5C/W, JC = 6.5C/W, JA DERIVED FROM 95mm x 76mm PCB WITH 4 LAYERS WEIGHT = 1.9g ORDER INFORMATION LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTM4601HVEV#PBF LTM4601HVEV#PBF LTM4601HVV 118-Lead (15mm x 15mm x 2.82mm) LGA -40C to 85C LTM4601HVIV#PBF LTM4601HVIV#PBF LTM4601HVV 118-Lead (15mm x 15mm x 2.82mm) LGA -40C to 85C LTM4601HVEY#PBF LTM4601HVEY#PBF LTM4601HVY 118-Lead (15mm x 15mm x 3.42mm) BGA -40C to 85C LTM4601HVIY#PBF LTM4601HVIY#PBF LTM4601HVY 118-Lead (15mm x 15mm x 3.42mm) BGA -40C to 85C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear.com/packaging/ 2 4601hvfb LTM4601HV ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the -40C to 85C temperature range (Note 2), otherwise specifications are at TA = 25C, VIN = 12V, per typical application (front page) configuration, RSET = 40.2k. SYMBOL PARAMETER VIN(DC) Input DC Voltage VOUT(DC) Output Voltage (With Remote Sense Amp) CONDITIONS CIN = 10F x3, COUT = 200F, RSET = 40.2k VIN = 12V, VOUT = 1.5V, IOUT = 0 MIN l 4.5 l 1.478 TYP MAX UNITS 28 V 1.5 1.522 V 4 V Input Specifications VIN(UVLO) Undervoltage Lockout Threshold IOUT = 0A 3.2 IINRUSH(VIN) Input Inrush Current at Startup IOUT = 0A. VOUT = 1.5V VIN = 5V VIN = 12V 0.6 0.7 A A IQ(VIN,NO LOAD) Input Supply Bias Current VIN = 12V, No Switching VIN = 12V, VOUT = 1.5V, Switching Continuous VIN = 5V, No Switching VIN = 5V, VOUT = 1.5V, Switching Continuous Shutdown, RUN = 0, VIN = 12V 3.8 38 2.5 42 22 mA mA mA mA A IS(VIN) Input Supply Current VIN = 12V, VOUT = 1.5V, IOUT = 12A VIN = 12V, VOUT = 3.3V, IOUT = 12A VIN = 5V, VOUT = 1.5V, IOUT = 12A 1.81 3.63 4.29 A A A INTVCC VIN = 12V, RUN > 2V No Load 4.7 5 5.3 V 12 A Output Specifications IOUTDC Output Continuous Current Range VIN = 12V, VOUT = 1.5V (Note 5) VOUT(LINE) VOUT Line Regulation Accuracy VOUT = 1.5V, IOUT = 0A, VIN from 4.5V to 28V l 0.3 % VOUT(LOAD) VOUT Load Regulation Accuracy VOUT = 1.5V, IOUT = 0A to 12A, with RSA (Note 5) VIN = 5V VIN = 12V l l 0.25 0.25 % % VOUT(AC) Output Ripple Voltage IOUT = 0A, COUT = 2x 100F X5R Ceramic VIN = 12V, VOUT = 1.5V VIN = 5V, VOUT = 1.5V 20 18 mVP-P mVP-P fS Output Ripple Voltage Frequency IOUT = 5A, VIN = 12V, VOUT = 1.5V 850 kHz VOUT(START) Turn-On Overshoot COUT = 200F, VOUT = 1.5V, IOUT = 0A, TRACK/SS = 10nF VIN = 12V VIN = 5V 20 20 mV mV COUT = 200F, VOUT = 1.5V, TRACK/SS = Open, IOUT = 1A Resistive Load VIN = 12V VIN = 5V 0.5 0.5 ms ms Load: 0% to 50% to 0% of Full Load, COUT = 2 x 22F Ceramic, 470F 4V Sanyo POSCAP VIN = 12V VIN = 5V 35 35 mV mV 25 s 17 17 A A tSTART VOUTLS Turn-On Time Peak Deviation for Dynamic Load tSETTLE Settling Time for Dynamic Load Step Load: 0% to 50%, or 50% to 0% of Full Load VIN = 12V IOUTPK Output Current Limit COUT = 200F Ceramic VIN = 12V, VOUT = 1.5V VIN = 5V, VOUT = 1.5V 0 4601hvfb 3 LTM4601HV ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the -40C to 85C temperature range (Note 2), otherwise specifications are at TA = 25C, VIN = 12V, per typical application (front page) configuration, RSET = 40.2k. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Remote Sense Amp (Note 3) VOSNS+, VOSNS- Common Mode Input Voltage Range VIN = 12V, RUN > 2V CM Range INTVCC - 1 V 0 INTVCC - 1 V DIFFVOUT Range Output Voltage Range VOS Input Offset Voltage Magnitude AV Differential Gain 1 V/V GBP Gain Bandwidth Product 3 MHz SR Slew Rate 2 V/s 20 kW 100 dB RIN Input Resistance CMRR Common Mode Rejection Mode VIN = 12V, DIFFVOUT Load = 100k 0 1.25 + to GND VOSNS mV Control Stage VFB Error Amplifier Input Voltage Accuracy IOUT = 0A, VOUT = 1.5V VRUN RUN Pin On/Off Threshold ITRACK/SS Soft-Start Charging Current VTRACK/SS = 0V tON(MIN) Minimum On Time (Note 4) tOFF(MIN) Minimum Off Time (Note 4) RPLLIN PLLIN Input Resistance IDRVCC Current into DRVCC Pin l 0.594 0.6 0.606 V 1 1.5 1.9 V -1.0 -1.5 -2.0 A 50 100 ns 250 400 ns 50 VOUT = 1.5V, IOUT = 1A, DRVCC = 5V 60.098 k 18 25 mA 60.4 60.702 k RFBHI Resistor Between VOUT_LCL and VFB VMPGM Margin Reference Voltage 1.18 V VMARG0, VMARG1 MARG0, MARG1 Voltage Thresholds 1.4 V PGOOD Output VFBH PGOOD Upper Threshold VFB Rising 7 10 13 % VFBL PGOOD Lower Threshold VFB Falling -7 -10 -13 % VFB(HYS) PGOOD Hysteresis VFB Returning Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. 4 1.5 % Note 2: The LTM4601HV is tested under pulsed load conditions such that TJ TA. The LTM4601HVE is guaranteed to meet performance specifications from 0C to 85C. Specifications over the -40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4601HVI is guaranteed over the -40C to 85C temperature range. Note 3: Remote sense amplifier recommended for 3.3V output. Note 4: 100% tested at wafer level only. Note 5: See output current derating curves for different VIN, VOUT and TA. 4601hvfb LTM4601HV TYPICAL PERFORMANCE CHARACTERISTICS 100 100 95 EFFICIENCY (%) EFFICIENCY (%) 90 85 80 75 0.6VOUT 1.2VOUT 1.5VOUT 2.5VOUT 3.3VOUT 70 65 60 0 5 95 95 90 90 85 85 80 80 75 70 0.6VOUT 1.2VOUT 1.5VOUT 2.5VOUT 3.3VOUT 5VOUT 65 60 55 10 50 15 Efficiency vs Load Current with 24VIN Efficiency vs Load Current with 12VIN EFFICIENCY (%) Efficiency vs Load Current with 5VIN (See Figures 19 and 20 for all curves) 0 LOAD CURRENT (A) 75 70 65 60 50 10 5 LOAD CURRENT (A) 4601HV G01 15 45 10 5 LOAD CURRENT (A) 0 4601HV G02 1.2V Transient Response 1.5V Transient Response 1.8V Transient Response VOUT 50mV/DIV VOUT 50mV/DIV 0A TO 6A LOAD STEP 0A TO 6A LOAD STEP 0A TO 6A LOAD STEP 4601HV G04 20s/DIV 1.5V AT 6A/s LOAD STEP COUT = 3 * 22F 6.3V CERAMICS 470F 4V SANYO POSCAP C3 = 100pF 2.5V Transient Response 4601HV G05 20s/DIV 1.8V AT 6A/s LOAD STEP COUT = 3 * 22F 6.3V CERAMICS 470F 4V SANYO POSCAP C3 = 100pF 4601HV G06 3.3V Transient Response VOUT 50mV/DIV VOUT 50mV/DIV 0A TO 6A LOAD STEP 0A TO 6A LOAD STEP 20s/DIV 2.5V AT 6A/s LOAD STEP COUT = 3 * 22F 6.3V CERAMICS 470F 4V SANYO POSCAP C3 = 100pF 15 4601HV G03 VOUT 50mV/DIV 20s/DIV 1.2V AT 6A/s LOAD STEP COUT = 3 * 22F 6.3V CERAMICS 470F 4V SANYO POSCAP C3 = 100pF 1.5VOUT 2.5VOUT 3.3VOUT 5.0VOUT 55 4601HV G07 20s/DIV 3.3V AT 6A/s LOAD STEP COUT = 3 * 22F 6.3V CERAMICS 470F 4V SANYO POSCAP C3 = 100pF 4601 G08 4601hvfb 5 LTM4601HV TYPICAL PERFORMANCE CHARACTERISTICS (See Figures 19 and 20 for all curves) Start-Up, IOUT = 12A (Resistive Load) Start-Up, IOUT = 0A VOUT 0.5V/DIV VOUT 0.5V/DIV IIN 1A/DIV IIN 0.5A/DIV 5ms/DIV VIN = 12V VOUT = 1.5V COUT = 470F, 3 x 22F SOFT-START = 10nF 2ms/DIV VIN = 12V VOUT = 1.5V COUT = 470F, 3 x 22F SOFT-START = 10nF 4601HV G09 VIN to VOUT Step-Down Ratio Track, IOUT = 12A 5.5 3.3V OUTPUT WITH 130k FROM VOUT TO ION 5.0 OUTPUT VOLTAGE (V) 4.5 5V OUTPUT WITH 100k RESISTOR ADDED FROM fSET TO GND 4.0 3.5 3.0 2.0 5V OUTPUT WITH NO RESISTOR ADDED FROM fSET TO GND 1.5 2.5V OUTPUT 1.0 1.8V OUTPUT 0.5 1.5V OUTPUT 2.5 0 4601HV G10 TRACK/SS 0.5V/DIV VFB 0.5V/DIV VOUT 1V/DIV 2ms/DIV VIN = 12V VOUT = 1.5V COUT = 470F, 3 x 22F SOFT-START = 10nF 4601HV G12 1.2V OUTPUT 0 2 4 6 8 10 12 14 16 18 20 22 24 INPUT VOLTAGE (V) 4601HV G11 Short-Circuit Protection, IOUT = 0A VOUT 0.5V/DIV VOUT 0.5V/DIV IIN 1A/DIV IIN 1A/DIV 50s/DIV VIN = 12V VOUT = 1.5V COUT = 470F, 3 x 22F SOFT-START = 10nF 6 Short-Circuit Protection, IOUT = 12A 4601HV G13 50s/DIV VIN = 12V VOUT = 1.5V COUT = 470F, 3 x 22F SOFT-START = 10nF 4601HV G14 4601hvfb LTM4601HV PIN FUNCTIONS (See Package Description for Pin Assignment) VIN (Bank 1): Power Input Pins. Apply input voltage between these pins and PGND pins. Recommend placing input decoupling capacitance directly between VIN pins and PGND pins. VOUT (Bank 3): Power Output Pins. Apply output load between these pins and PGND pins. Recommend placing output decoupling capacitance directly between these pins and PGND pins. See Figure 17. PGND (Bank 2): Power ground pins for both input and output returns. VOSNS- (Pin M12): (-) Input to the Remote Sense Amplifier. This pin connects to the ground remote sense point. The remote sense amplifier is used for VOUT 3.3V. Tie to INTVCC if not used. VOSNS+ (Pin J12): (+) Input to the Remote Sense Amplifier. This pin connects to the output remote sense point. The remote sense amplifier is used for VOUT 3.3V. Tie to ground if not used. DIFFVOUT (Pin K12): Output of the Remote Sense Amplifier. This pin connects to the VOUT_LCL pin. Leave floating if remote sense amplifier is not used. DRVCC (Pin E12): This pin normally connects to INTVCC for powering the internal MOSFET drivers. This pin can be biased up to 6V from an external supply with about 50mA capability, or an external circuit as shown in Figure 18. This improves efficiency at the higher input voltages by reducing power dissipation in the module. TRACK/SS (Pin A9): Output Voltage Tracking and SoftStart Pin. When the module is configured as a master output, then a soft-start capacitor is placed on this pin to ground to control the master ramp rate. A soft-start capacitor can be used for soft-start turn on of a stand alone regulator. Slave operation is performed by putting a resistor divider from the master output to ground, and connecting the center point of the divider to this pin. See the Applications Information section. MPGM (Pin A12): Programmable Margining Input. A resistor from this pin to ground sets a current that is equal to 1.18V/R. This current multiplied by 10k will equal a value in millivolts that is a percentage of the 0.6V reference voltage. See Applications Information. To parallel LTM4601HVs, each requires an individual MPGM resistor. Do not tie MPGM pins together. fSET (Pin B12): Frequency Set Internally to 850kHz. An external resistor can be placed from this pin to ground to increase frequency. See the Applications Information section for frequency adjustment. VFB (Pin F12): The Negative Input of the Error Amplifier. Internally, this pin is connected to VOUT_LCL pin with a 60.4k precision resistor. Different output voltages can be programmed with an additional resistor between VFB and SGND pins. See the Applications Information section. INTVCC (Pin A7): This pin is for additional decoupling of the 5V internal regulator. MARG0 (Pin C12): This pin is the LSB logic input for the margining function. Together with the MARG1 pin it will determine if margin high, margin low or no margin state is applied. The pin has an internal pull-down resistor of 50k. See the Applications Information section. PLLIN (Pin A8): External Clock Synchronization Input to the Phase Detector. This pin is internally terminated to SGND with a 50k resistor. Apply a clock with a high level above 2V and below INTVCC. See the Applications Information section. MARG1 (Pin D12): This pin is the MSB logic input for the margining function. Together with the MARG0 pin it will determine if margin high, margin low or no margin state is applied. The pin has an internal pull-down resistor of 50k. See the Applications Information section. 4601hvfb 7 LTM4601HV PIN FUNCTIONS (See Package Description for Pin Assignment) SGND (Pin H12): Signal Ground. This pin connects to PGND at output capacitor point. See Figure 17. COMP (Pin A11): Current Control Threshold and Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. The voltage ranges from 0V to 2.4V with 0.7V corresponding to zero sense voltage (zero current). PGOOD (Pin G12): Output Voltage Power Good Indicator. Open-drain logic output that is pulled to ground when the output voltage is not within 10% of the regulation point, after a 25s power bad mask timer expires. 8 RUN (Pin A10): Run Control Pin. A voltage above 1.9V will turn on the module, and when below 1V, will turn off the module. A programmable UVLO function can be accomplished by connecting to a resistor divider from VIN to ground. See Figure 1. This pin has a 5.1V Zener to ground. Maximum pin voltage is 5V. Limit current into the RUN pin to less than 1mA. VOUT_LCL (Pin L12): VOUT connects directly to this pin to bypass the remote sense amplifier, or DIFFVOUT connects to this pin when remote sense amplifier is used. 4601hvfb LTM4601HV SIMPLIFIED BLOCK DIAGRAM VOUT_LCL VIN R1 UVLO FUNCTION >1.9V = ON <1V = OFF MAX = 5V VOUT 1M RUN PGOOD R2 5.1V ZENER COMP 1.5F VIN 4.5V TO 28V + CIN 60.4k INTERNAL COMP Q1 POWER CONTROL SGND 0.47H VOUT 2.5V 12A MARG1 MARG0 22F VFB 50k 50k Q2 fSET MPGM 10k TRACK/SS CSS COUT 2.2 39.2k PLLIN 50k 4.7F + PGND INTVCC + - RSET 19.1k VOSNS- 10k 10k VOSNS+ 10k INTVCC DIFFVOUT DRVCC 4601HV F01 = SGND = PGND Figure 1. Simplified LTM4601HV Block Diagram T DECOUPLING REQUIREMENTS A = 25C, VIN = 12V. Use Figure 1 configuration. SYMBOL PARAMETER CONDITIONS MIN TYP CIN External Input Capacitor Requirement (VIN = 4.5V to 28V, VOUT = 2.5V) COUT External Output Capacitor Requirement (VIN = 4.5V to 28V, VOUT = 2.5V) MAX UNITS IOUT = 12A, 3x 10F Ceramics 20 30 F IOUT = 12A 100 200 F 4601hvfb 9 LTM4601HV OPERATION Power Module Description The LTM4601HV is a standalone nonisolated switching mode DC/DC power supply. It can deliver up to 12A of DC output current with some external input and output capacitors. This module provides a precisely regulated output voltage programmable via one external resistor from 0.6VDC to 5.0VDC over a 4.5V to 28V wide input voltage. The typical application schematics are shown in Figures 19 and 20. The LTM4601HV has an integrated constant on-time current mode regulator, ultralow RDS(ON) FETs with fast switching speed and integrated Schottky diodes. The typical switching frequency is 850kHz at full load. With current mode control and internal feedback loop compensation, the LTM4601HV module has sufficient stability margins and good transient performance under a wide range of operating conditions and with a wide range of output capacitors, even all ceramic output capacitors. Current mode control provides cycle-by-cycle fast current limit. Besides, foldback current limiting is provided in an overcurrent condition while VFB drops. Internal overvoltage and undervoltage comparators pull the open-drain PGOOD output low if the output feedback voltage exits a 10% window around the regulation point. Furthermore, 10 in an overvoltage condition, internal top FET Q1 is turned off and bottom FET Q2 is turned on and held on until the overvoltage condition clears. Pulling the RUN pin below 1V forces the controller into its shutdown state, turning off both Q1 and Q2. At low load current, the module works in continuous current mode by default to achieve minimum output voltage ripple. When DRVCC pin is connected to INTVCC an integrated 5V linear regulator powers the internal gate drivers. If a 5V external bias supply is applied on the DRVCC pin, then an efficiency improvement will occur due to the reduced power loss in the internal linear regulator. This is especially true at the high end of the input voltage range. The LTM4601HV has a very accurate differential remote sense amplifier with very low offset. This provides for very accurate output voltage sensing at the load. The MPGM pin, MARG0 pin and MARG1 pin are used to support voltage margining, where the percentage of margin is programmed by the MPGM pin, and MARG0 and MARG1 select margining. The PLLIN pin provides frequency synchronization of the device to an external clock. The TRACK/SS pin is used for power supply tracking and soft-start programming. 4601hvfb LTM4601HV APPLICATIONS INFORMATION The typical LTM4601HV application circuits are shown in Figures 19 and 20. External component selection is primarily determined by the maximum load current and output voltage. Refer to Table 2 for specific external capacitor requirements for a particular application. The MPGM pin programs a current that when multiplied by an internal 10k resistor sets up the 0.6V reference offset for margining. A 1.18V reference divided by the RPGM resistor on the MPGM pin programs the current. Calculate VOUT(MARGIN): VIN to VOUT Step-Down Ratios There are restrictions in the maximum VIN to VOUT step down ratio that can be achieved for a given input voltage. These constraints are shown in the Typical Performance Characteristics curves labeled VIN to VOUT Step-Down Ratio. Note that additional thermal derating may apply. See the Thermal Considerations and Output Current Derating section of this data sheet. Output Voltage Programming and Margining The PWM controller has an internal 0.6V reference voltage. As shown in the Block Diagram, a 1M and a 60.4k 0.5% internal feedback resistor connects VOUT and VFB pins together. The VOUT_LCL pin is connected between the 1M and the 60.4k resistor. The 1M resistor is used to protect against an output overvoltage condition if the VOUT_LCL pin is not connected to the output, or if the remote sense amplifier output is not connected to VOUT_LCL. In these cases, the output voltage will default to 0.6V. Adding a resistor RSET from the VFB pin to SGND pin programs the output voltage: VOUT = 0.6V 60.4k +RSET RSET %VOUT * VOUT 100 where %VOUT is the percentage of VOUT you want to margin, and VOUT(MARGIN) is the margin quantity in volts: RPGM = VOUT 1.18V * *10k 0.6V VOUT(MARGIN) where RPGM is the resistor value to place on the MPGM pin to ground. The margining voltage, VOUT(MARGIN), will be added or subtracted from the nominal output voltage as determined by the state of the MARG0 and MARG1 pins. See the truth table below: MARG1 MARG0 MODE LOW LOW NO MARGIN LOW HIGH MARGIN UP HIGH LOW MARGIN DOWN HIGH HIGH NO MARGIN Input Capacitors LTM4601HV module should be connected to a low AC impedance DC source. Input capacitors are required to be placed adjacent to the module. In Figure 20, the 10F ceramic input capacitors are selected for their ability to handle the large RMS current into the converter. An input bulk capacitor of 100F is optional. This 100F capacitor is only needed if the input source impedance is compromised by long inductive leads or traces. or equivalently: RSET = VOUT(MARGIN) = 60.4k VOUT -1 0.6V Table 1. RSET Standard 1% Resistor Values vs VOUT RSET (k) Open 60.4 40.2 30.1 25.5 19.1 13.3 8.25 VOUT (V) 0.6 1.2 1.5 1.8 2 2.5 3.3 5 For a buck converter, the switching duty-cycle can be estimated as: D= VOUT VIN 4601hvfb 11 LTM4601HV APPLICATIONS INFORMATION ICIN(RMS) = IOUT(MAX) % * D * (1-D) In the above equation, % is the estimated efficiency of the power module. CIN can be a switcher-rated electrolytic aluminum capacitor, OS-CON capacitor or high value ceramic capacitor. Note the capacitor ripple current ratings are often based on temperature and hours of life. This makes it advisable to properly derate the input capacitor, or choose a capacitor rated at a higher temperature than required. Always contact the capacitor manufacturer for derating requirements. In Figures 19 and 20, the 10F ceramic capacitors are together used as a high frequency input decoupling capacitor. In a typical 12A output application, three very low ESR, X5R or X7R, 10F ceramic capacitors are recommended. These decoupling capacitors should be placed directly adjacent to the module input pins in the PCB layout to minimize the trace inductance and high frequency AC noise. Each 10F ceramic is typically good for 2A to 3A of RMS ripple current. Refer to your ceramics capacitor catalog for the RMS current ratings. Multiphase operation with multiple LTM4601HV devices in parallel will lower the effective input RMS ripple current due to the interleaving operation of the regulators. Application Note 77 provides a detailed explanation. Refer to Figure2 for the input capacitor ripple current reduction as a function of the number of phases. The figure provides a ratio of RMS ripple current to DC load current as function of duty cycle and the number of paralleled phases. Pick the corresponding duty cycle and the number of phases to arrive at the correct ripple current value. For example, the 2-phase parallel LTM4601HV design provides 24A at 2.5V 12 output from a 12V input. The duty cycle is DC = 2.5V/12V = 0.21. The 2-phase curve has a ratio of ~0.25 for a duty cycle of 0.21. This 0.25 ratio of RMS ripple current to a DC load current of 24A equals ~6A of input RMS ripple current for the external input capacitors. Output Capacitors The LTM4601HV is designed for low output ripple voltage. The bulk output capacitors defined as COUT are chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient requirements. COUT can be a low ESR tantalum capacitor, a low ESR polymer capacitor or a ceramic capacitor. The typical capacitance is 200F if all ceramic output capacitors are used. Additional output filtering may be required by the system designer if further reduction of output ripple or dynamic transient spike is required. Table 2 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 5A/s transient. The table optimizes total equivalent ESR and total bulk capacitance to maximize transient performance. 0.6 RMS INPUT RIPPLE CURRENT DC LOAD CURRENT Without considering the inductor ripple current, the RMS current of the input capacitor can be estimated as: 0.5 1-PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE 12-PHASE 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 DUTY CYCLE (VOUT/VIN) 0.8 0.9 4601HV F02 Figure 2. Normalized Input RMS Ripple Current vs Duty Cycle for One to Six Modules (Phases) 4601hvfb LTM4601HV APPLICATIONS INFORMATION Multiphase operation with multiple LTM4601HV devices in parallel will lower the effective output ripple current due to the interleaving operation of the regulators. For example, each LTM4601HV's inductor current in a 12V to 2.5V multiphase design can be read from the Inductor 12 2.5V OUTPUT 10 5V OUTPUT 1.8V OUTPUT 1.5V OUTPUT 1.2V OUTPUT 6 3.3V OUTPUT WITH 130k ADDED FROM VOUT TO fSET 4 5V OUTPUT WITH 100k ADDED FROM fSET TO GND 2 0 0.2 0.4 0.6 DUTY CYCLE (VOUT/VIN) 0.8 4601HV F03 Figure 3. Inductor Ripple Current vs Duty Cycle Figure 4 provides a ratio of peak-to-peak output ripple current to the inductor current as a function of duty cycle and the number of paralleled phases. Pick the corresponding duty cycle and the number of phases to arrive at the correct output ripple current ratio value. If a 2-phase operation is chosen at a duty cycle of 21%, then 0.6 is the ratio. This 0.6 ratio of output ripple current to inductor ripple of 6A equals 3.6A of effective output ripple current. Refer to Application Note 77 for a detailed explanation of output ripple current reduction as a function of paralleled phases. The output ripple voltage has two components that are related to the amount of bulk capacitance and effective series resistance (ESR) of the output bulk capacitance. 1.00 0.95 1-PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE 0.90 0.85 0.80 PEAK-TO-PEAK OUTPUT RIPPLE CURRENT DIr 0 RATIO = IL (A) 8 Ripple Current vs Duty Cycle graph (Figure 3). The large ripple current at low duty cycle and high output voltage can be reduced by adding an external resistor from fSET to ground which increases the frequency. If the duty cycle is DC = 2.5V/12V = 0.21, the inductor ripple current for 2.5V output at 21% duty cycle is ~6A in Figure 3. 0.75 0.70 0.65 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 DUTY CYCLE (VO/VIN) 4601HV F04 Figure 4. Normalized Output Ripple Current vs Duty Cycle, Dlr = VOT/LI, Dlr = Each Phase's Inductor Current 4601hvfb 13 LTM4601HV APPLICATIONS INFORMATION Therefore, the output ripple voltage can be calculated with the known effective output ripple current. The equation: VOUT(P-P) (IL/(8 * f * m * COUT) + ESR * IL), where f is frequency and m is the number of parallel phases. This calculation process can be easily accomplished by using LTpowerCADTM. Fault Conditions: Current Limit and Overcurrent Foldback LTM4601HV has a current mode controller, which inherently limits the cycle-by-cycle inductor current not only in steady-state operation, but also in response to transients. To further limit current in the event of an overload condition, the LTM4601HV provides foldback current limiting. If the output voltage falls by more than 50%, then the maximum output current is progressively lowered to about one sixth of its full current limit value. The current limit returns to its nominal value once VOUT and VFB have returned to their nominal values. Soft-Start and Tracking Output voltage tracking can be programmed externally using the TRACK/SS pin. The output can be tracked up and down with another regulator. The master regulator's output is divided down with an external resistor divider that is the same as the slave regulator's feedback divider. Figure5 shows an example of coincident tracking. Ratiometric modes of tracking can be achieved by selecting different resistor values to change the output tracking ratio. The master output must be greater than the slave output for the tracking to work. Figure 6 shows the coincident output tracking characteristics. MASTER OUTPUT TRACK CONTROL VIN 100k ) t SOFTSTART = 0.8 * 0.6V VOUT(MARGIN) * VIN PGOOD SGND PLLIN TRACK/SS VOUT LTM4601HV PGND SLAVE OUTPUT VFB MARG0 MARG1 COUT VOUT_LCL DIFFVOUT VOSNS+ VOSNS- fSET RSET 40.2k 4601HV F05 Figure 5. Coincident Tracking Schematic CSS 1.5A When the RUN pin falls below 1.5V, then the TRACK/SS pin is reset to allow for proper soft-start control when the regulator is enabled again. Current foldback and forced continuous mode are disabled during the soft-start process. The soft-start function can also be used to control the output ramp up time, so that another regulator can be easily tracked to it. R2 60.4k R1 40.2k MPGM RUN COMP INTVCC DRVCC CIN The TRACK/SS pin provides a means to either soft-start the regulator or track it to a different power supply. A capacitor on this pin will program the ramp rate of the output voltage. A 1.5A current source will charge up the external soft-start capacitor to 80% of the 0.6V internal voltage reference plus or minus any margin delta. This will control the ramp of the internal reference and the output voltage. The total soft-start time can be calculated as: ( Output Voltage Tracking MASTER OUTPUT SLAVE OUTPUT OUTPUT VOLTAGE TIME 4601HV F06 Figure 6. Coincident Output Tracking Characteristics 14 4601hvfb LTM4601HV APPLICATIONS INFORMATION Run Enable INTVCC and DRVCC Connection The RUN pin is used to enable the power module. The pin has an internal 5.1V Zener to ground. The pin can be driven with a logic input not to exceed 5V. An internal low dropout regulator produces an internal 5V supply that powers the control circuitry and DRVCC for driving the internal power MOSFETs. Therefore, if the system does not have a 5V power rail, the LTM4601HV can be directly powered by VIN. The gate driver current through the LDO is about 20mA. The internal LDO power dissipation can be calculated as: The RUN pin can also be used as an undervoltage lock out (UVLO) function by connecting a resistor divider from the input supply to the RUN pin: VUVLO = R1+R2 *1.5V R2 See Figure 1, Simplified Block Diagram. Power Good The PGOOD pin is an open-drain pin that can be used to monitor valid output voltage regulation. This pin monitors a 10% window around the regulation point and tracks with margining. COMP Pin This pin is the external compensation pin. The module has already been internally compensated for most output voltages. Table 2 is provided for most application requirements. LTpowerCAD is available for other control loop optimization. PLDO_LOSS = 20mA * (VIN - 5V) The LTM4601HV also provides the external gate driver voltage pin DRVCC. If there is a 5V rail in the system, it is recommended to connect DRVCC pin to the external 5V rail. This is especially true for higher input voltages. Do not apply more than 6V to the DRVCC pin. A 5V output can be used to power the DRVCC pin with an external circuit as shown in Figure 18. Parallel Operation of the Module The LTM4601HV device is an inherently current mode controlled device. Parallel modules will have very good current sharing. This will balance the thermals on the design. The voltage feedback equation changes with the variable N as modules are paralleled: PLLIN The power module has a phase-locked loop comprised of an internal voltage controlled oscillator and a phase detector. This allows the internal top MOSFET turn-on to be locked to the rising edge of the external clock. The frequency range is 30% around the operating frequency of 850kHz. A pulse detection circuit is used to detect a clock on the PLLIN pin to turn on the phase-locked loop. The pulse width of the clock has to be at least 400ns and at least 2V in amplitude. The PLLIN pin must be driven from a low impedance source such as a logic gate located close to the pin. During the start-up of the regulator, the phase-locked loop function is disabled. 60.4k + R SET VOUT = 0.6V * N R SET or equivalently: 60.4k N R SET = V OUT - 1 0.6V where N is the number of paralleled modules. Figure 21 shows two LTM4601HV modules used in a parallel design. An LTM4601HV device can be used without the remote sense amplifier. 4601hvfb 15 LTM4601HV APPLICATIONS INFORMATION Thermal Considerations and Output Current Derating The power loss curves in Figures 7 and 8 can be used in coordination with the load current derating curves in Figures 9 to 16 for calculating an approximate JA for the module with various heat sinking methods. Thermal models are derived from several temperature measurements at the bench and thermal modeling analysis. Thermal Application Note 103 provides a detailed explanation of the analysis for the thermal models and the derating curves. Tables3 and 4 provide a summary of the equivalent JA for the noted conditions. These equivalent JA parameters are correlated to the measured values, and are improved with air flow. The case temperature is maintained at 100C or below for the derating curves. The maximum case temperature of 100C is to allow for a rise of about 13C to 25C inside the Module with a thermal resistance JC from junction to case between 6C/W to 9C/W. This will maintain the maximum junction temperature inside the Module below 125C. Safety Considerations The LTM4601HV modules do not provide isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. 6 5.0 4.5 5 24VIN 3.5 3.0 POWER LOSS (W) POWER LOSS (W) 4.0 12VIN 2.5 2.0 1.5 24VIN 3 12VIN 2 5VIN 1.0 1 0.5 0 4 0 2 6 8 4 LOAD CURRENT (A) 10 0 12 0 2 4 6 8 LOAD CURRENT (A) 10 4601HV F08 4601HV F07 Figure 8. 3.3VOUT Power Loss 12 12 10 10 MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) Figure 7. 1.5VOUT Power Loss 8 6 4 5VIN, 1.5VOUT 0LFM 5VIN, 1.5VOUT 200LFM 5VIN, 1.5VOUT 400LFM 2 0 50 100 60 70 80 90 AMBIENT TEMPERATURE (C) 4601HV F09 Figure 9. No Heat Sink 5VIN 16 12 8 6 4 5VIN, 1.5VOUT 0LFM 5VIN, 1.5VOUT 200LFM 5VIN, 1.5VOUT 400LFM 2 0 50 100 60 70 80 90 AMBIENT TEMPERATURE (C) 4601HV F10 Figure 10. BGA Heat Sink 5VIN 4601hvfb LTM4601HV 12 12 10 10 MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) APPLICATIONS INFORMATION 8 6 4 12VIN, 1.5VOUT 0LFM 12VIN, 1.5VOUT 200LFM 12VIN, 1.5VOUT 400LFM 2 0 50 6 4 12VIN, 1.5VOUT 0LFM 12VIN, 1.5VOUT 200LFM 12VIN, 1.5VOUT 400LFM 2 0 100 60 70 80 90 AMBIENT TEMPERATURE (C) 8 50 4601HV F12 4601HV F11 Figure 12. BGA Heat Sink 12VIN 12 12 10 10 MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) Figure 11. No Heat Sink 12VIN 8 6 4 0LFM 200LFM 400LFM 2 0 40 60 80 AMBIENT TEMPERATURE (C) 8 6 4 0 100 0LFM 200LFM 400LFM 2 40 60 80 AMBIENT TEMPERATURE (C) Figure 14. 12VIN, 3.3VOUT, BGA Heat Sink 12 12 10 10 MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) Figure 13. 12VIN, 3.3VOUT, No Heat Sink 8 6 4 24VIN, 1.5VOUT 0LFM 24VIN, 1.5VOUT 200LFM 24VIN, 1.5VOUT 400LFM 0 40 60 80 AMBIENT TEMPERATURE (C) 100 4601HV F15 Figure 15. 24VIN, 1.5VOUT, No Heat Sink 100 4601HV F14 4601HV F13 2 100 60 70 80 90 AMBIENT TEMPERATURE (C) 8 6 4 24VIN, 1.5VOUT 0LFM 24VIN, 1.5VOUT 200LFM 24VIN, 1.5VOUT 400LFM 2 0 40 60 80 AMBIENT TEMPERATURE (C) 100 4601HV F16 Figure 16. 24VIN, 1.5VOUT, BGA Heat Sink 4601hvfb 17 LTM4601HV APPLICATIONS INFORMATION Table 2. Output Voltage Response Versus Component Matrix* (Refer to Figures 19 and 20), 0A to 6A Load Step TYPICAL MEASURED VALUES PART NUMBER COUT1 VENDORS TDK C4532X5R0J107MZ (100F, 6.3V) TAIYO YUDEN JMK432BJ107MU-T (100F, 6.3V) TAIYO YUDEN JMK316BJ226ML-T501 (22F, 6.3V) VOUT (V) 1.2 1.2 PART NUMBER 6TPE330MIL (330F, 6.3V) 2R5TPE470M9 (470F, 2.5V) 4TPE470MCL (470F, 4V) 2 x 10F 35V CIN (BULK) 150F 35V COUT1 (CERAMIC) 3 x 22F 6.3V COUT2 (BULK) 470F 4V CCOMP NONE C3 47pF VIN (V) 5 DROOP (mV) 70 PEAK TO PEAK (mV) 140 RECOVERY TIME (s) 30 LOAD STEP (A/s) 6 RSET (k) 60.4 2 x 10F 35V 150F 35V 1 x 100F 6.3V 470F 2.5V NONE 100pF 5 35 70 20 6 60.4 1.2 2 x 10F 35V 150F 35V 2 x 100F 6.3V 330F 6.3V NONE 22pF 5 70 140 20 6 60.4 1.2 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 2 x 10F 35V 150F 35V 4 x 100F 6.3V NONE NONE 100pF 5 40 93 30 6 60.4 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 150F 35V 3 x 22F 6.3V 1 x 100F 6.3V 2 x 100F 6.3V 4 x 100F 6.3V 3 x 22F 6.3V 1 x 100F 6.3V 2 x 100F 6.3V 4 x 100F 6.3V 3 x 22F 6.3V 1 x 100F 6.3V 2 x 100F 6.3V 4 x 100F 6.3V 3 x 22F 6.3V 1 x 100F 6.3V 2 x 100F 6.3V 4 x 100F 6.3V 3 x 22F 6.3V 1 x 100F 6.3V 2 x 100F 6.3V 4 x 100F 6.3V 1 x 100F 6.3V 2 x 100F 6.3V 3 x 22F 6.3V 4 x 100F 6.3V 1 x 100F 6.3V 3 x 22F 6.3V 2 x 100F 6.3V 4 x 100F 6.3V 2 x 100F 6.3V 1 x 100F 6.3V 3 x 22F 6.3V 4 x 100F 6.3V 1 x 100F 6.3V 3 x 22F 6.3V 2 x 100F 6.3V 4 x 100F 6.3V 4 x 100F 6.3V 4 x 100F 6.3V 470F 4V 470F 2.5V 330F 6.3V NONE 470F 4V 470F 2.5V 330F 6.3V NONE 470F 4V 470F 2.5V 330F 6.3V NONE 470F 4V 470F 2.5V 330F 6.3V NONE 470F 4V 470F 2.5V 330F 6.3V NONE 470F 4V 330F 6.3V 470F 4V NONE 470F 4V 470F 4V 330F 6.3V NONE 330F 6.3V 470F 4V 470F 4V NONE 470F 4V 470F 4V 330F 6.3V NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE 100pF 100pF 22pF 100pF 100pF 33pF 100pF 100pF 100pF 33pF 100pF 100pF 47pF 100pF 100pF 100pF 100pF 100pF 100pF 100pF 100pF 220pF NONE 100pF 100pF NONE 220pF 220pF 100pF 100pF 100pF 100pF 100pF 150pF 100pF 100pF 22pF 22pF 12 12 12 12 5 5 5 5 12 12 12 12 5 5 5 5 12 12 12 12 5 5 5 5 12 12 12 12 7 7 7 7 12 12 12 12 15 20 70 35 70 49 48 54 44 61 48 54 44 54 48 44 68 65 60 60 68 65 48 56 57 60 48 51 56 70 120 110 110 114 110 110 110 114 188 159 140 70 140 98 100 109 84 118 100 109 89 108 100 90 140 130 120 120 140 130 103 113 116 115 103 102 113 140 240 214 214 230 214 214 214 230 375 320 30 20 20 20 35 30 30 30 35 30 25 25 30 20 30 30 30 30 30 20 30 30 30 25 30 30 30 25 30 30 30 30 30 35 35 30 25 25 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 60.4 60.4 60.4 60.4 40.2 40.2 40.2 40.2 40.2 40.2 40.2 40.2 30.1 30.1 30.1 30.1 30.1 30.1 30.1 30.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 13.3 13.3 13.3 13.3 13.3 13.3 13.3 13.3 8.25 8.25 1.2 1.2 1.2 1.2 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 5 5 CIN (CERAMIC) COUT2 VENDORS SANYO POSCAP SANYO POSCAP SANYO POSCAP * X7R is recommended for extended temperature range. 18 4601hvfb LTM4601HV APPLICATIONS INFORMATION Table 3. 1.5V Output at 12A DERATING CURVE VIN (V) POWER LOSS CURVE AIR FLOW (LFM) HEAT SINK qJA (C/W) LGA qJA (C/W) BGA Figures 9, 11, 15 5, 12, 24 Figure 7 0 None 15.2 15.7 Figures 9, 11, 15 5, 12, 24 Figure 7 200 None 14 14.5 Figures 9, 11, 15 5, 12, 24 Figure 7 400 None 12 12.5 Figures 10, 12, 16 5, 12, 24 Figure 7 0 BGA Heat Sink 13.9 14.4 Figures 10, 12, 16 5, 12, 24 Figure 7 200 BGA Heat Sink 11.3 11.8 Figures 10, 12, 16 5, 12, 24 Figure 7 400 BGA Heat Sink 10.25 10.75 POWER LOSS CURVE AIR FLOW (LFM) HEAT SINK qJA (C/W) LGA qJA (C/W) BGA Table 4. 3.3V Output at 12A DERATING CURVE VIN (V) Figure 13 12 Figure 8 0 None 15.2 15.7 Figure 13 12 Figure 8 200 None 14.6 15.0 Figure 13 12 Figure 8 400 None 13.4 13.9 Figure 14 12 Figure 8 0 BGA Heat Sink 13.9 14.4 Figure 14 12 Figure 8 200 BGA Heat Sink 11.1 11.6 Figure 14 12 Figure 8 400 BGA Heat Sink 10.5 11.0 Heat Sink Manufacturer Aavid Thermalloy Part No: 375424B00034G Phone: 603-224-9988 4601hvfb 19 LTM4601HV APPLICATIONS INFORMATION Layout Checklist/Example Frequency Adjustment The high integration of LTM4601HV makes the PCB board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary. The LTM4601HV is designed to typically operate at 850kHz across most input conditions. The fSET pin is normally left open. The switching frequency has been optimized for maintaining constant output ripple noise over most operating ranges. The 850kHz switching frequency and the 400ns minimum off time can limit operation at higher duty cycles like 5V to 3.3V, and produce excessive inductor ripple currents for lower duty cycle applications like 28V to 5V. The 5VOUT and 3.3VOUT drop out curves are modified by adding an external resistor on the fSET pin to allow for lower input voltage operation, or higher input voltage operation. * Use large PCB copper areas for high current path, including VIN, PGND and VOUT. It helps to minimize the PCB conduction loss and thermal stress. * Place high frequency ceramic input and output capacitors next to the VIN, PGND and VOUT pins to minimize high frequency noise. * Place a dedicated power ground layer underneath the unit. Refer frequency synchronization source to power ground. Example for 5V Output * To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. LTM4601HV minimum on-time = 100ns tON = ((VOUT * 10pF)/IfSET), for VOUT > 4.8V use 4.8V * Do not put vias directly on pads unless they are capped. tOFF = t - tON, where t = 1/Frequency * Use a separated SGND copper area for components connected to signal pins. Connect the SGND to PGND underneath the unit. Duty Cycle = tON/t or VOUT/VIN Figure 17 gives a good example of the recommended layout. VIN CIN CIN GND SIGNAL GND COUT COUT VOUT 4601HV F17 Figure 17. Recommended Layout (LGA and BGA PCB Layouts Are Identical with the Exception of Circle Pads for BGA. See Package Description.) 20 LTM4601HV minimum off-time = 400ns Equations for setting frequency: IfSET = (VIN /(3 * RfSET)), for 28V operation, IfSET = 238A, tON = ((4.8 * 10pF)/IfSET), tON = 202ns, where the internal RfSET is 39.2k. Frequency = (VOUT/(VIN * tON)) = (5V/(28 * 202ns)) ~ 884kHz. The inductor ripple current begins to get high at the higher input voltages due to a larger voltage across the inductor. This is noted in the Typical Inductor Ripple Current vs Duty Cycle graph (Figure3) where IL 10A at 20% duty cycle. The inductor ripple current can be lowered at the higher input voltages by adding an external resistor from fSET to ground to increase the switching frequency. A 7A ripple current is chosen, and the total peak current is equal to 1/2 of the 7A ripple current plus the output current. The 5V output current is limited to 8A, so the total peak current is less than 11.5A. This is below the 14A peak specified value. A 100k resistor is placed from fSET to ground, and the parallel combination of 100k and 39.2k equates to 28k. The IfSET calculation with 28k and 28V input voltage equals 333A. This equates to a tON of 144ns. This will increase the switching frequency from ~884kHz to ~1.24MHz for the 28V to 5V conversion. 4601hvfb LTM4601HV APPLICATIONS INFORMATION The minimum on-time is above 100ns at 28V input. Since the switching frequency is approximately constant over input and output conditions, then the lower input voltage range is limited to 10V for the 1.24MHz operation due to the 400ns minimum off-time. Equation: tON = (VOUT/VIN) * (1/Frequency) equates to a 400ns on-time, and a 400ns off-time. The "VIN to VOUT Step-Down Ratio Curve" reflects an operating range of 10V to 28V for 1.24MHz operation with a 100k resistor to ground as shown in Figure 18, and an 8V to 16V operation for fSET floating. These modifications are made to provide wider input voltage ranges for the 5V output designs while limiting the inductor ripple current, and maintaining the 400ns minimum off-time. off-time are within specification at 139ns and 1037ns. The 4.5V minimum input for converting 3.3V output will not meet the minimum off-time specification of 400ns. tON = 868ns, Frequency = 850kHz, tOFF = 315ns. Solution Lower the switching frequency at lower input voltages to allow for higher duty cycles, and meet the 400ns minimum off-time at 4.5V input voltage. The off-time should be about 500ns, which includes a 100ns guard band. The duty cycle for (3.3V/4.5V) = ~73%. Frequency = (1 - DC)/tOFF or (1 - 0.73)/500ns = 540kHz. The switching frequency needs to be lowered to 540kHz at 4.5V input. tON = DC/ frequency, or 1.35s. The fSET pin voltage compliance is 1/3 of VIN, and the IfSET current equates to 38A with the internal 39.2k. The IfSET current needs to be 24A for 540kHz operation. As shown in Figure 19, a resistor can be placed from VOUT to fSET to lower the effective IfSET current out of the fSET pin to 24A. The fSET pin is 4.5V/3 =1.5V and VOUT = 3.3V, therefore 130k will source 14A into the fSET node and lower the IfSET current to 24A. This enables the 540kHz operation and the 4.5V to 28V input operation for down converting to 3.3V output. The frequency will scale from 540kHz to 1.1 MHz over this input range. This provides for an effective output current of 8A over the input range. Example for 3.3V Output LTM4601HV minimum on-time = 100ns tON = ((VOUT * 10pF)/IfSET) LTM4601HV minimum off-time = 400ns tOFF = t - tON, where t = 1/Frequency Duty Cycle (DC) = tON /t or VOUT/VIN Equations for setting frequency: IfSET = (VIN /(3 * RfSET)), for 28V operation, IfSET = 238A, tON = ((3.3 * 10pF)/I fSET), tON = 138.7ns, where the internal RfSET is 39.2k. Frequency = (VOUT /(VIN * tON)) = (3.3V/(28 * 138.7ns)) ~ 850kHz. The minimum on-time and minimum VOUT VIN 10V TO 28V R2 100k TRACK/SS CONTROL R4 100k MPGM RUN COMP INTVCC DRVCC 5% MARGIN C2 10F 35V VIN PGOOD R1 392k 1% C1 10F 35V SGND PLLIN TRACK/SS VOUT LTM4601HV PGND REVIEW TEMPERATURE DERATING CURVE + VFB MARG0 MARG1 VOUT_LCL DIFFVOUT VOSNS+ VOSNS- C3 100F 6.3V SANYO POSCAP VOUT 5V 8A 22F 6.3V REFER TO TABLE 2 fSET RfSET 100k RSET 8.25k MARGIN CONTROL IMPROVE EFFICIENCY FOR 12V INPUT SOT-323 DUAL CMSSH-3C3 4601HV F18 Figure 18. 5V at 8A Design Without Differential Amplifier 4601hvfb 21 LTM4601HV APPLICATIONS INFORMATION VOUT VIN 4.5V TO 16V R2 100k R4 100k PGOOD C2 10F 25V x3 TRACK/SS CONTROL VIN PGOOD MPGM RUN COMP INTVCC DRVCC LTM4601HV R1 392k SGND REVIEW TEMPERATURE DERATING CURVE PLLIN TRACK/SS VOUT + VOUT_LCL DIFFVOUT VOSNS+ VOSNS- RfSET 130k fSET PGND 5% MARGIN VFB MARG0 MARG1 MARGIN CONTROL VOUT 3.3V 10A 22F 6.3V C3 100F 6.3V SANYO POSCAP RSET 13.3k 4601HV F19 Figure 19. 3.3V at 10A Design CLOCK SYNC C5 0.01F VOUT VIN 22V TO 28V R2 100k R4 100k PGOOD ON/OFF CIN BULK OPT + CIN 10F 35V x3 CER VIN PGOOD MPGM RUN COMP INTVCC DRVCC PLLIN TRACK/SS VOUT LTM4601HV R1 392k 5% MARGIN SGND PGND VFB MARG0 MARG1 VOUT_LCL DIFFVOUT VOSNS+ VOSNS- fSET REVIEW TEMPERATURE DERATING CURVE C3 100pF COUT1 100F 6.3V MARGIN CONTROL RfSET 175k VIN RSET 40.2k 4601HV F20 + COUT2 470F 6.3V VOUT 1.5V 10A REFER TO TABLE 2 FOR DIFFERENT OUTPUT VOLTAGE Figure 20. Typical 22V to 28V, 1.5V at 10A Design, 500kHz 22 4601hvfb LTM4601HV APPLICATIONS INFORMATION VOUT VIN 6V TO 28V 118k 1% R2 100k + C1 0.1F LTC6908-1 1 2 3 V+ OUT1 GND OUT2 SET MOD 6 5 4 CLOCK SYNC 0 PHASE C5* 100F 35V C2 10F 35V x2 R4 100k MPGM RUN COMP INTVCC DRVCC R1 392k PLLIN TRACK/SS VOUT VIN PGOOD LTM4601HV SGND PGND 5% MARGIN 2-PHASE OSCILLATOR VFB MARG0 MARG1 TRACK/SS CONTROL C6 220pF VOUT_LCL DIFFVOUT VOSNS+ VOSNS- fSET 60.4k + R SET N RSET N = NUMBER OF PHASES VOUT = 0.6V C3 22F 6.3V C4 470F 6.3V VOUT 3.3V 20A + REFER TO TABLE 2 RSET 6.65k 100pF MARGIN CONTROL CLOCK SYNC 180 PHASE TRACK/SS CONTROL C7 0.033F VIN PGOOD PGOOD MPGM RUN COMP INTVCC DRVCC C8 10F 35V x2 PLLIN TRACK/SS VOUT LTM4601HV 392k SGND PGND C3 22F 6.3V VFB MARG0 MARG1 + C4 470F 6.3V REFER TO TABLE 2 VOUT_LCL DIFFVOUT VOSNS+ VOSNS- fSET 4601HV F21 *C5 OPTIONAL TO REDUCE ANY LC RINGING. NOT NEEDED FOR LOW INDUCTANCE PLANE CONNECTION Figure 21. 2-Phase Parallel, 3.3V at 20A Design 4601hvfb 23 LTM4601HV TYPICAL APPLICATIONS LTC6908-1 2-PHASE OSCILLATOR C8 0.1F R1 118k V+ OUT1 GND OUT2 SET MOD 3.3V VIN 6V TO 28V C1 10F 35V R3 100k R4 100k VIN 0 PHASE 180 PHASE PLLIN VOUT PGOOD VFB RUN VOUT_LCL COMP DIFFVOUT INTVCC LTM4601HV DRVCC VOSNS+ MPGM VOSNS- MARG0 fSET TRACK/SS MARG1 R2 392k C3 0.15F 3.3V SGND R1 13.3k C2 100F 6.3V VOUT1 3.3V C4 10A 150F 6.3V 3.3V TRACK MARGIN CONTROL R7 100k R8 100k C5 10F 35V R16 60.4k R6 392k R15 19.1k PGND VIN PLLIN VOUT PGOOD VFB RUN VOUT_LCL COMP DIFFVOUT INTVCC LTM4601HV DRVCC VOSNS+ MPGM VOSNS- MARG0 fSET TRACK/SS MARG1 SGND R5 19.1k C6 100F 6.3V VOUT2 2.5V C7 10A 150F 6.3V MARGIN CONTROL PGND 4601HV F22 Figure 22. Dual Outputs (3.3V and 2.5V) with Coincident Tracking LTC6908-1 2-PHASE OSCILLATOR C8 0.1F R1 182k V+ OUT1 GND OUT2 SET MOD 3.3V VIN 6V TO 28V C1 10F 35V R3 100k R4 100k VIN 0 PHASE 180 PHASE PLLIN VOUT PGOOD VFB RUN VOUT_LCL COMP DIFFVOUT INTVCC LTM4601HV DRVCC VOSNS+ MPGM VOSNS- MARG0 fSET TRACK/SS MARG1 R2 392k C3 0.15F SGND PGND 3.3V C8 47pF R1 30.1k MARGIN CONTROL C2 100F 6.3V VOUT1 1.8V C4 10A 220F 6.3V 3.3V TRACK R16 60.4k R15 40.2k R7 100k R8 100k C5 10F 35V R6 392k VIN PLLIN VOUT PGOOD VFB RUN VOUT_LCL COMP DIFFVOUT INTVCC LTM4601HV DRVCC VOSNS+ MPGM VOSNS- MARG0 fSET TRACK/SS MARG1 SGND C9 47pF R5 40.2k C6 100F 6.3V VOUT2 1.5V C7 10A 220F 6.3V MARGIN CONTROL PGND 4601HV F23 Figure 23. Dual Outputs (1.8V and 1.5V) with Coincident Tracking 24 4601hvfb aaa Z 0.630 0.025 O 118x 3.1750 3.1750 SUGGESTED PCB LAYOUT TOP VIEW 1.9050 PACKAGE TOP VIEW E 0.6350 0.0000 0.6350 4 1.9050 PIN "A1" CORNER 6.9850 5.7150 4.4450 4.4450 5.7150 6.9850 Y 6.9850 5.7150 4.4450 3.1750 1.9050 0.6350 0.0000 0.6350 1.9050 3.1750 4.4450 5.7150 6.9850 X D 2.45 - 2.55 aaa Z SYMBOL A A1 A2 b b1 D E e F G aaa bbb ccc ddd eee NOM 3.42 0.60 2.82 0.75 0.63 15.0 15.0 1.27 13.97 13.97 DIMENSIONS 0.15 0.10 0.20 0.30 0.15 MAX 3.62 0.70 2.92 0.90 0.66 NOTES DETAIL B PACKAGE SIDE VIEW A2 TOTAL NUMBER OF BALLS: 118 MIN 3.22 0.50 2.72 0.60 0.60 DETAIL A b1 0.27 - 0.37 SUBSTRATE A1 ddd M Z X Y eee M Z DETAIL B MOLD CAP ccc Z Ob (118 PLACES) // bbb Z A (Reference LTC DWG # 05-08-1903 Rev A) BGA Package 118-Lead (15mm x 15mm x 3.42mm) Z e b L K J G G F e E PACKAGE BOTTOM VIEW H D C B A DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE BALL DESIGNATION PER JESD MS-028 AND JEP95 TRAY PIN 1 BEVEL BGA 118 0112 REV A PACKAGE IN TRAY LOADING ORIENTATION LTMXXXXXX Module 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu 5. PRIMARY DATUM -Z- IS SEATING PLANE 4 3 2. ALL DIMENSIONS ARE IN MILLIMETERS NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 COMPONENT PIN "A1" 3 SEE NOTES F b M DETAIL A 1 2 3 4 5 6 7 8 9 10 11 12 PIN 1 LTM4601HV PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 25 4601hvfb aaa Z 0.630 0.025 O 118x E PACKAGE TOP VIEW 3.1750 3.1750 SUGGESTED PCB LAYOUT TOP VIEW 1.9050 4 0.6350 0.0000 0.6350 PIN "A1" CORNER 1.9050 Y 6.9850 5.7150 4.4450 3.1750 1.9050 0.6350 0.0000 0.6350 1.9050 3.1750 4.4450 5.7150 6.9850 X D aaa Z 0.27 2.45 MIN 2.72 0.60 NOM 2.82 0.63 15.00 15.00 1.27 13.97 13.97 0.32 2.50 DIMENSIONS 0.37 2.55 0.15 0.10 0.05 MAX 2.92 0.66 NOTES DETAIL B PACKAGE SIDE VIEW TOTAL NUMBER OF LGA PADS: 118 SYMBOL A b D E e F G H1 H2 aaa bbb eee H1 SUBSTRATE eee S X Y DETAIL A 0.630 0.025 SQ. 118x DETAIL B H2 MOLD CAP A (Reference LTC DWG # 05-08-1801 Rev A) bbb Z 26 Z LGA Package 118-Lead (15mm x 15mm x 2.82mm) e b L K J G G F e E PACKAGE BOTTOM VIEW H D C B A DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE BALL DESIGNATION PER JESD MS-028 AND JEP95 TRAY PIN 1 BEVEL LGA 118 1011 REV A PACKAGE IN TRAY LOADING ORIENTATION LTMXXXXXX Module 5. PRIMARY DATUM -Z- IS SEATING PLANE 4 3 2. ALL DIMENSIONS ARE IN MILLIMETERS NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 COMPONENT PIN "A1" 3 SEE NOTES F b M DETAIL A 1 2 3 4 5 6 7 8 9 C(0.30) PAD 1 10 11 12 LTM4601HV PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 4601hvfb 6.9850 5.7150 4.4450 4.4450 5.7150 6.9850 LTM4601HV PACKAGE DESCRIPTION Table 5. Pin Assignment (Arranged by Pin Number) PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION A1 VIN B1 VIN C1 VIN D1 PGND E1 PGND F1 PGND A2 VIN B2 VIN C2 VIN D2 PGND E2 PGND F2 PGND A3 VIN B3 VIN C3 VIN D3 PGND E3 PGND F3 PGND A4 VIN B4 VIN C4 VIN D4 PGND E4 PGND F4 PGND A5 VIN B5 VIN C5 VIN D5 PGND E5 PGND F5 PGND A6 VIN B6 VIN C6 VIN D6 PGND E6 PGND F6 PGND A7 INTVCC B7 - C7 - D7 - E7 PGND F7 PGND A8 PLLIN B8 - C8 - D8 - E8 - F8 PGND A9 TRACK/SS B9 - C9 - D9 - E9 - F9 PGND A10 RUN B10 - C10 - D10 - E10 - F10 - A11 COMP B11 - C11 - D11 - E11 - F11 - A12 MPGM B12 fSET C12 MARG0 D12 MARG1 E12 DRVCC F12 VFB PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION G1 PGND H1 PGND J1 VOUT K1 VOUT L1 VOUT M1 VOUT G2 PGND H2 PGND J2 VOUT K2 VOUT L2 VOUT M2 VOUT G3 PGND H3 PGND J3 VOUT K3 VOUT L3 VOUT M3 VOUT G4 PGND H4 PGND J4 VOUT K4 VOUT L4 VOUT M4 VOUT G5 PGND H5 PGND J5 VOUT K5 VOUT L5 VOUT M5 VOUT G6 PGND H6 PGND J6 VOUT K6 VOUT L6 VOUT M6 VOUT G7 PGND H7 PGND J7 VOUT K7 VOUT L7 VOUT M7 VOUT G8 PGND H8 PGND J8 VOUT K8 VOUT L8 VOUT M8 VOUT G9 PGND H9 PGND J9 VOUT K9 VOUT L9 VOUT M9 VOUT G10 - H10 - J10 VOUT K10 VOUT L10 VOUT M10 VOUT G11 - H11 - J11 - K11 VOUT L11 VOUT M11 VOUT G12 PGOOD H12 SGND J12 VOSNS+ K12 DIFFVOUT L12 VOUT_LCL M12 VOSNS- 4601hvfb 27 LTM4601HV PACKAGE DESCRIPTION Table 6. Pin Assignment (Arranged by Pin Function) PIN NAME PIN NAME A1 A2 A3 A4 A5 A6 VIN VIN VIN VIN VIN VIN D1 D2 D3 D4 D5 D6 PGND PGND PGND PGND PGND PGND B1 B2 B3 B4 B5 B6 VIN VIN VIN VIN VIN VIN C1 C2 C3 C4 C5 C6 VIN VIN VIN VIN VIN VIN E1 E2 E3 E4 E5 E6 E7 PGND PGND PGND PGND PGND PGND PGND F1 F2 F3 F4 F5 F6 F7 F8 F9 PGND PGND PGND PGND PGND PGND PGND PGND PGND G1 G2 G3 G4 G5 G6 G7 G8 G9 PGND PGND PGND PGND PGND PGND PGND PGND PGND H1 H2 H3 H4 H5 H6 H7 H8 H9 PGND PGND PGND PGND PGND PGND PGND PGND PGND 28 PIN NAME PIN NAME J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT A7 A8 A9 A10 A11 A12 INTVCC PLLIN TRACK/SS RUN COMP MPGM B12 fSET C12 MARG0 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT D12 MARG1 E12 DRVCC F12 VFB G12 PGOOD H12 SGND J12 VOSNS+ K12 DIFFVOUT L12 VOUT_LCL L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT M12 VOSNS- M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT PIN NAME B7 B8 B9 B10 B11 - C7 C8 C9 C10 C11 - D7 D8 D9 D10 D11 - E8 E9 E10 E11 - F10 F11 - G10 G11 - H10 H11 - J11 - 4601hvfb LTM4601HV REVISION HISTORY (Revision history begins at Rev B) REV DATE DESCRIPTION PAGE NUMBER B 03/12 Revised entire data sheet to include the BGA package. 1-30 4601hvfb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 29 LTM4601HV PACKAGE PHOTOS 2.82mm 15mm 3.42mm 15mm 15mm 15mm RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTM4628 26V, Dual 8A, DC/DC Step-Down Module Regulator 4.5V VIN 26.5V, 0.6V VOUT 5V, Remote Sense Amplifier, Internal Temperature Sensing Output, 15mm x 15mm x 4.32mm LGA LTM4627 20V, 15A DC/DC Step-Down Module Regulator 4.5V VIN 20V, 0.6V VOUT 5V, PLL Input, VOUT Tracking, Remote Sense Amplifier, 15mm x 15mm x 4.32mm LGA LTM4611 1.5VIN(MIN), 15A DC/DC Step-Down Module Regulator 1.5V VIN 5.5V, 0.8V VOUT 5V, PLL Input, Remote Sense Amplifier, VOUT Tracking, 15mm x 15mm x 4.32mm LGA LTM4613 8A EN55022 Class B DC/DC Step-Down Module Regulator 5V VIN 36V, 3.3V VOUT 15V, PLL Input, VOUT Tracking and Margining, 15mm x 15mm x 4.32mm LGA LTM4601AHV 28V, 12A DC/DC Step-Down Module Regulator 4.5V VIN 28V, 0.6V VOUT 5V, PLL Input, Remote Sense Amplifier, VOUT Tracking and Margining, 15mm x 15mm x 2.82mm LGA or 15mm x 15mm x 3.42mm BGA LTM4601A 20V, 12A DC/DC Step-Down Module Regulator 4.5V VIN 20V, 0.6V VOUT 5V, PLL Input, Remote Sense Amplifier, VOUT Tracking and Margining, 15mm x 15mm x 2.82mm LGA or 15mm x 15mm x 3.42mm BGA LTM8027 60V, 4A DC/DC Step-Down Module Regulator 4.5V VIN 60V, 2.5V VOUT 24V, CLK Input, 15mm x 15mm x 4.32mm LGA LTM8032 36V, 2A EN55022 Class B DC/DC Step-Down Module Regulator 3.6V VIN 36V, 0.8V VOUT 10V, Synchronizable, 9mm x 15mm x 2.82mm LGA or 9mm x 15mm x 3.42mm BGA LTM8061 32V, 2A Step-Down Module Battery Charger with Programmable Input Current Limit Compatible with Single Cell or Dual Cell Li-Ion or Li-Poly Battery Stacks (4.1V, 4.2V, 8.2V, or 8.4V), 4.95V VIN 32V, C/10 or Adjustable Timer Charge Termination, NTC Resistor Monitor Input, 9mm x 15mm x 4.32mm LGA This product contains technology licensed from Silicon Semiconductor Corporation. 30 Linear Technology Corporation (R) 4601hvfb LT 0312 REV B * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 l FAX: (408) 434-0507 l www.linear.com LINEAR TECHNOLOGY CORPORATION 2007