DECEMBER 2004
DSC-6818/00
1
©2004 Integrated Device Technology, Inc.
Features
◆◆
◆◆
◆64K x 16 advanced high-speed CMOS Static RAM
◆◆
◆◆
◆Equal access and cycle times
— Automotive: 12/15/20ns
◆◆
◆◆
◆One Chip Select plus one Output Enable pin
◆◆
◆◆
◆Bidirectional data inputs and outputs directly
LVTTL-compatible
◆◆
◆◆
◆Low power consumption via chip deselect
◆◆
◆◆
◆Upper and Lower Byte Enable Pins
◆◆
◆◆
◆Single 3.3V power supply
◆◆
◆◆
◆Available in 44-pin Plastic SOJ, 44-pin TSOP, and
48-Ball Plastic FBGA packages
Description
The IDT71V016 is a 1,048,576-bit high-speed Static RAM organized
as 64K x 16. It is fabricated using IDT’s high-perfomance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective solution for high-
speed memory needs and automotive applications.
The IDT71V016 has an output enable pin which operates as fast
as 5ns, with address access times as fast as 10ns. All bidirectional
inputs and outputs of the IDT71V016 are LVTTL-compatible and operation
is from a single 3.3V supply. Fully static asynchronous circuitry is used,
requiring no clocks or refresh for operation.
The IDT71V016 is packaged in a JEDEC standard 44-pin Plastic
SOJ, a 44-pin TSOP Type II, and a 48-ball plastic 7 x 7 mm FBGA.
Functional Block Diagram
Output
Enable
Buffer
Address
Buffers
Chip
Enable
Buffer
Write
Enable
Buffer
Byte
Enable
Buffers
OE
A
0
–A
15
Row / Column
Decoders
CS
WE
BHE
BLE
64K x 16
Memory
Array
Sense
Amps
and
Write
Drivers
16
Low
Byte
I/O
Buffer
8
8
8
8
I/O
8
I/O
15
I/O
7
I/O
0
6818 drw 01
High
Byte
I/O
Buffer
3.3V CMOS Static RAM
for Automotive Applications
1 Meg (64K x 16-Bit) IDT71V016SA
6.422
IDT71V016SA, 3.3V CMOS Static RAM
for Automotive Applications 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges
123456
ABLE OE A
0
A
1
A
2
NC
BI/O
8
BHE A
3
A
4
CS I/O
0
CI/O
9
I/O
10
A
5
A
6
I/O
1
I/O
2
DV
SS
I/O
11
NC A
7
I/O
3
V
DD
EV
DD
I/O
12
NC NC I/O
4
V
SS
FI/O
14
I/O
13
A
14
A
15
I/O
5
I/O
6
GI/O
15
NC A
12
A
13
WE I/O
7
HNC A
8
A
9
A
10
A
11
NC
6818 tb l 02a
Pin Configurations
SOJ/TSOP
Top View
Pin Description
Truth Table(1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
I
/O
7
NC
A
12
A
13
A
14
A
15
WE
I
/O
6
I
/O
5
I
/O
4
V
SS
V
DD
I
/O
3
I
/O
2
I
/O
1
I
/O
0
C
S
A
0
A
1
A
2
A
3
A
4
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
6
A
7
OE
BHE
BLE
I/O
15
I/O
14
I/O
13
I/O
12
V
SS
V
DD
I/O
11
I/O
10
I/O
9
I/O
8
A
8
A
9
A
10
A
11
NC
A
5
NC
SO44-1
SO44-2
6818 drw 02
NOTE:
1. H = VIH, L = VIL, X = Don't care.
CS OE WE BLE BHE I/O
0
-I/O
7
I/O
8
-I/O
15
Function
H X X X X High-Z High-Z Deselected – Standby
LLHL H DATA
OUT
Hig h-Z Lo w By te R ead
L L H H L High-Z DATA
OUT
Hig h B yte Re ad
LLHL L DATA
OUT
DATA
OUT
Wo rd Re a d
LXL L L DATA
IN
DATA
IN
Wo rd Wri te
LXL L H DATA
IN
Hig h-Z Lo w By te Wri te
LXL H L High-Z DATA
IN
Hig h B yte Wri te
L H H X X High-Z High-Z Outputs Disabled
L X X H H High-Z High-Z Outputs Disabled
6818 tb l 02
FBGA (BF48-1)
Top View
6.42
3
IDT71V016SA, 3.3V CMOS Static RAM
for Automotive Applications 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1) Recommended Operating
Temperature and Supply Voltage
DC Electrical Characteristics
(VDD = Min. to Max., Automotive Temperature Ranges)
Capacitance
(TA = +25°C, f = 1.0MHz, SOJ/TSOP package)
Recommended DC Operating
Conditions
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
Symbol Rating Value Unit
V
DD
Supply Voltage Re lative to
V
SS
–0. 5 to + 4. 6 V
V
IN
, V
OUT
Te rminal Vo ltag e Re lati ve
to V
SS
–0. 5 to V
DD
+0.5 V
T
BIAS
Te mp e rature Und e r Bias –55 to +125
o
C
T
J
Junction Te mp e rature Pag e –40 to +150
o
C
T
STG
Storage Te m pe r ature –65 to + 15 0
o
C
P
T
Po we r Dis si p atio n 1.25 W
I
OUT
DC O utp ut Cu rrent 50 m A
6818 tb l 03
Grade Temperature V
SS
V
DD
Automotive Grade 1 -40°C to +125°C 0V See Below
Auto m oti ve Grad e 2 -40° C to + 105° C 0V Se e B e lo w
Auto m oti ve Grad e 3 -40° C to +85 °C 0V Se e B e lo w
Auto m oti ve Grad e 4 0° C to +70° C 0V Se e B e lo w
6818 tb l 04
Symbol Parameter Min. Typ. Max. Unit
V
DD
Sup p ly Vo l tag e 3.0 3.3 3.6 V
Vss Ground 0 0 0 V
V
IH
Inp ut Hig h Vo ltag e 2. 0
____
V
DD
+0.3
(1)
V
V
IL
Inp ut Lo w Vo ltag e –0. 3
(1)
____
0.8 V
6818 tb l 05
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Input Capac i tanc e V
IN
= 3d V 6 pF
C
I/O
I/ O Capac itan ce V
OUT
= 3d V 7 pF
6818 tbl 0 6
S ymb ol Parameter Test Condi tions
Automotive
Temperature
Grade
IDT71V016SA
UnitMin. Max.
|I
LI
| Input Leak ag e Curre nt V
DD
= Max., V
IN
=
V
SS
to V
DD
1 and 2
___
5µA
3 and 4
___
1
|I
LO
| Outp ut Le ak ag e Curre nt V
DD
= Max., CS = V
IH
, V
OUT
= V
SS
to V
DD
1 and 2
___
5µA
3 and 4
___
1
V
OL
Outp ut Lo w Vo l tage I
OL
= 8mA, V
DD
= Min.
___
0.4 V
V
OH
Outp ut Hig h Vo l tag e I
OH
= -4mA, V
DD
= M in. 2. 4
___
V
6818 tb l 07
NOTE:
1. Refer to maximum overshoot/undershoot diagram below. The measured
voltage at device pin should not exceed half sinusoidal wave with 2V peak and
half period of 2ns.
Maximum Overshoot/Undershoot
V
IL
V
IH
6818 drw 12
+2V
-2V
2ns
2ns
6.424
IDT71V016SA, 3.3V CMOS Static RAM
for Automotive Applications 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges
AC Test Conditions
AC Test Loads
Figure 3. Output Capacitive Derating
Figure 1. AC Test Load
Figure 2. AC Test Load
(for t CLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
*Including jig and scope capacitance.
+
1
.
5
V
50
W
I
/O Z
0
=
50W
6818 drw 03
30pF
6818 drw 04
320
W
350
W
5pF*
D
ATA
OUT
3
.
3
V
(
Input Pulse Levels
In pu t R i se/Fa l l T imes
Inp ut Tim ing Re fe re nc e Le v e ls
Outp ut Re fe re nc e Le v e ls
AC Te st Load
GND to 3. 0V
1.5ns
1.5V
1.5V
See Figure 1, 2 and 3
6818 tb l 09
Parameter
71V016SA12 71V016SA15 71V016SA20
Unit
Symbol Auto moti ve Grade Autom otive Grade Automotive Grade
1 2 3 and 4 1 2 3 and 4 1 2 3 and 4
I
CC
Dynamic Operating Current
CS < V
LC
,
Outp uts Op e n, V
DD
= Max., f = f
MAX
(3)
Max. 110 100 90 80 80 80 80 80 80 mA
Typ.
(4)
75 75 75 70 70 70 70 70 70
I
SB
Dynamic Stand by Power Supply Curre nt
CS > V
HC
,
Outputs Open, V
DD
= Max., f = f
MAX
(3)
45 45 35 35 35 30 30 30 30 mA
I
SB
1
Full Standby Power Sup ply Current (static)
CS > V
HC
,
Outputs Open, V
DD
= Max., f = 0
(3)
552552552mA
6818 tbl 8
DC Electrical Characteristics(1,2)
(VDD = Min. to Max., VLC = 0.2V, VHC = VDD – 0.2V, Automotive Temperature Ranges)
NOTES:
1. All values are maximum guaranteed values.
2. All inputs switch between 0.2V (Low) and VDD – 0.2V (High).
3. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing .
4. Typical values are measured at 3.3V, 25°C and with equal read and write cycles. These parameter is guaranteed by device characterization but is not production
tested.
6.42
5
IDT71V016SA, 3.3V CMOS Static RAM
for Automotive Applications 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges
71V016SA12 71V016SA15 71V016SA20
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
RE AD CYCLE
t
RC
Re ad C y c le Tim e 12
____
15
____
20
____
ns
t
AA
Address Access Time
____
12
____
15
____
20 ns
t
ACS
Chip Se lect Acce ss Ti me
____
12
____
15
____
20 ns
t
CLZ
(1,2)
Chip S elect Lo w to Output in Low-Z 4
____
5
____
5
____
ns
t
CHZ
(1,2)
Chip S elect High to Outp ut in Hig h-Z
____
6
____
6
____
8ns
t
OE
Outp ut Enab le Lo w to Outp ut Val id
____
6
____
6
____
8ns
t
OLZ
(1,2)
Outp ut Enab le Lo w to Outp ut i n Lo w-Z 1
____
1
____
1
____
ns
t
OHZ
(1,2)
Outp ut Enab l e Hig h to O utp ut in Hi gh-Z
____
6
____
6
____
8ns
t
OH
Outp ut Ho ld from A dd re ss Ch ange 4 — 4 — 4 — ns
t
BE
B yte E nab l e Lo w to O utp ut Val id — 6 — 6
____
8ns
t
BLZ
(1,2)
By te E nab le Lo w to Outp ut in Lo w-Z 1
____
1
____
1
____
ns
t
BHZ
(1,2)
Byte Enab le Hig h to Outp ut in Hig h-Z
____
6
____
6
____
8ns
t
PU
(3)
Chi p Se le c t Lo w to P o we r Up 0
____
0
____
0
____
ns
t
PD
(3)
Chi p Se le c t Hi gh to P o we r Do wn
____
12
____
15
____
20 ns
WRI TE CYCL E
t
WC
Write Cycle Ti me 12
____
15
____
20
____
ns
t
AW
Add ress Valid to End o f Write 8
____
10
____
12
____
ns
t
CW
Chip Select Lo w to End o f Write 8
____
10
____
12
____
ns
t
BW
B y te Enabl e L o w to E nd of W ri te 9
____
10
____
12
____
ns
t
AS
Add ress Se t-up Time 0
____
0
____
0
____
ns
t
WR
Address Hold from End of Write 0
____
0
____
0
____
ns
t
WP
Write P ulse Wid th 8
____
10
____
12
____
ns
t
DW
Data Valid to End of Write 6
____
8
____
9
____
ns
t
DH
Data H o l d Tim e 0
____
0
____
0
____
ns
t
OW
(1,2)
Write Enab le Hig h to Ou tp ut in Lo w-Z 3
____
3
____
3
____
ns
t
WHZ
(1,2)
Write Enable Lo w to Output in Hig h-Z
____
6
____
6
____
8ns
6818 tb l 10
Timing Waveform of Read Cycle No. 1(1,2,3)
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. OE, BHE, and BLE are LOW.
AC Electrical Characteristics (VDD = Min. to Max., Automotive Temperature Ranges)
DATA
OUT
A
DDRESS
6818 drw 06
t
RC
t
AA
t
OH
t
OH
DATA
OUT
VALID
PREVIOUS DATA
OUT
VALID
NOTES:
1. At any given temperature and voltage condition, tCHZ is less than tCLZ, tOHZ is less than tOLZ, and tWHZ is less than tOW for any given device.
2. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
3. This parameter is guaranteed by design and not production tested.
6.426
IDT71V016SA, 3.3V CMOS Static RAM
for Automotive Applications 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 2(1)
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)
NOTES:
1. WE is HIGH for Read Cycle.
2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter.
3. Transition is measured ±200mV from steady state.
ADDRESS
OE
CS
DATA
OUT
6818 drw 07
(3)
(3)
(3)
DATA VALID
t
AA
t
RC
t
OE
t
OLZ
t
CHZ
t
OHZ
OUT
BHE, BLE
(3)
t
ACS
(3)
t
BLZ
t
CLZ
(2)
t
BE
t
OH
t
BHZ
(3)
(2)
V
DD
Supply
Current
I
CC
I
SB
t
PD
t
PU
A
DDRESS
C
S
DATA
IN
6818 drw 08
(5) (5)
(5)
DATA
IN
VALID
t
WC
t
AS
t
WHZ
(2)
t
CW
t
CHZ
t
OW
t
WR
WE
t
AW
DATA
OUT
t
DW
t
DH
PREVIOUS DATA VALID DATA VALID
BHE
,
BLE
t
BW
t
WP
(5)
t
BHZ
(3)
6.42
7
IDT71V016SA, 3.3V CMOS Static RAM
for Automotive Applications 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4)
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)(1,4)
ADDRESS
C
S
DATA
IN
6818 drw 09
DATA
IN
VALID
t
WC
t
AS (2)
t
CW
t
WR
WE
t
AW
D
ATA
OUT
t
DW
t
DH
BHE, BLE t
BW
t
WP
A
DDRESS
C
S
DATA
IN
6818 drw 10
DATA
IN
VALID
t
WC
t
AS
(2)
t
CW
t
WR
WE
t
AW
DATA
OUT
t
DW
t
DH
BHE, BLE
t
BW
t
WP
6.428
IDT71V016SA, 3.3V CMOS Static RAM
for Automotive Applications 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges
Ordering Information
SA
Power
XX
Speed
XXX
Package
XProcess/
Temperature
Range
1
2
3
4
Automotive Grade 1 (-40°C to +125°C)
Automotive Grade 2 (-40°C to +105°C)
Automotive Grade 3 (-40°C to +85°C)
Automotive Grade 4 (0°C to +70°C)
Y
PH
BF
400-mil SOJ (SO44-1)
400-mil TSOP Type II (SO44-2)
7.0 x 7.0 mm FBGA (BF48-1)
12
15
20
71V016
Device
Type
I
DT
Speed in nanoseconds
6818 drw 11
X
Tape & Reel
8
X
GRestricted hazardous substance device
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
9
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-bit) Commercial and Industrial Temperature Ranges
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or ipchelp@idt.com
San Jose, CA 95138 408-284-8200 800-345-7015
fax: 408-284-2775
www.idt.com
Rev Date Page Description
0 12/17/04 p. 1-8 Released Automotive datasheet
