PRELIMINARY CY7C09079V/89V/99V CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9 synchronous Dual-Port Static RAM Features * * True Dual-Ported memory cells which allow simulta- neous access of the same memory lIccation 6 Flow-Through/Pipelined devices 32K x 8/9 organizations (CY7CO9079V/179V) 64K x 8/9 organizations (CY7CO9089V/1 89V) 128K x 8/9 organizations (CY7CO9099V/199V) 3 Modes Flow-Through Pipelined Burst Pipelined output mode on both ports allows fast 83-MHz operation * * * * * * 0.35-micron CMOS for optimum speed/power High-speed clock to data access 7.5!"1/9/12 ns (max.) 3.3V Low operating power Active= 115 mA (typical) Standby= 10 pA (typical) Fully synchronous interface for easier operation Burst counters increment addresses internally Shorten cycle times Minimize bus noise Supported in Flow-Through and Pipelined modes Dual Chip Enables for easy depth expansion Automatic power-down + Commercial and Industrial temperature ranges + Available in 100-pin TQFP Logic Block Diagram CEor CEs FT/Pipe, (2) 89 VO g_VO7/aL He) Control 3] 15A 67 15/1617 [3] Ao-Araist6c Aog-Atan516R CLK, Counter/ Counter! CLKp ADS Address True Dual-Ported Address ADS at Register RAM Array Register A CNTEN, Decode Decode CNTENR CNTRST( CNTRSTp CEor CEyR FT/Piper 8/9 [2] (Oorn-VOs78R vo Control Notes: 1. 2. 3. Cypress Semiconductor Corporation + Call for availability. VO9-/O, for x8 devices; /O,-I/O, for x9 devices. Ap-Ay4 for 32K: Ap-Ays for 64K: and Ap-Ay, for 128K devices. For the most recent information, visit the Cypress web site at www.cypress.com 3901 North First Street + CA 95134 +* 408-943-2600 November 23, 1998 San Jose +FRSECUMINE RY CY7CO09079V/89V/99V CY7C09179V/89V/99V Functional Description The CY7COSO79V/89V/99V and CY7C09179V/89V/S9V are high speed synchronous CMOS 32K, 64K, and 128K x 8/9 dual-port static RAMs. Two ports are provided, permitting in- dependent, simultaneous access for reads and writes to any location in memory.!4! Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined out- put mode, data is registered for decreased cycle time. Clock to data valid tep2 = 7.5 ns (pipelined). Flow-through mode can also be used to bypass the pipelined output register to elimi- nate access latency. In flow-through mode data will be avail- able tep, = 18 ns after the address is clocked into the device. Pipelined output or flow-through mode is selected via the FT/Pipe pin. Each port contains a burst counter on the input address regis- ter. The internal write pulse width is independent of the LOW-to-HIGH transition of the clock signal. The internal write pulse is self-timed to allow the shortest possible cycle times. Pin Configurations A HIGH on CEg or LOW on CE, for one clock cycle will power down the internal circuitry to reduce the static power consump- tion. The use of multiple Chip Enables allows easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CEg LOW and CE, HIGH to reactivate the outputs. Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port's burst counter is loaded with the port's address strobe (ADS). When the ports count enable (CNTEN) is asserted, the address counter will increment on each LOW-to-HIGH transi- tion of that port's clock signal. This will read/write_one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop back to the start. Counter reset (CNTRST) is used to reset the burst counter. All parts are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages. 100-Pin TQFP (Top View) CNTENL a o Soe PR Res al 522k iam 222 ASR rrrr oe g2Eng28 MNININANNANAANAANAANAANN 100 99 98 97 96 9% 94 93 92 91 90 89 88 87 BE 85 84 83 82 B81 8 79 78 77 76 ne] 1 75 [-_I nec nc Ll] 2 7 (J nc AvL[L_] 3 73 [-_] a7 as. _] 4 72 [] aan ao. C=] 5 71 [C2 =J aor AioL LJ 6 70 [] ator AtiL_L_] 7 s9 [L_] atin Aip_ [Cl] 8 68 [-_] A12R AisL ==] 9 87 Co) aise Ai4.7] 10 66 [-_] aAtar wor sat Ef 1 CY7CO9099V (128K x 8) ss Fase noes (Note 6] Ais. [7] 12 64 [- _] Ater [Note 6] vec Ly 13 CY7CO09089V (64K x 8) ca FJenn no[7 =] 14 62 [-_Ine ne 15 CY7C09079V (32K x 8) 1 Fane ncL_] 16 so (J ne nceL-~] 17 so _I nc ceo. (CJ 18 58 [__] CEor ceEIL[L_] 19 s7 Co) ceir CNTRSTL [I] 20 56 [=] CnTAsTr AWL ECW] 21 55 (J) rawr oFL[C_] 22 54 [__] o&R [Note 7] FIVPIPEL [2] 23 53 [-__] FTPIPER[Noie 7] no [==] 24 52 [7] end nc [==] 25 51 [J] ne 26 27 28 29 30 31 32 33 34 35 36 37 38 30 40 41 42 43 44 45 46 47 48 49 50 ui UUUUULUU UU UU OU ee ee Qo o 4 ee EC REE SG RE ES -SSSSRSSCSS ss ESSE SERS SF? Notes: 4. When writing simultaneously to the same location, the final value cannot be guaranteed. 5. This pinis NC for CY7C09079V. 6. This pin is NC for CY7C09079V and CY7Co9089V. 7. For CY7C09079V and CY7CO9089V, pin #23 connected to Vor is pin compatible with an IDT 5V x8 pipelined device; connecting pin #23 and #53 to GND is pin compatible with an IDT 5V x16 flow-through device.CY7CO09079V/89V/99V PSELINENASY CY7C09179V/89V/99V Pin Configurations (continued) 100-Pin TQFP (Top View) nn iin NNN Tn 100 99 98 97 96 95 4 93 9P 91 90 89 88 87 86 85 84 83 8? 81 8 79 78 77 76 ncLl=J 1 7% (=I) ne nc (l_] 2 4 (J) nc Ar_C_] 3 73 [Jaz as. L-_] 4 yz [__]asr Aa [C_] 5 71 [J] asr7 Ato. L__] 6 70 [__] ator ait _] 7 eo [J atunr, Ato: L_] 3s 68 [_] ater Ais. L-_] 9 ey [-_] A13R AL LJ 10 66 [__] A14R [Note 8] Aish [J 11 CY7C091 99V 1 BK x9 65 [-] AisR [Note 8] [Note 9] AisL L___] 12 ( ) 64 [___] ater [Note 9] voo L] 13 CY7C09189V (64K x 9) es Eon no Dla] 14 ez Ll] nc no 1s CY7C09179V (32K x 9) 1 Fine nc ==] 16 co [] ne no =<] 17 s9 [I] ne ceo. [C_] 18 ss [__] Gor cei (CJ 19 57 [_] ce1A GNTRSTL [L__] 20 56 [-__] oNTRSTA RW [CZ] 21 ss [__] AWA or. [l_] 22 54 [__] o&R FIPIPEL [7] 23 53 [__] FrPiper NcL_] 24 52 [_] end nce [7] 25 51 [-_] nec ?P6 PF 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 TNNOOOTUOUTO LOOT 6gsegssessSeFseesrssesgsggg* * Selection Guide CY7CO90D7TSV/B9V/99V CY7CO90T9V/B9V/99V CY7CO9079V/89V/9I9V CY7C091 TON /BOV/99V CY7C09179V/89V/99V C7C091 79V/89V/99V - -9 -12 imaxz (MHz} (Pipelined) 83 67 50 Max Access Time (ns) (Clock to data, 7.5 9 12 Pipelined) Typical Operating Current leg (mA) 155 135 115 Typical Standby Current for Iggy (mA) 25 20 20 (Both ports TTL Level} Typical Standby Current for Isp3 (HA} 10 pA 10 pA 10 nA (Both ports CMOS level) Shaded area contains advance information. Notes: 8. This pinis NC for CY7CO09179V. 9. This pinis NG for C7C09179V and CY7C09189V.CY7CO09079V/89V/99V SELINA RY CY7C09179V/89V/99V Pin Definitions Left Port Right Port Description AgtAteL Agr-Aisr Address Inputs (AgAy4 for 32K; Ag-Ajs for 64K; and ApAj, for 128K devices). ADS, ADSp Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to access the part using an externally supplied address. Asserting this signal LOW also loads the burst counter with the address present on the address pins. CEpLCE;. | CEor.CEip | Chip Enable Input. To select either the left or right port, both CEg AND CE, must be asserted to their active states (CE, < Vj, and CE, > Vjy4). CLK, CLKr Clock Signal. This input can be free running or strobed. Maximum clock input rate is fax. CNTENL CNTEN|, Counter Enable Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW. CNTRSTL CNTRSTR Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN. VOg_-VGg_ | /OgR-OgR_ | Data Bus Input/Output (I/O 9-l/O7 for x8 devices; I/Ogl/Og for x9 devices). OE, OER Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read operations. RAW, RiWar Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For read operations, assert this pin HIGH. FI/PIPE, FT/PIPE, Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For pipelined mode operation, assert this pin HIGH. GND Ground Input. NG No Connect. Vee Power Input. Maximum Ratings Static Discharge Voltage ....0...0ccccccccsesetee sere >1100V Latch-Up Current... eee teen >200mA (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature cece eees -65C to +150C Operating Range Ambient Temperature with Power Applied ..-55C to +125C Ambient Supply Voltage to Ground Potential... 0.5V to +4.6V Range Temperature Vee De Voltage Applied to Commercial 0C to +70C 3.3V + 300 mV Outputs in High Z State oo. O0.5V to Voo+0.5V Industrial 40C to 485C 3 3V +300 mV DG Input Voltage... ee 0.5V to Voc+0.5V Shaded area contains advance information. Output Current into Outputs (LOW)... 20 mACY7CO09079V/89V/99V SELINA RY CY7C09179V/89V/99V Electrical Characteristics Over the Operating Range CY7CO9079V/89V/99V CY7CO9179V/89V/99V 7H -9 -12 Symbol Parameter Min| Typ | Max |Min| Typ | Max | Min| Typ | Max | Units Vou Output HIGH Voltage (Voc=Min, loH= 4.0mA) 24 2.4 2.4 Vv Voi Output LOW Voltage (Vec=Min, loH= +4.0mA) 04 0.4 0.4 Vv Vin Input HIGH Voltage 2.2 2.2 2.2 V Vit Input LOW Voltage Q.8 0.8 0.8 V loz Output Leakage Current -10 1a |-10 10 |-10 10 HA lec Operating Current (Voc=Max, Com. 155 | 275 135 | 230 115 180 | mA lour=0 MA) Outputs Disabled indust. 185 | 300 155 | 250 | mA Isp Standby Current (Both Ports TTL Com. 25 | 85 20 | 75 20 | 70 | mA Level) ICE, & CER > Vin. ffmax [Indust a5 | 85 30 | 80 | mA Isao Standby Gutrent (One Port TTL Com'l. 105 | 165 95 155 85 140 | mA Level ICE, |CER> Vin. ffmax Tndust 105 | 165 95 | 150 | mA Ispa eentlae soe. Ports CMOS =| Com. 16 | 100 10 100 10 100 | pA Level) ICE, & CER2> Vec-0.2V, Pagust 10 | 100 10. | 100 | pA lana Standby Gurrent (C (One Port CMOS Caml. 95 | 125 85 115 75 100 | mA Level" CEL! CER? Vin. f=Imax indust. 05 | 125 85 | 110 | mA Shaded area contains advance information. Capacitance Parameter Description Test Conditions Max. Unit Cin Input Capacitance Ta = 25C, f= 1 MHz, 10 pF Cour Output Capacitance Voc =3.3V 10 pF AC Test Loads 3.3V 3.3V Ri= 5900 RTH = 2502 OUTPUT, OUTPUT Rt = 5900 C = 30pF OUTPUT C= 30pF T R2= 4350 L Cus = 5pF = R2= 4350 (a) Normal Load (Load 1) Viy= 14V ALL INPUT PULSES Note: (b) Thvenin Equivalent (Load 1) (c) Three-State Delay (Load 2) (Used for texz, torz, & touz including scope and jig) 10. CE, and CE, are internal signals. To select either the left or right port, both CE, AND CE, must be asserted to their active states (CE, < Vj. and CE, > Vj).CY7CO09079V/89V/99V PSELINENASY CY7C09179V/89V/99V Switching Characteristics Over the Operating Range CY7CO9079V/89V/99V CY7C09179V/89V/99V 7 -9 -12 Symbol Parameter Min Max Min Max Min Max Units TMAXA fyiax Flow-Through 45 40 33 MHz imaxe tmax Pipelined 83 67 50 MHz teye1 Clock Cycle Time - Flow-Through 22 25 30 ns levee Clock Cycle Time - Pipelined 12 15 20 ns tout Clock HIGH Time - Flow-Through 7.5 12 12 ns tout Clock LOW Time - Flow-Through 7.5 12 12 ns toue Clock HIGH Time - Pipelined 5 6 8 ns tote Clock LOW Time - Pipelined 5 6 8 ns tr Clock Rise Time 3 3 3 ns tp Clock Fall Time 3 3 3 ns tsa Address Set-Up Time 4 4 4 ns tua Address Hold Time 0 1 1 ns Isc Chip Enable Set-Up Time 4 4 4 ns tuc Chip Enable Hold Time G 1 1 ns isw RW Set-Up Time 4 4 4 ns tuw RW Hold Time G 1 1 ns tsp Input Data Set-Up Time 4 4 4 ns tup Input Data Hold Time 6 1 1 ns tsap ADS Set-Up Time 4 4 4 ns tap ADS Hold Time 0 1 1 ns Iscn CNTEN Set-Up Time 45 5 5 ns tucn CNTEN Hold Time 0 1 1 ns tsast CNTRST Set-Up Time 4 4 4 ns tuRST CNTRST Hold Time 0G 1 1 ns toe Output Enable to Data Valid 9 10 12 ns to.z'' 4 [OE to Low Z 2 2 2 ns tonz 4 | OE to High Z 1 7 1 7 1 7 ns tep1 Clock to Data Valid - Flow-Through 18 20 25 ns topz Clock to Data Valid - Pipelined 7.5 9g 12 ns tpc Data Output Hold After Clock HIGH 2 2 2 ns toxyz 14 | Clock HIGH to Output High Z 2 9 2 9 2 9 ns toxiz!' |=! | Clock HIGH to Qutput Low Z 2 2 2 ns Port to Port Delays tcwop Write Port Glock HIGH to Read Data Delay 35 40 40 ns tecs Clock to Glock Set-Up Time 16 15 15 ns Notes: 11. Test conditions used are Load 2. 12. This parameter is guaranteed by design, but itis not production tested.CY7CO09079V/89V/99V PSELINENASY CY7C09179V/89V/99V Switching Waveforms Read Cycle for Flow-Through Output (FT/PIPE = V,,)!19:14.15.161 lever e ton toL1 CLK _ fo NY NN ce, KON LAX KOON AXON, KOKO |) KOOL tse | fe] tHe tec [>] | fic N \ ce, KY OXY | OOOO OOOOH, | KOO nm 2H | KX | XO XOOOOY | XK tsw tow tsa tha +_ tent DATA pur }+- tcxLz OE Read Cycle for Pipelined Operation (FT/PIPE = Vj,)i'9.14.'5.16] ZO | ROO" | ROO" | XO" | XOOKY tsa tHA ADDRESS A, 7 A A = t DAT Agyr 1 Latency tops pe Q, Ona Q, +2 toxLz [+ * toe * Notes: OE is asynchronously controlled: all other inputs are synchronous to the rising clock edge. 14. ADS = Vj, CNTEN and CNTRST = Vy . The output is disabled (high-impedance state} by CE =Viy or CE, = V'_ following the next rising edge of the clock. Addresses do not have to be accessed sequentially since ADS = V|_ constantly loads the address onthe rising edge of the CLK. Numbers are for reference only.FRSECUMINE RY CY7CO09079V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) Bank Select Pipelined Read!'7:'4 CLK, __ tovee + tHe ten tHA CEo pt) x tec te 4 XX top OATAour PRP DIRK KMD tsa tHa ADDRESS pp, SOK A CEp Be) x yf DATAouriB2) ~ KY ts tHe tobe teKLz Left Port Write to Flow-Through Right Port Read!'9.20.21 22] CLK, RAW, ADDRESS, DATAgy, CLK RW, ADDRESS, DATAgutR toe tbe Notes: 17. Inthis depth expansion example, Bi represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet. ADDRESS OE and ADS 18. GE andA 1) = ADDRESS. oe 1 CE eo}. RW, CNTEN, and CNTRST = Vi. = Vis Eye 19. The same waveforms apply for a right port write to flow-through left port read. 20. CE, and ADS =V,; CE,, CNTEN, and CNTRST = Vi... 21. OE =V), for the Right Port, which is being read from. OE = Vj, for the Lett Port, which is being written to. 22. ittces maximum specified, then data from right port READ is not valid until the maximum specified for toypp. Ifteeg>maximum specitied, then data is not valid unt foos + toot toypp does not apply in this case.FRSECUMINE RY Switching Waveforms (continued) Pipelined Read-to-Write-to-Read (OE = V,, )' 3.24.25 CLK 7 Or CE, levee ton2 AX CY7CO09079V/89V/99V CY7C09179V/89V/99V SON HNN NN tsc tic oc, XO KOO aw XY tsw pooress QOK& HOOK Aw tga DATAny NXY tw tHa DATAgur H+NO OPERATION? WRITE Pipelined Read-to-Write-to-Read (OE Controlled)!!.3 24.25] CLK 7 ON teves , XOX AX tsc tic ce, KX WY OO aw XO lA ALIN ee sw tuw tow I+ taw ADDRESS tsa tHa tg tu | D NA \/7 OAT = KKK KK tcp2 teKLz tone DATAour Q, Qh44 HZ L ~ EE COCOCCON - READ _-+ WRITE READ Notes: 23. Output state (HIGH, LOW, or High-Ilmpedance) is determined by the previous cycle control signals. 24. GE, and ADS =V,,; CE,, CNTEN, and GNTRST = V 25. During No operation, data in memory at the selected address may be corrupted and should be re-written to ensure data integrity. = Vin.CY7CO09079V/89V/99V PSELINENASY CY7C09179V/89V/99V Switching Waveforms (continued) Flow-Through Read-to-Write-to-Read (OE = Vj,)!14.18.23.24.25] tever tout teu CLK ADDRESS DATA DATAgut Qaut teKHz NO OPERATI Flow-Through Read-to-Write-to-Read (OE Controlled)!'4.17.23.24.25) tever tout teu CLK CE, RW ADDRESS DATA Qnia DATAour toe OE READ - - 10CY7CO09079V/89V/99V PSELINENASY CY7C09179V/89V/99V Switching Waveforms (continued) Pipelined Read with Address Counter Advance!@4 levee tore toe CLK tHa ADDRESS tscn DATAgyr Qnsg Quip Ona Qy-4 Q, Q, READ - EXTERNAL ADDRESS tbe COUNTER HOLD READ WITH COUNTER = READ WITH COUNTER Flow-Through Read with Address Counter Advancell lover toHi tou CLK ADDRESS tuaD thon Q, +2 en +3 Qy Ona DATAour tp Cc READ READ ~ EXTERNAL READ WITH COUNTER COUNTER HOLD WITH ADDRESS COUNTER Note: 26. CE, and OF = V\; CE,, RW and CNTRST = V\,. 11CY7CO09079V/89V/99V PSELINENASY CY7C09179V/89V/99V Switching Waveforms (continued) Write with Address Counter Advance (Flow-Through or Pipelined Outputs)? 7! tevee tone | tere ADDRESS 7 KXKKX KKKXKIDXRAKADIOKXK ADDRESS DN OK Aaa xX Ae KA KA tsaD J tuaD wx | A COMO CANO CAENC. CAEN. CAEN C.C4 | omen Of | NOON 107 [OOK IAD. TAN 1OOn tHeN DATA Pn Ont KROME: a tsp tub WRITE EXTERNAL WRITE WITH | WRITE COUNTER ~~ ADDRESS 7r_ COUNTER F_ HOLD "7 A oO n+2 Daeg Dna WRITE WITH COUNTER - Notes: 27. CE, and RW =V\; CE, and CNTRST = Vi. 28. The Internal Address is equal to the External Address when ADS = Vj, and equals the counter output when ADS = Vjy. 12FRSECUMINE RY CY7CO09079V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) Counter Reset (Pipelined Outputs)!'23.29.3] _ leyco toHe tore CLK _ 7 INTERNAL Ay x ADDRESS tow amt XXKXXA tgap tuaD ADS x Y |X tscn tHcn CNTEN KY NOK tsRST | CNTRST DATAiy DATAour KX COUNTER RESET ~~ WRITE *~ ADDRESS 0~ READ ~ ADDRESS 0~ OOK 2. READ OOK READ " ADDRESS 1 ADDRESS n~1 Notes: 29. CEg=V; CEy = Vy. 30. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. 13CY7CO09079V/89V/99V SELINA RY CY7C09179V/89V/99V Read/Write and Enable Operation!*' 2741 Inputs Outputs OE | CLK | CE, | CE, | RAW] WOO Operation igh- [34] X cr H X X High-Z Deselected igh- [34] xX ir x L x High-2 Deselected X _ L H L Din Write Ly oe L H H Dout Read!#41 H x L H x High-Z Outputs Disabled Address Counter Control Operation!*' 5.3697] Previous Address | Address | CLK DS | CNTEN | CNTRST 1/0 Mode Operation x X ir X X L Dautcoy Reset Counter Reset to Address 0 An X ir L x H Doutiny Load Address Load into Counter x An cr H H H Doutny Hold External Address BlockedCounter Disabled x An rr H L H Doutinet) | Increment | Counter EnabledInternal Address Generation Notes: 31. X" = Don't Care, H = Vy, "L" = Vi. 32. ADS, CNTEN, CNTRST = Don't Care. 33. OE is an asynchronous input signal. 34. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle. 35. CE, and OF = V\; CE, and R/W= Vj, 36. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle. 37. Counter operation is independent of CE, and CE). 14CY7CO09079V/89V/99V SELINA RY CY7C09179V/89V/99V Ordering Information 32K x8 3.3V Synchronous Dual-Port SRAM Speed Package Operating (ns) Ordering Code Name Package Type Range 75 | GY7C09079V-7AC A100 160-Pin Thin Quad Flat Pack Commercial 9 CY7C09079V-9ACG A100 100-Pin Thin Quad Flat Pack Commercial CY7G09079V-9Al A106 100-Pin Thin Quad Flat Pack Industrial 12 CY7C09079V-12AG A100 100-Pin Thin Quad Flat Pack Commercial CY7C09079V-12Al A100 100-Pin Thin Quad Flat Pack Industrial Shaded area contains advance information. 64K x8 3.3V Synchronous Dual-Port SRAM Speed Package Operating Ins) Ordering Code Name Package Type ange 750 | GY7C0g089V-7AC A100 100-Pin Thin Quad Flat Pack Commercial 9 CY7C0S9089V-9AC A100 100-Pin Thin Quad Flat Pack Commercial CY7CO0S089V-9AI A100 100-Pin Thin Quad Flat Pack Industrial 12 CY7CO9089V-12AC A100 100-Pin Thin Quad Flat Pack Commercial CY7COSG89V-12Al A100 100-Pin Thin Quad Flat Pack Industrial Shaded area contains advance information. 128K x8 3.3V Synchronous Dual-Port SRAM Speed Package Operating (ns) Ordering Code Name Package Type Range 7541 | C7CogOS9V-7AC A100 100-Pin Thin Quad Flat Pack Commercial 9 CY7COS0S9V-9AC A100 100-Pin Thin Quad Flat Pack Commercial CY7CO90S9V-SAl A100 100-Pin Thin Quad Flat Pack Industrial 12 CY7C09099V-12AC A100 100-Pin Thin Quad Flat Pack Commercial CY7GO9099V-12Al A100 100-Pin Thin Quad Flat Pack Industrial Shaded area contains advance information. 32K x9 3.3V Synchronous Dual-Port SRAM Speed Package Operating (ns) Ordering Code Name Package Type Range 75H | CY7C09179V-7AC A100 100-Pin Thin Quad Flat Pack Commercial 9 CY7C09179V-9C A100 100-Pin Thin Quad Flat Pack Commercial GY7C09179V-9Al A100 100-Pin Thin Quad Flat Pack Industrial 12 CY7C09179V-12AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09179V-12Al A106 100-Pin Thin Quad Flat Pack Industrial Shaded area contains advance information. 64K x9 3.3V Synchronous Dual-Port SRAM Speed Package Operating (ns) Ordering Code Name Package Type Range 75UL | C7CO9489V-7AC A100 100-Pin Thin Quad Flat Pack Commercial 9 CY7C09189V-9AC A100 100-Pin Thin Quad Flat Pack Commercial GY7C09 189V-9Al A100 100-Pin Thin Quad Flat Pack Industrial 12 CY7C09189V-12AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09 t89V-12Al A100 100-Pin Thin Quad Flat Pack Industrial Shaded area contains advance information. 15PEIN SY CY7CO09079V/89V/99V CY7C09179V/89V/99V Ordering Information (continued) 128K x9 3.3V Synchronous Dual-Port SRAM Speed Package Operating (ns) Ordering Code Name Package Type Range 75 | GY7COS199V-7AC A100 160-Pin Thin Quad Flat Pack Commercial 9 CY7C09199V-9AG A100 100-Pin Thin Quad Flat Pack Commercial CY7G091t99V-9Al A106 100-Pin Thin Quad Flat Pack Industrial 12 CY7C09199V-12AG A100 100-Pin Thin Quad Flat Pack Commercial CY7C09199V-12Al A108 100-Pin Thin Quad Flat Pack Industrial Shaded area contains advance information. Document #: 38-00667-D Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 16002025 $0 DIMENSIONS ARE IN MILLIMETERS. 0222005 R O08 MIN, O MIN. WAX. STAND-DFF C1 005 MIN. ws max | Onn GAUGE PLANE ; See R OC8 NIN. 0.20 MAX o*-7* asa 020 MIN TYR. he 1.602015 1.00 REF. 51-85048-A DETAIL A SEATING PLANE [ 160 MAX. STUCCO UO x f / SEE DETaL A O20 MAX. Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility tor the use ofany circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical componenis in life-support systems where a maliunction or failure may reasonably be expecied to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that ine manutacturer assumes all risk of Such Use and in doing so indemnifies Cypress Semiconductor against all charges.