www.fairchildsemi.com User Guide for FEBFAN9611_S388V1 FAN9611 400-W Interleaved Dual-BCM PFC Controller Evaluation Board Featured Fairchild Products: FAN9611 Direct questions or comments about this evaluation board to: "Worldwide Direct Support" Fairchild Semiconductor.com Please contact a local Fairchild Sales representative for an evaluation board. (c) 2010 Fairchild Semiconductor Corporation 1 FEBFAN9611_S388V1 * Rev. 0.0.5 www.fairchildsemi.com Table of Contents Table of Contents ............................................................................................................................ 2 1. Overview of the Evaluation Board ............................................................................................. 3 2. Key Features ............................................................................................................................... 5 3. Specifications .............................................................................................................................. 6 4. Test Procedure ............................................................................................................................ 7 5. Schematic .................................................................................................................................... 8 6. Boost Inductor Specification....................................................................................................... 9 7. Line Filter Inductor Specifications ........................................................................................... 10 8. PCB Layout ............................................................................................................................... 11 9. Bill of Materials (BOM) ........................................................................................................... 15 10. Test Results ....................................................................................................................... 17 10.1. Startup ..................................................................................................................... 17 10.2. Normal Operation ................................................................................................... 19 10.3. Line Transient ......................................................................................................... 21 10.4. Load Transient ........................................................................................................ 22 10.5. Brownout Protection ............................................................................................... 23 10.6. Phase Management ................................................................................................. 25 10.7. Efficiency ................................................................................................................ 28 10.8. Harmonic Distortion and Power Factor .................................................................. 29 11. References ......................................................................................................................... 31 12. Ordering Information ........................................................................................................ 31 13. Revision History ............................................................................................................... 31 (c) 2010 Fairchild Semiconductor Corporation 2 FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com The following user guide supports the FAN9611 400-W evaluation board for interleaved boundary-conduction-mode power-factor-corrected supply. It should be used in conjunction with the FAN9611 datasheet as well as the Fairchild application note AN-6086 Design Considerations for Interleaved Boundary-Conduction Mode PFC Using FAN9611 / FAN9612. The evaluation board can be interchangeably used to evaluate either the FAN9611 (10 V turn-on threshold) or FAN9612 controller (12.5 V turn-on threshold). Please visit Fairchild's website at www.fairchildsemi.com for additional information. This Evaluation board can be identified by the top side silkscreen marking "FAN9612 400W INTERLEAVED PFC CONVERTER" and "FEB388". 1. Overview of the Evaluation Board The FAN9611 interleaved dual Boundary-Conduction-Mode (BCM) Power-FactorCorrection (PFC) controllers operate two parallel-connected boost power trains 180 out of phase. Interleaving extends the maximum practical power level of the control technique from about 300 W to greater than 800 W. Unlike the continuous conduction mode (CCM) technique often used at higher power levels, BCM offers inherent zerocurrent switching of the boost diodes (no reverse-recovery losses), which permits the use of less expensive diodes without sacrificing efficiency. Furthermore, the input and output filters can be smaller due to ripple current cancellation between the power trains and doubling of effective switching frequency. The advanced line feedforward with peak detection circuit minimizes the output voltage variation during line transients. To guarantee stable operation with less switching loss at light load, the maximum switching frequency is clamped at 525 kHz. Synchronization is maintained under all operating conditions. Protection functions include output over-voltage, over-current, open-feedback, undervoltage lockout, brownout, and redundant latching over-voltage protection. The FAN9611 is available in a lead-free 16-lead SOIC package. This FAN9611 evaluation board is a four-layer board designed for 400 W (400 V / 1 A) rated power. Thanks to the phase management, the efficiency is maintained above 96% at low-line and high-line, even down to 10% of the rated output power. Efficiency is 96.4% at line voltage 115 VAC and 98.2% at 230 VAC under full-load conditions. (c) 2010 Fairchild Semiconductor Corporation 3 FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com Figure 1. Figure 2. (c) 2010 Fairchild Semiconductor Corporation Top View Bottom View 4 FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com 2. Key Features ZCD1 Low Total Harmonic Distortion, High Power Factor 180 Out-of-Phase Synchronization Automatic Phase Disable at Light Load 1.8-A Sink, 1.0-A Source, High-Current Gate Drivers Transconductance (gM) Error Amplifier for Reduced Overshoot Voltage-Mode Control with (VIN)2 Feed-forward Closed-Loop Soft-Start with Programmable Soft-Start Time for Reduced Overshoot Minimum Restart Timer Frequency to Avoid Audible Noise Maximum Switching Frequency Clamp Brownout Protection with Soft Recovery Non-Latching OVP on FB Pin and Second-Level Latching Protection on OVP Pin Open-Feedback Protection Over-Current and Power-Limit Protection for Each Phase Low Startup Current: 80 A Typical Works with DC Input Voltage and 50-Hz to 400-Hz AC Inputs CHANNEL 1 VALLEY DETECTOR 1 A 16 CS1 15 CS2 14 VDD 13 DRV1 12 DRV2 11 PGND 10 VIN 9 OVP B SYNCHRONIZATION RESTART TIMERS FREQUENCY CLAMPS ZCD2 CHANNEL 2 VALLEY DETECTOR 2 0.2V VDD VDD 5V 5V 5VB 5V BIAS 3 K1 0.195V 2 VIN UVLO IMOT A IMOT MOT 4 R Q S Q R Q S Q A 1.25V 5V 0.195V AGND 2 K1 VIN IMOT 5 B B 5V 5A SS 6 3VREF COMP gm FB INPUT VOLTAGE SENSE (Input Voltage Squarer, Input UVLO, Brownout) 7 Phase Management 2A PROTECTION LOGIC (Open FB, Brownout Protection, OVP, Latched OVP) 8 Figure 3. (c) 2010 Fairchild Semiconductor Corporation Block Diagram 5 FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com 3. Specifications This board has been designed and optimized for the following conditions: Input Voltage Range Rated Output Power Output Voltage (Rated Current) VIN Nominal : 85~264 VAC VDD Supply : 13 VDC~18 VDC 400 W 400 V - 1 A Note: 1. Minimum output voltage during the 20 ms hold-up time is 330 VDC. VLINE = 85~264 VAC VOUT = 400 V fSW > 50 kHz Efficiency > 96% down to 20% load (115 VAC) Efficiency > 97% down to 20% load (230 VAC) PF > 0.99 at full load The trip points for the built-in protections are set as below in the evaluation board. The non-latching output OVP trip point is set at 108% of the nominal output voltage. The latching output OVP trip point is set at 117% of the nominal output voltage. The line UVLO (brownout protection) trip point is set at 68 VAC (10 VAC hysteresis). The pulse-by-pulse current limit for each MOSFET is set at 9.1 A. The maximum power limit is set at ~120% of the rated output power. The phase management function permits phase shedding/adding ~15% of the nominal output power for high line (230 VAC). This level can be programmed by modifying MOT resistor (R6). (c) 2010 Fairchild Semiconductor Corporation 6 FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com 4. Test Procedure Before testing the board; DC voltage supply for VDD, AC voltage supply for line input, and DC electric load for output should be connected to the board properly. 1. Supply VDD for the control chip first. It should be higher than 13 V (refer to the specification for VDD turn-on threshold voltage in Table 1). Table 1. Specification Excerpt from FAN9611 Datasheet Symbol Parameter Conditions Min. Typ. Max. Unit Supply Startup Supply Current VDD = VON - 0.2 V 80 110 A Operating Current Output Not Switching 3.7 5.2 mA Dynamic Operating Current fSW = 50 kHz; CLOAD = 2 nF 4 6 mA VON UVLO Start Threshold VDD Increasing 9.5 10.0 10.5 V VOFF UVLO Stop Threshold VDD Decreasing 7.0 7.5 8.0 V VHYS UVLO Hysteresis VON - VOFF ISTARTUP IDD IDD_DYM 2.5 V 2. Connect the AC voltage (85~265 VAC) to start the FAN9611 / 12 evaluation board. Since FAN9611 / 12 has brownout protection, any input voltages lower than operation range triggers the protection. 3. Change load current (0~1 A) and check the operation. (c) 2010 Fairchild Semiconductor Corporation 7 FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com 5. Schematic Figure 4. (c) 2010 Fairchild Semiconductor Corporation FAN9611 400-W Evaluation Board Schematic 8 FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com 6. Boost Inductor Specification 750312943 from Wurth Electronics Midcom (www.we-online.com/midcom) OR PA2975NL-5P4 from Pulse Electronics (www.pulseelectronics.com) Core: PQ3230 (Ae=161 mm2) Bobbin: PQ3230 Inductance : 200 H 4 Outside NAUX 2 NAUX 3 NBOOST NBOOST Inside 5 Figure 5. Table 2. Boost Inductor used in this FAN9611 / 12 Evaluation Board Inductor Turns Specifications N1 Pin Turns 53 30 24 3 Insulation Tape N2 Insulation Tape (c) 2010 Fairchild Semiconductor Corporation 9 FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com 7. Line Filter Inductor Specifications A : 30 mm (max.) B: 15 mm (max.) C: 11 mm D: 13 mm E: 15 mm Electrical Specifications (1 kHz, 1 V) - Inductance: 9.0 mH (min.) for each winding - DC resistance: 0.05 (max.) for each winding - Number of turns: 0.9 mmx2/30.5 turns for each winding Figure 6. Table 3. Line Filter Inductor Specification Materials List Component Material Manufacturer Core T22x14x08 Core T22x14x08, TOMITA Wire Solder UL File Number THFN-216 Ta Ya Electric Wire Co,. Ltd. E197768 UEWN/U PACIFIC Wire and cable Co., Ltd. E201757 UEWE Tai-1 Electric Wire & Cable Co., Ltd. E85640 UWY Jang Shing Wire Co., Ltd. E174837 96.5%, Sn, 3%, Ag, 0.5% Cu Xin Yuan Co., Ltd. (c) 2010 Fairchild Semiconductor Corporation 10 FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com 8. PCB Layout Figure 7. First Layer (Top Side) Figure 8. (c) 2010 Fairchild Semiconductor Corporation Second Layer (Plane Layer) 11 FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com (c) 2010 Fairchild Semiconductor Corporation Figure 9. Third Layer (Ground Layer) Figure 10. Fourth Layer (Bottom Side) 12 FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com Figure 11. Figure 12. (c) 2010 Fairchild Semiconductor Corporation 13 Top Solder Mask Bottom Solder Mask FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com Figure 13. Figure 14. (c) 2010 Fairchild Semiconductor Corporation 14 Top Silkscreen Bottom Silkscreen FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com 9. Bill of Materials (BOM) Qty. Reference Part Number Value Description Package Type Manufacturer 2 C1 C6 0.22 F CAP, SMD, CERAMIC, 25 V, X7R 805 STD 1 C2 390 nF CAP, SMD, CERAMIC, 25 V, X7R 805 STD 2 C4 C9 150 nF CAP, 400 V, 5%, POLYPROPYLENE Radial, Thru-Hole Panasonic-ECG 1 C5 470 nF CAP, SMD, CERAMIC,25 V, X7R 805 STD 2 C7 C11 C23 B32914A3474 470 nF, 330 V CAP, 330 VAC, 10%, POLYPROPYLENE Box, Thru-Hole EPCOS 2 C8 C13 EETUQ2W221E 220 F CAP, ALUM, ELECT. Radial, Thru-Hole Panasonic 2 C10 C14 2.2 F CAP, SMD, CERAMIC, 25 V, X7R 1206 STD 1 C12 CAP, X SERIES, 250 VAC, 5%, POLYPROPYLENE Box, Thru-Hole Fuhjyyu Electronic Industrial Co. 1 C15 15 nF CAP, SMD, CERAMIC,25 V, X7R 805 STD 1 C16 0.1 F CAP, SMD, CERAMIC, 25 V, X7R 805 STD 1 C18 1 F CAP, SMD, CERAMIC,50 V, X5R 805 STD 1 C19 PHE840MB 6100MB05R17 0.1 F CAP, X TYPE, 275 VAC, 10%, POLYPROPYLENE Box, Axial KEMET 2 C20-21 CS85B2GA471KYNS 470 pF CAP, CERAMIC, 250 VAC, 10%, Y5P, Disc, Thru-hole TDK Corporation 1 C22 CAP, SMD, CERAMIC, 25 V, X7R 805 STD 3 D1 D3-4 S3J Diode, 600 V, 3 A, Std recovery SMC 2 D2 D8 MBR0540 Diode, Schottky,40 V, 500 mA SOD-123 1 D5 GBU8J Bridge Rectifier, 600 V, 8 A Thru-Hole 2 D6-7 ES1J DIODE FAST REC 1 A 600 V SMA 1 D10 MBR0530 DIODE SCHOTTKY 30 V 500 mA SOD-123 SOD-123 Fairchild Semiconductor 1 F1 31.8201 Fuseholder, 5x20 mm, 250 VAC, 10 A PCB mount, Thruhole Schurter Inc 2 H1 H3 534202B33453G 1"x0.475"x1.18" Aavid Thermalloy 1 H2 639BG 1.65"x1.5" Aavid Thermalloy 1 J1 ED100/3DS Thru-hole On Shore Technology, Inc. 14 J2 J8-18 J21-22 3103-1-00-15-0000-08-0 Thru-Hole Mill-Max 3 J3-5 Thru-Hole Custom 2 J6 J19 571-0500 Thru-Hole Deltron 2 J7 J20 571-0100 Thru-Hole Deltron 2 L1-2 2 L3-4 TRN-0197 2 Q1 Q4 2 Q2-3 ECWF2W154JAQ HQX104K275R2 0.1 F, 275 V 1 nF 750312943 PA2975NL-5P4 Heatsink, 13.4C/W, TO-220 with Tab-Koolclip for Q2-3 TO-220 Heat sink for D5, Bridge Rectifier Terminal Block, 5 mm Vert., 3 Pos. Probe-pin, Gold, 0.3" x 40mil dia., 31mil mounting length Jumper wire, #16, Insulated, for current probe measurement Banana Jack, .175, Horizontal, Insulated_RED Banana Jack, .175, Horizontal, Insulated_BLK 200 H Coupled Inductor, PQ3230, Pri-30T, Thru-Hole Sec-3T Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Wurth Midcom Pulse Electronics Common Mode Choke Thru-Hole SEN HUEI INDUSTRIAL CO.,LTD ZXTP25020DFL Transistor, PNP, 20 V, 1.5 A SOT-23 Zetex FDPF18N50 MOSFET, NCH, 500 V, 18 A, 0.265 TO-220 Fairchild Semiconductor (c) 2010 Fairchild Semiconductor Corporation 15 FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com BOM (Continued) Qty. Reference 2 R1-2 6 R3 R9 R2728 R33-34 1 R4 1 1 2 Part Number Value Description Package Type Manufacturer 47 k RES, SMD, 1/8 W 805 STD 665 k RES, SMD, 1/8 W 805 STD 332 k RES, SMD, 1/8 W 805 STD R5 68 k RES, SMD, 1/8 W 805 STD R6 100 k RES, SMD, 1/8 W 805 STD R7-8 340 k RES, SMD, 1/8 W 805 STD 2 R10 R20 100 RES, SMD, 1/8 W 805 STD 2 R11-12 15 RES, SMD, 1/8 W 805 STD 1 R15 DNP RES, SMD, 1/8 W 805 STD 1 R16 49.9 RES, SMD, 1/8 W 805 STD 1 R17 0 RES, SMD, 1/2 W 2010 STD 1 R18 Thermistor, 5 Thru-Hole EPCOS RES, SMD, 1/8 W 805 STD LOCKING BOARD SUPPORT 3/4", 1 for each PCB corner Standoff Richco Plastic Company B57237S0509M000 1 R19 4 1 inserted into each corner of PCB LCBS-12-01 1 1 at D5, H2 3103 1 1 1 at D5, H2 1 at D5, H2 MLWZ 003 HNZ440 1 1 at D5, H2 PMS 440 0050 PH 1 PWB FAN9611/12 FEB388 Rev. 0.0.1 5 14.7 k Nylon Shoulder Washer #4x0.187", Black Split Lock Washer, Metric M 3 Zinc Nut Hex, #4-40 Zinc Screw Machine Phillips, 4-40x1/2" Zinc Washer Nut Keystone Electronics B&F Fastener B&F Fastener Screw B&F Fastener Washer FEB388 PWB, 9.8" x 6.8" PWB Fairchild Semiconductor 2 R1-2 47 k RES, SMD, 1/8 W 805 STD 6 R3 R9 R2728 R33-34 665 k RES, SMD, 1/8 W 805 STD 1 R4 332 k RES, SMD, 1/8 W 805 STD 1 R5 68 k RES, SMD, 1/8 W 805 STD 1 R6 100 k RES, SMD, 1/8 W 805 STD 2 R7-8 340 k RES, SMD, 1/8 W 805 STD 2 R10 R20 100 RES, SMD, 1/8 W 805 STD 2 R11-12 15 RES, SMD, 1/8 W 805 STD 2 R13-14 0.022 RES, SMD, 1/2 W 1812 STD 1 R15 DNP RES, SMD, 1/8 W 805 STD 1 R16 49.9 RES, SMD, 1/8 W 805 STD 1 U1 Interleaved Dual-BCM PFC Controller SOIC-16 Fairchild Semiconductor FAN9611 Note: 2. DNP = Do not populate. STD = standard components. (c) 2010 Fairchild Semiconductor Corporation 16 FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com 10. Test Results 10.1. Startup Figure 15 and Figure 16 show the startup operation at 115 VAC line voltage for no-load and full-load condition, respectively. Due to the closed-loop soft-start, almost no overshoot is observed for no-load startup and full-load startup. Gate Drive 1 COMP Voltage Output Voltage Line Current CH1: Gate Drive 1 Voltage (20 V / div), CH2: COMP Voltage (2 V / div), CH3: Output Voltage (200 V / div), CH4: Line Current (5 A / div), Time (100 ms / div) Figure 15. No-Load Startup at 115 VAC Gate Drive 1 COMP Voltage Output Voltage Line Current CH1: Gate Drive 1 Voltage (20 V / div), CH2: COMP Voltage (2 V / div), CH3: Output Voltage (200 V / div), CH4: Line Current (10 A / div), Time (200 ms / div) Figure 16. (c) 2010 Fairchild Semiconductor Corporation Full-Load Startup at 115 VAC 17 FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com Figure 17 and Figure 18 show the startup operation at 230 VAC line voltage for no-load and full-load conditions, respectively. Due to the closed-loop soft-start, almost no overshoot is observed for no-load startup and full-load startup. Gate Drive 1 COMP Voltage Output Voltage Line Current CH1: Gate Drive 1 Voltage (20 V / div), CH2: COMP Voltage (2 V / div), CH3: Output Voltage (200 V / div), CH4: Line Current (5 A / div), Time (100 ms / div) Figure 17. No-Load Startup at 230 VAC Gate Drive 1 COMP Voltage Output Voltage Line Current CH1: Gate Drive 1 Voltage (20 V / div), CH2: COMP Voltage (2 V / div), CH3: Output Voltage (200 V / div), CH4: Line Current (5 A / div), Time (100 ms / div) Figure 18. (c) 2010 Fairchild Semiconductor Corporation Full-Load Startup at 230 VAC 18 FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com 10.2. Normal Operation Figure 19 and Figure 20 show the two inductor currents and sum of two inductor currents at 115 VAC line voltage and full-load conditions. The sum of the inductor currents has relatively small ripple due to the ripple cancellation of interleaving operation. IL1 IL2 IL1 + IL2 CH3: Inductor L1 Current (5 A / div), CH4: Inductor L2 Current (5 A / div), F1: Sum of Two Inductor Current (5 A / div), Time (2 ms / div) Figure 19. Inductor Current Waveforms at Full-Load and 115 VAC IL1 IL2 IL1 + IL2 CH3: Inductor L1 Current (5 A / div), CH4: Inductor L2 Current (5 A / div), F1: Sum of Two Inductor Current (5 A / div), Time (5 s / div) Figure 20. Zoom of Inductor Current Waveforms of Figure 19 at Peak of Line Voltage (c) 2010 Fairchild Semiconductor Corporation 19 FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com Figure 21 and Figure 22 show the two inductor currents and sum of two inductor currents at 230 VAC line voltage and full-load conditions. The sum of the inductor currents has relatively small ripple due to the ripple cancellation of interleaving operation. IL1 IL2 IL1 + IL2 CH3: Inductor L1 Current (2 A / div), CH4: Inductor L2 Current (2 A / div), F1: Sum of Two Inductor Current (2 A / div), Time (2 ms / div) Figure 21. Inductor Current Waveforms at Full-Load and 230 VAC IL1 IL2 IL1 + IL2 CH3: Inductor L1 Current (2 A / div), CH4: Inductor L2 Current (2 A / div), F1: Sum of Two Inductor Current (2 A / div), Time (2 s / div) Figure 22. Zoom of Inductor Current Waveforms of Figure 21 at Peak of Line Voltage (c) 2010 Fairchild Semiconductor Corporation 20 FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com 10.3. Line Transient Figure 23 and Figure 24 show the line transient operation and minimal effect on output voltage due to the line feed-forward function. When the line voltage changes from 230 VAC to 115 VAC, about 20 V (5% of nominal output voltage) voltage undershoot is observed. When the line voltage changes from 115 VAC to 230 VAC, almost no voltage undershoot is observed. Rectified Line Voltage VCOMP VOUT Line Current CH1: Rectified Line Voltage (100 V / div), CH2: COMP Voltage (2 V / div), CH3: Output Voltage (100 V / div), CH4: Line Current (5 A / div), Time (50 ms / div) Figure 23. Line Transient Response at Full-Load Condition (230 VAC 115 VAC) Rectified Line Voltage VCOMP VOUT Line Current CH1: Rectified Line Voltage (100 V / div), CH2: COMP Voltage (2 V / div), CH3: Output Voltage (100 V / div), CH4: Line Current (5 A / div), Time (50 ms / div) Figure 24. Line Transient Response at Full-Load Condition (115 VAC 230 VAC) (c) 2010 Fairchild Semiconductor Corporation 21 FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com 10.4. Load Transient Figure 25 and Figure 26 show the load-transient operation. When the output load changes from 100% to 0%, 26 V (6.5% of nominal output voltage) voltage overshoot is observed. When the output load changes from 0% to 100%, 43 V (11% of nominal output voltage) voltage undershoot is observed. VOUT Rectified Line Voltage Line Current CH2: Rectified line voltage (100 V / div), CH3: Output voltage (100 V / div), CH4: Line current (5 A / div), Time (50 ms / div) Figure 25. Load Transient Response at 230 VAC (Full Load No Load) VOUT Rectified Line Voltage Line Current CH2: Rectified Line Voltage (100 V / div), CH3: Output Voltage (100 V / div), CH4: Line Current (5 A / div), Time (50 ms / div) Figure 26. Load Transient Response at 230 VAC (No Load Full Load) (c) 2010 Fairchild Semiconductor Corporation 22 FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com 10.5. Brownout Protection Figure 27 and Figure 28 show the startup operation at slowly increasing line voltage. The power supply starts up when the line voltage reaches around 78 VAC. Line Voltage Gate Drive 1 Line Current CH1: Line Voltage (100 V / div), CH2: Gate Drive 1 Voltage (20 V / div), CH4: Line Current (5 A / div), Time (200 ms / div) Figure 27. Startup Slowly Increasing the Line Voltage Line Voltage Gate Drive 1 Line Current CH1: Line Voltage (100 V / div), CH2: Gate Drive 1 Voltage (20 V / div), CH4: Line Current (5 A / div), Time (20 ms / div) Figure 28. (c) 2010 Fairchild Semiconductor Corporation Shutdown Slowly Decreasing the Line Voltage 23 FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com Figure 29 and Figure 30 show the shutdown operation at slowly decreasing line voltage. The power shuts down when line voltage drops below 68 VAC. Line Voltage Gate Drive 1 Line Current CH1: Line Voltage (100 V / div), CH2: Gate Drive 1 Voltage (20 V / div), CH4: Line Current (5 A / div), Time (200 ms / div) Figure 29. Startup Slowly Increasing the Line Voltage Line Voltage Gate Drive 1 Line Current CH1: Line Voltage (100 V / div), CH2: Gate Drive 1 Voltage (20 V / div), CH4: Line Current (5 A / div), Time (20 ms / div) Figure 30. (c) 2010 Fairchild Semiconductor Corporation Shutdown Slowly Decreasing the Line Voltage 24 FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com 10.6. Phase Management Figure 31 and Figure 32 show the phase-shedding waveforms. As observed, when the gate drive signal of Channel 2 is disabled, the duty cycle of Channel 1 gate drive signal is doubled to minimize the line current glitch and guarantee smooth transient. Gate Drive 1 Gate Drive 2 IL1 IL2 CH1: Gate Drive 1 Voltage (20 V / div), CH2: Gate Drive 2 Voltage (20 V / div), CH3: Inductor L1 Current (1 A / div), CH4: Inductor L2 Current (1 A / div), Time (5 ms / div) Figure 31. Phase-Shedding Operation Gate Drive 1 Gate Drive 2 IL1 IL2 CH1: Gate Drive 1 Voltage (20 V / div), CH2: Gate Drive 2 Voltage (20 V / div), CH3: Inductor L1 Current (1 A / div), CH4: Inductor L2 Current (1 A / div), Time (5 s / div) Figure 32. (c) 2010 Fairchild Semiconductor Corporation Phase-Shedding Operation (Zoomed-in Timescale) 25 FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com Figure 33 and Figure 34 show the phase-adding waveforms. As observed, just before the Channel 2 gate drive signal is enabled, the duty cycle of Channel 1 gate drive signal is halved to minimize the line current glitch and guarantee smooth transient. In Figure 34, the first pulse of gate drive 2 during the phase-adding operation is skipped to ensure 180 degrees out-of-phase interleaving operation during transient. Gate Drive 1 Gate Drive 2 IL1 IL2 CH1: Gate Drive 1 Voltage (20 V / div), CH2: Gate Drive 2 Voltage (20 V / div), CH3: Inductor L1 Current (1 A / div), CH4: Inductor L2 Current (1 A / div), Time (5 ms / div) Figure 33. Phase-Adding Operation Gate Drive 1 Gate Drive 2 IL1 IL2 CH1: Gate Drive 1 Voltage (20 V / div), CH2: Gate Drive 2 Voltage (20 V / div), CH3: Inductor L1 Current (1 A / div), CH4: Inductor L2 Current (1 A / div), Time (5 s / div) Figure 34. (c) 2010 Fairchild Semiconductor Corporation Phase-Adding Operation (Zoomed-in Timescale) 26 FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com Figure 35 and Figure 36 show the sum of two-inductor current and line current for phase shedding and adding, respectively. The small line-current glitch during phase management exists because the actual average value of inductor current is less than half of the peak value due to the negative portion of inductor current, as shown in Figure 32 and Figure 34. However, the phase management takes place at relatively light-load condition and the effect of this phenomenon is negligible. Gate Drive 1 Gate Drive 2 IL1 + IL1 Line Current CH1: Gate Drive 1 Voltage (20 V / div), CH2: Gate Drive 2 Voltage (20 V / div), CH3: Sum of Two Inductor Currents (1 A / div), CH4: Line Current (1 A / div), Time (5 ms / div) Figure 35. Phase Shedding and Line Current Gate Drive 1 Gate Drive 2 IL1 + IL1 Line Current CH1: Gate Drive 1 Voltage (20 V / div), CH2: Gate Drive 2 Voltage (20 V / div), CH3: Sum of Two Inductor Currents (1 A / div), CH4: Line Current (1 A / div), Time (5 ms / div) Figure 36. (c) 2010 Fairchild Semiconductor Corporation Phase Adding Operation and Line Current 27 FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com 10.7. Efficiency Figure 37 through Figure 40 show the measured efficiency of the 400 W evaluation board with and without phase management at input voltages of 115 VAC and 230 VAC. Phase management improves the efficiency at light load by up to 7%, depending on the line voltage and load condition. The phase management thresholds on the test evaluation board are around 15% of the nominal output power (Figure 37 and Figure 38). They can be adjusted upwards to achieve a more desirable efficiency profile (Figure 39 and Figure 40) by increasing the MOT resistor. Since phase shedding reduces the switching loss by effectively decreasing the switching frequency at light load, a greater efficiency improvement is achieved at 230 VAC, where switching losses dominate. Relatively less improvement is obtained at 115 VAC since the MOSFET is turned on with zero voltage and switching losses are negligible. Efficiency vs. Load Efficiency vs. Load (115 V AC Input, 400 V DC Output, 400W) (230 V AC Input, 400 VDC Output, 400W) 100 100 95 95 Efficiency (%) Efficiency (%) The efficiency measurements include the losses in the EMI filter as well as cable loss; however, the power consumption of the control IC (<< 1 W) is not included since an external power supply is used for VDD. With Phase Management With Phase Management 90 90 Without Phase Management Without Phase Management 85 85 0 10 20 30 40 50 60 70 80 90 0 100 10 20 30 40 Figure 37. 50 60 70 80 90 100 Output Power (%) Output Power (%) Measured Efficiency at 115 VAC (Default Thresholds) Figure 38. Measured Efficiency at 230 VAC (Default Thresholds) Efficiency vs. Load Efficiency vs. Load (115 VAC Input, 400 VDC Output, 400 W) (230 VAC Input, 400 VDC Output, 400 W) 100 100 Efficiency (%) Efficiency (%) 95 95 With Phase Management With Phase Management 90 90 Without Phase Management Without Phase Management 85 85 0 10 20 30 40 50 60 70 80 90 0 100 10 Figure 39. Measured Efficiency at 115 VAC (Adjusted Thresholds) (c) 2010 Fairchild Semiconductor Corporation 20 30 40 50 60 70 80 90 100 Output Power (%) Output Power (%) Figure 40. 28 Measured Efficiency at 230 VAC (Adjusted Thresholds) FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com 10.8. Harmonic Distortion and Power Factor Figure 41 and Figure 42 compare the measured harmonic current with EN61000 class D and C, respectively, at input voltages of 115 VAC and 230 VAC. Class D is applied to TV and PC power, while Class C is applied to lighting applications. As can be observed, both regulations are met with sufficient margin. EN61000 Class-D 1.4 1.2 Harmonic Current (A) 1.0 EN61000-D 0.8 115 Vac 230 Vac 0.6 0.4 0.2 0.0 3 7 11 15 19 23 27 31 35 39 Harmonic Order Figure 41. Measured Harmonic Current and EN61000 Class-D Regulation EN61000 Class-C 30% Harmonic Current (% of Fundamental Current) 25% EN61000-C 20% 115 Vac 230 Vac 15% 10% 5% 0% 3 7 11 15 19 23 27 31 35 39 Harmonic Order Figure 42. Measured Harmonic Current and EN61000 Class-C Regulation (c) 2010 Fairchild Semiconductor Corporation 29 FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com Figure 43 shows the measured power factors at input voltage of 115 VAC and 230 VAC. As observed, high power factor above 0.98 is obtained from 100% to 50% load. Table 4 shows the total harmonic distortion at input voltages of 115 VAC and 230 VAC. Power Factor vs. Load 100 Power Factor (%) 95 115 Vac 230 Vac 90 85 80 0 20 40 60 80 100 Output Power (%) Figure 43. Table 4. Measured Power Factor Total Harmonic Distortion (THD) Line Voltage 100% Load 75% Load 50% Load 25% Load 115 VAC 9.68% 11.82% 15.87% 24.08% 230 VAC 11.36% 12.95% 15.30% 16.81% (c) 2010 Fairchild Semiconductor Corporation 30 FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com 11. References FAN9611- Interleaved Dual BCM PFC Controller -Product Folder FAN9612- Interleaved Dual BCM PFC Controller -Product Folder AN-6086 - "Design Consideration for interleaved Boundary Conduction Mode (BCM) PFC Using FAN9611 / FAN9612" 12. Ordering Information Orderable Part Number Description FEBFAN9611_S388V1 FAN9611 400 W Evaluation Board 13. Revision History Date Rev. # Description May 2013 0.0.5 Initial release/replacing AN-9717 (FEB388-001) December 2014 0.0.6 Updated links (c) 2010 Fairchild Semiconductor Corporation 31 FEBFAN9611_S388V1 * Rev. 0.0.6 www.fairchildsemi.com (c) 2010 Fairchild Semiconductor Corporation 32 FEBFAN9611_S388V1 * Rev. 0.0.6 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Fairchild Semiconductor: FEBFAN9611_S388V1