AK4393VF - AKM Semiconductor, Inc.

ASAHI KASEI [AK4393]

M0039-E-01 2000/5

- 1 -

GENERAL DESCRIPTI ON

The AK4393 is a high performance stereo DAC for the 96kHz sampling mode of DAT, DVD including a

24bit digital filter. The AK4393 int roduces the advanced multi-bit system for DS modulator. This new

architecture achieves t he wider dynamic range, while keeping much the same superior distortion

characteristics as convent ional Single-Bit way. In the AK4393, the analog output s are filtered in the

analog domain by switched-capacitor filt er (SCF) with high tolerance to clock jitter. The analog out put s

are full differential output, so the device is suitable for hi-end applications. The operating voltages support

analog 5V and digital 3.3V, so it is easy to I/ F w it h 3.3V logic IC.

FEATURES

· 128x Oversampling

· Sampling Rate up to 108kHz

· 24Bit 8x Digital Filter

Ripple: ±0.005dB, Attenuation: 75dB

· High Tolerance to Cl ock Ji tter

· Low Distorti on Di f ferentia l Output

· Digital de-emphasi s for 32, 44.1, 48 & 96kHz sampling

· Soft Mute

· THD+N: -100dB

· DR, S/N: 120dB

· I/F format : MSB justified, 16/20/24bit LSB justified, I2S

· Master Clock: Normal Speed: 256fs, 384fs, 512fs or 768fs

Double Speed: 128fs, 192fs, 256fs or 384fs

· Power Supply: 4.75 to 5.25V (Anal og), 3 to 5.25V (Digital)

· Small Package: 28pin VSO P

DEM1

LRCK

BICK

SDAT

Audio Data

Interface

DEM0DVDD

CSN

AVDD

AOUTR+

Interpolator SCF

Modulator

AOUTR-

SCF

De-emphasis

Soft Mute

Control Register Clock Divider

De-emphasis

Control

PDN

CCLK CDTI P/S MCLK CKS0 CKS1 CKS2 VREFH VREFL

AOUTL+

AOUTL-

VCOM

BVSS

AVSSDVSS

DIF2DIF1DIF0

SMUTE De-emphasis

Soft Mute 8x

Interpolator DS

Modulator

DFS

Advanced Multi-Bit 96kHz 24-Bit DS DAC

AK4393

ASAHI KASEI [AK4393]

M0039-E-01 2000/5

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n Ordering Guide

AK4393VF -40 ~ +85 °C 28pin VSOP (0.65mm pitch)

AKD4393 Evaluation Board

n Pin Layout

DVSS

DVDD

PDN

MCLK

BICK

SDATA

LRCK 7

SMUTE/CSN 8

CKS2

CKS1

CKS0

P/S

VCOM

AOUTL+

AOUTL-

AOUTR+

Top

View

DFS

DEM0/CCLK

DEM1/CDTI 11

DIF0 12

AOUTR-

AVSS

AVDD

VREFH

DIF1

DIF2

VREFL

BVSS

ASAHI KASEI [AK4393]

M0039-E-01 2000/5

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PIN/FUNCTION

No. Pin Name I/O Function

1 DVSS - Digital Ground Pin

2 DVDD - Digital Power Supply Pin, 3.3V or 5.0V

3 MCLK I Master Clock Input Pin

4PDN I Power-Down Mode Pin

When at “L”, the AK4393 is in power-down mode and is held in reset.

The AK4393 should always be reset upon power-up.

5BICK I Audio Serial Data Clock Pin

The clock of 64fs or more than is recommended to be input on this pin.

6SDATA I Audio Serial Data Input Pin

2’s complement MSB-first data is input on this pin.

7 LRCK I L/R Cloc k Pin

SMUTE I Soft Mute Pin in pa rallel mode

When this pin goes "H", soft mute cycle is initiated.

When returning “L”, the output mute releases.

CSN I Chip Select Pin in serial mode

9DFS I Double Speed Sampling Mode Pin (Internal pull-down pin)

“L”: Normal Speed , “H”: Double Speed

DEM0 I De-emphasis Enable Pin in parallel mode

10 CCLK I Control Data Clock Pin in serial mode

DEM1 I De-emphasis Enable Pin in parallel mode

11 CDTI I Control Data Input Pin in serial mode

12 DIF0 I Digital Input Format Pin

13 DIF1 I Digital Input Format Pin

14 DIF2 I Digital Input Format Pin

15 BVSS - Substrate Ground Pin, 0V

16 VREFL I Low Level Voltage Reference Input Pin

17 VREFH I Hi gh Level Volta ge Reference Input Pin

18 AVDD - Analog Power Supply Pin, 5.0V

19 AVSS - Ana log Ground Pin, 0V

20 AOUTR- O Rch Negative analog output Pin

21 AOUTR+ O Rch Positive analog output Pin

22 AOUTL- O Lch Negative analog output Pin

23 AOUTL+ O Lch Positive analog o utput Pin

24 VCOM O Common Voltage Output Pin, 2.6V

25 P/S I Parallel/Serial Select Pin (Internal pull-up pin)

“L”: Serial control mode, “H”: Parallel control mode

26 CKS0 I Master Clock Select Pin

27 CKS1 I Master Clock Select Pin

28 CKS2 I Master Clock Select Pin

Note: All input pins except internal pull-up/down pins should no t be left floating.

ASAHI KASEI [AK4393]

M0039-E-01 2000/5

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ABSOLUTE MA XIMUM RATINGS

(AVSS, BVSS, DVSS = 0V; Note 1)

Parameter Symbol min max Units

Power Supplies: Analog

Digital

| BVSS-DVSS | (Note 2)

AVDD

DVDD

D GND

-0.3

6.0

0.3

Input Current , Any pin Except Supplies IIN - ±10 mA

Input Voltage VIND -0.3 DVDD+0.3 V

Ambient Operating Temperature Ta -40 85 °C

Storage Temperature Tstg -65 150 °C

Notes: 1. All voltages with respect to ground.

2. AVSS, BVSS and DVSS must be connected to the same analog ground plane.

WARNING: Operation at or be yond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDI TIONS

(AVSS, BVSS, DVSS=0V; Note 1)

Parameter Symbol min typ max Units

Power Supplies:

(Note 3) Analog

Digital AVDD

DVDD 4.75

3.0 5.0

3.3 5.25

5.25 V

Voltage Reference

(Note 4) “H” vo ltage reference

“L” volta ge reference

VREFH-VREFL

VREFH

VREFL

D VREF

AVDD-0.5

AVSS

3.0

AVDD

Notes: 3. The power up sequence between AVDD and DVDD is not critical.

4. Analog output voltage scales with the voltage of (VREFH-VREFL).

AOUT (typ.@0dB) = (AOUT+) - (AOUT-) = ±2.4Vpp×(VREFH-VREFL)/5.

* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.

ASAHI KASEI [AK4393]

M0039-E-01 2000/5

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ANALOG CHARACTERISTI CS

(Ta = 25°C; AVDD = 5V, DVDD = 3.3V; AVSS, BVSS, DVSS = 0V, VREFH = AVDD, VREFL = AVSS;

fs = 44.1kHz; BICK = 64fs; Signal Frequency = 1kHz; 24bit Input Data; Measurement Bandwidth = 20Hz~20kHz;

RL ³ 600W; External circuit: Figure 11 ; unless o therwise specified)

Parameter min typ max Units

Resolution 24 Bits

Dynamic Characteristics (Note 5)

fs=44.1kHz

BW=20kHz 0dBFS

-60dBFS -100

-53 -90

-dB

THD+N

fs=96kHz

BW=40kHz 0dBFS

-60dBFS -97

-51 -86

-dB

fs=44.1kHz (Note 6)

(Note 7) 112

-117

120 dB

Dynamic Range

(-60dBFS with A-weighted) fs=96kHz

(Note 7) 111

-116

118 dB

fs=44.1kHz (Note 8)

(Note 7) 112

-117

120 dB

S/N (A-weighted

fs=96kHz

(Note 7) 111

-116

118 dB

Interchannel Isolation (1kHz) 100 120 dB

DC Accuracy

Interchannel Gain Mismatch 0.15 0. 3 dB

Gain Drift (Note 9) 20 - ppm/°C

Output Voltage (Note 10) ±2.25 ±2.4 ±2.55 Vpp

Load Resistance (Note 11) 600 W

Output Current 3.5 mA

Power Supplies

Power Supply Current

Normal Operation (PDN = “H”)

AVDD

DVDD(fs=44.1kHz)

DVDD(fs=96kHz)

AVDD + DVDD

Power-Down Mode (PDN = “L”)

AVDD + DVDD (Note 12) 10 50 µA

Power Supply Rejection (Note 13) 50 dB

Notes: 5. At 44.1kHz, measured by Audio Precision, System Two. Averaging mode.

At 96kHz, measured by ROHDE & SCHWARZ, UPD. Averaging mode.

Refer to the eva board manual.

6. 101dB at 16bit data and 116dB at 20bit data.

7. By Figure12. External LPF Circuit Example 2.

8. S/N does not depend on input bit length.

9. The voltage on (VREFH-VREFL) is held +5V externally.

10. Full-scale voltage (0dB). Output voltage scales with the voltage of (VREFH-VREFL).

AOUT (typ.@0dB) = (AOUT+) - (AOUT-) = ±2.4Vpp×(VREFH-VREFL)/5.

11. For AC-load. 1kW for DC-load.

12. In the power-down mode. P/S = DVDD, and all other digital input pins including clock pins (MCLK, BICK and

LRCK) are held DVSS.

13. PSR is applied to AVDD, DVDD with 1kHz, 100mVpp. VREFH pin is held +5V.

ASAHI KASEI [AK4393]

M0039-E-01 2000/5

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FILTER CHARACTERISTI CS ( f s = 44.1kHz)

(Ta = 25°C; AVDD = 4.75~5.25V; DVDD = 3.0~5.25V; fs = 44.1kHz; Normal Speed Mode; DEM = OFF)

Parameter Symbol min typ max Units

Digital Filter

Passband ±0.01dB (Note 14)

-6.0dB PB 0

- 22.05 20.0

-kHz

kHz

Stopband (Note 14) SB 24.1 kHz

Passband Ripple PR ± 0.005 dB

Stopband Attenuation SA 75 dB

Group Delay (Note 15) GD - 28 - 1/fs

Digital Filter + SCF

Frequency Response 0 ~ 20.0kHz - ± 0.2 - dB

Note: 14. The passband and stopband frequencies scale with fs.

For example, PB = 0.4535×fs (@±0.01dB), SB = 0.546×fs.

15. The calculating delay time which occurred by digital filtering. This time is from setting the 16/20/24bit data of

both channels to inp ut register to the output of analog signal.

FILTER CHARACTERISTI CS (fs = 96kHz)

(Ta = 25°C; AVDD = 4.75~5.25V; DVDD = 3.0~5.25V; fs = 96kHz; Double Speed Mode; DEM = OFF)

Parameter Symbol min typ max Units

Digital Filter

Passband ±0.01dB (Note 14)

-6.0dB PB 0

- 48.0 43.5

-kHz

kHz

Stopband (Note 14) SB 52.5 kHz

Passband Ripple PR ± 0.005 dB

Stopband Attenuation SA 75 dB

Group Delay (Note 15) GD - 28 - 1/fs

Digital Filter + SCF

Frequency Response 0 ~ 40.0kHz - ± 0.3 - dB

DC CHARACTERISTICS

(Ta = 25°C; AVDD = 4.75~5.25V; DVDD = 3.0~5.25V)

Parameter Symbol min typ max Units

High-Level Input Voltage

Low-Level Input Voltage VIH

VIL 70%DVDD

30%DVDD V

Input Leakage Current (Note 16) Iin - - ± 10 µA

Note: 16. DFS and P/S pins have internal pull-down or pull-up devices, nominally 100kW.

ASAHI KASEI [AK4393]

M0039-E-01 2000/5

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SWITCHING CHARACTERISTI CS

(Ta = 25°C; AVDD = 4.75~5.25V; DVDD = 3.0~5.25V; CL = 20pF)

Parameter Symbol min typ max Units

Master Clock Timing

Normal Speed: 256fs, Double Speed: 128fs

Pulse Width Low

Pulse Width Hi gh

fCLK

tCLKL

tCLKH

7.7

13.824 MHz

Normal Speed: 384fs, Double Speed: 192fs

Pulse Width Low

Pulse Width Hi gh

fCLK

tCLKL

tCLKH

11.5

20.736 MHz

Normal Speed: 512fs, Double Speed: 256fs

Normal Speed: 768fs, Double Speed: 384fs

Pulse Width Low

Pulse Width Hi gh

fCLK

tCLKL

tCLKH

15.4

23.0

27.648

41.472 MHz

MHz

LRCK Frequency (Note 17)

Normal Speed Mode (DFS = “L”)

Double Speed Mode (DFS = “H”)

Duty Cycle

fsn

fsd

Duty

44.1

88.2 54

108

kHz

Serial Interface Timing

BICK Period

BICK Pulse Width Low

Pulse Width High

BICK “” to LRCK Edge (Note 18)

LRCK Edge to BICK “” (Note 18)

SDATA Hold Time

SDATA Setup Time

tBCK

tBCKL

tBCKH

tBLR

tLRB

tSDH

tSDS

140

Control Interface Timing

CCLK Period

CCLK Pulse Width Low

Pulse Width High

CDTI Setup Time

CDTI Hold Time

CSN High Time

CSN “¯” to CCLK “”

CCLK “” to CSN “”

tCCK

tCCKL

tCCKH

tCDS

tCDH

tCSW

tCSS

tCSH

200

150

Reset Timing

PDN Pulse Width (Note 19) tP W 150 ns

Notes: 17. When the normal and double speed modes are switched, AK4393 should be reset by PDN pin or RSTN bit.

18. BICK rising edge must not occur at the same time as LRCK edge.

19. The AK4393 can be reset by bringing PDN “L” to “H”.

When the states of CKS2-0 or DFS change, the AK4393 should be reset by PDN pin or RSTN bit.

ASAHI KASEI [AK4393]

M0039-E-01 2000/5

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n Timi ng Diagram

1/fCLK

tCLKL

50%DVDD

tCLKH

MCLK

1/fns,1/fds

50%DVDD

LRCK

tBCK

tBCKL

50%DVDD

tBCKH

BICK

Clock Timing

tLRB

LRCK

BICK

tSDS

SDATA

tSDH

50%DVDD

tBLR

50%DVDD

Audio Interface Timing

ASAHI KASEI [AK4393]

M0039-E-01 2000/5

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tCSS

CSN

CCLK

CDTI

50%DVDD

C1 C0 R/W A4

tCCKL tCCKH

tCDS tCDH

50%DVDD

WRITE Command Input Timing

CSN

CCLK

CDTI

50%DVDD

D3 D2 D1 D0

tCSW

tCSH

50%DVDD

WRITE Data Input Timing

tPW

30%DVDD

PDN

Power-down Timing

ASAHI KASEI [AK4393]

M0039-E-01 2000/5

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OPERATION OVERVIEW

n System Clock

The external clocks, which are required to operate the A K4393, are MCL K, L RCK an d BICK. The m aster clock (MCL K)

should be synchronized with LRCK but the phase is not critical. The MCLK is used to o perate the digital interpolation

filter and the delta-sigma modulator. The sampling speed is set by DFS (Table 1 ) . The sampling rate (LRCK), CKS0/1/2

and DFS determine the frequency of MCLK (Table 2).

All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4393 is in normal operation

mode (PDN = “H”). If these clocks are not provided, the AK4393 may draw excess current because the device utilizes

dyn amic refresh ed log ic in tern ally. If th e ex ternal clocks are n ot presen t, th e A K4393 sh ou ld be in th e power- down mode

(PDN = “L”) or in the reset m ode (RSTN = “0”). A fter exitin g reset at pow er-u p etc., the AK4393 is in power- down m ode

until MCLK and LRCK are input.

DFS Sampling Rate (fs)

0 Normal Speed Mode 30kHz~54kHz Default

1 Double Speed Mode 60kHz~108kHz

Table 1. Sampling Speed

Mode CKS2 CKS1 CKS0 Normal Double

0 0 0 0 256fs 128fs Default

1 0 0 1 256fs 256fs

2 0 1 0 384fs 192fs

3 0 1 1 384fs 384fs

4 1 0 0 512fs 256fs

5 1 0 1 512fs N/A

6 1 1 0 768fs 384fs

7 1 1 1 768fs N/A

Table 2. System Clocks

LRCK MCLK BICK

fs 256fs 384fs 512fs 768fs 64fs

32.0kHz 8.1920MHz 12.2880MHz 16.3840MHz 24.5760MHz 2.0480MHz

44.1kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz 2.8224MHz

48.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz 3.0720MHz

Table 3. System clock example (Normal Speed Mode)

LRCK MCLK BICK

fs 128fs 192fs 256fs 384fs 64fs

88.2kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz 5.6448MHz

96.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz 6.1440MHz

Table 4. System clock example (Double Speed Mode)

ASAHI KASEI [AK4393]

M0039-E-01 2000/5

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n Audio Serial I nterface Format

Data is shifted in via the SDATA pin using BICK and LRCK inputs. Five data formats are supported and selected by the

DIF0-2 as shown in Table 5. In all formats the serial data is MSB-first, 2's complim ent f orm at and is latched on the rising

edge of BICK. Mode 2 can be used for 20 and 16 MSB j ustified formats by zeroing the unused LSBs.

Mode DIF2 DIF1 DIF0 Mode BICK Figure

0 0 0 0 0: 16b it LSB Justified ³32fs Figure 1

1 0 0 1 1: 20b it LSB Justified ³40fs Figure 2

2 0 1 0 2: 24bit MSB Justified ³48fs Figure 3

30113: I

2S Compatible ³48fs Figure 4

4 1 0 0 4: 24b it LSB Justified ³48fs Figure 2

Table 5. Audio Data Formats

SDATA

BICK

LRCK

SDATA 15 14 6 5 4

BICK

0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1

3210 1514

(

32fs

)

(

64fs

)

014

115 16 17 31 0 1 14 15 16 17 31 0 1

15 14 0 15 14 0

Mode 0 Don’t care Don’t care

15:MSB, 0:LSB

Mode 0 15 14 6 5 4 3 2 1 0

Lch Data Rch Data

Figure 1. Mode 0 Timing

SDATA

LRCK

BICK

(

64fs

)

091 10 11 12 31 0 1 9 10 11 12 31 0 1

19 0 19 0

Mode 1 Don’t care Do n ’t care

19:MSB, 0:LSB

SDATA

Mode 4 23:MSB, 0:LSB

20 19 0 20 19 0

Do n’t care Don’t care

22 21 22 21

Lch Data Rch Data

23 23

Figure 2. Mode 1,4 Timing

ASAHI KASEI [AK4393]

M0039-E-01 2000/5

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LRCK

BICK

(

64fs

)

SDATA

0221 2 24 31 0 1 31 0 1

23:MSB, 0:LSB

22 1 0 Don’t c ar e23

Lch Data Rch Data

23 30 2222423 30

22 1 0 Don ’t c are

23 2223

Figure 3. Mode 2 Timing

LRCK

BICK

(

64fs

)

SDATA

031 2 24 31 0 1 31 0 1

23:MSB, 0:LSB

22 10Don’t care

Lch Data Rch Data

23 25 322423 25

22 1 0D on’t care23 23

Figure 4. Mode 3 Timing

n De-emphasis filter

A digital de-emphasis filter is available for 32, 44.1, 48 or 96kHz sampling rates (tc = 50/15µs) and is enabled or disabled

with the DEM0, DEM1 and DFS input pins.

DEM1 DEM0 DFS Mode

0 0 0 44.1kHz Default

010OFF

1 0 0 48kHz

1 1 0 32kHz

001OFF

011OFF

1 0 1 96kHz

111OFF

Table 6 . De-emphasis filter control

ASAHI KASEI [AK4393]

M0039-E-01 2000/5

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n Soft mute operation

Soft mute operation is performed at digital domain. When SMUTE goes to “H”, the output signal is attenuated by -¥

during 1024 LRCK cycles. When SMUTE is returned to “L”, the mute is cancelled and the output attenuation gradually

changes to 0dB during 1024 LRCK cycles. If the soft mute is cancelled within 1024 LRCK cycles after starting the

operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for changing the signal source

without stopping the signal transmission.

SMUTE

Attenuation

1024/fs

0dB

-¥

AOUT

1024/fs

GD GD

(1)

(2)

(3)

Notes:

(1) The output signal is attenuated by -¥ during 1024 LRCK cycles (1024/fs).

(2) Analog output corresponding to digital input has the group delay (GD).

(3) If the soft mute is cancelled within 1024 LRCK cycles, the attenuation is discontinued and returned to 0dB.

Figure 5. Soft mute operation

ASAHI KASEI [AK4393]

M0039-E-01 2000/5

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n System Reset

The AK4393 should be reset once by bringing PDN = “L” upon power-up. The AK4393 is powered up and the internal

timing starts clocking by LRCK “” after exiting reset and power dow n state by MCLK. The AK4393 is in the pow er-down

mode until MCLK and LRCK are input.

n Power-Down

The AK4393 is placed in the pow er-dow n m ode by bring ing PDN pin “L ” and the anlog ou tputs are floatin g (Hi-Z). Figu re

6 shows an example of the system timing at the power-down and power-up.

Norma l Operation

Internal

State

PDN

Power-down Normal Opera tion

GD GD

“0” data

D/A Out

(Analog)

D/A In

(Digital)

Clock In

MCLK, LRCK, BICK

(1) (3)

External

MUTE (5)

(3) (1)

Mute ON

(2)

(4)

Don’t care

Notes:

(1) The analog output corresponding to digital input has the group delay (GD).

(2) Analog outputs are floating (Hi -Z) at the power-down mode.

(3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.

(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”).

(5) Please mute the analog output externally if the click noise (3) influences system application.

The timing example is shown in this figure.

Figure 6. Power-down/up sequence example

n Click Noise from anal og output

Click noise occurs from analog output in the following cases.

1) When switching de-emphasis mode by DEM0, DEM1 and DFS pins,

2) When switching serial data mode by DIF0, DIF1 and DIF2 pins,

3) When going and exiting power down mode by PDN pin,

4) W he n switching normal speed and double speed by DFS pin,

However in case of 1) & 2), If the input data is “0” or the soft mute is enabled (after 1024 LRCK cycles from SMUTE =

“H”), no click noise occur except for switching DFS pin.

ASAHI KASEI [AK4393]

M0039-E-01 2000/5

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n Mode Control Interface

Pins (parallel control mode) or registers (serial control mode) can control each functions of the AK4393. For DIF2-0,

CKS2-0 and DFS, the setting of pin and register are “ORed” internally. So, even serial control mode, pin setting can also

control these functions.

The serial control interface is enabled by the P/S pin = “L”. In this m ode, pin setting m ust be all “L ”. Internal reg isters m ay

be written by 3-w ire µP interface pins: CSN, CCLK and CDTI. The data on this interface consists of Chip address (2bits,

C1/0; fixed to “01”), Read/Write (1bit; fixed to “1”), Register address (MSB first, 5bits) and Control data (MSB first,

8bits). The AK4393 latches the data on the rising edge of CCLK, so data should be clocked in on the falling edge. The

writing of data becomes valid by CSN “”. The clock speed of CC LK is 5MHz(max). The CSN and CCL K must be f ix ed

to “H” when the register does not be accessed.

PDN = “L” res ets the reg isters to their default v alues. When the state of P/S pin is change d, the AK4393 should be reset by

PDN = “L”. In serial mode, the internal timing circuit is reset by RSTN bit, but the registers are not initialized.

CDTI

CCLK

012345678 9 10 11 12 13 14 15

D4D5D6D7A1A2A3A4R/WC0 A0 D0D1D2D3

CSN

C1-C0: Chip Address (Fixed to “01”)

R/W: READ/WRITE (Fixed to “1”, W r ite only)

A4-A0: Register Address

D7-D0: Control Data

Figure 7. Control I/F Timing

*The AK4393 does not support the read command and chip address. C1/0 and R/W are fixed to “011”

*When the AK4393 is in the pow er down mode (PDN = “L”) or th e MCLK is not provided, writin g into the control register

is inhibited.

*For setting the registers, the following sequence is recommended.

 Control 1 register

(1) Writing RSTN = “0” and other bits (D6-D1) to the register at the same time.

(2) Writing RSTN = “1” to the register. The other bits are no change.

 Control 2 register

This writing sequence has no limitation like control 1 register.

*When RST N = “0”, the click noise is output fro m AOUT pins.

*If the mode setting is done without setting RSTN = “0”, large noise may be output from AOUT pins. (Especially when

CKS0/1/2 are changed.)

ASAHI KASEI [AK4393]

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n Register Map

Addr Re

ister Name D7 D6 D5 D4 D3 D2 D1 D0

00H Control 1 0 CKS2 CKS1 CKS0 DIF2 DIF1 DIF0 RSTN

01H Control 2 0 0 0 0 DFS DEM1 DEM0 SMUTE

02H Test TEST7 TEST6 TEST5 TEST4 TEST3 TEST2 TEST1 TEST0

Notes:

For addresses from 03H to 1FH, data must not be written.

When PDN pin goes to “L”, the registers are initialized to their default values. When RSTN bit goes to “0”, the only

internal timing is reset and the registers are not initialized to their default values. DIF2-0, CKS2-0 and DFS bits are

ORed with pins respectively.

n Register Definiti ons

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

00H Co ntrol 1 0 CKS2 CKS1 CKS0 DIF2 DIF1 DIF0 RSTN

default 00000001

RSTN: Internal timing reset

0: Reset. All registers are not initialized.

1: Normal Operation

When the states of CKS2-0 or DFS change, the AK4393 should be reset by PDN pin or RSTN bit.

DIF2-0: Audio data interface modes (see Table 5)

Initial: “000”, Mode 0

CKS2-0: Master Clock Frequency Select (see Table 2)

Initial: “000”, Mode 0

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

01H Control 2 0 0 0 0 DFS DEM1 DEM0 SMUTE

default 00000000

SMUTE: Soft Mute Enable

0: Normal operation

1: DAC outputs soft-muted

DEM1-0: De-emphasis response (see T a ble 6)

Initial: “00”, 44.1kHz

DFS: Sampling speed control (see Table 1)

0: Normal speed

1: Double speed

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

02H Test TEST7 TEST6 TEST5 TEST4 TEST3 TEST2 TEST1 TEST0

default 00000000

TEST7-0: Test mode. Do not write any data to 02H.

ASAHI KASEI [AK4393]

M0039-E-01 2000/5

- 17 -

SYSTEM DESIGN

Figu re 8 and 9 show the sy stem connection diagram. A n evalu ation board (AKD4393) is available w hich dem onstrates the

optimum layout, power supply arrangements and measurement results.

DVSS

DVDD

MCLK

PDN

BICK

SDATA6

LRCK

CSN

DFS9

CCLK10

CDTI

DIF0

CKS2 28

CKS1 27

CKS0 26

P/S 25

VCOM 24

AOUTL+ 23

AOUTL- 22

AOUTR+ 21

AOUTR- 20

AVSS 19

AVDD 18

VREFH 17

Master Clock

Micro-

controller

0.1u10u

10u

0.1u +

10u

+Supply 5V

AK4393

0.1u

Digital

Supply

DIF1

DIF2

VREFL

BVSS

24bit Audio Data

Reset & Power down

64fs 10u

0.1u +

Lch

LPF

Rch

LPF

Lch Out

Analog GroundDigital Ground

Analog

Rch Out

Figure 8. Typical Connection Diagram (Serial mode)

Notes:

- LRCK = fs, BICK = 64fs.

- Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of

regulator etc.

- AVSS, BVSS and DVSS must be connected to the same analog ground plane.

- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive

load.

- All input pins except pull-down/pull-up pins should not be left floating.

ASAHI KASEI [AK4393]

M0039-E-01 2000/5

- 18 -

DVSS

DVDD

MCLK

PDN

BICK

SDATA6

LRCK

SMUTE

DFS9

DEM010

DEM1

DIF0

CKS2 28

CKS1 27

CKS0 26

P/S 25

VCOM 24

AOUTL+ 23

AOUTL- 22

AOUTR+ 21

AOUTR- 20

AVSS 19

AVDD 18

VREFH 17

Master Clock

Mode

setting

0.1u10u

10u

0.1u +

10u

+Supply 5V

AK4393

0.1u

Digital

Supply

DIF1

DIF2

VREFL

BVSS

24bit Audio Data

Reset & Power down

64fs 10u

0.1u +

Lch

LPF

Rch

LPF Rch Out

Lch Out

Master

Clock

Select

Analog

Analog GroundDigital Ground

Figure 9. Typical Connection Diagram (Parallel mode)

Notes:

- LRCK = fs, BICK = 64fs.

- Power lines of AVDD and DVDD should be distribu ted separately from the poin t with low impedance of regulator

etc.

- AVSS, BVSS and DVSS must be connected to the same analog ground plane.

- When AOUT drives some capacitive load, some resistor should be added in series between A OUT and capacitive

load.

- All input pins except pull-down/pull-up pins should not be left floating.

Analog GroundDigital Ground

System

Controller

DVSS

DVDD

MCLK

PDN

BICK

SDATA6

LRCK

SMUTE

DFS9

DEM010

DEM1

DIF0

CKS2 28

CKS1 27

CKS0 26

P/S 25

VCOM 24

AOUTL+ 23

AOUTL- 22

AOUTR+ 21

AOUTR- 20

AVSS 19

AVDD 18

VREFH

AK4393

DIF1

DIF2

VREFR

BVSS

Figure 10. Ground La yout

ASAHI KASEI [AK4393]

M0039-E-01 2000/5

- 19 -

1. Groundi ng and Power Supply Decoupl i ng

To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD and DVDD, respectively.

AVDD is supplied from analog supply in system and DVDD is supplied from digital supply in system. If AVDD and

DVDD are supplied separately, the power up sequence is not critical. AVSS, BVSS and DVSS must be connected

to analog ground plane. System analog ground and digital ground should be connected together near to where the

supplies are bro ught onto the printed circuit board. Decoupling capacitors for high frequency should be p laced as near as

possible.

2. Voltage Reference

The differential Voltage between VREFH and VREFL set the analog output range. VREFH pin is normally connected to

AVDD and VREFL pin is normally connected to AVSS. VREFH and VREFL should be connected with a 0.1µF ceramic

capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 10µF pa rallel with a 0.1µF ceramic capacitor

attached to VCOM pin elim inates the ef fects of h igh f requency n oise. No load curren t m ay be draw n f rom VC OM pin. All

signals, especially clocks, should be kept away from the VREFH, VREFL and VCOM pins in order to avoid unwanted

coupling into the AK4393.

3. Analog Outputs

The analog outputs are full differential outputs and 2.4Vpp (typ@VREF=5V) centered around VCOM. The differential

outputs are sum m ed externally , VAOUT = (AOUT+) - (AOUT-) betw een A OUT+ and AOUT-. If th e sum min g gain is 1, the

output range is 4.8 Vpp (typ@VREF=5V). The bias voltage of the external summing circuit is supplied externally. The

input data format is 2's complement. The output voltage (VAOUT) is a positive full scale for 7FFFFFH (@24bit) and a

negative full scale for 800000H (@24bit). The ideal VAOUT is 0V for 000000H(@24bit).

The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond the audio

passband.

Figure 11 shows an example of external LPF circuit summing the differential outputs by an op-amp.

Figure 12 shows an example of differential outputs and LPF circuit example by three op-amps.

1k 1k

1k 1n

+Vop

-Vop

AOUT-

AOUT+

3.3n Analog

Out

AK4393

Figure 11. External LPF Circuit Example 1

ASAHI KASEI [AK4393]

M0039-E-01 2000/5

- 20 -

300

47u 300

AOUTL-

620

10n

300

220

10n

2710u

0.1u

0.1u 10u

10u

NJM5534D

300

47u

300

AOUTL+

620

10n

300

220

10n

2710u

0.1u

0.1u 10u

NJM5534D

100

0.1u +

NJM5534D

0.1u 10u

100

4.7n

620

430

4.7n

Lch

-15

+15

430

Figure 12. External LPF Circuit Example 2

ASAHI KASEI [AK4393]

M0039-E-01 2000/5

- 21 -

PACKAGE

0.1±0.1

0-10°

D eta il A

Seating Plane

NO TE: Dimension "*" does not include mold flash.

0.10

0.15-0.05

0.22±0.1 0.65

*9.8±0.2 1.25±0.2

114

28pin VSO P

(

Unit: mm

)

*5.6±0.2

7.6±0.2

0.5±0.2

+0.1

0.675

n Material & Lead finish

Package molding compound: Epoxy

Lead frame material: Cu

Lead frame surface treatment: Solder plate

ASAHI KASEI [AK4393]

M0039-E-01 2000/5

- 22 -

MARKING

AKM

AK4393VF

XXXBYYYYC

XXXXBYYYYC data code identifier

XXXB: Lot number (X : Digit number, B : Alpha character )

YYYYC: Assembly date (Y : Digit number C : Alpha character)

IMPORTANT NOTICE

· These products and their specifications are subject to change without notice. Before considering any

use or application, c onsult the Asahi Kasei Mic rosystems Co., Ltd. (AKM) sales off ice or authorized

distributor c oncerning their cur rent status.

· AKM assum es no liability for infringem ent of any patent, intellectual property, or other right in the

application or use of any inform ation contained her ein.

· Any export of these products, or devices or sy stems containing them, may require an export license or

other official approval under the law and regulations of the country of export pertaining to customs and

tariff s, currenc y exchange, or s trategic m aterials.

· AKM products ar e neither intended nor authorized for use as critical com ponents in any safety, life

support, or other hazard related device or system, and AKM assumes no responsibility relating to any

such use, ex cept with the express written c onsent of the Repres entative Director of AKM. As used

here:

(a) A hazard r elated device or system is one designed or intended f or lif e support or m aintenanc e of

safety or for applications in medic ine, aerospace, nuclear energy, or other fields, in which its

failure to f unction or perf orm m ay reasonably be expected to r esult in loss of life or in signif icant

injury or damage to pers on or property.

(b) A critic al com ponent is one whose failure to f unction or perf orm may reasonably be expected to

result, whether directly or indirectly, in the loss of the saf ety or effectiveness of the device or

system containing it, and which m ust theref ore m eet very high standards of perf ormanc e and

reliability.

· It is the respons ibility of the buyer or distributor of an AKM product who distributes, dis poses of, or

otherwise places the product with a third party to notify that party in advance of the above content and

conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and

hold AKM harmless from any and all claims arising from the use of said product in the absence of such

notification.