U2783B 1250-MHz / 400-MHz Twin PLL Description The IC U2783B is a low-power twin PLL manufactured with Atmel Wireless & Microcontrollers' advanced UHF process. The maximum operating frequency is 1250 MHz and 400 MHz respectively. It features a wide supply-voltage range from 2.7 V to 5.5 V. Prescaler and power-down function for both PLLs is integrated. Applications are CT1, CT2, IS54 etc. Features Benefits D Very low current consumption (typical 3 V/10 mA) Electrostatic sensitive device. Observe precautions for handling. D Supply-voltage range 2.7 V to 5.5 V D Low current consumption leads to extended talk time D Maximum input frequency PLL1: 1250 MHz, PLL2: 400 MHz D Twin PLL saves costs and space D 2 pins for separate power-down functions D One foot print for all Atmel Wireless & Microcontrollers twin PLLs saves design-in time D Output for PLL lock status D Prescaler 64/65 for PLL1 and 32/33 for PLL2 D SSO20 package D ESD protected according to MIL-STD 833 method 3015 cl.2 Block Diagram 1 VS analog 4 VS digital 2 DGND 6 9 Power down Test AGND 15 7 OSCi 8 OSCo Oscillator Control functions Clock Lock select 64/65 Prescaler 1 11 3-bit 10 HPD1/Port 1 HPD2/Port 4 Port3 Lock Port2 12-bit latch 1 12-bit reference divider 1 17-bit latch 1 5 14 20 16-bit latch On / off divide by 2 RFi1 Ports 5I/Port 0 Phase detector 1 Charge pump 1 3 17 17-bit main divider 1 17-bit Shift register Pump bias 19 CP1 VScp Iset Data 12 Enable 13 Load control 12-bit latch 2 12-bit reference divider 2 15-bit latch 2 RFi2 16 32/33 Prescaler 2 Phase detector 2 Charge pump 2 18 CP2 15-bit main divider 2 94 8918 Figure 1. Block diagram Rev. A5, 07-Sep-00 1 (11) U2783B Ordering Information Extended Type Number Package Remarks U2783B-AFS SSO20 Tube, MOQ 830 pcs U2783B-AFSG3 SSO20 Taped and reeled, MOQ 4000 pcs Pin Description 5I/Port 0 1 VS digital 20 Port 3 2 19 Iset Pin Symbol 1 5I/Port 0 2 VS digital Power supply digital section 3 CP 1 3 VS analog 4 17 VScp RFi 1 5 16 RFi 2 GNDD 6 15 GNDA OSCi 7 OSCo 8 18 CP 2 4 13 Enable 12 Data Lock/Port 2 10 11 Clock 95 9622 Figure 2. Pinning 5I - Control input / o.c.output Charge-pump output of synthesizer 1 VS analog Power supply analog section 5 RFi 1 RF divider input synthesizer 6 GNDD Ground for digital section 7 OSCi Reference oscillator input 8 OSCo Reference oscillator output 9 HPD 1/ Port 1 Hardware power-down input of synthesizer 1 / o.c.output 10 Lock/ Port 2 Lock output / o.c.output / testmode output 11 Clock 3-wire-bus: serial clock input 12 Data 3-wire-bus: serial data input 13 Enable 3-wire-bus: serial enable input 14 HPD 2/ Port 4 Hardware power-down input of synthesizer 2 / o.c.output 15 GNDA Ground for analog section 16 RFi 2 RF divider input synthesizer 2 17 VScp Charge-pump supply voltage 18 CP 2 Charge-pump output of synthesizer 2 19 Iset Reference pin for charge-pump currents 20 Port 3 14 HPD2/Port 4 HPD1/Port 1 9 2 (11) CP 1 Function o.c.output Rev. A5, 07-Sep-00 U2783B Absolute Maximum Ratings Parameters Supply voltage Pins 2, 4 and 17 Input voltage Pins 1, 3, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18 and 20 Junction temperature Storage-temperature range Symbol Value Unit VS, VScp 6 V Vi 0 to VS V Tj 125 C Tstg -40 to +125 C Symbol Value Unit VS, VScp 2.7 to 5.5 V Tamb -40 to +85 C Symbol Value Unit Rthja 140 K/W Operating Range Parameters Supply voltage Pins 2, 4 and 17 Ambient-temperature range Thermal Resistance Parameters Junction ambient Rev. A5, 07-Sep-00 SSO20 3 (11) U2783B Electrical Characteristics Tamb = 25_C, VS = 2.7 to 5.5 V, VScp = 5 V, unless otherwise specified AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAA AAAA AAA AAA AAA AAAA AAAAAAAAAAAA AAAAAAAAA AAAA AAA AAA AAA AAAA AAAAAAAAAAAA AAAAAAAAA AAAA AAA AAA AAA AAAA AAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAA AAAA Parameters Test Conditions Symbol Min. Typ. Max. Unit DC Supply Supply current VS = 3 V IS 10 mA Supply current CP VCP = 5 V, PLL in lock condition ICP 1 A fRFi1 = 200 - 1250 MHz VRFi1 PLL 1 Input voltage Scaling factor prescaler 20 SPSC 200 mVRMS 64/65 Scaling factor main counter SM 5 2047 Scaling factor swallow counter SS 0 63 Reference counter SR 5 4096 VRFi2 40 20 200 200 PLL 2 Input voltage fRFi2 = 50 MHz fRFi2 = 100 - 400 MHz Scaling factor prescaler SPSC mVRMS 32/33 Scaling factor main counter SM 5 1023 Scaling factor swallow SS 0 31 Reference counter SR 5 4096 RS 10 200 W 1 1 20 40 MHz Reference oscillator Recommended crystal series resistance External reference input frequency External reference input amplitude AC coupled sinewave RF/2 = 0 RF/2 = 1 AC coupled sinewave OSCi 2) OSCi 100 mVRMS Logic input levels (Clock, Data, Enable, HPD1, HPD2, 5I) High input level ViH 1.5 V Low input level ViL 0 0.4 V High input current IiH -5 5 mA Low input current IiL -5 5 mA Logic output levels (Ports 0, 1, 2, 3, 4, Lock) Leakage current VOH = 5.5 V IL 10 mA Saturation voltage IOL = 0.5 mA VSL 0.4 V Charge-pump output (Rset = 10 kW, see figure 3) Source current VCP x VScp/2 5I = L 5I = H VCP x VScp/2 5I = L 5I = H VCP x VScp/2 Sink current Leakage current 1) RMS voltage at 50 W; 4 (11) 2) PLL2 PLL1 PLL1 PLL2 PLL1 PLL1 Isource Isink IL -1 -0.2 -1 1 0.2 1 "5 mA mA nA OSCo is open if an external reference frequency is applied Rev. A5, 07-Sep-00 U2783B Serial Bus Programming Reference and programmable counters can be programmed by 3-wire bus (Clock, Data and Enable). After setting enable signal to high condition, the data status is transfered bit by bit on the rising edge of the clock signal into the shift register, starting with the MSB bit. After the Enable signal returns the addressed latch. Additional leading bits are ignored and there is no check made how many clock pulses arrived during enable high condition. In power-down mode the 3-wire-bus remains active and the IC can be programmed. Data is entered with the most significant bit first. The leading bits deliver the divider or control information. The trailing three bits are the address field. There are six different addresses used. The trailing address bits are decoded upon the falling edge of the Enable signal. The internal loadpulse is beginning with the falling edge of the Enable signal and ending with the falling edge of the Clock signal. Therefore a minimum holdtime clock-enable tHCE is required. Bit Allocation MSB Bit 1 Bit 2 LSB Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 Bit 16 Bit 17 Bit 18 Data bits D16 D15 PLL1 M10 M9 D14 M8 D13 M7 D12 M6 D11 D10 D9 D8 RF/2 Test M8 5IP M7 TRI2 Bit 20 Address bits D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 0 0 1 M5 M4 M3 M2 M1 M0 S5 S4 S3 S2 S1 PLL1 S0 PLL1 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 PLL1 R0 0 1 0 M6 M5 M4 M3 M2 M1 M0 S4 S3 S2 S1 PLL2 S0 0 1 1 PLL2 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 PLL2 R0 1 0 0 TRI1 PS2 PS1 H2P H1P P4 P3 P2 P1 P0 1 0 1 SPD 1 1 1 0 PLL2 M9 Bit 19 LPB LPA SPD SPD 5I 2 Scaling Factors PGD of PLL1: RFD of PLL1 and PLL2: S0 ... S5: R0 ... R11: These bits are setting the reference counter SR. SR = R0*20 + ... + R10*210 + R11*211 allowed scaling factors for SR: 5 ... 4096 RF/2 = 1: SRFD = 2 * SR RF/2 = 0: SRFD = SR These bits are setting the swallow counter SS. TS = S0*20 + S1*21 + ... + S4*24 + S5*25 allowed scaling factors for SS: 0 ... 63, TS < TM M0 ... M10: These bits are setting the main counter SM. TM = M0*20 + M1*21 + ... + M9*29 + M10*210 allowed scaling factors for SM: 5 ... 2047 Total scaling factor of the programmable counter: SPGD: SPGD = (64*SM) + SS Condition: SS < SM PGD of PLL2: S0 ... S4: M0 ... M9: SPGD: These bits are setting the swallow counter SS. TS = S0*20 + S1*21 + ... + S3*23 + S4*24 allowed scaling factors for SS: 0 ... 31, TS < TM These bits are setting the main counter SM. TM = M0*20 + M1*21 + ... + M8*28 + M9*29 allowed scaling factors for SM: 5 ... 1023 Total scaling factor of the programmable counter: SPGD = (32*SM) + SS Condition: SS < SM Rev. A5, 07-Sep-00 5 (11) U2783B Serial Programming Bus Control Bits: P0 ... P4: o.c. output ports (1 = high impedance) LPA, LPB: selection of P2 output or locksignal function of Pin 10 TEST 0 0 0 0 H1P, H2P: 5IP: LPA 0 0 1 1 LPB 0 1 0 1 o.c. output P2 locksignal of synthesizer 2 locksignal of synthesizer 1 wiredor locksignal of both synthesizer selection of P1/4 output or hardware power-down input of synthesizer 1/2 (0 = Port / 1 = HPD) selection of P0 output or high current switching input for the charge-pump current of synthesizer 1 (0 = Port / 1 = charge-pump 1 current switch input) PS1, PS2: phase selection of synthesizer 1 and synthesizer 2 (1 = normal / 0 = invers) PS-PLL1/2 = 1 PS-PLL1/2 = 0 CP1/2 CP1/2 fR > fP Isink Isource fR < fP Isource Isink fR = fP 0 0 RF/2: divide by 2 prescaler for reference divider (0 = off / 1 = on) SPD1, SPD2: software power down bit of synthesizer 1/2 (0 = power down / 1 = power up) 5I: software switch for the charge-pump current of synthesizer 1 (0 = low current / 1 = high current) TRI1, TRI2: enables tristate for the charge pump of synthesizer 1/2 (0 = normal / 1 = tristate) TEST: enables counter testmode (0 = disabled / 1 = enabled) TEST LPA LPB PS1 PS2 Testsignal at Pin 10 1 1 0 1 x RFD1 1 1 0 0 x PGD1 1 0 1 x 1 RFD2 1 0 1 x 0 PGD2 To operate the software power-down mode the following condition must be set: HXP = 0; power up and power down will be set by SPDX = 1 (on) and SPDX = 0 (off). To operate the hardware power-down mode the following condition must be set: HXP = 1; SPDX = 1; power up and power down will be set by high and low state at the hardware power down Pins 9/14. High current of charge pump synthesizer 1 is active when 5I = 1 and if 5IP = 1 the charge-pump current control input Pin 1 is in high state. 6 (11) Rev. A5, 07-Sep-00 Rev. A5, 07-Sep-00 47u 12 51 Crystal-oscillator input RF1 VS VS VCO 10n VCO1 10n 10n 10n C1 18 12 18 18 51 C2 R1 47u 10n 10n 10n Rset 18 18 18 C2 10n 10n R1 LOCK / PORT2 / TEST CLOCK DATA ENABLE HPD1 / PORT1 HPD2 / PORT4 51 P3 5I / P0 C1 94 9621 VCO2 47u 10n 12 10n RF2 47u VScp 12 U2783B Application Circuit Figure 3. Application circuit 7 (11) U2783B Timing Diagram Serial Bus Data Clock Enable tEL tSEC tCH tCL tSDC tHDC tHCE tHEC Internal Loadpulse 96 11828 Figure 4. Timing diagram serial bus Table 1 Timing Parameters Symbol Value Unit Clock-High Time tCH > 750 ns Clock-Low Time tCL > 350 ns Clock Period tPER > 1100 ns Set-up Time Data to Clock tSDC > 100 ns Hold Time Data to Clock tHDC > 400 ns Hold Time Clock to Enable tHCE > 400 ns Hold Time Enable to Clock tHEC > 400 ns Enable Low Time tEL > 200 ns Set-up Time Enable to Clock tSEC > 4000 ns 8 (11) Rev. A5, 07-Sep-00 U2783B 1000 4.0 3.5 1m Veff on 50W Icp / mA 3.0 2.5 5I=1 2.0 1.5 100 Guaranteed Area 10 1.0 0.5 0.0 3000 1 30000 300000 R19/ W 96 11679 Figure 5. Charge pump characteristics 0 96 11682 100 200 300 400 Frequency/ MHz 500 600 Figure 7. Input sensitivity of PLL2 1m Veff on 50W 1000 100 Guaranteed Area 10 1 0 200 400 96 11681 600 800 1000 1200 1400 Frequency/ MHz Figure 6. Input sensitivity of PLL1 Rev. A5, 07-Sep-00 9 (11) U2783B Input Impedance of PLL1 and PLL2 j 0.5j 2j 0.2j 5j AA AA A AA A AAAA A AA A 0 0.2 0.5 1 2 1 5 100 MHz -0.2j -5j 500 MHz PLL2 1 GHz 1.5 GHz PLL1 -0.5j 96 11687 -2j Z0 = 50 W -j Figure 8. Output impedance of PLL1 and PLL2 Package Information Package SSO20 5.7 5.3 Dimensions in mm 6.75 6.50 4.5 4.3 1.30 0.15 0.15 0.05 0.25 6.6 6.3 0.65 5.85 20 11 technical drawings according to DIN specifications 13007 1 10 (11) 10 Rev. A5, 07-Sep-00 U2783B Ozone Depleting Substances Policy Statement It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. 2. We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify TEMIC Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Data sheets can also be retrieved from the Internet: http://www.temic-semi.com TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423 Rev. A5, 07-Sep-00 11 (11)