U2783B-AFSG3 - Atmel Corporation

U2783B

Rev. A5, 07-Sep-00 1 (11)

1250-MHz / 400-MHz Twin PLL

Description

The IC U2783B is a low-power twin PLL manufactured

with Atmel Wireless & Microcontrollers’ advanced UHF

process. The maximum operating frequency is 1250 MHz

and 400 MHz respectively. It features a wide supply-volt-

age range from 2.7 V to 5.5 V.

Prescaler and power-down function for both PLLs is inte-

grated. Applications are CT1, CT2, IS54 etc.

Electrostatic sensitive device.

Observe precautions for handling.

Features

DVery low current consumption (typical 3 V/10 mA)

DSupply-voltage range 2.7 V to 5.5 V

DMaximum input frequency PLL1: 1250 MHz,

PLL2: 400 MHz

D2 pins for separate power-down functions

DOutput for PLL lock status

DPrescaler 64/65 for PLL1 and 32/33 for PLL2

DSSO20 package

DESD protected according to MIL-STD 833

method 3015 cl.2

Benefits

DLow current consumption leads to extended talk time

DTwin PLL saves costs and space

DOne foot print for all Atmel Wireless &

Microcontrollers twin PLLs saves design-in time

Block Diagram

12-bit reference divider 2

12-bit latch 2

15-bit latch 2

15-bit main divider 2

17-bit

Shift register

17-bit latch 1

17-bit main divider 1

12-bit reference divider 1

12-bit latch 1

16-bit latch

Control functions

Oscillator

On / off

divide by 2

64/65 Prescaler 1

32/33 Prescaler 2

3-bit

Load control

Phase

detector 1

Phase

detector 2

Charge

pump 1

Charge

pump 2

Pump

bias

Lock

select

Ports

Power

down Test

5I/Port 0

HPD1/Port 1

HPD2/Port 4

Port3

Lock Port2

CP1

VScp

Iset

CP2

VS analog

VS digital

DGND

AGND

OSCi

OSCo

RFi1

Clock

Data

Enable

RFi2

94 8918

Figure 1. Block diagram

U2783B

Rev. A5, 07-Sep-002 (11)

Ordering Information

Extended Type Number Package Remarks

U2783B-AFS SSO20 Tube, MOQ 830 pcs

U2783B-AFSG3 SSO20 Taped and reeled, MOQ 4000 pcs

Pin Description

20 Port 3

Iset

CP 2

VScp

RFi 2

GNDA

HPD2/Port 4

Enable

Data

Clock

5I/Port 0

VS digital

CP 1

VS analog

RFi 1

GNDD

OSCi

OSCo

HPD1/Port 1

Lock/Port 2

95 9622

Figure 2. Pinning

Pin Symbol Function

15I/Port 0 5I – Control input / o.c.output

2 VS digital Power supply digital section

3CP 1 Charge-pump output of

synthesizer 1

4 VS analog Power supply analog section

5RFi 1 RF divider input synthesizer

6 GNDDGround for digital section

7 OSCiReference oscillator input

8 OSCoReference oscillator output

9HPD 1/

Port 1 Hardware power-down input of

synthesizer 1 / o.c.output

10 Lock/

Port 2 Lock output / o.c.output /

testmode output

11 Clock 3-wire-bus: serial clock input

12 Data 3-wire-bus: serial data input

13 Enable 3-wire-bus: serial enable input

14 HPD 2/

Port 4 Hardware power-down input of

synthesizer 2 / o.c.output

15 GNDAGround for analog section

16 RFi 2 RF divider input synthesizer 2

17 VScp Charge-pump supply voltage

18 CP 2 Charge-pump output of

synthesizer 2

19 Iset Reference pin for charge-pump

currents

20 Port 3 o.c.output

U2783B

Rev. A5, 07-Sep-00 3 (11)

Absolute Maximum Ratings

Parameters Symbol Value Unit

Supply voltage Pins 2, 4 and 17 VS, VScp 6 V

Input voltage Pins 1, 3, 5, 8, 9, 10, 11, 12,

13, 14, 15, 16, 18 and 20 Vi0 to VSV

Junction temperature Tj125 °C

Storage-temperature range Tstg –40 to +125 °C

Operating Range

Parameters Symbol Value Unit

Supply voltage Pins 2, 4 and 17 VS, VScp 2.7 to 5.5 V

Ambient-temperature range Tamb –40 to +85 °C

Thermal Resistance

Parameters Symbol Value Unit

Junction ambient SSO20 Rthja 140 K/W

U2783B

Rev. A5, 07-Sep-004 (11)

Electrical Characteristics

Tamb = 25_C, VS = 2.7 to 5.5 V, VScp = 5 V, unless otherwise specified

Parameters Test Conditions Symbol Min. Typ. Max. Unit

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DC Supply

ÁÁÁÁÁÁÁÁÁÁÁÁ

Supply current

ÁÁÁÁÁÁÁÁÁ

VS = 3 V

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁ

Supply current CP

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

VCP = 5 V, PLL in lock

condition

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ICP

ÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

µA

PLL 1

Input voltage fRFi1 = 200 – 1250 MHz VRFi1 20 200 mVRMS

Scaling factor prescaler SPSC 64/65

Scaling factor main counter SM5 2047

Scaling factor swallow counter SS0 63

Reference counter SR5 4096

PLL 2

Input voltage fRFi2 = 50 MHz VRFi2 40 200 mVRMS

Input voltage fRFi2 = 50 MHz

fRFi2 = 100 – 400 MHz VRFi2 40

20 200

200 mVRMS

Scaling factor prescaler SPSC 32/33

Scaling factor main counter SM5 1023

Scaling factor swallow SS0 31

Reference counter SR5 4096

Reference oscillator

Recommended crystal

series resistance RS10 200 W

External reference input frequency AC coupled sinewave

RF/2 = 0

RF/2 = 1

OSCi1

120

40 MHz

External reference input amplitude AC coupled sinewave 2) OSCi100 mVRMS

Logic input levels (Clock, Data, Enable, HPD1, HPD2, 5I)

High input level ViH 1.5 V

Low input level ViL 0 0.4 V

High input current IiH –5 5 mA

Low input current IiL –5 5 mA

Logic output levels (Ports 0, 1, 2, 3, 4, Lock)

Leakage current VOH = 5.5 V IL10 mA

Saturation voltage IOL = 0.5 mA VSL 0.4 V

Charge-pump output (Rset = 10 kW, see figure 3)

Source current VCP x VScp/2 PLL2

5I = L PLL1

5I = H PLL1 Isource

– 1

–0.2

–1mA

Sink current VCP x VScp/2 PLL2

5I = L PLL1

5I = H PLL1 Isink

0.2

1mA

Leakage current VCP x VScp/2 IL"5 nA

1) RMS voltage at 50 W; 2) OSCo is open if an external reference frequency is applied

U2783B

Rev. A5, 07-Sep-00 5 (11)

Serial Bus Programming

Reference and programmable counters can be pro-

grammed by 3-wire bus (Clock, Data and Enable). After

setting enable signal to high condition, the data status is

transfered bit by bit on the rising edge of the clock signal

into the shift register, starting with the MSB bit. After the

Enable signal returns the addressed latch. Additional

leading bits are ignored and there is no check made how

many clock pulses arrived during enable high condition.

In power-down mode the 3-wire-bus remains active and

the IC can be programmed.

Data is entered with the most significant bit first. The

leading bits deliver the divider or control information.

The trailing three bits are the address field. There are six

different addresses used. The trailing address bits are

decoded upon the falling edge of the Enable signal. The

internal loadpulse is beginning with the falling edge of the

Enable signal and ending with the falling edge of the

Clock signal. Therefore a minimum holdtime

clock-enable tHCE is required.

Bit Allocation

MSB LSB

Bit

1Bit

2Bit

3Bit

4Bit

5Bit

6Bit

7Bit

8Bit

9Bit

10 Bit

11 Bit

12 Bit

13 Bit

14 Bit

15 Bit

16 Bit

17 Bit

18 Bit

19 Bit

Data bits Address bits

D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0

PLL1

M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 S5 S4 S3 S2 S1 PLL1

S0 0 0 1

PLL1

R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 PLL1

R0 0 1 0

PLL2

M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 S4 S3 S2 S1 PLL2

S0 0 1 1

PLL2

R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 PLL2

R0 1 0 0

RF/2 Test 5IP TRI2 TRI1 PS2 PS1 H2P H1P LPB LPA P4 P3 P2 P1 P0 1 0 1

SPD

5I SPD

2SPD

1 1 1 0

Scaling Factors

PGD of PLL1:

S0 ... S5: These bits are setting the swallow counter SS.

TS = S0*20 + S1*21 + ... + S4*24 + S5*25

allowed scaling factors for SS: 0 ... 63, TS < TM

M0 ... M10: These bits are setting the main counter SM.

TM = M0*20 + M1*21 + ... + M9*29 + M10*210

allowed scaling factors for SM: 5 ... 2047

SPGD: Total scaling factor of the programmable counter:

SPGD = (64*SM) + SS Condition: SS < SM

PGD of PLL2:

S0 ... S4: These bits are setting the swallow counter SS.

TS = S0*20 + S1*21 + ... + S3*23 + S4*24

allowed scaling factors for SS: 0 ... 31, TS < TM

M0 ... M9: These bits are setting the main counter SM.

TM = M0*20 + M1*21 + ... + M8*28 + M9*29

allowed scaling factors for SM: 5 ... 1023

SPGD: Total scaling factor of the programmable counter:

SPGD = (32*SM) + SS Condition: SS < SM

RFD of PLL1 and PLL2:

R0 ... R11: These bits are setting the reference counter SR.

SR = R0*20 + ... + R10*210 + R1 1*211

allowed scaling factors for SR: 5 ... 4096

RF/2 = 1: SRFD = 2 * SR

RF/2 = 0: SRFD = SR

U2783B

Rev. A5, 07-Sep-006 (11)

Serial Programming Bus

Control Bits:

P0 ... P4: o.c. output ports (1 = high impedance)

LPA, LPB: selection of P2 output or locksignal function of Pin 10

TEST LPA LPB

0 0 0 o.c. output P2

0 0 1 locksignal of synthesizer 2

0 1 0 locksignal of synthesizer 1

0 1 1 wiredor locksignal of both synthesizer

H1P, H2P: selection of P1/4 output or hardware power-down input of synthesizer 1/2 (0 = Port / 1 = HPD)

5IP: selection of P0 output or high current switching input for the charge-pump current of synthesizer 1

(0 = Port / 1 = charge-pump 1 current switch input)

PS1, PS2: phase selection of synthesizer 1 and synthesizer 2 (1 = normal / 0 = invers)

PS-PLL1/2 = 1 PS-PLL1/2 = 0

CP1/2 CP1/2

fR > fPIsink Isource

fR < fPIsource Isink

fR = fP0 0

RF/2: divide by 2 prescaler for reference divider (0 = off / 1 = on)

SPD1, SPD2: software power down bit of synthesizer 1/2 (0 = power down / 1 = power up)

5I: software switch for the charge-pump current of synthesizer 1 (0 = low current / 1 = high current)

TRI1, TRI2: enables tristate for the charge pump of synthesizer 1/2 (0 = normal / 1 = tristate)

TEST:enables counter testmode (0 = disabled / 1 = enabled)

TEST LPA LPB PS1 PS2 Testsignal

at Pin 10

1 1 0 1 x RFD1

1 1 0 0 x PGD1

1 0 1 x 1 RFD2

1 0 1 x 0 PGD2

To operate the software power-down mode the following condition must be set: HXP = 0; power up and power down

will be set by SPDX = 1 (on) and SPDX = 0 (off).

To operate the hardware power-down mode the following condition must be set: HXP = 1; SPDX = 1; power up and

power down will be set by high and low state at the hardware power down Pins 9/14.

High current of charge pump synthesizer 1 is active when 5I = 1 and if 5IP = 1 the charge-pump current control input

Pin 1 is in high state.

U2783B

Rev. A5, 07-Sep-00 7 (11)

Application Circuit

5I / P0

RF2

HPD1 / PORT1

HPD2 / PORT4

RF1

Crystal-oscillator

CLOCK

DATA

ENABLE

LOCK / PORT2 / TEST

47u 10n

Rset

47u 10n

10n 18

10n 10n

10n

18 18

1851 10n 47u

10n

5118

10n

10n51

VCO1 VCO2

input

94 9621

V VCO

VScp

Figure 3. Application circuit

U2783B

Rev. A5, 07-Sep-008 (11)

Timing Diagram Serial Bus

tSEC tCH tCL

tEL

tHEC

tHCE

tSDC tHDC

Data

Clock

Enable

Internal

Loadpulse 96 11828

Figure 4. Timing diagram serial bus

Table 1 Timing

Parameters Symbol Value Unit

Clock-High Time tCH > 750 ns

Clock-Low Time tCL > 350 ns

Clock Period tPER > 1100 ns

Set-up Time Data to Clock tSDC > 100 ns

Hold Time Data to Clock tHDC > 400 ns

Hold Time Clock to Enable tHCE > 400 ns

Hold Time Enable to Clock tHEC > 400 ns

Enable Low Time tEL > 200 ns

Set-up Time Enable to Clock tSEC > 4000 ns

U2783B

Rev. A5, 07-Sep-00 9 (11)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

3000 30000 300000

Icp / mA

R19/ W96 11679

5 I = 1

Figure 5. Charge pump characteristics

100

1000

0 200 400 600 800 1000 1200 1400

1m Veff on 50

Frequency/ MHz96 11681

Guaranteed Area

Figure 6. Input sensitivity of PLL1

100

1000

0 100 200 300 400 500 600

1m Veff on 50

Frequency/ MHz96 11682

Guaranteed Area

Figure 7. Input sensitivity of PLL2

U2783B

Rev. A5, 07-Sep-0010 (11)

Input Impedance of PLL1 and PLL2

–0.2j

–0.5j

–j

–2j

–5j

0.2j

0.5j

ÁÁ

0.2

ÁÁ

0.5

ÁÁ

96 11687

1 GHz

500 MHz

100 MHz

1.5 GHz Z0 = 50 WPLL1

PLL2

Figure 8. Output impedance of PLL1 and PLL2

Package Information

13007

technical drawings

according to DIN

specifications

Package SSO20

Dimensions in mm 6.75

6.50

0.25

0.65 5.85

1.30

0.15

0.05

5.7

5.3

4.5

4.3

6.6

6.3

0.15

20 11

110

U2783B

Rev. A5, 07-Sep-00 11 (11)

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